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Logic Circuit Simplifications and Results

The document contains a series of logical expressions and truth tables related to digital logic design, specifically for the course CMP-101L. It includes multiple expressions involving variables A, B, C, and D, along with their corresponding truth values. Each section demonstrates the application of Boolean algebra principles to derive final results from the given expressions.

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35 views6 pages

Logic Circuit Simplifications and Results

The document contains a series of logical expressions and truth tables related to digital logic design, specifically for the course CMP-101L. It includes multiple expressions involving variables A, B, C, and D, along with their corresponding truth values. Each section demonstrates the application of Boolean algebra principles to derive final results from the given expressions.

Uploaded by

sweeraansir24
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Course Title: DLD lab Name: Mina Fiaz

Course Code: CMP-101L Roll No: BS-IT-F24-S-10


Instructor: Miss Ayesha Nawaz

(1) (A + B’ + C) (A + B + C’)
A B C A+B'+C A+B+C (A+B'+C)(A+B+C')
'
0 0 0 1 1 1
0 0 1 1 0 0
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 1 1 1
1 1 1 1 1 1

(2) A’B’C’ + A’BC + AB’C’ + AB’C + ABC’ + ABC


A B C A'B'C' A'BC AB'C' AB'C ABC' ABC Final Result
0 0 0 1 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0
0 1 1 0 1 0 0 0 0 1
1 0 0 0 0 1 0 0 0 1
1 0 1 0 0 0 1 0 0 1
1 1 0 0 0 0 0 1 0 1
1 1 1 0 0 0 0 0 1 1
(3) A’BC + ABC’
A B C A'BC ABC' A'BC+ABC'
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 0 0 0
1 1 0 0 1 1
1 1 1 0 0 0
(4) (A + B + C) (A + B + C’) (A + B’ + C) (A’ + B + C) (A’ + B + C’)

A B C A+B+C A+B+C' A+B'+C A'+B+ A'+B+C' Result


C
0 0 0 0 1 1 0 1 0
0 0 1 1 0 1 1 0 0
0 1 0 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1
1 0 0 1 1 1 0 0 0
1 0 1 1 1 1 0 0 0
1 1 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1

(5) (A + C’) (A + B’)

A B C A+C A+B' (A+C')(A+B')


'
0 0 0 1 1 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 1 1 1
1 1 1 1 1 1
(6) A’BC’ + ABC + ABC’ + AB’C’

A B C A'BC' ABC ABC' AB'C' Result


0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 0 0
1 0 0 0 0 0 1 1
1 0 1 0 0 0 0 0
1 1 0 0 0 1 0 1
1 1 1 0 1 0 0 1
(7) AB+A’BD+A’CD’
A B C D AB A' BD A'BD CD' A'CD' AB+A'BD+A'CD'
0 0 0 0 0 1 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0
0 0 1 0 0 1 0 0 1 1 1
0 0 1 1 0 1 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 0 1 0 1 1 1 0 0 1
0 1 1 0 0 1 0 0 1 1 1
0 1 1 1 0 1 1 1 0 0 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 1
1 1 0 1 1 0 1 0 0 0 1
1 1 1 0 1 0 0 0 1 0 1
1 1 1 1 1 0 1 0 0 0 1
(8) (A+B’+C+D)(A+B+C+D)’(A+B’+C+D)(A’+B+C+D)(A’+B+C+D’)
A B C D A+B'+C+D (A+B+C+D) A'+B+C+D A'+B+C+D' Final Result
'
0 0 0 0 1 1 1 1 1
0 0 0 1 1 0 1 0 0
0 0 1 0 1 0 1 1 0
0 0 1 1 1 0 1 0 0
0 1 0 0 0 0 1 1 0
0 1 0 1 1 0 1 0 0
0 1 1 0 1 0 1 1 0
0 1 1 1 1 0 1 0 0
1 0 0 0 1 0 0 0 0
1 0 0 1 1 0 1 0 0
1 0 1 0 1 0 1 1 0
1 0 1 1 1 0 1 0 0
1 1 0 0 1 0 1 1 0
1 1 0 1 1 0 1 0 0
1 1 1 0 1 0 1 1 0
1 1 1 1 1 0 1 0 0

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