DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

Name of the Examination: [Link]./[Link]./M.S./Ph.D. End-Semester (Spring) Examination 2024

Subject Code: EC6208 Subject Name: Testing and Verification of VLSI Circuits
No. of Pages: 2 Maximum Marks: 50 Duration: 3 Hours
All parts of a question should be answered in single contiguous space.
Answer All Questions

Q.
No. Questions Marks

1 a) Explain the Full Scan method in the context of testing of VLSI circuits with the 3+
help of a diagram.
b) Design an 8-bit moving average calculator circuit which will calculate moving 3+3+
average of eight 1-bit data coming sequentially through a serial communication 1
port. Next, include DFT (design for testability) in your moving average
calculator circuit using full scan method to accommodate testing of the whole
circuit. Calculate overheads in terms of area and delay in the final circuit after
incorporating DFT compared to the non-testable circuit.

2 a) What is an LFSR? State three applications of an LFSR. 2+

b) Derive the polynomial generated by the LFSR shown below. Derive whether the 2+3+
generated polynomial is primitive or not, showing all possible states by the
LFSR.

What is the calculated fault coverage of the above LFSR? How this LFSR can be 1+2
modified to work as an ORA (output response analyser)?

3 a) Compare among Testing, Validation and Verification (in tabular form). 3+

b) Explain various stages of verification flow for VLSI circuits with an example. 3+
c) How functional verification is different from the formal verification method in 3+
case of VLSI Circuits. Explain with the example of a full adder verification.
d) What is Linting? How is it different from Simulation? 1

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4 a) What is fault tolerance and how to achieve it in VLSI circuits? Assume one of
the inputs of a two input OR gate is at s-a-1 fault. How to test and rectify (tolerate
the fault) it so that you can use the OR gate in your circuit? 3+
b) Analyse the triple transistor (TT) inverter logic shown in the figure below and
explain its functionality. Find out the errors for which the TT inverter circuit
would give erroneous outputs? (assume transistor stuck-on and stuck-off faults 4+
only)

Assuming failure probability of single transistor as p, calculate the reliability of

the above TT inverter.
5 Write short notes on (any Two)
a) Boundary Scan Method
5+5
b) Dynamic Redundancy Technique
c) Verification Techniques in the Backend Design of VLSI Circuits

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 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

Name of the Examination: M. Tech. / Ph. D. End-Semester (Spring) Examination 2023

Subject Code: EC6208 Subject Name: Testing and Verification of VLSI Circuits
No. of Pages: 2 Maximum Marks: 50 Duration: 3 Hours
All parts of a question should be answered in single contiguous space.
Answer All Questions

Q. Marks
No. Questions
1 a) Define Controllability and Observability of a circuit with examples.
b) What is Syndrome checking and what is its importance?
c) What are the various methods for Verification of VLSI circuits? How is it
different from Validation? 5×2

d) What are the major parameters that affect Verification costs in VLSI industry and
how?
e) What is Built in Logic Block Observer (BILBO) and what is its use?
2 a) What is Scan Path method? Explain with diagram. How is it different from the 3+1
Boundary Scan method? Draw the Boundary Scan architecture and explain how +3+
IEEE or JTAG standards work with it. Elaborate various applications and 2+1
advantages of the Boundary Scan technique. How the same can be used to check
interconnection faults?

3 a) Derive the polynomial generated by the LFSR shown below. Derive whether the 5
generated polynomial is primitive or not.

b) Design a 3:1 majority voter circuit using NAND gates. Suppose you want test
the circuit using scan method (at gate level) with exhaustive test patterns. Derive 5
the test pattern and explain how the scan chain will work using suitable diagram.
4 a) Define aliasing error with respect to Signature Analysis. Assume output of the 4
circuit under test is 10-bit long, which is compared with golden signature
generated by a signature generator circuit. How much aliasing error is possible,
if the signature generator is of size 8-bit.
+

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 b) Consider the following Dining Philosophers Problem:
Three philosophers seated around a circular table with one spoon between each
pair of philosophers. There is only one spoon between each philosopher and hence
total three spoons are available in the table. A philosopher may eat if he can pick
up the two spoons adjacent to him. Assume, there are three states of each
philosopher: Thinking (T), Hungry (H), and Eating (E). If Thinking, a philosopher 6
is not eating or taking the spoons. Hungry means, the philosopher tries to take both
the spoons and takes whichever available. Eating represents both spoons are with
the philosopher. Once Hungry the philosopher cannot go back to Thinking unless
his Eating is completed. After each Eating, the philosopher puts down both the
spoons and goes to Thinking until he is again Hungry.
Draw a state diagram so that the situation never leads to a deadlock (Deadlock
happens when all philosophers are hungry and each philosopher is holding single
spoon, so none of them can get the second spoons and hence cannot eat).
5 Write short notes on (Any Two)
a) Automatic Test Pattern Generator
2×5
b) Generation of Golden Signatures
c) Formal Verification of VLSI Circuits

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 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

Name of the Examination: M. Tech. / Ph. D. End-Semester (Spring) Examination 2022

Subject Code: EC6208 Subject Name: Testing and Verification of VLSI Circuits
No. of Pages: 2 Maximum Marks: 50 Duration: 3 Hours
All parts of a question should be answered in single contiguous space.
Answer ALL Questions

Q. Questions Marks
No.
1 a) What do you mean by validation? How is it different from formal verification?
b) What are undetectable and equivalent faults, explain with examples.
c) What are the major parameters that affect testing and verification costs in VLSI 5x2
industry and how?
d) What do you mean by golden signature? How is it generated?
e) What is IEEE 1149.1 standard? What are its needs and pitfalls?

2 a) What is the difference between transient faults and intermittent faults?

Suppose a soft error affects the storage node of a memory element and flips 3
the stored logic value from ‘1’ to ‘0’. Being transient in nature, the cause of the
fault disappears almost immediately. Should we care about such types of faults
in memory? Explain with proper example.
b) What is boundary scan? Draw its complete architecture and explain. What is +7
Boundary Scan Cell (explain with figure)? How boundary scan is helpful in
detecting faults in multiple chips and intermediate interconnections (provide
example)?
3 a) Derive the companion matrix and the feedback polynomial generated by the
LFSR shown below. Find out whether the generated polynomial is primitive or
not.

Page 1 of 2
 b) Draw the complete architecture for BIST. Discuss with examples various
compaction techniques utilized in ORA design for a BIST. +5

4 a) Assuming failure probability of single transistor as p, calculate the reliability of

the following triple transistor inverter logic. 4

b) Suppose three users want to access an online book. The book can be used for
both reading and writing. All the users can read from the book simultaneously, only +4

one can write at a time. While somebody is writing, the book cannot be read as
well. Draw the state model of the possible scenarios assuming that initially neither
of the users is reading or writing.

c) Draw random access scan architecture and explain. +2

5 Write short notes on: (ANY TWO)

a) Verification of VLSI Circuits
b) ATPG 2x5

c) MISR

Page 2 of 2
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

Name of the Examination: M. Tech. / Ph. D. End-Semester (Spring) Examination 2021

Subject Code: EC6208 Subject Name: Testing and Verification of VLSI Circuits
No. of Pages: 2 Maximum Marks: 50 Duration: 2 Hours
All parts of a question should be answered in single contiguous space.
Answer All Questions

Q.
Questions Marks
No.
1 a) Plot the K-map of the following function and determine hazard-free
implementation of the same using 3-input NOR gates only. 7+
F(A,B,C,D) = ∑(3,4,5,6,11,12,13,14,15)
b) What is the difference between static redundancy and dynamic reconfiguration
method? Elaborate the advantages and disadvantages with the design for two-bit 6+
fault tolerant ripple carry adder using both the methods.
c) Find out the minimal test set for following logic circuit using any of the
suitable methods.

2 a) What is Scan Path technique? How is it different from the Boundary Scan
method? Draw the Boundary Scan architecture and explain how IEEE or JTAG 8+
standards work with it. Elaborate various applications and advantages of the
Boundary Scan technique.

b) Derive the polynomial generated by the LFSR shown below. Find out whether
the generated polynomial is primitive or not.

7+

Page 1 of 2
 Modify the above LFSR so that it works as an Output Response Compactor?

b) Write a short note on ATPG (Automatic Test Pattern Generator). 5

3 a) What are the basic differences between testing and verification of a VLSI
circuit?
b) What do you mean by validation? How is it different from verification?
c) What are the various methods for verification of VLSI circuits? 5×2
d) What is formal verification? Why is it important?
e) What are the major parameters that affect verification costs in VLSI industry
and how?

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