ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print) IJECT Vol.

4, Issue Spl - 2, Jan - March 2013

An Efficient VLSI Design Approach to Reduce Static Power

using Variable Body Biasing
1
Abindas P K, 2Barani Priyanga, 3M.Jayaprakash
1,2,3
Dept. of Electronics and Communication, Park College of Engineering and Technology,
Kaniyur, Coimbatore

Abstract existing transistors into two half size transistors like the stack
In CMOS integrated circuit design there is a trade-off between approach. Then sleep transistors are added in parallel to one of
static power consumption and technology scaling. Recently, the divided transistors. During sleep mode, sleep transistors are
the power density has increased due to combination of higher turned off and stacked transistors suppress leakage current while
clock speeds, greater functional integration, and smaller process saving state. Area penalty is a significant matter for this approach
geometries. As a result static power consumption is becoming since every transistor is replaced by three transistors.
more dominant. This is a challenge for the circuit designers.
However, the designers do have a few methods which they can C. Sleepy Keeper Approach
use to reduce this static power consumption. But all of these Sleepy keeper utilizes leakage feedback technique [5] (fig. 3). In
methods have some drawbacks. In order to achieve lower static this approach, a PMOS transistor is placed in parallel to the sleep
power consumption, one has to sacrifice design area and circuit transistor (S) and a NMOS transistor is placed in parallel to the
performance. In this paper, we propose a new method to reduce sleep transistor (S'). The two transistors are driven by the output
static power in the CMOS VLSI circuit using Variable Body of the inverter. During sleep mode, sleep transistors are turned off
Biasing technique without being penalized in area requirement and one of the transistors in parallel to the sleep transistors keep
and circuit performance. the connection with the appropriate power rail.

Keywords
Variable Body Biasing, State Saving Technique, Stack Effect,
Dual V-th, Static Power Reduction

I. Introduction
CMOS technology feature size and threshold voltage have been
scaling down for decades. Because of this technology trend,
transistor leakage power has increased exponentially. As the
feature size becomes smaller, shorter channel lengths result in
increased sub-threshold leakage current through a transistor when
it is off. Low threshold voltage also results in increased sub-
threshold leakage current because transistors cannot be turned
off completely. For these reasons, static power consumption, i.e.,
leakage power dissipation, has become a significant portion of total
power consumption for current and future silicon technologies.
There are several VLSI techniques to reduce leakage power. Each
technique provides an efficient way to reduce leakage power, but
disadvantages of each technique limit the application of each Fig. 1: Sleep Approach
technique. We propose a new approach, thus providing a new
choice to low-leakage power VLSI designers. Previous techniques
are summarized and compared with our new approach presented
in this paper.

II. Previous Works

We here review previously proposed circuit level approaches for
sub-threshold leakage power reduction.

A. Sleep Transistor Approach

The most well-known traditional approach is the sleep approach
(fig. 1). These sleep transistors turn off the circuit by cutting off
the power rails. By cutting off the power source, this technique
can reduce leakage power effectively. However, the technique
results in destruction of state plus a floating output voltage in
sleep mode.

B. Sleepy Stack Approach

The sleepy stack approach combines the sleep and stack
approaches [3-4] (fig. 2). The sleepy stack technique divides Fig. 2: Sleepy Stack

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IJECT Vol. 4, Issue Spl - 2, Jan - March 2013 ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)

Fig. 5: Dual Stack

Fig. 3: Sleepy Keeper III. Variable Body Biasing Approach

To reduce the leakage current in the sleep mode we ensured that
D. Dual Sleep Approach the body to source voltage of the sleep transistor is increased. To
Dual sleep approach [6] (fig. 4) uses the advantage of using the do that we added a PMOS(M2) and a NMOS (M5) in the previouly
two extra pull-up and two extra pull-down transistors in sleep discussed sleepy keeper circuit (fig. 6). During sleep mode PMOS
mode either in OFF state or in ON state. Since the dual sleep (M2) is OFF so the body to source voltage of the pull up PMOS
portion can be made common to all logic circuitry, less number (M1) is higher than in the active mode. For a turned off single
of transistors is needed to apply a certain logic circuit. transistor leakage current (Isub0) can be expressed as follows:

E. Dual Stack Approach

In dual stack approach [7] (fig. 5), 2 PMOS in the pull-down (1)
network and 2 NMOS in the pull-up network are used. The where swing coefficient, and Vθ is the thermal voltage. Vgs0,
advantage is that NMOS degrades the high logic level while PMOS Vth0, Vsb0 and Vds0 are the gate-to-source voltage, the zero-bias
degrades the low logic level. Compared to previous approaches threshold voltage, the base-to-source voltage and the drain-to-
it requires greater area. The delay is also increased. source voltage, respectively, γ is the body-bias effect coefficient,
and η is the Drain Induced Barrier Lowering (DIBL) coefficient,
µ is zero-bias mobility, Cox is the gate-oxide capacitance, W is the
width of the transistor, and Leff is the effective channel length [8].
From equation (1) we see that leakage current (Isub0) decreases as
Vsb0 increases. As a result of Body effect, Vth also increases which
lowers the performance. During the active mode, the performance
is improved as the PMOS (M2) is ON which makes the Vth of the
pull up PMOS (M1) lower again. The same discussion is applicable
for the pull down NMOS (M4) and NMOS (M5). The remaining
NMOS (M3) and PMOS (M6) works together for retaining the
state in the sleep mode. If the output is high, in the sleep mode,
the NMOS (M3) will keep the output high. Similarly, the PMOS
(M6) will maintain the state in sleep mode if the output is low.

Fig. 4: Dual Sleep

Fig. 6: Variable Body Biasing Approach (Chain of 4 Inverters)

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ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print) IJECT Vol. 4, Issue Spl - 2, Jan - March 2013

IV. Simulation Methodology Table 1: Chosen Technology and VDD Value

We compare the variable body biasing technique with four of the
previous approaches explained earlier namely; sleep transistor,
sleepy stack, dual sleep and dual stack. Thus, we compare five
design approaches in terms of power consumption (dynamic and
static), delay and area. To show that the variable body biasing V. Simulation Results
approach is applicable to general logic design and memory, we We measure static power consumption, dynamic power consumption,
choose a chain of 4 inverters (fig. 6) and a SRAM cell (fig. 7). We propagation delay and area for five design approaches, which are
use HSPICE [8] for simulation purpose to estimate delay and power sleep, sleepy stack, dual sleep, dual stack and variable body biasing
consumption. Area is estimated with the help of MICROWIND. approach. Fig.8 shows the static power consumption, Fig.9 shows
All considered approaches are evaluated for performance by using the dynamic power consumption, Fig.10 shows the propagation
a single, low-Vth for all transistors. Dual Vth technology is applied delay comparison and fig.11 shows area consumed for a chain of
and tested only for the sleep, dual sleep, dual stack and proposed four inverters.
approaches since applying high-Vth. For the dual Vth technique,
high-Vth is used for leakage reduction transistors and low-Vth is
used for the other transistors. The high-Vth is set to have 0.1V
higher Vth than the Vth of a normal transistor (low-Vth).The inverter
chain uses four inverters each with W/L=6 for PMOS and W/L=3
for NMOS for the base case. Sleep transistors used in the pull-up
and pull-down networks of the base case inverter chain have W/
L=6 and W/L=3. The variable body biasing approach transistor
size is shown in fig. 7.

Fig. 8: Static Power Comparison (Chain of 4 Inverters)

Fig. 7: Variable Body Biasing Approach (SRAM Cell)

Fig. 10: Propagation Delay Comparison (Chain of 4 Inverters)

Fig. 9: Dynamic Power Comparison (Chain of 4 Inverters)

The chosen technologies are BSIM4 PTM Model [9] and their
supply voltages are given in Table 1.
Fig. 11: Area Comparison (Chain of 4 Inverters)

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IJECT Vol. 4, Issue Spl - 2, Jan - March 2013 ISSN : 2230-7109 (Online) | ISSN : 2230-9543 (Print)

The static power consumption, dynamic power dissipation, The comparisons of Variable body biasing approach using 65 nm
propagation delay and area consumed for a SRAM cell are shown technology with the existing methods for a chain of four inverters
in fig. 12, fig. 13, fig. 14 and fig. 15, respectively. and for a SRAM cell are summarized in Table II and Table III,
respectively. Here ‘+’ denotes improved and ‘-’ denotes degraded
performance.

Table 2: Comparison of VBB Approach for a Chain of Four

Inverters

Table 3: Comparison of VBB Approach for a SRAM Cell

Fig. 12: Static Power Comparison (SRAM Cell)

Power delay products for a chain of four inverters are 0.34fJ,

0.266fJ and 0.139fJ for dual sleep, dual stack and Variable Body
Biasing, respectively. Therefore, the Variable Body Biasing
approach shows the least power delay product among all.

VI. Conclusion
Miniaturization of CMOS technology achieving high performance
has resulted in increase of leakage power dissipation. We have
presented an efficient methodology for reducing leakage power
in VLSI design. Our Variable Body Biasing approach shows
Fig. 13: Dynamic Power Comparison (SRAM Cell) improved results in terms of static power, dynamic power and
power delay product. It gives the CMOS circuit designers another
option in designing integrated circuits more efficiently.

References
[1] S. Mutoh et al.,“1-V Power Supply High-speed Digit al
Circuit Technology with Multithreshold-Voltage CMOS,”
IEEE Journal of Solis-State Circuits, Vol. 30, No. 8, pp.
847-854, August 1995.
[2] J.C. Park, V. J. Mooney III, P. Pfeiffenberger,“Sleepy Stack
Reduction of Leakage Power”, Proceeding of the Int ernational
Workshop on Power and Timing Modeling, Optimization and
Simulation, pp. 148-158, September 2004.
[3] J. Park,“Sleepy Stack: a New Approach to Low Power VLSI
Fig. 14: Propagation Delay Comparison (SRAM Cell) and Memory”, Ph.D. Dissertation, School of Electrical a
nd Computer Engineering, Georgia Institute of Technology,
2005. [Online]. Available http://etd.gatech.edu/these
[4] M. S. Islam, et al., “Dual Stack Method: A Novel Ap proach
to Low Leakage and Speed Power Product VLSI Design”
Proc. ICECE2010, Dhaka, Bangladesh. 18-20 December
2010, pp. 89-92
[5] [Online] Available: http://www.synopsys.com
[6] [Online] Available: http://www.eas.asu.edu/~ptm

Fig. 15: Area Comparison (SRAM Cell)

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