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A 0.7 V, 2.7 μW, 12.9 ppm/° C over 180° C CMOS subthreshold voltage reference

Article in International Journal of Circuit Theory and Applications · November 2016

DOI: 10.1002/cta.2292

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Int. J. Circ. Theor. Appl. (2016)
Published online in Wiley Online Library ([Link]). DOI: 10.1002/cta.2292

A 0.7 V, 2.7 μW, 12.9 ppm/◦ C over 180◦ C CMOS subthreshold

voltage reference

Charalambos M. Andreou1,2,*,† and Julius Georgiou2

1
Cypress Semiconductors, Cork, Ireland
2
Department of Electrical and Computer Engineering, University House ‘Anastasios G. Leventis’, University of
Cyprus, 1 Panepistimiou Avenue, 2109 Aglanzia, 1678 Nicosia, Cyprus

SUMMARY
An all-CMOS, low-power, wide-temperature-range, curvature-compensated voltage reference is presented.
The proposed topology achieves a measured temperature coefficient of 12.9 ppm/◦ C for a wide temperature
range of 180◦ C (−60 to 120◦ C) at a bias voltage of 0.7 V while consuming a mere 2.7 μW. The high-order
curvature compensation, which leads to a low-temperature sensitivity of the reference voltage, is performed
using a new, simple, but efficient methodology. The non-linearities of an N-type metal-oxide-semiconductor
(NMOS) device operated in subthreshold are combined with the non-linearities of two different kinds of
polysilicon resistors, leading to the improved performance. The extended temperature range of this volt-
age reference gives it an important competitive advantage, especially at lower temperatures, where prior
art designs’ performance deteriorate abruptly. In addition, it utilizes an innovative trimming methodol-
ogy whereby two trimmable resistors enable the tuning of both the overall slope and non-linearities of the
temperature sensitivity. The design was fabricated using TowerJazz Semiconductor’s CMOS 0.18 μm tech-
nology, without using diodes or any external components such as compensating capacitors. It has an area of
0.023 mm2 and is suitable for high-performance power-aware applications as well as applications operating
in extreme temperatures. Copyright © 2016 John Wiley & Sons, Ltd.

Received 25 April 2016; Accepted 19 October 2016

KEY WORDS: bandgap voltage reference; BGR; CMOS analogue integrated circuits; curvature correction;
reference circuits; subthreshold; temperature compensation; low voltage; low power; voltage
reference; wide temperature range

1. INTRODUCTION

High-performance voltage references are sine qua non in most electronic systems because of
the necessity of supplying a temperature and voltage insensitive reference to constituent ana-
logue, digital and mixed-signal circuits, for example, operational amplifiers, sensors, flash mem-
ories, digital analog converters (DACs), filters and regulators. The accuracy and robustness of
the reference voltage will undoubtedly be of major importance if the resolution of the sub-
sequent circuits is to have any significance at the system level. Extending the temperature
range beyond the commercial application range, while sustaining similar temperature coefficient
(TC) performance (especially at low temperatures [1]), becomes extremely challenging. Further-
more, many applications require low-power and low-area voltage references in order to fulfil
the requirements of a wide range of battery-powered, miniaturized applications. Indeed, many
recent digital and VLSI circuits for power-aware applications are designed in the subthreshold
regime, requiring a consistent low-voltage reference voltage for many of their subsequent circuits.

*Correspondence to: Charalambos Andreou, Cypress Semiconductors, Cork, Ireland and Department of Electrical and
Computer Engineering, University of Cyprus, 1 Panepistimiou Avenue, 2109 Aglanzia, 1678 Nicosia, Cyprus.
† E-mail: [Link]@[Link]

Copyright © 2016 John Wiley & Sons, Ltd.

 C. M. ANDREOU AND J. GEORGIOU

Consequently, satisfying all the constraints of modern, high-performance applications is a major

challenge, which in order to be addressed requires new approaches, such as the one proposed.
Conventional voltage reference designs use the temperature dependence of the bipolar transistor’s
pn junction [1–5] to create a proportional to absolute temperature (PTAT) voltage, which is used to
provide a first-order temperature-compensated reference. These designs are limited by the base-emitter
non-linearities at a TC of around 20 ppm/◦ C, over a temperature range of 100◦ C. Alternative pro-
posed topologies provide high-order curvature compensation [6–19] by cancelling part of the nonlinear
dependence of the bipolar junction transistor (BJT) base-emitter voltage, although they require complex
structures with a high power consumption and large area. More recent topologies use the temperature-
dependent threshold voltage of a MOSFET and carrier mobility, to generate a PTAT voltage/current
and a complementary to absolute temperature (CTAT) voltage/current, which are summed in order
to provide a first-order compensated voltage [20–30]. This approach has advantages with respect to
power consumption and digital process compatibility, but suffers from TC performance due to the larger
non-linearities of MOSFETs in comparison to bipolar transistors. Alternative modern approaches are
utilizing a digital-based virtual voltage reference [31], which although promising has a few limitations
in terms of area and power consumption due to signal processing requirements.
In this paper, a voltage reference topology is presented, which achieves high-order, non-linear com-
pensation using only subthreshold CMOS devices and two types of polysilicon resistors (high ohmic
p-type poly resistors and medium ohmic p-type poly resistors). The proposed voltage reference achieves
a reduced reference voltage TC, over a wide temperature range, with a low-supply voltage and power
consumption. The design requires two trimmable resistors in order to overcome post-fabrication devi-
ations in performance. These deviations are caused by the characteristic sensitivity of subthreshold
circuits to process variations and from the variability of the resistors.

2. SUBTHRESHOLD MOSFET OPERATION AND TEMPERATURE DEPENDENCE

The drain-source current of a CMOS transistor, operating in the subthreshold region, depends expo-
nentially on the gate-source voltage and drain-source voltage [32, 33] as
( ) ( ( ))
VGS − VTH VDS
IDS = KI0 exp × 1 − exp − (1)
nUT UT

where K is the transistor size aspect ratio Weff ∕Leff , VTH is the transistor threshold voltage and UT =
kT∕q is the thermal voltage that is temperature-dependent. I0 can be described by

I0 = 𝜇Cox (n − 1)UT2 (2)

where 𝜇 is the mobility of carriers in the device channel, Cox is the oxide capacitance per unit area and
n is the subthreshold slope factor that is expressed as
Cd
n=1+ (3)
Cox

where Cd is the surface depletion capacitance per unit area and is described by
√
N
Cd = q𝜀si CH (4)
2𝜙S

where q is the electron charge, 𝜀si is the silicon permittivity, NCH is the doping concentration of the
channel and ΦS is the surface potential.
The device is considered to be in the saturation region if (5) is valid:
( )
V
1 ≫ exp − DS (5)
UT

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

Inequality (5) is valid approximately when VDS ≥ 4UT [34], thus, IDS in saturation becomes
( )
VGS − VTH
IDS = K𝜇Cox (n − 1)UT2 exp (6)
nUT

One can observe from (6) that the drain-source current temperature dependencies are the thermal volt-
age, the threshold voltage and the mobility. The mobility temperature dependence is approximately
expressed [35] as
( )−m
T
𝜇(T) = 𝜇0 (7)
T0

where 𝜇0 is the mobility at room temperature T0 , T is the absolute temperature and m is the mobil-
ity temperature exponent, which is a technology-dependent constant, ranging between 1.2 and 2. The
threshold voltage and gate-source voltage temperature dependence can be expressed as

VTH (T) = VTH (T0 ) + KT (T − T0 )

(8)
VGS (T) = VGS (T0 ) + KT (T − T0 )

where KT is the threshold voltage temperature coefficient that ranges between −0.5 and −3 mV/◦ C
and depends on the doping level, the oxide thickness and the source-bulk voltage, VSB . An increase
in temperature will increase the drain-source current since the threshold voltage drops; however, this
will concurrently decrease the current as the mobility drops. The overall effect will depend on which
mechanism is dominant at a particular bias point. For low currents, the threshold voltage temperature
dependence dominates, while for high currents, the mobility temperature dependence dominates [35].

3. PROPOSED SUBTHRESHOLD/HETEROGENOUS RESISTOR-BASED METHODOLOGY

AND CORRESPONDING REFERENCE CIRCUIT

The principle of the methodology that was used to improve the TC performance can be explained by
using the simulations shown in Figure 1. The currents, through two different kinds of polysilicon resis-
tors, Figure1(a) and(b), and one subthreshold NMOS transistor, Figure 1(d), are plotted as a function
of temperature, at the voltage that corresponds to the nominal bias point in the proposed circuit.
The high ohmic p-type polysilicon resistor current profile (Irphpoly ) and the medium ohmic p-type
polysilicon resistor current profile (Irpmpoly ), have both, to a certain extent, a complementary non-linear
(NL) behaviour to that of the subthreshold CMOS device, by giving a convex as opposed to a concave
curve. By combining the two resistors in series, it is possible to control the degree of this ‘compli-
mentary’ non-linearity, as shown in Figure 1(c), where the curvature of IR_2,3 is moderately convex,
as opposed to marginally convex in the case of Irphpoly and strongly convex in the case of Irpmpoly . A
similar methodology has been successfully tested with a different circuit topology [23, 30] to the one
presented here. The circuit proposed in this paper has been shown to outperform the measured results
of that particular circuit, while using a simpler and more straightforward methodology and circuit
implementation.
The schematic of the proposed design is illustrated in Figure 2, where standard 0.18𝜇m CMOS
devices were used, with all transistors operating in the subthreshold regime. The topology consists of
three main modules. A PTAT circuit, including the start-up circuit (MPsu1 , MPsu2 , C1 ) [27, 32], is shown
in Figure 2(a), which generates a PTAT current for supplying the module of Figure 2(b). Figure 2(b)
shows the core module, where both the linear and the non-linear compensation predominantly takes
place. The devices dimensions are shown in Table I.
Assuming a , at node X, the current passing through the series resistors R2 and R3 will be marginally
PTAT and moderately convex as illustrated in Figure 1(c). Similarly the current through device MN5
will be strongly PTAT and concave as shown in Figure 1(d). Thus, with a constant bias voltage, the
sum of the two aforementioned currents (i.e. IC ) is strongly PTAT. In order to maintain IC constant,
via the feedback loop, the bias voltage at node X needs to be decreasing with respect to temperature

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

Figure 1. Medium ohmic p-type polysilicon resistors, subthreshold CMOS and high ohmic p-type polysil-
icon resistors were independently biased at a constant voltage and simulated against temperature, where a
complementary non-linear behaviour is revealed. PTAT, proportional to absolute temperature.

(Figure 3), thus transforming the current though the resistors R2 and R3 into a marginally CTAT current
and the current through MN5 into a marginally PTAT current, as shown in Figure 4. Thus, IC is now
approximately constant.
The correct rate of decrease of the voltage at node X, with increasing temperature, is controlled
by various concurrent factors. Firstly, the threshold voltage of MN4 decreases; additionally, the drain
current of MN4 increases linearly with temperature, because of IB_PTAT . However, this is not sufficient
to satisfy the exponential increase in drain current of MN4 arising due to the decrease in threshold
voltage, hence the gate-source voltage of MN4 decreases to accommodate the current IB_PTAT , via the
feedback loop that consists of MN3 , MP4 , MP5 . Finally, the source degeneration resistor R4 is used to
control the rate of the drop of the voltage at node X with temperature. Note that IC is actually adjusted
to be slightly PTAT, so that it can counter the drop in resistance of R5,6 and gives a constant VREF . To

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

Figure 2. Schematic of the proposed voltage reference. (a) Proportional to absolute temperature (PTAT)
circuit including the start-up (MPsu1, MPsu2,C1), (b) core module for implementing the high-order compen-
sation and (c) output stage to supply the reference voltage. CTAT, complementary to absolute temperature.

Table I. Circuit elements’ dimensions of the proposed

voltage reference architecture.

Component Parameter

MPsu1 W = 3 μm, L = 10 μm
MPsu2 W = 2 μm, L = 10 μm
MP1 , MP2 , MP3 W = 12 μm, L = 4 μm
MP4 , MP5 , MP6 W = 20 μm, L = 4 μm
MN1 W = 15 μm, L = 4 μm
MN2 W = 300 μm, L = 4 μm
MN3 W = 8 μm, L = 8 μm
MN4 W = 100 μm, L = 4 μm
MN5 W = 40 μm, L = 4 μm
R1 (rpmpoly) 330 KΩ
R2 (rphpoly), R3 (rpmpoly) 500 KΩ
R4 (rphpoly) 220 KΩ
R5 (rphpoly) 157.5 KΩ
R6 (rpmpoly) 130 KΩ
C1 2 pF
C2 3 pF

better understand the complete compensation mechanism via the feedback loop, one can start from
MN4 . Here, the combination of the PTAT biasing current, the temperature-dependent threshold voltage
and the feedback loop is modifying the gate-source voltage of MN3 with respect to temperature. MN3
in turn controls the current IC through the current mirror (MP4 and MP5 ). IC then controls the voltage
at node X and thus the compensation between ICTAT and IPTAT .
In order to explain the non-linear correction methodology, one can define the ICTAT current as being
composed of a linear IL−CTAT component plus a nonlinear INL−CTAT . Similarly, IPTAT constitutes of linear
IL−PTAT plus non-linear INL−PTAT . Thus, the final reference voltage is dependent on current IC , which is
derived from two currents as shown on Figure 2(b): ICTAT (flowing through resistors R2 , R3 ) and IPTAT
(flowing through transistor MN5 ). The INL−CTAT leads to a convex current profile (Figure1(c)), while the
INL−PTAT leads to a concave current profile (Figure1(d)). By selecting an appropriate ratio between the
two non-linear currents, one can easily optimize the circuit to reduce the non-linear effects, and give a
temperature insensitive output voltage. Recall also that, for a given total resistance (R2 +R3 ), the degree
of convex curvature with respect to temperature, that is, INL−CTAT , can also be adjusted in a continuous
manner to attain a value between each resistor’s temperature coefficients by changing the resistance
contribution of each of R2 , R3 . In the same way, the non-linear temperature coefficient of MN5 can be
modified in a continuous manner by changing the contribution of MN4 source degeneration resistor

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

Figure 3. Simulation of the voltage at node X across temperature.

Figure 4. The current profiles of ICTAT and IPTAT with respect to temperature. A complementary profile is
revealed. PTAT, proportional to absolute temperature; CTAT, complementary to absolute temperature.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

Figure 5. The complementary to absolute temperature (CTAT) and proportional to absolute temperature
(PTAT) currents can be modified in a continuous manner in terms of linear and non-linear shape so as to
achieve an optimum compensation of the reference voltage across temperature.

R4 . This leads to a more accurate compensation current than that used in prior art reference circuits
where the two complementary non-linear currents are superimposed but, however, do not have a way
of independently adjusting the degree of non-linearity from the linear part. This concept is illustrated
in Figure 5.
The reference voltage at the output of the proposed topology in Figure 2 can be expressed as

VREF = IC × R5,6 (9)

where Rx,y = Rx + Ry and the current IC consists of the currents through resistors R2 and R3 , and the
current through the transistor MN5 as

IC = IR2,3 + IMN5 (10)

where (10) can be expanded in the form of

( )
VGS4 + IB_PTAT × R4 VGS5 − VTH
IC = + KMN5 I0 exp (11)
R2,3 nUT
By rearranging (11), we obtain
( )
VGS4 R VGS5 − VTH
IC = + 4 IB_PTAT + KMN5 I0 exp (12)
R2,3 R2,3 nUT
where IB_PTAT is expressed by [32]
( )
UT KMP3 KMP2 × KMN2
IB_PTAT = × ln (13)
R1 KMP2 KMP1 × KMN1

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

KMP3 KMP2
In the proposed design topology, the transistors were sized so as to give KMP2
=1 and KMP1
= 1,
thus simplifying IC to the form
( ) ( )
V R U KMN2 VGS5 − VTH
IC = GS4 + 4 T ln + KMN5 I0 exp (14)
R2,3 R2,3 R1 KMN1 nUT

Finally, by substituting the IC of (14) in (9), the detailed equation for the output reference voltage
value is obtained (without including the temperature as an explicit parameter):
( ) ( )
VGS4 R5,6 R4 R5,6 KMN2 VGS5 − VTH
VREF = + × UT ln + R5,6 KMN5 I0 exp (15)
R2,3 R1 R2,3 KMN1 nUT
⏟⏞⏟⏞⏟ ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟ ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟
𝛾 𝛿 𝜖

From (15), one can observe that the resistors of terms 𝛾 and 𝛿, which are found in both the numerator
and denominator, partially cancel out the effects of resistor process variations. Only in term 𝜖 will
resistor process variations, of R5,6 , fully affect the intended non-linear compensation.
In order to analyse the temperature dependence of the circuit to a first approximation, one initially
assumes ideal resistors and then substitutes terms that have temperature dependence in the remaining
devices, that is, substitute (2), (7) and (8) into (15) and manipulate into the following form:
( )
VGS4 (T0 )R5,6 R5,6 R4 R5,6 k KMN2
VREF = + KT ΔT + × ln
R2,3 R2,3 R1 R2,3 q KMN1
⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟ ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟
𝛾 𝛿T
( )−m ( )2 ( ) (16)
T kT VGS5 (T0 ) − VTH (T0 )
+ R5,6 KMN5 Cox (n − 1) × 𝜇0 exp
T0 q n kTq
⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟
𝜖

The gate-source voltage of transistor MN5 , at room temperature, which appears in segment 𝜖, can
also be expressed as VGS5 (T0 ) = VGS4 (T0 ) + IB_PTAT ∗ R4 .
After extracting the approximate temperature dependence of the proposed topology (assuming ideal
resistors) as described by (16), one can identify the non-linear term 𝜖, which is what needs to be com-
pensated by using the non-linearities of the resistors. Thus the next step is to integrate the resistors’
temperature dependence, in order to achieve the high temperature independence of the proposed circuit.
This essentially relies on the high-order non-linear compensation between the subthreshold NMOS
non-linearities and two types of polysilicon resistors non-linearities.
The temperature dependence of the polysilicon resistors that are used in the proposed topology is
expressed by

Rx (T) = Rx (T0 )(1 + 𝛼ΔT + 𝛽ΔT 2 ) (17)

where 𝛼 and 𝛽 are technology-dependent constants, which are different for each resistor type. One can
obtain a detailed equation for the output voltage VREF that includes explicit temperature parameters by
substituting (17) into (16).
In order to find the sensitivity of VREF to changes in temperature, as a next step, one can replace
the particular technology-dependent constants (𝛼, 𝛽) in (17), for each of the two types of resistors, as
well as the general-dependent and technology-dependent constants for 0.18 μm CMOS technology (e.g.
KT , k, q, n, K, Cox , 𝜇0 , T0 , VTH , VGS , Rx ) in (16). As expected, the derivative of this analytical model,
with respect to temperature, turns out to be very complex, making it worthwhile to use a mathemat-
ical tool, such as MATLAB, to evaluate the solution. After using MATLAB, and after some manual
manipulations, the result was tidied up to give an equation in the form of

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

∑
5
∑
4
c1 − c2 T + c3 T 2 + c7 × T (2n+1) − c8 × T (2n+2)
dVREF n=1 n=1
= [ ]2
dT 3 ( c4 )
c9 T × exp
2
T
c10 − c11 T + c12 T 2 − c13 T 3 + c14 T 4
[ ( 4n+3 ) ( 4n+1 ) ] (18)
( c4 ) ∑
4
∑
4
exp T
× c5_n × T 2 − c6_n × T 2

n=1 n=1
+ [ ]2
3 ( c4 )
c9 T 2 × exp T
c10 − c11 T + c12 T 2 − c13 T 3 + c14 T 4

with cn being constants and T being the reference circuit temperature. The derivative of VREF with
respect to temperature, as shown by (18), gives an analytical expression of the curvature correction of
the proposed voltage reference circuit. The terms T n originate from the resistors’ non-linearity, while
c
the terms exp( Tn ) originate from the subthreshold MOSFETs.
Thus, in order to verify the validity of the full expression for VREF , that is (16), with each R expanded
to the form of (17), we plot this along with its analytical derivative as expressed by (18) using MATLAB.
The resulting plots, of the reference voltage and its derivative with respect to temperature, are shown in
Figure 6. The derived model as is shown in Figure 6 gives a good approximation of the linear (slope) as
well as the non-linear compensation that is performed in the proposed circuit of Figure 2. This model
can be used as an approximate guide to evaluate the effects of different process and design dependent
parameters, such as KT , n, K, Cox , 𝜇0 , VTH , VGS , Rx , on the circuit performance. Rx is particularly
important, because one can identify an optimal trimming strategy.
The combination of two complementary high-order non-linear curvature corrections, multiplied
across temperature, results in a higher order non-linear compensation, which leads to an improved tem-
perature stability over a wider temperature range. By changing the values of the resistors R2 and R4 in
this model, one can effectively trim the linear (slope) as well as the non-linear shape of the reference
voltage of Figure 6. By proper sizing of the resistance ratios, the optimum TC of the reference volt-
age can be achieved. The strategy for optimum sizing of R2 and R4 during the design phase as well
as for post-fabrication trimming is explained in details in the following section with the support of
Cadence simulations.

Figure 6. Modelling of the non-linear behaviour of the proposed voltage reference circuit. The figure was
obtained by plotting the derived analytical model of the circuit and its analytical derivative across temperature
using MATLAB.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

4. TRIMMING METHODOLOGY

While operating in the subthreshold region, process variations can affect the performance of the
fabricated integrated circuits. Thus, resistor trimming may be required to ensure that the desired per-
formance is maintained after fabrication. In this paper, we propose a new trimming methodology that
has essential advantages compared with prior art. The developed trimming method is very simple and
efficient, because with only two trimmable resistors, one can correct four different out-of-spec sce-
narios. Through extensive Monte Carlo simulations and corner simulations, it was found that resistors
R2 (nominally 500 KΩ) and R4 (nominally 220 KΩ) can adequately restore the pre-fabrication perfor-
mance of the circuit with three trimming bits, giving R2 ± 12.8% and R4 ± 14.5% in eight discrete
steps respectively.
The four different scenarios of the reference voltage deviation are demonstrated through Cadence
simulations in Figure 7. In Figure 7(a), the reference voltage average slope is not zero, as one would
expect from a constant reference voltage with respect to temperature. It exhibits a positive slope (PS)
or a negative slope (NS). In example VREF (PS), the current drawn by transistor MN5 (IPTAT ) dominates
that drawn by resistors R2 and R3 (ICTAT ), while, conversely, in example VREF (NS), the current drawn
by the resistors R2 and R3 (ICTAT ) dominates that drawn by MN5 (IPTAT ). The non-linearities in these
examples are small, because of optimal non-linearity compensation. In Figure 7(b), the PTAT and CTAT
currents are optimally balanced; however, the non-linearity compensation is not optimal. Therefore, the
reference voltage can exhibit convex non-linearities when the resistors dominate (RD) or concave non-
linearities when the NMOS dominate (ND). For example ,VREF (RD) indicates that the poly-Si resistors’
(R2 and R3 ) non-linearities (convex) dominate the non-linearities (concave) of devices MN4 and MN5 .
Similarly, in example VREF (ND) , the non-linearities (concave) of devices MN4 and MN5 dominate the
non-linearities (convex) of R2 and R3 .
Although, there are multiple candidate resistors for the trimming strategy, we selected two resistors
that can effect both the trimming of the PTAT, in relation to the CTAT (R2 ), and the trimming of the
relative non-linearity (concave versus convex). A clear and detailed strategy of trimming is shown in
Table II. With 22 combinations of the two resistors, all four aforementioned scenarios have a counter
measure for optimizing the performance. Once produced, a chip requires a full temperature sweep to
identify its untrimmed performance characteristics and which correction measures should be taken to

Figure 7. Simulations of the four different cases that can deviate the temperature coefficient (TC) of the ref-
erence voltage from the optimum value. All four cases have countermeasures with the proposed trimming
method of Table II. (a) Two extreme cases that may be encountered after manufacturing, related to the average
TC slope. One extreme, overall-negative slope (NS) and one extreme, overall-positive slope (PS). (b) Devi-
ations of the non-linearities influencing the TC of the reference voltage (resistor non-linearities dominate
(RD) and NMOS non-linearities dominate(ND)).

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

Table II. Strategy for post-layout tuning

and post-fabricated trimming.

Case Correction strategy

VREF_ND R2 ↓ & R4 ↑
VREF_RD R 2 ↑ & R4 ↓
VREF_NS R2 ↑ & R4 ↑
VREF_PS R2 ↓ & R4 ↓
ND, NMOS dominate; RD, resistors domi-
nate; NS, negative slope; PS, positive slope.

Figure 8. Settling times of the reference voltage for different ramp-up times of the supply voltage.

Figure 9. Monte Carlo process and mismatch simulations of the settling times of the reference voltage during
start-up. The slowest and fastest ramp-up times of the supply voltage of Figure 8 are chosen for this anal-
ysis. (a) Settling time for supply voltage ramp-up of 15 ns and (b) settling time for supply voltage ramp-up
of 200μs.

restore it, if necessary. This trimming strategy, using resistors R2 and R4 , was also successfully verified
using the analytical mathematical model that was previously derived. This is important because an
analytical model can support an automated trimming methodology, where the particular run device
parameters, extracted from wafer test structures, can be used along with the reference measurements
to accurately determine the required trim parameters.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

5. SIMULATIONS RESULTS

The proposed topology of Figure 2 was simulated in Cadence using CMOS 0.18 μm technology. The
Cadence simulations of Figure 8 demonstrate the start-up robustness of the circuit under different supply
ramp-up times. The circuit start-up was also tested against process and mismatch variations. The Monte
Carlo results for a faster and slower ramp-up time are presented in Figure 9. For 15 ns of supply voltage
ramp-up, the reference voltage mean settling time is 59.39 μs with a sigma of 0.982 μs. For 200 μs of
supply voltage ramp-up time, the mean settling time is 27.8 μs with a sigma of 1.63 μs. After the circuit
settles, the turn-off current of the transistor MPsu1 is below 1 fA, while the turn-off current of MPsu2
is 649 fA.
The simulation results of the reference voltage across temperature are presented in Figure 10. The TC
is 2.5 ppm∕◦ C across a temperature range of −32 to 125o C, with a bias of 0.7 V. The simulated results

Figure 10. Simulated temperature coefficient (TC) of the voltage reference output. TC performance is
2.5 ppm∕◦ C while biased at 0.7 V.

Figure 11. Cadence Monte Carlo simulation (process and mismatch) of the reference voltage across a
temperature range of −32 to 125◦ C .

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

reveal the non-linear compensation with its characteristic shape, which is in line with the analytical
model plotted in Figure 6.
The proposed circuit was simulated for process and mismatch variations across a temperature range
of −32 to 125◦ C using Cadence’s Monte Carlo analysis. The histogram of the reference voltage distri-
bution is shown in Figure 11, where the mean value is 299 mV and the sigma is 8.9 mV. The distribution
of the TC is shown in Figure 12, where the untrimmed mean TC amounts to 31.2 ppm∕◦ C and the sigma
is 21.32 ppm∕◦ C. The curves of the process and mismatch variations across temperature are shown in
Figure 13. The circuit is sensitive to process variations because of the resistors and the fact that the
transistors are biased in subthreshold. Therefore, resistor trimming is required in the post-fabricated
circuits in order to achieve comparable results with the simulated ones. However, even without trim-
ming, most samples (approximately 85%) are below 40 ppm∕◦ C, which although not exceptional are
still sufficient for most applications, especially considering the extended temperature range. The family

Figure 12. Cadence Monte Carlo simulation (process and mismatch) of the untrimmed temperature coeffi-
cient of the reference voltage across a temperature range of −32 to 125◦ C .

Figure 13. Cadence Monte Carlo simulation (process and mismatch) of the untrimmed curves of the
reference voltage across a temperature range of −32 to 125◦ C .

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

of curves of the process and mismatch simulations, shown in Figure 13, reveals that the curves that
deviate the most from the target reference voltage are the ones that also have the highest deviation
in terms of TC. On the other hand, the curves in the middle of the range (around 300 mV) have
the smallest deviation in terms of the TC. This links the results of Figure 13 with the results of
Figures 11 and 12, where the corners of the reference voltage along with the highest TC are due
to a concurrent combination of the corners of mismatch, process variations and temperature corners
(i.e. −32 or 125◦ C) .

6. EXPERIMENTAL RESULTS

The proposed voltage reference of Figure 2 was fabricated in a commercially available CMOS 0.18 μm
semiconductor technology, provided by TowerJazz Ltd., with the devices sized as shown in Table I. Nine
fabricated chips were extensively measured and characterized. The measurements were performed with
a Keithley 4200 semiconductor characterization system and an Espec SU-261 temperature chamber.
The untrimmed as well as the post-trimmed measured performance of the nine chips, at a supply voltage
of 0.7 V, is presented in Table III, where the trimmed TC ranges between 12.9 and 23.4 ppm/◦ C. The
absolute value of the measured reference voltage varies between 295 to 309 mV.

Table III. Measured temperature coefficient

(TC) of nine samples with bias voltage of
0.7 V for a temperature range of 180◦ C
(−60 to 120◦ C).

Untrimmed TC Trimmed TC
Sample (ppm∕◦ C) (ppm∕◦ C)

1 43.8 23.4
2 39.1 21.3
3 34.5 20.7
4 34.7 19.0
5 31.2 17.2
6 27 14.8
7 25.4 14.1
8 29.5 13.5
9 23 12.9

Figure 14. Measured temperature coefficient of 12.9 ppm∕◦ C of the proposed reference circuit over a
temperature range of 180◦ C (−60 to 120◦ C) while biased at 0.7 V.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

The topology can operate reliably for a wide range of bias voltages that are between 0.7 and 1.8 V.
The TC was measured using the box method and is presented in Figure 14, where the proposed voltage
reference achieves a TC of 12.9 ppm∕◦ C over a wide temperature range of 180◦ C (−60 to 120◦ C), at
a bias voltage of 0.7 V. The trimming requirements for the results that are presented in Table III varied
between 3 and 7 out of the 8 trimming points. The proposed trimming method allows for even better
TC performance than 12.9 ppm∕◦ C, at the expense of narrowing the temperature range to commercial
specifications (0 to 85◦ C). The measured TC is higher than the simulated one because of mismatch
and process variations, as well as the precision limitations of the trimming mechanism for correcting
the reference voltage. Higher precision on the trimming network can be achieved by more fine resistor
steps in the cost of more silicon area. In addition, it is usual that the technology process models are
not well optimized for the MOS subthreshold region and for low temperatures. This is an additional
explanation for the difference between simulation results and experimental measurements, especially in

Figure 15. Measured and simulated power supply rejection ratio (PSRR) of the proposed topology with
different biased voltages at 27◦ C.

Figure 16. Measured noise spectrum of the proposed topology biased at 0.7 V for −60, 27 and 125◦ C.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 Table IV. Comparison of the proposed voltage reference with prior art.

Copyright © 2016 John Wiley & Sons, Ltd.

Parameter [2] [26] [18] [36] [37] [38] [39] Proposed

Year reported 2010 2011 2014 2012 2011 2013 2013 2015
VDD (V) 2.8 0.45 to 2 1.2 0.75 to 1.6 1.85 to 4.5 0.7 to 1.8 0.7 to 1.8
Power (μW) 138.6 0.00315 at 0.7 V 43.2 0.17 48 120.25 0.0525 2.7 at 0.7V
VREF (mV) 650 263.5 767 256 487.6 905.5 548 302
Temperature coefficient (ppm/◦ C) 10.4 142 3.4 40 8.9 14.8 114 12.9 at 0.7V
Temperature 100 125 160 105 150 100 160 180
Range (◦ C) 0 to 100 0 to 125 −40 to 120 −20 to 85 −40 to 110 0 to 100 −40 to 120 −60 to 120
Chip area (mm2 ) 0.011 0.0430 0.036 0.07 0.096 0.01 0.0246 0.023
CMOS technology (μm) 0.25 0.18 0.18 0.13 0.5 0.35 0.18 0.18
C. M. ANDREOU AND J. GEORGIOU

DOI: 10.1002/cta
Int. J. Circ. Theor. Appl. (2016)
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

low-temperature range, where the TC curve slope does not switch to an NS, as shown by the simulated
results. Despite these limitations, the proposed topology achieved competitive results in terms of TC
in the widest temperature range compared with the state-of-the-art.
The measured and simulated power supply rejection ratio (PSRR) at 27◦ C is presented in Figure 15. It
is around 28 dB for bias voltage of 0.7 V, and it increases for higher supply voltages. Although the PSRR
is not optimal, when compared with prior art designs, it can be significantly improved by regulating the
available supply via an low-dropout (LDO) regulator at the global level to protect all the subthreshold
circuits. In addition, techniques that utilize a cascode transistors in series with the power supply for
improving power-supply noise attenuation (PSNA) [40] can be applied to the circuit at the expense
of minimum operating voltage, which would require an additional 125 mV of voltage headroom. The
PSRR drops substantially for supply variation frequencies higher than 1 kHz. This can be explained by
the coupling of the supply rail to the output via transistor MP6 (ac path).
The measured noise power spectral density, at −60, 27 and at 125◦ C is presented in Figure 16. The
total root-mean-square voltage noise measured at the output, at room temperature, between 0.1 and
50 Hz is 59 μV without any external capacitors. Thus the total noise is well below the temperature-
induced variations of reference voltage. Although not necessary, the addition of a load capacitor at the
output can further improve the noise performance. The 1/f corner extracted from Figure 16 is approx-
imately at 3 Hz. The subthreshold noise in the MOSFET are basically contributed by shot noise and
flicker, and the noise power density SID is given by [41, 42]
KID2 1
SID = 2qID + 2 f
(19)
WLCox
where q is the electron charge, ID is the transistor drain-source current, K is a process-dependent param-
eter, W and L are the channel width and length, respectively, Cox is the oxide thickness and f is the
frequency. Hence, equalling the two components of the aforementioned equation, one can derive the
noise corner frequency:
KID
fC = 2
(20)
2qWLCox

The device area to be taken into account is of MP6 whose dimensions are W = 20μm, L = 4μm.
The process-dependent constants are Cox = 1.08 × 10−2 F/m2 and K = 4 × 10−26 F2 /m2 for a 0.18-μm

Figure 17. Microphotograph of the proposed voltage reference.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

process [43] and q = 1.6 × 10−19 C, while the current through MP6 is ID =1 μA. This results in fc =
13.4 Hz, which is very close to the observed measured value (Figure 16), which is around 3 Hz. The
difference can be easily justified from the parasitic capacitance of the measuring equipment.
The power consumption at room temperature with a bias of 0.7 V is 2.7 μW, and the chip area is
0.023 mm2 . The topology did not exhibit any start-up problems, in any bias point within the supply
range, in both simulations and actual measurements. A performance summary and a comparison of this
topology with prior art is presented in Table IV, and the microphotograph is shown in Figure 17.

7. CONCLUSION

A low-power, low-voltage, all-CMOS, wide-temperature-range, voltage reference topology is pre-

sented. The proposed circuit is simple to design and demonstrates the feasibility of designing circuits
in subthreshold for power-aware applications, while maintaining a competitive performance for a wide
temperature range. The performance is maintained even at the extremely low temperature of −60◦ C,
unlike other prior art CMOS voltage reference designs. The key factor that limits performance of
voltage references, that is, device non-linearities, was eliminated via a straightforward and effective
methodology, where resistors, of different temperature coefficent, are combined with the temperature
dependence of a CMOS subthreshold device. The all-CMOS design, which does not require exter-
nal capacitors, allows an on-chip implementation that minimizes the cost and size of the system. The
proposed straightforward trimming method can compensate the reference voltage average slope and
non-linear variations. The presented design and methodologies were successfully verified through an
analytical model, Cadence simulations and through multiple measured results. The proposed volt-
age reference is suitable for power-aware applications as well as applications operating in extreme
temperatures, such as those found in the military, automotive (Grade 0) and space.

ACKNOWLEDGEMENT
This work was supported by the European Union SkyFlash Project 262890 FP7-SPACE-2010-1
(SPA.2010.2.2-01 Space technologies).

REFERENCES
1. Tsividis YP. Accurate analysis of temperature effects in Ic −Vbe characteristics with application to bandgap reference
sources. IEEE Journal of Solid-State Circuits 1980; 15(6):1076–1084. DOI: 10.1109/JSSC.1980.1051519.
2. Indika UKBA, Okura S, Ido T, Taniguchi K. An area-efficient CMOS bandgap reference utilizing a switched-
current technique. IEEE Transactions on Circuits and Systems II, Express Briefs 2010; 57(10):762–766. DOI:
10.1109/TCSII.2010.2058593.
3. Banba H, Shiga H, Umezawa A, Miyaba T, Tanzawa T, Atsumi S, Sakui K. A CMOS bandgap reference circuit with
sub-1-V operation. IEEE Journal of Solid-State Circuits 1999; 34(5):670–674. DOI: 10.1109/4.760378.
4. Bendali A, Audet Y. A 1-V CMOS current reference with temperature and process compensation. IEEE Transactions
on Circuits and Systems I, Regular Papers 2007; 54(7):1424–1429. DOI: 10.1109/TCSI.2007.900176.
5. Bohannon E, Washburn C, Mukund PR. 1.2-V: An ultra-thin oxide sub-1 V CMOS bandgap voltage reference.
International Journal of Circuit Theory and Applications 2014; 42(8):842–857. DOI: 10.1002/cta.1892.
6. Tsitouras A, Plessas F, Birbas M, Kikidis J, Kalivas G. A sub-1V supply CMOS voltage reference generator.
International Journal of Circuit Theory and Applications 2012; 40(8):745–758. DOI: 10.1002/cta.753.
7. Geng J, Zhao Y, Zhao H. A high-order curvature-corrected CMOS bandgap voltage reference with constant current
technique. International Journal of Circuit Theory and Applications 2014; 42(1):43–52. DOI: 10.1002/cta.1836.
8. Liang C-J, Chung C-C, Lin H. A low-voltage band-gap reference circuit with second-order analyses. International
Journal of Circuit Theory and Applications 2011; 39(12):1247–1256. DOI: 10.1002/cta.699.
9. Lee KK, Lande TS, Hafliger PD. A sub-𝜇w bandgap reference circuit with an inherent curvature-
compensation property. IEEE Transactions on Circuits and Systems I, Regular Papers 2015; 62(1):1–9. DOI:
10.1109/TCSI.2014.2340553.
10. Duan Q, Roh J. A 1.2-V 4.2-ppm/◦ C high-order curvature-compensated CMOS bandgap reference. IEEE Transac-
tions on Circuits and Systems I, Regular Papers 2015; 62(3):662–670. DOI: 10.1109/TCSI.2014.2374832.
11. Zhou Z-K, Zhu P-S, Shi Y, Wang H-Y, Ma Y-Q, Xu X-Z, Tan L, Ming X, Zhang B. A CMOS voltage reference
based on mutual compensation of Vtn and Vtp. IEEE Transactions on Circuits and Systems II, Express Briefs 2012;
59(6):341–345. DOI: 10.1109/TCSII.2012.2195065.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 LOW-POWER, CURVATURE-COMPENSATED, CMOS SUBTHRESHOLD VOLTAGE REFERENCE

12. Leung KN, Mok PKT, Leung CY. A 2-V 23-𝜇A 5.3-ppm/◦ C curvature-compensated CMOS bandgap voltage
reference. IEEE Journal of Solid-State Circuits 2003; 38(3):561–564. DOI: 10.1109/JSSC.2002.808328.
13. Malcovati P, Maloberti F, Fiocchi C, Pruzzi M. Curvature-compensated BiCMOS bandgap with 1-V supply voltage.
IEEE Journal of Solid-State Circuits 2001; 36(7):1076–1081. DOI: 10.1109/4.933463.
14. Andreou CM, Koudounas S, Georgiou J. A novel wide-temperature-range, 3.9ppm/◦ C CMOS bandgap reference
circuit. IEEE Journal of Solid-State Circuits 2012; 47(2):574–581. DOI: 10.1109/JSSC.2011.2173267.
15. Rincon-Mora GA, Allen PE. A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference.
IEEE Journal of Solid-State Circuits 1998; 33(10):1551–1554. DOI: 10.1109/4.720402.
16. Ming X, Ma Y-Q, Zhou Z-K, Zhang B. A high-precision compensated CMOS bandgap voltage reference
without resistors. IEEE Transactions on Circuits and Systems II, Express Briefs 2010; 57(10):767–771. DOI:
10.1109/TCSII.2010.2067770.
17. Rincon-Mora GA. Voltage References: From Diodes to Precision High-Order Bandgap Circuits. Wiley-IEEE Press:
New York, 2001.
18. Ma B, Yu F. A novel 1.2V 4.5-ppm∕◦ C curvature-compensated CMOS bandgap reference. IEEE Transactions on
Circuits and Systems I, Regular Papers 2014; 61(4):1026–1035. DOI: 10.1109/TCSI.2013.2286032.
19. Basyurt PB, Aksin DY. Untrimmed 6.2 ppm/◦ C bulk-isolated curvature-corrected bandgap voltage reference. Inte-
gration, the VLSI Journal 2014; 47(1):30–37. DOI: 10.1016/[Link].2013.03.005.
20. Palaniappan A, Maurath D, Kalathiparambil F, Siek L. A higher order curvature corrected 2 ppm/◦ C CMOS voltage
reference circuit. Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), 2015; 505–508.
21. Basyurt PB, Bonizzoni E, Aksin DY, Maloberti F. Voltage reference architectures for low-supply-voltage low-power
applications. Microelectronics Journal 2015; 46(11):1012–1019. DOI: 10.1016/[Link].2015.08.005.
22. De Vita G, Iannaccone GA. Sub-1-V, 10 ppm∕◦ C, nanopower voltage reference generator. IEEE Journal of Solid-
State Circuits 2007; 42(7):1536–1542. DOI: 10.1109/JSSC.2007.899077.
23. Andreou CM, Georgiou J. An all-subthreshold, 0.75 V supply, 2 ppm/◦ C, CMOS voltage reference. Proceedings
of IEEE International Symposium on Circuits and Systems (ISCAS): Beijing, China, 2013; 1476–1479. DOI:
10.1109/ISCAS.2013.6572136.
24. Albano D, Crupi F, Cucchi F, Iannaccone G. A picopower temperature-compensated, subthreshold CMOS
voltage reference. International Journal of Circuit Theory and Applications 2014; 42(12):1306–1318. DOI:
10.1002/cta.1925.
25. Albano D, Crupi F, Cucchi F, Iannaccone G. A sub-kT/q voltage reference operating at 150 mV. IEEE Transactions
on VLSI Systems 2014; 23(8):1547–1551. DOI: 10.1109/TVLSI.2014.2340576.
26. Magnelli L, Crupi F, Corsonello P, Pace C, Iannaccone G. A 2.6 nW, 0.45 V temperature-compensated
subthreshold CMOS voltage reference. IEEE Journal of Solid-State Circuits 2011; 46(2):465–474. DOI:
10.1109/JSSC.2010.2092997.
27. Giustolisi G, Palumbo G, Criscione M, Cutri F. A low-voltage low-power voltage reference based on subthreshold
MOSFETs. IEEE Journal of Solid-State Circuits 2003; 38(1):151–154. DOI: 10.1109/JSSC.2002.806266.
28. Ueno K, Hirose T, Asai T, Amemiya Y. A 300 nW, 15 ppm/◦ C, 20 ppm/V CMOS voltage reference cir-
cuit consisting of subthreshold MOSFETs. IEEE Journal of Solid-State Circuits 2009; 44(7):2047–2054. DOI:
10.1109/JSSC.2009.2021922.
29. Seok M, Kim G, Blaauw D, Sylvester D. A portable 2-transistor picowatt temperature-compensated voltage refer-
ence operating at 0.5 V. IEEE Journal of Solid-State Circuits 2012; 47(10):2534–2545. DOI: 10.1109/JSSC.2012.
2206683.
30. Andreou CM, Georgiou J. A 0.75-V, 4-𝜇W, 15-ppm/◦ C, 190◦ C temperature range, voltage reference. International
Journal of Circuit Theory and Applications 2016; 44(5):1029–1038. DOI: 10.1002/cta.2122.
31. Crovetti P. A digital-based virtual voltage reference. IEEE Transactions on Circuits and Systems I, Regular Papers
2015; 62(5):1315–1324. DOI: 10.1109/TCSI.2015.2402991.
32. Vittoz E, Fellrath J. CMOS analog integrated circuits based on weak inversion operations. IEEE Journal of Solid-State
Circuits 1977; 12(3):224–231. DOI: 10.1109/JSSC.1977.1050882.
33. Razavi B. Design of Analog CMOS Integrated Circuits. McGraw-Hill: USA, 2002.
34. MOSFET operation in weak and moderate inversion (the MOS transistor in weak inversion). Available: [Link]
[Link]/harrison/ece5720/[Link] [Online].
35. Tsividis Y, McAndrew C. Operation and Modelling of the MOS Transistor, 3rd edition. Oxford Series in Electrical
and Computer Engineering: USA, 2010.
36. Ivanov V, Brederlow R, Gerber J. An ultra low power bandgap operational at supply from 0.75 V. IEEE Journal of
Solid-State Circuits 2012; 47(7):1515–1523. DOI: 10.1109/JSSC.2012.2191192.
37. Li JH, Xing-bao Z, Ming-yan Y. A 1.2-V piecewise curvature-corrected bandgap reference in 0.5 𝜇m CMOS
process. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2011; 19(6):1118–1122. DOI:
10.1109/TVLSI.2010.2045519.
38. Zhou Z-K, Zhu P-S, Shi Y, Qu X, Wang H-Y, Zhang X-M, Qiu S, Li N, Gou C, Wang Z, Zhang B. A resistorless
CMOS voltage reference based on mutual compensation of VT and VTH . IEEE Transactions on Circuits and Systems
II, Express Briefs 2013; 60(9):582–586. DOI: 10.1109/TCSII.2013.2268639.
39. Osaki Y, Hirose T, Kuroki N, Numa M. 1.2-V Supply, 100-nW, 1.09-V bandgap and 0.7-V supply, 52.5-nW,
0.55-V subbandgap reference circuits for nanowatt CMOS LSIs. IEEE Journal of Solid-State Circuits 2013; 48(6):
1530–1538. DOI: 10.1109/JSSC.2013.2252523.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
DOI: 10.1002/cta
 C. M. ANDREOU AND J. GEORGIOU

40. Giustolisi G, Palumbo G. A detailed analysis of power-supply noise attenuation in bandgap voltage references. IEEE
Transactions on Circuits and Systems-I 2003; 50(2):185–197. DOI: 10.1109/TCSI.2002.808188.
41. Sarpeshkar R, Delbruck T, Mead C. White noise in mos transistors and resistors. IEEE Circuits and Devices Magazine
1993; 9(6):23–29. DOI: 10.1109/101.261888.
42. Linares-Barranco B, Serrano-Gotarredona T. On the design and characterization of femtoampere current-mode
circuits. IEEE Journal of Solid-State Circuits 2003; 38(8):1353–1363. DOI: 10.1109/JSSC.2003.814415.
43. Zhang L, Yu Z, He X. Design and implementation of ultralow current-mode amplifier for biosensor applications. IEEE
Transactions on Circuits and Systems II, Express Briefs 2009; 56(7):540–544. DOI: 10.1109/TCSII.2009.2022206.

Copyright © 2016 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2016)
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