Chapter 3
Combinational Logic
circuits
Designing method
Consider the statements of the problem.
Define the inputs and outputs
The inputs are considered the variables.
The outputs are considered functions
Draw the block diagram of the circuit
Write the Truth Table to express the relationship
between the inputs and outputs so that the requirements
of the problem are met.
The Truth Table consists of 2n binary combinations for n
inputs. The outputs’ binary values are defined based on
the statements of problem.
+ If the inputs’ binary combinations are valid
The output will be “0” or “1”.
+ If the inputs’ binary combinations are not mentioned
(or do not happen)
The output is considered “don’t care” case.
Define the Boolean functions simplified for the output
functions
The output’s Boolean functions are defined from the
Truth Table by algebraic methods or K-map.
Draw the logic diagrams.
Example
Given a function F with 4 inputs. The function F=1 if the
number of inputs “1” is greater than or equal to the
number of inputs “0”. Otherwise, F=0.
a. Represent the function F in K-map.
b. Simplify the function F and draw the circuit using
only NAND gates.
Example
Given a combinational circuit having the operation as
in the table below.
E X1 X0 Y0 Y1 Y2 Y3
1 X X 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 0
0 1 1 0 0 0 1
a. Design this circuit using logic gates.
b. Using the combinational circuit designed in question a (drawn in the
Block diagram) and logic gates to implement the Boolean function
F(A,B,C) = (4,6)
We can use common MSI chips such as:
Decoder/Encoder.
Multiplexer- MUX.
Demultiplexer- DEMUX.
Adder, …
to implement a combinational logic circuit.
Combinational logic circuits
1. Decoder:
The most common decoder is binary decoder.
+ It has n inputs, 2n outputs.
+ There are enable inputs.
When all enable inputs are active, decoder starts operation.
Only one of 2n outputs are active at one time.
The active output is the output whose index is defined from
the inputs’ binary combinations.
Example:
Consider the decoder 2 to 4, high active outputs.
Circuit diagram:
Example:
Consider the decoder 2 to 4, low active outputs.
Circuit diagram:
Example:
Consider the decoder 2 to 4, low active
outputs, 1 low active enable input.
Circuit diagram:
Combinational logic circuits
74LS139 consists 2 decoders 2 to 4
Combinational logic circuits
74LS138: decoder 3 to 8
Combinational logic circuits
Truth Table of 74LS138
Combinational logic circuits
Two decoders n to 2n can be connected together to create a
decoder (n+1) to 2n+1.
Combinational logic circuits
Each output of the decoder n to 2n (high active output) is a
n-variable minterm.
If the output is low active, each output is a maxterm
A decoder n to 2n connecting to logic gates can be used
to implement one or n-variable Boolean function.
Combinational logic circuits
Example:
Using 74LS138 and logic gates to implement the
following functions
Combinational logic circuits
Combinational logic circuits
Combinational logic circuits
Example: Using 74LS138 and logic gates to implement
the following functions
Combinational logic circuits
2. Encoder:
Comparing with decoder, it operates reversely .
Has 2n (or less) inputs and n outputs.
Among 2n inputs, there is only one active input at one
time. The index of the active input defines the output’s
binary combinations.
Combinational logic circuits
Example:
Consider the encoder 4 to 2.
Combinational logic circuits
Circuit diagram
Combinational logic circuits
Priority encoder:
is the encoder having the priority property.
In case of having 2 or more inputs are active at the
same time, the input having the most priority will impact
on the output
Combinational logic circuits
Priority encoder 4 to 2: priority order is increased from x3
to x0
Combinational logic circuits
Circuit diagram:
Combinational logic circuits
74LS148: priority encoder 8 to 3
74LS148
Chapter 3
Combinational Logic
circuits
Multiplexer
Multiplexer:
2n inputs, 1 output and n control inputs
(or selected inputs)
At one time, one output is connected to one input, the
index of which is defined by n-bit binary number
(created by n control inputs)
Multiplexer
Multiplexer 4 to 1
Block diagram Truth Table Output functions
Multiplexer
Circuit diagram:
Multiplexer
Generally :
The output function of MUX 2n to 1 is:
whereas
mi is the ith minterm
Di is the ith input
Multiplexer
74LS157: consists 4 multiplexers 2 to 1
Multiplexer
74LS153: consists 2 multiplexers 4 to 1
Multiplexer
74LS151: multiplexer 8 to 1
Using MUX
to implement the Boolean function
A MUX 2n to 1 can be used to implement a n-variable
(or (n+1)-variable) Boolean function.
a. Using MUX 2n to 1 to implement n-variable Boolean function.
b. Using MUX 2n to1 to implement m-variable Boolean function, m>n.
Using MUX to implement the
n-variable Boolean function
The output function of MUX 2n to 1 is:
The general form of a n-variable Boole is:
Using MUX to implement the
n-variable Boolean function
F can be produced from the output Y of MUX by
connecting n variables of Boolean function to n control
inputs of MUX. This is done by:
+ connecting 0 (similar to ground)
+ connecting 1 (similar to the source)
to inputs (Di) corresponding to values of function (Fi)
Using MUX to implement the
n-variable Boolean function
Example:
Using MUX to implement the
n-variable Boolean function
Using MUX to implement the
(n+1)-variable Boolean function
Connect any n variables of Boolean function to n
control inputs of MUX.
The left variable is connected to some of 2n data inputs.
Find the relation of the left variable, the output
(the Boolean function) and the data inputs to implement the
circuit.
Using MUX to implement the
(n+1)-variable Boolean function
Example:
Using 74LS153 to implement the function
Connect X,Y to control inputs, Z to some of data inputs
x y z f Y
0 0 0 1 C0
f = C0 = 1
0 0 1 1 C0
0 1 0 0 C1
f = C1 = 0
0 1 1 0 C1
1 0 0 0 C2
f = C2 = Z
1 0 1 1 C2
1 1 0 1 C3
f = C3 = Z’
1 1 1 0 C3
Using MUX to implement the
(n+1)-variable Boolean function
Connect Y,Z to control inputs, X to some of data inputs
x y z f Y
0 0 0 1 C0 f = C0 = X’
0 0 1 1 C1 f = C1 = 1
0 1 0 0 C2 f = C2 = X
0 1 1 0 C3 f = C3 = 0
1 0 0 0 C0
1 0 1 1 C1
1 1 0 1 C2
1 1 1 0 C3
Using MUX to implement the
(n+1)-variable Boolean function
Using MUX to implement the
(n+1)-variable Boolean function
Example:
Using 74LS151 to implement the function
Connect D, C, B to control inputs, A to some of data inputs
D C B A f Y
0 0 0 0 1 D0
0 0 0 1 1 D0
f = D0 = 1
0 0 1 0 0 D1
0 0 1 1 0 D1
f = D1 = 0
0 1 0 0 1 D2
f = D2 = A’
0 1 0 1 0 D2
0 1 1 0 0 D3
0 1 1 1 1 D3
f = D3 = A
1 0 0 0 0 D4
f = D4 = 0
1 0 0 1 0 D4
1 0 1 0 0 D5
f = D5 = 0
1 0 1 1 0 D5
1 1 0 0 0 D6
1 1 0 1 0 D6
f = D6 = 0
1 1 1 0 0 D7
f = D7 = 0
1 1 1 1 0 D7
Using MUX to implement the
(n+1)-variable Boolean function
D0=1
D1=0
D2=A’
D3=A
D4=0
D5=0
D6=0
D7=0
Connect C,B,A to control inputs, D to some of data inputs
D C B A f Y
0 0 0 0 1 D0 f = D0 = D’
0 0 0 1 1 D1 f = D1 = D’
0 0 1 0 0 D2 f = D2 = 0
0 0 1 1 0 D3 f = D3 = 0
0 1 0 0 1 D4 f = D4 = D’
0 1 0 1 0 D5 f = D5 = 0
0 1 1 0 0 D6 f = D6 = 0
0 1 1 1 1 D7 f = D7 = D’
1 0 0 0 0 D0
1 0 0 1 0 D1
1 0 1 0 0 D2
1 0 1 1 0 D3
1 1 0 0 0 D4
1 1 0 1 0 D5
1 1 1 0 0 D6
1 1 1 1 0 D7
Using MUX to implement the
(n+1)-variable Boolean function
D0=D’
D1=D’
D2=0
D3=0
D4=D’
D5=0
D6=0
D7=D’
Practice
1. Using 74LS153 to implement the function
2. Using 74LS151 to implement the function
f( D,C,B,A)=(0,3,9,14)
Using MUX to implement the
(n+i)-variable Boolean function, i2
Connect any n variables of Boolean function to n control
inputs of MUX.
The left variables are connected to some of 2n data inputs.
Find the relation of the left variables, the output
(the Boolean function) and the data inputs to implement the
circuit.
Using MUX to implement the
(n+i)-variable Boolean function, i2
Example:
Using 74LS153 to implement the function
Connect D and C to control inputs, B and A to some of data inputs
D C B A f Y
0 0 0 0 1 C0
0 0 0 1 1 C0
f = C0 = B’A’+B’A = B’
0 0 1 0 0 C0
0 0 1 1 0 C0
0 1 0 0 1 C1
0 1 0 1 0 C1
f = C1 = B’A’+BA= B’ A
0 1 1 0 0 C1
0 1 1 1 1 C1
1 0 0 0 0 C2
1 0 0 1 0 C2
f = C2 = 0
1 0 1 0 0 C2
1 0 1 1 0 C2
1 1 0 0 0 C3
1 1 0 1 0 C3 f = C3 = 0
1 1 1 0 0 C3
1 1 1 1 0 C3
Connect B and A to control inputs, D and C to some of data inputs
D C B A f Y
0 0 0 0 1 C0 f = C0 = D’
0 0 0 1 1 C1
0 0 1 0 0 C2 f = C1 = D’C’
0 0 1 1 0 C3
0 1 0 0 1 C0 f = C2 = 0
0 1 0 1 0 C1
0 1 1 0 0 C2
0 1 1 1 1 C3 f = C3 = D’C
1 0 0 0 0 C0
1 0 0 1 0 C1
1 0 1 0 0 C2
1 0 1 1 0 C3
1 1 0 0 0 C0
1 1 0 1 0 C1
1 1 1 0 0 C2
1 1 1 1 0 C3
Chapter 3
Combinational Logic
circuits
De-multiplexer - DEMUX
The de-multiplexer consist of 2n outputs and n control
inputs (or selected inputs). At one time, the input is
connected to one output, the index of which is defined by
the n-bit binary (created by n control inputs).
De-multiplexer - DEMUX
De-multiplexer 1 to 4
Block diagram Truth Table Output functions
De-multiplexer - DEMUX
Circuit diagram
De-multiplexer - DEMUX
74LS155: consists of two De-multiplexers 1 to 4
ADDER
1. Half Adder - HA
A half adder is an adder which adds two one-bit binary
numbers A and B. It produces a sum (S) bit and a carry
(C) bit. Truth Table:
Block diagram:
S = A’B + A B’= A B
Output functions:
C = AB
ADDER
Circuit diagram: S = A’B + A B’= A B
C = AB
ADDER
2. Full Adder - FA:
Full adder is an adder which adds 2 one-bit binary
numbers An and Bn with 1 carry bit Cn-1.
FA produces 1 bit Sn (sum) and 1 bit Cn (carry).
It also is an adder used to add 3 one-bit binary numbers
(An, Bn and Cn-1) and produce a two-bit binary number
C n Sn .
ADDER
Block diagram Truth Table
Output function:
ADDER
Circuit diagram
ADDER
3. Parallel Adder - PA
A n-bit parallel adder:
is a n-bit binary number adder, has a carry at the
input, produces sum which is a n-bit binary number
and a carry at the output.
is designed from n FAs connected in series, the carry
at the output of the previous FA is connected to be the
carry at the input of the next FA.
ADDER
Block diagram
ADDER
Connection diagram
ADDER
Example: Add 1101 and 1110 = (1) 1011
IC for adders
74LS83: 4-bit parallel adder
Comparators
a. Comparator for 2 one-bit binary numbers:
Block diagram Truth Table
Output function
Comparators
Circuit diagram
Comparators
b. Comparator for 2 one-bit binary numbers having control inputs
Block diagram
Comparators
b. Comparator for 2 one-bit binary numbers having control inputs
Truth Table
Comparators
b. Comparator for 2 one-bit binary numbers having control inputs
Output function:
Comparators
Circuit diagram
Comparators
c. Comparator for 2 n-bit binary numbers:
Block diagram
IC for Comparators
74LS85: 4-bit comparators
Parity generator & checker
Parity generator & checker is used to detect errors when
transmitting information from the transmitter to the receiver
+ At transmitter: transmit data and 1 Parity bit.
The Parity bit is based on data bits.
There are two kinds of Parity bit.
Even Parity bit
Odd Parity bit
+ At receiver: check the data bits and the Parity bit received:
If the number of bits “1” is even (for Even Parity checker) or odd
(for Odd Parity checker), the transmission is exact.
If not, the transmission has errors.
Parity generator
Consider the circuit generating a 3-bit Even-Parity
Block diagram:
3-bit Even Parity generator
Truth table Output functions
3-bit Even Parity generator
Circuit diagram
Practice
Design:
a. A 4-bit Even Parity generator
b. A 3-bit Odd Parity generator
IC for Even/Odd Parity checker
74LS280: 9-bit Even/Odd Parity generator
3-bit Even Parity checker
We can use 3-bit even parity generator to be 3-bit even
checker by add the 3 checked bits and the even parity bit
generated in a 4-bit even parity generator.
If the number of bits “1” in 4 bits is even (without error)
P = 0.
If the number of bits “1” in 4 bits is odd (with errors)
P = 1.
P lets you know whether errors are appeared or not.
