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DSP Question Bank Revised

The document is a question bank for the course CEC337 - DSP Architecture and Programming at J.J. College of Engineering and Technology. It includes the program's vision, mission, educational objectives, outcomes, and specific outcomes, along with detailed course objectives and content divided into units. Additionally, it provides a mapping of course outcomes to program outcomes and includes textbooks and reference materials for further study.

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Ranjith Kumar
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0% found this document useful (0 votes)
31 views19 pages

DSP Question Bank Revised

The document is a question bank for the course CEC337 - DSP Architecture and Programming at J.J. College of Engineering and Technology. It includes the program's vision, mission, educational objectives, outcomes, and specific outcomes, along with detailed course objectives and content divided into units. Additionally, it provides a mapping of course outcomes to program outcomes and includes textbooks and reference materials for further study.

Uploaded by

Ranjith Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CEC337–DSP ARCHITECTURE AND PROGRAMMING

QUESTION BANK

R-2021

Prepared by
Dr. M. Shobana Page 1
J.J. College of Engineering and Technology, Trichy.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

III YEAR / VI SEMESTER

REGULATION 2021

CEC337–DSP ARCHITECTURE AND PROGRAMMING

Faculty In Charge Head of the Department


Dr. M. Shobana Dr. S. Sumithra,M.E.,Ph.D
Associate Professor/ECE Professor/ECE

Prepared by
Dr. M. Shobana Page 2
J.J. College of Engineering and Technology, Trichy.
INSTITUTE VISION & MISSION

VISION:

To become a globally recognized “Centre of Academic Excellence” providing Quality


Education to all students.

MISSION:

To provide Quality Education in the fields of Engineering, Management, Information,


Technology and other Engineering areas.

DEPARTMENT VISION & MISSION

VISION:

To impart latest knowledge and skills so as to kindle innovation and creativity among
students.

MISSION:

To develop and sustain a culture of research while promoting values, ethics


M1
and professionalism.
To develop competent technocrats who strives continuously in pursuit of professional
M2
excellence in the field of Electronics and Communication Engineering.

M3 To offer well-balanced curriculum to acquire professional competencies.

To develop the state of the art infrastructure and research for effective teaching
M4
learning process.

To strengthen the soft skills especially for rural students through co-curricular and
M5
extracurricular activities.

Prepared by
Dr. M. Shobana Page 3
J.J. College of Engineering and Technology, Trichy.
PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

To provide the students with a strong foundation in the required sciences in order to
PEO1
pursue studies in Electronics and Communication Engineering.

To gain adequate knowledge to become good professional in electronic and


PEO2
communication engineering associated industries, higher education and research.

To develop attitude in lifelong learning, applying and adapting new ideas and technologies
PEO3
as their field evolves.

To prepare students to critically analyze existing literature in an area of specialization and


PEO4 ethically develop innovative and research oriented methodologies to solve the problems
identified.

To inculcate in the students a professional and ethical attitude and an ability to visualize
PEO5
the engineering issues in a broader social context.

PROGRAM OUTCOMES (POs):

Engineering knowledge: Apply the knowledge of mathematics, science, engineering


PO1 fundamentals and an engineering specialization to the solution of complex engineering
problems.
Problem analysis: Identify, formulate, review research literature, and analyze complex
PO2 engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.

Design/development of Solutions: Design solutions for complex engineering problems and


design system components or processes that meet the specified needs with appropriate
PO3
consideration for public health and safety, and the cultural, societal, and environmental
considerations.
Conduct investigations of Complex Problems: Use research-based knowledge and research
PO4 methods including the design of experiments, Analysis and interpretation of data, and
synthesis of the information to provide valid conclusions.
Modern tool Usage: Create, select, and apply appropriate techniques, resources, and
PO5 modern engineering and IT tools including prediction and modeling to complex
Engineering activities with an understanding of the limitations.
The engineer and society: Apply to reason in formed by the contextual Knowledge
PO6 to assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
Environment and Sustainability: Understand the impact of the professional engineering
PO7 solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.

Prepared by
Dr. M. Shobana Page 4
J.J. College of Engineering and Technology, Trichy.
Ethics: Apply ethical principles and commit to professional ethics and Responsibilities and
PO8
norms of the engineering practice.

Individual and team work: Function effectively as an individual, and as a member or leader
PO9
in Diverse teams, and in multidisciplinary settings.

Communication: Communicate effectively on complex engineering activities with the


engineering community and with society at large, such as, being able to comprehend and
PO10
write effective reports and design documentation, make effective presentations, and give and
receive clear instructions.

Project management and finance: Demonstrate knowledge and understanding of the


PO11 engineering and management principles and apply these to one’s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.

Life-long learning: Recognize the need for and have the preparation and ability to Engage
PO12
in in dependent and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs):

Design, develop and analyze electronic systems through application of relevant


PSO1
electronics, mathematics and engineering principles.

Design, develop and analyze communication systems through application of


PSO2 fundamentals from communication principles, signal processing, and RF System
Design & Electromagnetics.

Adapt to emerging electronics and communication technologies and develop


PSO3
innovative solutions for existing and newer problems.

Prepared by
Dr. M. Shobana Page 5
J.J. College of Engineering and Technology, Trichy.
CEC337 DSP ARCHITECTURE AND PROGRAMMING LTPC
20 2 3

COURSE OBJECTIVES:
● Study the architecture of programmable DSP processors
● Learn to implement various standard DSP algorithms in DSP Processors
● Use the Programmable DSP Processors to build real-time DSP systems

UNIT I ARCHITECTURES FOR PROGRAMMABLE DSP PROCESSORS


9
Basic Architectural features, DSP Computational building blocks, Bus architecture and memory, Data
addressing capabilities, Address generation Unit, Programmability and program execution, Speed issues,
Features for external interfacing

UNIT II TMS320C5X PROGRAMMABLE DSP PROCESSOR


9
Architecture of TMS320C54xx DSP processors, Addressing modes – Assembly language Instructions -Memory
space, interrupts, and pipeline operation of TMS320C54xx DSP Processor, On-Chip peripherals, Block
Diagram of TMS320C54xx DSP starter kit

UNIT III TMS320C6X PROGRAMMABLE DSP PROCESSOR


9
Commercial TI DSP processors, Architecture of TMS320C6x DSP Processor, Linear and Circular addressing
modes, TMS320C6x Instruction Set, Assembler directives, Linear Assembly, Interrupts, Multichannel buffered
serial ports, Block diagram of TMS320C67xx DSP Starter Kit and Support Tools

UNIT IV IMPLEMENTATION OF DSP ALGORITHMS


9
DSP Development system, On-chip, and On-board peripherals of C54xx and C67xx DSP development boards,
Code Composer Studio (CCS) and support files, Implementation of Conventional FIR, IIR, and Adaptive filters
in TMS320C54xx/TMS320C67xx DSP processors for real-time DSP applications, Implementation of FFT
algorithm for frequency analysis in real-time.

UNIT V APPLICATIONS OF DSP PROCESSORS 9

Voice scrambling using filtering and modulation, Voice detection and reverse playback, Audio effects, Graphic
Equalizer, Adaptive noise cancellation, DTMF signal detection, Speech thesis using LPC, Automatic speaker
recognition

TOTAL: 45 PERIODS

Prepared by
Dr. M. Shobana Page 6
J.J. College of Engineering and Technology, Trichy.
COURSE OUTCOMES

On completion of this course, the students expected to be able to:


CO1 Understand the architectural features of DSP Processors
CO2 Comprehend the organization of TMS320C54xx DSP processors
CO3 Build solutions using TMS320C6x DSP Processor
CO4 Implement DSP Algorithms
CO5 Study the applications of DSP Processors.

CO’s – PO’s & PSO’s MAPPING

Correlation of COs with POs / PSOs

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

CO1 3 3 3 2 2 2 - - - 1 - 3 3 3 3

CO2 3 3 3 2 2 2 - - - 1 - 2 3 3 3
CO3 3 3 3 2 2 2 - - - 1 - 2 2 2 2
CO4 3 3 3 3 2 2 - - - 1 - 2 2 2 2
CO5 3 3 3 2 2 2 - - - 1 - 2 2 2 2
AVG 3 3 3 2 2 2 - - - 1 - 2 2 3 2
3 – High; 2 – Medium; 1 – Low ;– no correlation

Prepared by
Dr. M. Shobana Page 7
J.J. College of Engineering and Technology, Trichy.
TEXT BOOKS

1. Avtar Singh and S. Srinivasan, Digital Signal Processing – Implementations using DSP
Microprocessors with Examples from TMS320C54xx, Cengage Learning India Private
Limited, Delhi 2012
2. Rulph Chassaing and Donald Reay, Digital Signal Processing and Applications with the
TMS320C6713 and TMS320C6416 DSK, Second Edition, Wiley India (P) Ltd, New
Delhi, 2008

REFERENCE BOOKS

1. B. Venkataramani and M. Bhaskar, “Digital Signal Processors – Architecture, Programming


and Applications”, Tata McGraw – Hill Publishing Company Limited. New Delhi, 2003.
2. TMS320C5416/6713 DSK user manual at [Link]

Prepared by
Dr. M. Shobana Page 8
J.J. College of Engineering and Technology, Trichy.
UNIT– I
ARCHITECTURES FOR PROGRAMMABLE DSP PROCESSORS

PART–A
CO
Q. No Questions BT Level Complexity
Mapping
1 What is the role of a shifter in Medium
CO1 Understand
DSP?
What is meant by circular
2 addressing mode? CO1 Understand Medium
What is a DSP system? Give one
3 CO1 Understand Medium
example
What are the main features of
4 CO1 Understand Medium
DSP architecture?
Define pipelining in DSP
5 CO1 Remember Low
architecture.
What are the flags available in
6 CO1 Understand Medium
DSP architecture?
What are hardware interrupts
7 CO1 Understand Medium
available in DSP architecture?
8 Define DMA. CO1 Remember Low
Define maskable and non
9 CO1 Remember Low
maskable interrupt.
10 Define Hard Vard architecture. CO1 Understand Medium
What is address bus and data
11 CO1 Understand Medium
bus?

12 Define assembly language. CO1 Remember Low

13 What are guard bits? CO1 Understand Medium

14 Define a flag. CO1 Remember Low

15 What are the types of memory? CO1 Understand Medium

Prepared by
Dr. M. Shobana Page 9
J.J. College of Engineering and Technology, Trichy.
PART–B
CO
Q. No Questions BT Level Complexity
Mapping
Describe the addressing modes
1 of DSP processor. CO1 Understand Medium

Draw the computational blocks


2 of DSP. Explain in detail about CO1 Create High
it.
Discuss Arithmetic and logical
3 instructions with examples in CO1 Understand Medium
DSP processor.
Describe Von Neuman
4 architecture. CO1 Understand Medium
Explain data addressing
CO1 Understand Medium
5 capability.
Elaborate the interrupts
6 available in DSP Processor. CO1 Understand Medium

7 Enumerate chip memories. CO1 Understand Medium


Discuss Parallel multipliers in
8 detail. CO1 Understand Medium
Describe program sequencer in
9 DSP Processor. CO1 Understand Medium
Explain MAC unit in DSP
10 Processor. CO1 Understand Medium
What are the on chip peripherals
11 available in DSP Processor? CO1 Understand Medium
Explain in detail.
Elaborate Programmability and
12 program execution in DSP CO1 Understand Medium
Processor.

Prepared by
Dr. M. Shobana Page 10
J.J. College of Engineering and Technology, Trichy.
UNIT – II
TMS320C5X PROGRAMMABLE PROCESSOR

PART–A

CO
Q. No Questions BT Level Complexity
Mapping
1 Define TDM. CO2 Remember Low

2 Define data address generation unit. CO2


Remember Low
3 What is program address generation
CO2 Understand Medium
unit?
4 What is the function of carry bit in
CO2 Understand Medium
ALU?
What is the use of stack point
5 CO2 Understand Medium
register?

6 Define Memory Mapped Registers. CO2 Remember Low

7 What is On chip ROM? CO2 Understand Medium


What are program control
8 instructions? CO2 Understand Medium

List the number of address buses in


9 CO2 Remember Low
54X.

10 Define overflow. CO2 Remember Low

11 What is a multiplier? CO2 Understand Medium


What is the use of the following
12 registers of 54X? CO2 Understand Medium
(a) TX (b)TRN (c) BIC (d) XPC
Explain branch call and Return
13 CO2 Understand Medium
Instructions.

Prepared by
Dr. M. Shobana Page 11
J.J. College of Engineering and Technology, Trichy.
PART–B
CO
[Link] Questions BT Level Complexity
Mapping
Explain various register in
1 TMS320C45XX. CO2 Understand Medium
Write a program in C to plot
Sawtooth waveform using
2 CO2 Create High
TMS32054XX.
Draw the architecture of
CO2 Create High
3 TMS320C54XX.
Write a program in C to plot sine
4 waveform using TMS32054XX. CO2 Create High

Discuss the operation of CSUU of


5 54X with an application. CO2 Understand Medium

Elaborate Arithmetic and logic


6 unit of TMS320C54XX. CO2 Understand Medium

Describe the instruction set of


7 CO2 Understand Medium
C54X.
Enumerate CPU of
8 CO2 Understand Medium
TMS320C54XX.
Write a program in C to plot
Triangular waveform using
9 CO2 Create High
TMS32054XX.
Discuss in detail about exponent
10 encoder. CO2 Understand Medium

Prepared by
Dr. M. Shobana Page 12
J.J. College of Engineering and Technology, Trichy.
UNIT – III
TMS320C6X PROGRAMMABLE DSP PROCESSOR

PART–A

CO
Q. No Questions BT Level Complexity
Mapping
What is VLIW?
1 CO3 Understand Medium
What are the features of
2 TMS320C6X Programmable DSP
CO3 Understand Medium
Processor?

3 List the 8 functional units of


TMS320C6X Programmable DSP CO3 Remember Low
Processor.
4 What is the function of D unit in
TMS320C6X Programmable DSP CO3 Understand Medium
Processor?
5 What are the addressing modes in
CO3 Understand Medium
TMS320C6X?

6 Define accessible peripherals in


TMS320C6X. CO3 Remember Low

7 What is code composer studio? CO3 Understand Medium

8 Define power down logic. CO3 Remember Low

9 What is a timer? CO3 Understand Medium

10 Define EMIF. CO3 Remember Low

11 What is pipeline operation? CO3 Understand Medium


12 Define cache. CO3 Remember Low
13 List the advantages of VelociT1
CO3 Remember Low
architecture.

Prepared by
Dr. M. Shobana Page 13
J.J. College of Engineering and Technology, Trichy.
PART–B
CO
Q. No Questions BT Level Complexity
Mapping
Explain how the C6X architecture
differs from those of C5Xand CO3 Understand Medium
1
C54X.
Discuss the functional units in
C6X and explain the function Understand Medium
2 CO3
performed by each of them.
Describe the addressing modes
3 CO3 Understand Medium
supported by C6X.
Elaborate the internal and external
4 Understand Medium
memory organization in C6X. CO3
Explain the operation of L2 cache
5 CO3 Understand Medium
controller.
Enumerate the use of memory
6 attribute registers in C6X. CO3 Understand Medium

What is the function of EMIF in


7 C6X? Discuss in detail. CO3 Understand Medium

Explain the C6X pipeline


8 operation. CO3 Understand Medium

9 What is meant by glueless


interface? Elaborate the process. CO3 Understand Medium

What is the use of HP1 in C6X?


10 CO3 Understand Medium
Enumerate in detail.

Prepared by
Dr. M. Shobana Page 14
J.J. College of Engineering and Technology, Trichy.
UNIT – IV
IMPLEMENTATION OF DSP ALGORITHMS

PART–A
CO
Q. No Questions BT Level Complexity
Mapping
1 What is FIR filter? CO4 Understand Medium

2 What is IIR filter? CO4 Understand Medium


3 Define Adaptive filter. CO4 Remember Low
List the applications of DSP
4 CO4 Remember Low
Processor.
5 List some of DSK support tools. CO4 Remember Low
6 What are DSK boards? CO4 Understand Medium

7 What is VLIW? CO4 Understand Medium


What is multiply accumulate
8 CO4 Understand Medium
instruction?

9 Define assembly language? Remember Low


CO4
10 What is compiler? CO4 Understand Medium

11 Define an assembler. CO4 Remember Low

12 What is hamming window? CO4 Understand Medium

Prepared by
Dr. M. Shobana Page 15
J.J. College of Engineering and Technology, Trichy.
PART–B
CO
Q. No Questions BT Level Complexity
Mapping
Write the assembly language
program for TMS320C54XX
1 CO4 Create High
processor to implement an
FIR filter.

2 Explain code composer studio. CO4 Understand Medium

Write the assembly language


program for TMS320C54XX CO4
3 Create High
processor to implement
FFT.
Write the assembly language
program for TMS320C54XX
CO4 Create High
4 processor to implement an
FIR filter.

Explain TMS320C 6416 Digital


5 CO4 Understand Medium
Signal Processor.

Enumerate code composer


6 CO4 Understand Medium
studio.

Discuss about circular


7 CO4 Understand Medium
addressing in TMS320C 6413.
Describe the instruction set of
8 CO4 Understand Medium
TMS320C 6413.
Elaborate the interrupts of
9 CO4 Understand Medium
TMS320C 6413.
Explain the various support files
10 CO4 Understand Medium
of CCS.

Prepared by
Dr. M. Shobana Page 16
J.J. College of Engineering and Technology, Trichy.
UNIT – V
APPLICATIONS OF DSP PROCESSORS

PART–A
CO
Q. No Questions BT Level Complexity
Mapping

1 Define DTMF signal. CO5 Remember Low


2
Define FFT. CO5 Remember Low
3 What is speech synthesis? CO5 Understand Medium

4 What is LPC? CO5 Understand Medium

5 Define Vector Quantization. CO5 Remember Low

6 What is codebook? CO5 Understand Medium

7 Define code word. CO5 Remember Low

8 Define windowing. CO5 Remember Low


What are fixed point and
9 Medium
floating point operations? CO5 Understand

10 What is convolution? CO5 Understand Medium

11 Define voice scrambling. Remember Low


CO5

12 What is speaker recognition? CO5 Understand Medium

13 Write short note on Equalizer. CO5 Medium


Understand
What is meant by voice
14 CO5 Understand Medium
detection?

15 Define sampling. CO5 Remember Low

Prepared by
Dr. M. Shobana Page 17
J.J. College of Engineering and Technology, Trichy.
PART–B
CO
Q. No Questions BT Level Complexity
Mapping
Explain how automatic speaker
1 recognition is implemented in DSP CO5 Understand Medium
Processor.
Describe how DTMF signal
detection is implemented in DSP
2 CO5 Understand Medium
Processor.
Discuss how speech synthesis is
3 done using DSP Processor. CO5 Understand Medium
Elaborate voice scrambling using
4 filtering and modulation in DSP CO5 Understand Medium
Processor.
Explain how equalizer is
5 CO5 Understand Medium
implemented in DSP Processor.
Emunerate how Voice detection and
6
reverse playback is implemented in CO5 Understand Medium
DSP Processor.

Prepared by
Dr. M. Shobana Page 18
J.J. College of Engineering and Technology, Trichy.
THANK YOU

ALL THE BEST

Prepared by
Dr. M. Shobana Page 19
J.J. College of Engineering and Technology, Trichy.

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