SRI SHANMUGHA COLLEGE OF ENGINEERING AND

TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

LAB MANUAL

EC8661-VLSI DESIGN LAB

REGULATION 2017
EX. NO DATE NAME OF THE EXPERIMENT MARK SIGNATURE

10

11

12
EC8661 VLSI DESIGN LABORATORY LTPC 0032

CONTENT BEYOND SYLLABUS:

1. Design and Simulate a Ripple Carry Adder

2. Design and Simulate a Multiplexer and De-Multiplexer.

VLSI DESIGN
EXP: Design of Logic gates
1.1 Introduction
The purpose of this experiment is to simulate the behavior of several of the basic logic gates and you will
connect several logic gates together to create simple digital model.

1.2 Software tools Requirement

Equipments:

Computer with Modelsim Software

Specifications:

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Modelsim - 5.7c, Xilinx - 6.1i.

Algorithm
STEP 1: Open ModelSim XE II / Starter 5.7C

STEP 2: File -> Change directory -> D:\<register number>

STEP 3: File -> New Library -> ok

STEP 4: File -> New Source -> Verilog

STEP 5: Type the program

STEP 6: File -> Save -><filename.v>

STEP 7: Compile the program

STEP 8: Simulate -> expand work -> select file -> ok

STEP 9: View -> Signals

STEP 10: Select values -> Edit -> Force -> input values

STEP 11: Add -> Wave -> Selected signals -> Run

STEP 12: Change input values and run again

1.3 Logic Gates and their Properties

Gate Description Truth Table Logic Symbol Pin Diagram

The output is active high A B Output Q
if any one of the input is
OR in active high state, 0 0 0
Mathematically,
0 1 1
Q = A+B
1 0 1

1 1 1

The output is active high A B Output Q

only if both the inputs
AND are in active high state, 0 0 0
Mathematically,
0 1 0
Q = A.B
1 0 0

1 1 1
In this gate the output is A Output Q
opposite to the input
NOT state, Mathematically, 0 1

Q=A 1 0

The output is active high A B Output Q

only if both the inputs
NOR are in active low state, 0 0 1
Mathematically,
0 1 0
Q = (A+B)'
1 0 0

1 1 0
The output is active high A B Output Q
only if any one of the
NAND input is in active low 0 0 1
state, Mathematically,
0 1 1
Q = (A.B)'
1 0 1

1 1 0
 The output is active high A B Output Q 7486
only if any one of the
XOR input is in active high 0 0 0
state, Mathematically,
0 1 1
Q = A.B' + B.A'
1 0 1

1 1 0

1.4 Pre lab Questions

1. What is truth table?

2. Which gates are called universal gates?

3. A basic 2-input logic circuit has a HIGH on one input and a LOW on the other input, and the output
is HIGH. What type of logic circuit is it?

4. A logic circuit requires HIGH on all its inputs to make the output HIGH. What type of logic circuit
is it?

5. Develop the truth table for a 3-input AND gate and also determine the total number of possible
combinations for a 4-input AND gate.

VERILOG Program

a) AND Gate

Structural Model Data Flow Model BehaviouralModel

moduleandstr(x,y,z); moduleanddf(x,y,z); module andbeh(x,y,z);

inputx,y; inputx,y; input x,y;

output z; output z; output z;

and g1(z,x,y); assign z=(x&y); reg z;

endmodule endmodule always @(x,y)

z=x&y;

endmodule
b) NAND Gate

Structural Model Data Flow Model BehaviouralModel

modulenandstr(x,y,z); modulenanddf(x,y,z); module nandbeh(x,y,z);

inputx,y; inputx,y; input x,y;

output z; output z; output z;

nand g1(z,x,y); assign z= !(x&y); reg z;

endmodule endmodule always @(x,y)

z=!(x&y);

endmodule
c) OR Gate

Structural Model Data Flow Model BehaviouralModel

module orstr(x,y,z); module ordf(x,y,z); module orbeh(x,y,z);

inputx,y; inputx,y; input x,y;

output z; output z; output z;

or g1(z,x,y); assign z=(x|y); reg z;

endmodule endmodule always @(x,y)

z=x|y;

endmodule
d) NOR Gate

Structural Model Data Flow Model BehaviouralModel

modulenorstr(x,y,z); modulenordf(x,y,z); Modulenorbeh(x,y,z);

inputx,y; inputx,y; input x,y;

output z; output z; output z;

nor g1(z,x,y); assign z= !(x|y); reg z;

endmodule endmodule always @(x,y)

z=!(x|y);

endmodule
e) XOR Gate

Structural Model Data Flow Model BehaviouralModel

module xorstr(x,y,z); module xordf(x,y,z); module xorbeh(x,y,z);

inputx,y; inputx,y; input x,y;

output z; output z; output z;

xor g1(z,x,y); assign z=(x^y); reg z;

endmodule endmodule always @(x,y)

z=x^y;

endmodule
f) XNOR Gate

Structural Model Data Flow Model BehaviouralModel

modulexnorstr(x,y,z); modulexnordf(x,y,z); module xnorbeh(x,y,z);

inputx,y; inputx,y; input x,y;

output z; output z; output z;

xnor g1(z,x,y); assign z= !(x^y); reg z;

endmodule endmodule always @(x,y)

z=!(x^y);

endmodule
g) NOT Gate

Structural Model Data Flow Model BehaviouralModel

module notstr(x,z); module notdf(x,z); module notbeh(x,z);

input x; input x; input x;

output z; output z; output z;

not g1(z,x); assign z= !x; reg z;

endmodule endmodule always @(x)

z=!x;

endmodule
Out put waveforms
AND Gate:

OR Gate:

NOT Gate:

NOR Gate:

NAND Gate:

XOR Gate:
RESULT

Thus the logic gates were implemented using XILINX .

EXP: Design of Binary Adders

2.1 Introduction
The purpose of this experiment is to introduce the design of simple combinational circuits, in this case half
adders, half subtractors, full adders and full subtractors.

2.2 Software tools Requirement

Equipments:

Computer with Modelsim Software

Specifications:

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Modelsim - 5.7c, Xilinx - 6.1i.

Algorithm

STEP 1: Open ModelSim XE II / Starter 5.7C

STEP 2: File -> Change directory -> D:\<register number>

STEP 3: File -> New Library -> ok

STEP 4: File -> New Source -> Verilog

STEP 5: Type the program

STEP 6: File -> Save -><filename.v>

STEP 7: Compile the program

STEP 8: Simulate -> expand work -> select file -> ok

STEP 9: View -> Signals

STEP 10: Select values -> Edit -> Force -> input values

STEP 11: Add -> Wave -> Selected signals -> Run

STEP 12: Change input values and run again

2.3 Logic Diagram

Half adder

Full adder

Halfsubtractor
Full subtractor

2.4 Pre lab Questions

1. What is meant by combinational circuits?

2. Write the sum and carry expression for half and full adder.

3. Write the difference and borrow expression for half and full subtractor.

4. What is signal? How it is declared?

5. Design a one bit adder.

VERILOG Program

HALF ADDER:

Structural model Dataflow model Behaviouralmodel

modulehalfaddstr(sum,carry,a,b); modulehalfadddf(sum,carry,a,b); modulehalfaddbeh(sum,carry,a,b);

outputsum,carry; outputsum,carry; outputsum,carry;

inputa,b; inputa,b; inputa,b;

xor(sum,a,b); assign sum = a ^ b; regsum,carry;

and(carry,a,b); assign carry=a&b; always @(a,b);

endmodule endmodule sum = a ^ b;

carry=a&b;

endmodule
FULL ADDER:

Structural model Dataflow model Behaviouralmodel

module modulefulladddf(sum,carry,a,b,c); modulefulladdbeh(sum,carry,a,b,c);
fulladdstr(sum,carry,a,b,c);
outputsum,carry; outputsum,carry;
outputsum,carry;
inputa,b,c; inputa,b,c;
inputa,b,c;
assign sum = a ^ b^c; regsum,carry;
xor g1(sum,a,b,c);
assign carry=(a&b) | (b&c) | always @ (a,b,c)
and g2(x,a,b); (c&a);
sum = a ^ b^c;
and g3(y,b,c); endmodule
carry=(a&b) | (b&c) | (c&a);
and g4(z,c,a);
endmodule
or g5(carry,x,z,y);

endmodule

HALF SUBTRACTOR:

Structural model Dataflow Model BehaviouralModel

modulehalfsubtstr(diff,borrow,a,b); modulehalfsubtdf(diff,borrow,a,b); modulehalfsubtbeh(diff,borrow,a,b);

outputdiff,borrow; outputdiff,borrow; outputdiff,borrow;

inputa,b; inputa,b; inputa,b;

xor(diff,a,b); assign diff = a ^ b; regdiff,borrow;

and( borrow,~a,b); assign borrow=(~a&b); always @(a,b)

endmodule endmodule diff = a ^ b;

borrow=(~a&b);

endmodule
FULL SUBTRACTOR:

Structural model Dataflow Model BehaviouralModel

module modulefullsubtdf(diff,borrow,a,b,c); modulefullsubtbeh(diff,borrow,a,b,c);
fullsubtstr(diff,borrow,a,b,c);
outputdiff,borrow; outputdiff,borrow;
outputdiff,borrow;
inputa,b,c; inputa,b,c;
inputa,b,c;
assign diff = a^b^c; outputdiff,borrow;
wire a0,q,r,s,t;
assign borrow=(~a&b)|(~(a^b)&c); always@(a,b,)
not(a0,a);
endmodule diff = a^b^c;
xor(x,a,b);
borrow=(~a&b)|(~(a^b)&c);
xor(diff,x,c);
endmodule
and(y,a0,b);

and(z,~x,c);

or(borrow,y,z);

endmodule

Output waveforms:
Half Adder:

Half subtractor:
Full adder Dataflow modeling:

Full adder structural modeling:

Full Subtractor Dataflow modeling:

RESULT

Thus the Half-adder, Full adder, Four bit adder were implemented using Xilinx.
EXP: Design of Ripple carry,Carry select and Carry save Adders

3.1 Introduction
The purpose of this experiment is to introduce the design of Ripple carry,Carry select and Carry save Adders

3.2 Software tools Requirement

Equipments:

Computer with Modelsim Software

Specifications:

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Modelsim - 5.7c, Xilinx - 6.1i.

Algorithm

STEP 1: Open ModelSim XE II / Starter 5.7C

STEP 2: File -> Change directory -> D:\<register number>

STEP 3: File -> New Library -> ok

STEP 4: File -> New Source -> Verilog

STEP 5: Type the program

STEP 6: File -> Save -><filename.v>

STEP 7: Compile the program

STEP 8: Simulate -> expand work -> select file -> ok

STEP 9: View -> Signals

STEP 10: Select values -> Edit -> Force -> input values

STEP 11: Add -> Wave -> Selected signals -> Run

STEP 12: Change input values and run again

3.3 Ripple carry adder

VHDL Program

8-bit Ripple Carry Adder

Structural code for RCA Test bench for RCA

module rippe_adder(X, Y, S, Co); ENTITY Tb_Ripple_Adder IS

input [3:0] X, Y; END Tb_Ripple_Adder;
output [3:0] S;
output Co; ARCHITECTURE behavior OF Tb_Ripple_Adder IS
wire w1, w2, w3;
-- Component Declaration for the Unit Under Test
fulladder u1(X[0], Y[0], 1'b0, S[0], w1); (UUT)
fulladder u2(X[1], Y[1], w1, S[1], w2);
fulladder u3(X[2], Y[2], w2, S[2], w3); COMPONENT Ripple_Adder
fulladder u4(X[3], Y[3], w3, S[3], Co); PORT(
endmodule A : IN std_logic_vector(3 downto 0);
module fulladder(X, Y, Ci, S, Co); B : IN std_logic_vector(3 downto 0);
input X, Y, Ci; Cin : IN std_logic;
output S, Co; S : OUT std_logic_vector(3 downto 0);
wire w1,w2,w3; Cout : OUT std_logic
);
END COMPONENT;
xor G1(w1, X, Y);
xor G2(S, w1, Ci);
--Inputs
and G3(w2, w1, Ci); signal A : std_logic_vector(3 downto 0) := (others =>
and G4(w3, X, Y); '0');
or G5(Co, w2, w3); signal B : std_logic_vector(3 downto 0) := (others =>
endmodule '0');
signal Cin : std_logic := '0';

--Outputs
signal S : std_logic_vector(3 downto 0);
signal Cout : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Ripple_Adder PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "0110";
B <= "1100";

wait for 100 ns;

 A <= "1111";
B <= "1100";

wait for 100 ns;

A <= "0110";
B <= "0111";

wait for 100 ns;

A <= "0110";
B <= "1110";

wait for 100 ns;

A <= "1111";
B <= "1111";

wait;

end process;

END;

Output Waveform
3.4 Carry select adder

Logic diagram

Verilog program

Structural code for CSA Structural code for CSA

Module carry select (a,b,s,cin,cout); ENTITY Tb_carry_select_adder IS
Input [3:0]a,b; END Tb_carry_select_adder;
Input cin;
Output cout; ARCHITECTURE behavior OF
Output [3:0]s; Tb_carry_select_adder IS
Wire [3:0]s;
Wire Cout; -- Component Declaration for the
Unit Under Test (UUT)
Wire
s1,c1,s2,c2,s3,c3,s4,c4,s11,c11,s22,c22,s33,c33,s44,c44;
COMPONENT carry_select_adder
fa x1(a[0],b[0],0,s1,c1); PORT(
fa x2(a[1],b[1],c1,s2,c2); X : IN std_logic_vector(3 downto
fa x3(a[2],b[2],c2,s2,c2); 0);
fa x4(a[3],b[3],c3,s3,c3); Y : IN std_logic_vector(3 downto
fa x5(a[0],b[0],1,s11,c11); 0);
fa x6(a[1],b[1],c11,s22,c22); CARRY_IN : IN std_logic;
fa x7(a[2],b[2],c22,s33,c33); SUM : OUT std_logic_vector(3
fa x8(a[3],b[3],c33,s44,c44); downto 0);
CARRY_OUT : OUT std_logic
mux x9(s1,s11,cin,s[0]);
);
mux x10(s2,s22,cin,s[1]); END COMPONENT;
mux x11(s3,33,cin,s[2]);
mux x12(s4,s44,cin,s[3]); --Inputs
mux x12(c4,c44,cin,cout); signal X : std_logic_vector(3
downto 0) := (others => '0');
endmodule signal Y : std_logic_vector(3
downto 0) := (others => '0');
signal CARRY_IN : std_logic :=
'0';

--Outputs
signal SUM : std_logic_vector(3
downto 0);
signal CARRY_OUT : std_logic;

BEGIN
 -- Instantiate the Unit Under
Test (UUT)
uut: carry_select_adder PORT MAP
(
X => X,
Y => Y,
CARRY_IN => CARRY_IN,
SUM => SUM,
CARRY_OUT => CARRY_OUT
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
X <= "1011";
Y <= "1111";

wait for 100 ns;

X <= "0001";
Y <= "1010";

wait for 100 ns;

X <= "0111";
Y <= "1111";
wait;
end process;

END;

Output waveform of CSA

3.5 Carry save adder

Logic diagram

VHDL Program
 Structural code for CSA Test bench for CSA
ENTITY Tb_carry_save IS
entity carry_save_adder is END Tb_carry_save;

Port ( A : in STD_LOGIC_VECTOR (3 ARCHITECTURE behavior OF

downto 0); Tb_carry_save IS
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0); -- Component Declaration for the
S : OUT STD_LOGIC_VECTOR (4 downto 0); Unit Under Test (UUT)
Cout : OUT STD_LOGIC);
end carry_save_adder; COMPONENT carry_save_adder
PORT(
architecture Behavioral of A : IN std_logic_vector(3 downto
carry_save_adder is 0);
B : IN std_logic_vector(3 downto
component full_adder_vhdl_code 0);
Port ( A : in STD_LOGIC; C : IN std_logic_vector(3 downto
B : in STD_LOGIC; 0);
Cin : in STD_LOGIC; S : OUT std_logic_vector(4 downto
S : out STD_LOGIC; 0);
Cout : out STD_LOGIC); Cout : OUT std_logic
end component; );
END COMPONENT;
-- Intermediate signal
signal X,Y: STD_LOGIC_VECTOR(3 downto --Inputs
0); signal A : std_logic_vector(3
signal C1,C2,C3: STD_LOGIC; downto 0) := (others => '0');
signal B : std_logic_vector(3
begin downto 0) := (others => '0');
-- Carry save adder block signal C : std_logic_vector(3
FA1: full_adder_vhdl_code PORT downto 0) := (others => '0');
MAP(A(0),B(0),C(0),S(0),X(0));
FA2: full_adder_vhdl_code PORT --Outputs
MAP(A(1),B(1),C(1),Y(0),X(1)); signal S : std_logic_vector(4
FA3: full_adder_vhdl_code PORT downto 0);
MAP(A(2),B(2),C(2),Y(1),X(2)); signal Cout : std_logic;
FA4: full_adder_vhdl_code PORT
MAP(A(3),B(3),C(3),Y(2),X(3)); BEGIN

-- Ripple carry adder block -- Instantiate the Unit Under Test

FA5: full_adder_vhdl_code PORT (UUT)
MAP(X(0),Y(0),'0',S(1),C1); uut: carry_save_adder PORT MAP (
FA6: full_adder_vhdl_code PORT A => A,
MAP(X(1),Y(1),C1,S(2),C2); B => B,
FA7: full_adder_vhdl_code PORT C => C,
MAP(X(2),Y(2),C2,S(3),C3); S => S,
FA8: full_adder_vhdl_code PORT Cout => Cout
MAP(X(3),'0',C3,S(4),Cout); );

end Behavioral; -- Stimulus process

stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= "1100";
B <= "1101";
C <= "1110";

wait for 100 ns;

A <= "1111";
B <= "1000";
C <= "1001";
 wait for 100 ns;
A <= "1110";
B <= "0101";
C <= "0111";

wait;
end process;

END;

Output waveform

RESULT

Thus the Ripple carry,Carry select and Carry save Adders were implemented using XILINX .
EXP: Design of Multiplexers and Demultiplexers

4.1 Introduction
The purpose of this experiment is to write and simulate a VERILOG program for Multiplexers
and Demultiplexers.

4.2 Software tools Requirement:

Equipments:

Computer with Modelsim Software

Specifications:

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Modelsim - 5.7c, Xilinx - 6.1i.

Algorithm

STEP 1: Open ModelSim XE II / Starter 5.7C

STEP 2: File -> Change directory -> D:\<register number>

STEP 3: File -> New Library -> ok

STEP 4: File -> New Source -> Verilog

STEP 5: Type the program

STEP 6: File -> Save -><filename.v>

STEP 7: Compile the program

STEP 8: Simulate -> expand work -> select file -> ok

STEP 9: View -> Signals

STEP 10: Select values -> Edit -> Force -> input values

STEP 11: Add -> Wave -> Selected signals -> Run

STEP 12: Change input values and run again

4.3 Logic Diagram

Function Table

4:1 Multiplexer Block diagram

1:4 Demux Symbol Function Table

Logic Diagram

2:1 Multiplexer
 4:1 Multiplexer

4.4 Pre lab Questions

1. Define mux and demux. Write

2. their applications.
3. What is the relationship b/w input lines and select lines.
4. Design 4:1 mux and 1:4 demux.
5. Write brief notes on case statement.
VERILOG Program
Multiplexers 2:1 MUX

Structural Model Dataflow Model BehaviouralModel

module mux21str(i0,i1,s,y); module mux21df(i0,i1,s,y); module mux21beh(i0,i1,s,y);

input i0,i1,s; input i0,i1,s; input i0,i1,s;

output y; output y; output y;

wire net1,net2,net3; assign y =(i0&(~s))|(i1&s); reg y;
not g1(net1,s);
endmodule always@(i0,i1)
and g2(net2,i1,s);
begin
and g3(net3,i0,net1);
if(s==0) y=i1;
or g4(y,net3,net2);
if(s==1)y=i0;
endmodule
end

endmodule

4:1 MUX

Structural Model Dataflow Model BehaviouralModel

module module module mux41beh(in,s,y );
mux41str(i0,i1,i2,i3,s0,s1,y); mux41df(i0,i1,i2,i3,s0,s1,y); output y ;
input i0,i1,i2,i3,s0,s1; input [3:0] in ;
input i0,i1,i2,i3,s0,s1; input [1:0] s ;
wire a,b,c,d;
reg y;
output y;
always @ (in,s)
output y;
begin
assign
and g1(a,i0,s0,s1); y=((i0&(~(s0))&(~(s1)))| if (s[0]==0&s[1]==0)
y = in[3];
and g2(b,i1,(~s0),s1); (i1&(~(s0))&s1)| else if (s[0]==0&s[1]==1)
y = in[2];
and g3(c,i2,s0,(~s1)); |(i2&s0&(~(s1)))| else if (s[0]l==1&s[1]==0)
y = in[1];
and g4(d,i3,(~s0),(~s1)); (i3&s0&s1); else
y = in[0];
or(y,a,b,c,d); endmodule
end
endmodule
endmodule
Logic Diagram

8:1 Multiplexer
VERILOG Program

8:1 MUX

Structural Model Dataflow Model BehaviouralModel

modulemux81str(i0,i1,i2,i3,i4,i5,i6,i7,s modulemux81df(y,i,s) modulemux81beh(s,i0,i1,i2,i3,i4,i5
0,s1,s2,y); ; ,i6,i7,y);

input i0,i1,i2,i3,i4,i5,i6,i7,s0,s1,s2; output y; input [2:0] s;

input i0,i1,i2,i3,i4,i5,i6,i7;
wire a,b,c,d,e,f,g,h; input [7:0] i;

output y; input [2:0] s; regy;

always@(i0,i1,i2,i3,i4,i5,i6,i7,s) be
and g1(a,i7,s0,s1,s2); wire se1;
gin
and g2(b,i6,(~s0),s1,s2); assign case(s) begin
se1=(s[2]*4)|(s[1]*2)|
3'd0:MUX_OUT=i0;
and g3(c,i5,s0,(~s1),s2); (s[0]);
3'd1:MUX_OUT=i1;
and g4(d,i4,(~s0),(~s1),s2); assign y=i[se1]; 3'd2:MUX_OUT=i2;

and g5(e,i3,s0,s1,(~s2)); endmodule 3'd3:MUX_OUT=i3;

3'd4:MUX_OUT=i4;
and g6(f,i2,(~s0),s1,(~s2));
3'd5:MUX_OUT=i5;
and g7(g,i1,s0,(~s1),(s2)); 3'd6:MUX_OUT=i6;
3'd7:MUX_OUT=i7;
and g8(h,i0,(~s0),(~s1),(~s2));
endcase
or(y,a,b,c,d,e,f,g,h); end

endmodule endmodule
Logic Diagram

1:4 Demultiplexer

1:8 Demultiplexer
VERILOG Program

1:4 DEMUX

Structural Model Dataflow Model BehaviouralModel

module module demux14df( module demux14beh(
demux14str(in,d0,d1,d2,d3,s0,s1); in,d0,d1,d2,d3,s0,s1); din,sel,dout );
output [3:0] dout ;
output d0,d1,d2,d3; output d0,d1,d2,3; reg [3:0] dout ;
input in,s0,s1; input din ;
input in,s0,s1; wire din ;
assign s0 = in & (~s0) & (~s1);
input [1:0] sel ;
and g1(d0,in,s0,s1); assign d1= in & (~s0) & s1; wire [1:0] sel ;
assign d2= in & s0 & (~s1); always @ (din or sel) begin
and g2(d1,in,(~s0),s1);
assign d3= in & s0 & s1; case (sel)
and g3(d2,in,s0,(~s1)); 0 : dout = {din,3'b000};
endmodule
1 : dout = {1'b0,din,2'b00}; 2
and g4(d3,in,(~s0),(~s1)); : dout = {2'b00,din,1'b0};
default : dout = {3'b000,din};
endmodule endcase

end

endmodule
1:8 DEMUX

Structural Model Dataflow Model BehaviouralModel

module module module demux18beh(i,
demux18str(in,s0,s1,s2,d0,d1,d2 demux18df(in,s0,s1,s2,i0,d1,d2,d3,d4,d5 sel, y);
,d3,d4,d5,d6,d7); ,d6,d7);
input i;
input in,s0,s1,s2; input in,s0,s1,s2;
input [2:0] sel;
output d0,d1,d2,d3,d4,d5,d6,d7; output d0,d1,d2,d3,d4,d5,d6,d7;
output [7 :0] y ;
and g1(d0,in,s0,s1,s2); assign d0 = in & s0 & s1 & s2;
reg [7:0] y;
and g2(d1,in,(~s0),s1,s2); assign d1 = in & (~s0) & s1 & s2;
always@(i,sel)
and g3(d2,in,s0,(~s1),s2); assign d2 = in & s0 & (~s1) & s2;
begin
and g4(d3,in,(~s0),(~s1),s2); assign d3 = in & (~s0) &( ~s1) & s2;
y=8'd0;
and g5(d4,in,s0,s1,(~s2)); assign d4 = in & s0 & s1 & (~s2);
case(sel)
and g6(d5,in,(~s0),s1,(~s2)); assign d5 = in & (~s0) & s1 & (~s2);
3'd0:y[0]=i;
and g7(d6,in,s0,(~s1),(~s2)); assign d6 = in & s0 & (~s1) & (~s2);
3'd1:y[1]=i;
and g8(d7,in,(~s0),(~s1),(~s2)); assign d7 = in & (~s0) & (~s1) & (~s2);
3'd2:y[2]=i;
endmodule endmodule
3'd3:y[3]=i;

3'd4:y[4]=i;

3'd5:y[5]=i;

3'd6:y[6]=i;

default:y[7]=i;

endcase

end

endmodule
Output Wave forms:
2 X 1 MUX:

4 X 1 MUX DATAFLOW MODELING

4 X 1 MUX STRUCTURAL MODELING

MUX 8:1 Using 4:1 & 2:1

1 TO 4 DEMUX BEHAVIOURAL MODELING

8 bit multiplier

VHDL Program

Structural code for multiplier

module multipliermod(a, b, out);

input [4:0] a;
input [4:0] b;
output [9:0] out;
assign out=(a*b);
endmodule

TEST BENCH

module multipliert_b;
reg [4:0] a;
reg [4:0] b;
wire [9:0] out;
multipliermod uut (.a(a),.b(b),.out(out) );
initial begin
#10 a=4’b1000;b=4’b0010;
#10 a=4’b0010;b=4’b0010;
#10 a=4’b0100;b=4’b0100;
#10 a=4’b1000;b=4’b0001;
#10$stop;
end
endmodule
Output waveform

RESULT

Thus the multiplexers, demultiplexers and 8 bit Multiplier were simulated using
Xilinx.
EXP 5: Design of Flip Flops

5.1 Introduction
The purpose of this experiment is to introduce you to the basics of flip-flops. In this lab, you will test
the behavior of several flip-flops and you will connect several logic gates together to create simple
sequential circuits.

5.2 Software tools Requirement

Equipments:

Computer with Modelsim Software

Specifications:

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Modelsim - 5.7c, Xilinx - 6.1i.

Algorithm

STEP 1: Open ModelSim XE II / Starter 5.7C

STEP 2: File -> Change directory -> D:\<register number>

STEP 3: File -> New Library -> ok

STEP 4: File -> New Source -> Verilog

STEP 5: Type the program

STEP 6: File -> Save -><filename.v>

STEP 7: Compile the program

STEP 8: Simulate -> expand work -> select file -> ok

STEP 9: View -> Signals

STEP 10: Select values -> Edit -> Force -> input values

STEP 11: Add -> Wave -> Selected signals -> Run

STEP 12: Change input values and run again

51
5.3 Flip-Flops Logic diagram and their properties
Flip-flops are synchronous bitable devices. The term synchronous means the output changes state
only when the clock input is triggered. That is, changes in the output occur in synchronization with the
clock.

A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the stored
bit. Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the behavior
of various flip-flop types before proceeding further.

All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of
inputs and in the response invoked by different value of input signals. The four types of flip-flops are
defined in the Table 5.1. Each of these flip-flops can be uniquely described by its graphical symbol,
its characteristic table, its characteristic equation or excitation table. All flip-flops have output signals Q and
Q'.

Flip-
Flip-Flop Characteristic
Flop Characteristic Table Excitation Table
Symbol Equation
Name

S R Q(next)
Q Q(next) S R
0 0 Q Q(next) = S + R'Q 0 0 0 X
SR 0 1 0 0 1 1 0
SR = 0 1 0 0 1
1 0 1
1 1 X0
1 1 ?

J K Q(next) Q Q(next) J K
0 0 Q 0 0 0 X
JK 0 1 0 Q(next) = JQ' + K'Q 0 1 1 X
1 0 1 1 0 X1 1
1 Q' 1 1 X0

Q Q(next) D
D Q(next) 0 0 0
D 0 0 Q(next) = D 0 1 1
1 1 1 0 0
1 1 1

Q Q(next) T
T Q(next) 0 0 0
T 0 Q Q(next) = TQ' + T'Q 0 1 1
1 Q' 1 0 1
1 1 0

Table 5.3 Flip-flops and their properties

52
D- Flip Flop

JK Flip Flop

T Flip Flop

T Flip Flop

53
5. 4 Pre-lab Questions

1. Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop.

2. How does a JK flip-flop differ from an SR flip-flop in its basic operation?

3. Describe the basic difference between pulse-triggered and edge-triggered flip-flops.

4. What is use of characteristic and excitation table?

5. What are synchronous and asynchronous circuits?

6. How many flip flops due you require storing the data 1101?

Verilog prohram

S-R Flip Flop

Behavioral Modelling Structural Modelling Dataflow Modelling

modulesr_df (s, r, q, q_n); module sr_st(s,r,q,q_n); module sr_beh(s,r,q,q_n);

input s, r; input s, r; input s, r;
output q, q_n; output q, q_n; output q, q_n;
assignq_n = ~(s | q); or g1(q_n,~s,~q); regq, q_n;
assign q = ~(r | q_n); or g2(q,~r,~q_n); always@(s,r)
endmodule endmodule begin
q,n = ~(s|q);
assign q = ~(r | q_n);
endmodule

T Flip Flop

Behavioral Modelling Structural Modelling Dataflow Modelling

module t_beh(q,q1,t,c); module t_st(q,q1,t,c); module t_df(q,q,1,t,c);

output q,q1; output q,q1; output q,q1;
inputt,c; input t,c; input t,c;
reg q,q1; wire w1,w2; and g1(w1,t,c,q);
initial assign w1=t&c&q; and g2(w2,t,c,q1);
begin assign w2=t&c&q1; nor g3(q,w1,q1);
q=1'b1; assign q=~(w1|q1); nor g4(q1,w2,q);
q1=1'b0; assign q1=~(w2|q); endmodule
end endmodule
always @ (c)
begin
if(c)
begin
if (t==1'b0) begin
q=q; q1=q1; end
else begin q=~q;
q1=~q1; end
end
end
end module

D flip flop
Behavioral Modelling Structural Modelling Dataflow Modelling

module dff_df(d,c,q,q1);
Module dff_async_reset( data, clk, module dff_df(d,c,q,q1);
input d,c;
reset ,q ); input d,c;
output q,q1;
input data, clk, reset ; output q,q1;
and g1(w1,d,c);
output q; assign w1=d&c;
and g2(w2,~d,c);
reg q; assign w2=~d&c;
nor g3(q,w1,q1);
always @ ( posedgeclk or negedge q=~(w1|q1);
nor g4(q1,w2,q);
reset) q1=~(w2|q);
endmodule
if (~reset) begin endmodule
q <= 1'b0;
end
else begin
q <= data;
end

JK flip flop
Behavioral Modelling Structural Modelling Dataflow Modelling

module jk(q,q1,j,k,c); module jkflip_df (j,k,q,qn); module jkflip_st(j,k,q,qn);

output q,q1; input j,k,q; input j,k,q;
output qn; output qn;
input j,k,c;
wire w1,w2; and g1(w1,j,~q);
reg q,q1; assign w1=~q; and g2(w2,~k,q);
initial begin q=1'b0; q1=1'b1; end assign w2=~k; or g3(qn,w1,w2);
always @ (posedge c) assign qn=(j & w1 | w2 & endmodule
begin q);
case({j,k}) endmodule
{1'b0,1'b0}:begin
q=q; q1=q1; end
{1'b0,1'b1}: begin
q=1'b0; q1=1'b1; end
{1'b1,1'b0}:begin
q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin
q=~q; q1=~q1; end
endcase
 end

Output Waveforms

D flip flop

T flip flop
RESULT

Thus the VHDL code for flip-flop was implemented and simulated using Xilinx.
EXP : Design of Counters

6.1 Introduction
The purpose of this experiment is to introduce the design of Synchronous Counters, asynchronous,ring,johnson up/down
Counter.

6.2 Software tools Requirement

Equipments:

Computer with Modelsim Software

Specifications:

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Modelsim - 5.7c, Xilinx - 6.1i.

Algorithm

STEP 1: Open ModelSim XE II / Starter 5.7C

STEP 2: File -> Change directory -> D:\<register number>

STEP 3: File -> New Library -> ok

STEP 4: File -> New Source -> Verilog

STEP 5: Type the program

STEP 6: File -> Save -><filename.v>

STEP 7: Compile the program

STEP 8: Simulate -> expand work -> select file -> ok

STEP 9: View -> Signals

STEP 10: Select values -> Edit -> Force -> input values

STEP 11: Add -> Wave -> Selected signals -> Run

STEP 12: Change input values and run again

6.3 Logic Diagram

Updown Counter

Verilog program

Up down counter

Verilog code

moduleupdown(out,clk,reset,updown);
output [3:0]out;
inputclk,reset,updown;
reg [3:0]out;
always @(posedgeclk)
if(reset) begin
out<= 4'b0;
end else if(updown) begin
out<=out+1;
end else begin
out<=out-1;
end
endmodule
Asynchronous counter & Synchronous Counters

VHDL code VHDL code

entity counter_8 is entity counter is

port(clk,en,rst:in std_logic; port(C, S : in std_logic;
count:out std_logic_vector(7 downto 0)); Q : out std_logic_vector(3 downto 0));
end counter_8; end counter;
architecture beh of counter_8 is architecture archi of counter is
signal cnt:std_logic_vector(7 downto 0); signal tmp: std_logic_vector(3 downto 0);
begin begin
process(clk,en,rst) process (C)
begin begin if (C'event and C='1') then
if(rst='0')then if (S='1') then
cnt<=(others=>'0'); tmp <= "1111"; else
elsif(clk'event and clk='1')then tmp <= tmp - 1; end if; end if;
if(en='1')then end process; Q <= tmp;
cnt<=cnt+'1';end if;end if; end archi;

end process;count<=cnt; end beh;

Output Waveform
Ring counter & Johnson counter

Logic diagram

Ring counter

Johnson counter

VHDL program

Ring counter Johnson counter

entity ring_counter is entity johnson_counter is

'0'); port (
begin DAT_O : out unsigned(3 downto 0);
RST_I : in std_logic;
DAT_O <= temp; CLK_I : in std_logic
process(CLK_I) );
begin end johnson_counter;
if( rising_edge(CLK_I) ) then architecture Behavioral of johnson_counter is
if (RST_I = '1') then signal temp : unsigned(3 downto 0):=(others =>
temp <= (0=> '1', others => '0'); '0');
 else begin
temp(1) <= temp(0); DAT_O <= temp;
temp(2) <= temp(1); process(CLK_I)
temp(3) <= temp(2); begin
temp(0) <= temp(3); if( rising_edge(CLK_I) ) then
end if; if (RST_I = '1') then
end if; temp <= (others => '0');
end process; else
end Behavioral; temp(1) <= temp(0);
temp(2) <= temp(1);
temp(3) <= temp(2);
temp(0) <= not temp(3);
end if;
end if;
end process;

end Behavioral;

Output waveform

Ring counter

Johnson counter
RESULT

Thus the Counter VHDL code were implemented and simulated by using Xilinx project navigator
EXP: Design of State machines
1.1 Introduction
The purpose of this experiment is to simulate the behavior of Moore and Mealy model

1.2 Software tools Requirement

Equipments:

Computer with Modelsim Software

Specifications:

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Softwares: Modelsim - 5.7c, Xilinx - 8.1i.

Algorithm

STEP 1: Open ModelSim XE II / Starter 5.7C

STEP 2: File -> Change directory -> D:\<register number>

STEP 3: File -> New Library -> ok

STEP 4: File -> New Source -> Verilog

STEP 5: Type the program

STEP 6: File -> Save -><filename.v>

STEP 7: Compile the program

STEP 8: Simulate -> expand work -> select file -> ok

STEP 9: View -> Signals

STEP 10: Select values -> Edit -> Force -> input values

STEP 11: Add -> Wave -> Selected signals -> Run

STEP 12: Change input values and run again

 Mealy model

Moore model

Program

VHDL Moore model Verilog Mealy model

entity mealy is module seq_dect

port (clk : in std_logic; (
reset : in std_logic; input clk, data_in, reset,
input : in std_logic; output reg data_out
output : out std_logic );
); // Declare state register
end mealy; reg [2:0]state;
// Declare states
architecture behavioral of mealy is parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4
type state_type is (s0,s1,s2,s3); --type of state = 4;
machine.
signal current_s,next_s: state_type; --current // Determine the next state
and next state declaration. always @ (posedge clk or posedge reset)
begin
begin if (reset)
state <= S0;
process (clk,reset) else
begin case (state)
if (reset='1') then S0:
current_s <= s0; --default state on reset. if (data_in)
elsif (rising_edge(clk)) then state <= S1;
current_s <= next_s; --state change. else
end if; state <= S0;
end process; S1:
--state machine process. if (data_in)
process (current_s,input) state <= S1;
begin else
case current_s is state <= S2;
when s0 => --when current state is "s0" S2:
if(input ='0') then if (data_in)
output <= '0'; state <= S3;
next_s <= s1; else
else state <= S2;
output <= '1'; S3:
next_s <= s2; if (data_in)
end if; state <= S4;
when s1 =>; --when current state is else
"s1" state <= S2;
if(input ='0') then S4:
output <= '0'; if (data_in)
next_s <= s3; state <= S1;
else else
output <= '0'; state <= S2;
next_s <= s1; endcase // case (state)
end if; end // always @ (posedge clk or posedge
reset)
when s2 => --when current state is "s2" // Output depends only on the state
if(input ='0') then always @ (state) begin
output <= '1'; case (state)
next_s <= s2; S0:
else data_out = 1'b0;
output <= '0'; S1:
next_s <= s3; data_out = 1'b1;
end if; S2:
data_out = 1'b0;
when s3 => --when current state is "s3" S3:
if(input ='0') then data_out = 1'b1;
output <= '1'; S4:
next_s <= s3; data_out = 1'b1;
 else default:
output <= '1'; data_out = 1'b0;
next_s <= s0; endcase // case (state)
end if; end // always @ (state)
end case;
end process; endmodule // moore_mac

end behavioral;

Output waveform

Mealy model

Moore model

RESULT

Thus the Moore and Mealy state machines code were implemented and simulated by using Xilinx
project navigator
EXP: Design of CMOS inverter
8.1 Introduction

To perform the functional verification of the CMOS Inverter through schematic entry

8.2 Software tools Requirement

S-Edit using cadance Tool

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Algorithm

STEP 1: Draw the schematic of CMOS Inverter using S-edit.

STEP 2: Perform Transient Analysis of the CMOS Inverter.

STEP 3: Obtain the output waveform from W-edit

STEP 4: Obtain the spice code using T-edit.

Circuit diagram of CMOS inverter

CIRCUIT USING TANNER

RESULT

Thus the functional verification of the CMOS Inverter through schematic [Link] the
output also verified successfully.
EXP: Design of Differential Amplifier
8.1 Introduction

To calculate the gain, bandwidth and CMRR of a differential amplifier through schematic entry.

8.2 Software tools Requirement

S-Edit using cadance Tool

HP Computer P4 Processor - 2.8 GHz, 2GB RAM, 160 GB Hard Disk

Algorithm

STEP 1: Draw the schematic of differential amplifier using S-edit and generate the symbol.

STEP 2: Draw the schematic of differential amplifier circuit using the generated symbol.

STEP 3: Perform AC Analysis of the differential amplifier.

STEP 4: Obtain the frequency response from W-edit.

STEP 5: Obtain the spice code using T-edit.
SCHEMATIC DIAGRAM:
RESULT

Thus the functional verification of the Differential Amplifier through

schematic entry and the output also verified successfully.
EXP: CMOS LOGIC GATES

Aim:

To Synthesize CMOS logic gates using Tanner

Description:

Diagram:

Result:
EXP: DESIGN OF ALU

Aim:
To Design an ALU and simulate using Xilinx.

PROGRAM:

module alu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[8]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
 ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end

endmodule

RESULT:
EXP: DESIGN OF UNIVERSAL SHIFT REGISTER

Aim:
To Design a universal shift register and simulate using
Xilinx.

DESCRIPTION:
PROGRAM:

module Universal_shift_reg (data_out, msb_out, lsb_out, data_in,

msb_in, lasb_in, s1, s0, clk, rst);

output [3:0] data_out; // Hold

output msb_out, lsb_out; // Serial shift from msb
input [3:0] data_in; // Serial shift from lsb
input msb_in, lsb_in; // Parallel load
input s1, s0, clk, rst;
reg data_out;

assign msb_out= data_out[3];

assign lsb_out= data-out[0];

always @ (posedge clk)

begin
if (rst) data_out<=0;
else case ({s1, s0})
0 : data_out <= data_out;
1 : data_out <= {msb_in, data_out[3:1]};
2 : data_out <= {data_out[2:0], lsb_in};
3 : data_out <= data_in;
endcase
end
endmodule

RESULT:
EXP: DESIGN OF MEMORY

Aim:
To Design a memory and simulate using Xilinx.

DESCRIPTION:

PROGRAM:

RESULT:
EXP: DESIGN OF CMOS INVERTING AMPLIFIER

Aim:
To Design and simulate a CMOS inverting amplifier.

DESCRIPTION:

RESULT:
EXP: DESIGN OF COMMON SOURCE, COMMON GATE AND COMMON

DRAIN AMPLIFIER

Aim:
To Design and simulate a CS,CG and CD amplifier.

DESCRIPTION:

COMMON SOURCE AMPLIFIER:

COMMON DRAIN AMPLIFIER:

COMMON GATE AMPLIFIER

RESULT: