8-bit Carry Select Adder using 180nm CMOS
Process Technology
June 19, 2025
1 Introduction
Addition is the heart of computer arithmetic and the arithmetic unit is often the work house of
a computational circuit. There are many ways to design adder. The ripple carry adder (RCA)
provides the most compact design but takes longer computing time. If there is N-bit RCA, the
delay is linearly proportional to N. Thus for large values of N the RCA gives highest delay of
all the adders. The carry look ahead adder (CLA) gives fast results but consumes large area.
If there is N-bit adder, CLA is fast for N4, but for large values of N its delay increases more
than other adders. The problem of the ripple-carry adder is that each adder has to wait for the
arrival of its carry-input signal before the actual addition can start. The basic idea of the carry
select adder [1] is to use blocks of two ripple carry adders, one of which is fed with a constant
0 carry-in while the other is fed with a constant 1 carry-in. Thus, both blocks can calculate in
parallel. When the actual carry-in signal for the block arrives, multiplexers are used to select
the correct one of both precalculated partial sums. Also, the resulting carry-out is selected
and propagated to the next carry select block. Hence, the time for the implementation of carry
select adder is expressed in equation 1, where tRCAcarry is the delay for the carryout of a full
adder tRCAsum is the delay for the sum of a full adder Propagation Delay (tRCAprop) = (N-1)
× (tRCAcarry + tRCAsum ) (1) From equation 1, we can see that the delay is proportional
to the length of the adder. An example of a worst case propagation delay input pattern for
a 4 bit ripple-carry adder is where the input operands change from 1111 and 0000 to 1111
and 0001, resulting in a sum changing from 01111 to 10000. The proposed carry select adder
is implemented using Cadence EDA tool [2]. The tool provides sophisticated features such
as Cadence Virtuoso Schematic Editor which provides sophisticated capabilities which speed
and ease the design, efficiently analyzes the performance of the design and Cadence Virtuoso
Layout Suite that speeds up the physical layout of the design.
2 Motivation
As the demand for high-speed computation increases, especially in processors, digital signal
processors (DSPs), and real-time embedded systems, optimizing arithmetic operations becomes
crucial. The speed of an adder directly influences the performance of these systems. Traditional
adders introduce significant delays due to sequential carry propagation. The carry select adder
architecture provides a promising solution by computing results for both carry-in possibilities
in parallel, significantly reducing the worst-case delay. The primary motivation for this project
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is to explore this architecture, understand its working, and validate its efficiency over ripple
carry adders.
3 Methodology
The 8-bit carry select adder [2] is implemented as shown in Figure [Link] adder is split into two
4-bit groups. The lower order bits a3 a2 a1 a0 and b3 b2 b1 b0 are fed into the 4-bit adder L to
produce the sum bits s3 s2 s1 s0 and a carry-out bit c4. The higher order bits a7 a6 a5 a4 and
b7 b6 b5 b4 are used as inputs to two 4-bit adders.
Figure 1: Circuit diagram for 8 bit CSA
Adder U0 calculates the sum with a carry-in of c=0, while adder U1 calculates with a carry-
in of c =1. Both sets of results are used as inputs to an array of 2:1 multiplexers. The carry bit
from the c4 of adder L is used as the MUX select signal. If c4 = 0, then the results of U0 are
sent to the output, while a value of c4 =1 selects the results of U1 for s7 s6 s5 s4. The carry-out
bit c8 is also selected by the MUX array.
3.1 Implementation of 4-Bit Adder
The 4-bit adder block used in CSA is ripple carry adder. In ripple carry adder each carry bit
from a full adder “ripples” to the next full adder [3]. The simple implementation of 4-bit ripple
carry adder is shown below in Figure 2. C0 is the input carry, x3 x2 x1 x0 and y3 y2 y1 y0
represents two 4-bit input binary numbers.C4 is the output carry and s3 s2 s1 s0 is the sum
output.
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Figure 2: 4-bit carry select adder
The ripple carry adder is designed using a full adder cell with 18-transisitors based on
transmission gate logic [4]. The full adder is constructed using an XOR gate and two 2:1
multiplexers as shown in Figure [Link] SUM (A xor B xor Cin) is formed by a multiplexer
controlled by A xor B (and complement). Examining the adder truth table reveals that when A
xor B is true, COUT=C and SUM=complement of C. When A xor B is false, COUT=A (or B)
and SUM=C.
3.2 Full adder
Figure 3: Full adder schematic
3.3 4-bit adder
Figure 4: Schematic of 4-bit Adder
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3.4 Implementation of 2:1 Multiplexer
In this design of multiplexer, two transmission gates are used as shown in Figure 4. The trans-
mission gates select input A or B on the basis of the value of the control signal S. When S=0,
Y=A and when S=1, Y=B.
Figure 5: 2:1 Multiplexer
3.4.1 2:1 MUX
Figure 6: Schematic of 2:1 Multiplexer
3.5 Implementation of 8-bit CSA
The transistor-level diagram of each block of CSA is implemented in Cadence Virtuoso schematic
editor [5]. Subsequently, the instances of all the individual blocks are integrated to form the
schematic of the complete CSA circuit. The schematic is designed and is simulated creating its
test schematic.
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Figure 7: Schematic of 8bit CSA
4 Results
The 8-bit CSA design was successfully implemented and simulated. The simulation results
showed that the output matched expected values for various input combinations, validating
the correctness of the design. When compared to a traditional 8-bit ripple carry adder, the
CSA demonstrated a reduction in propagation delay. Although the CSA design required more
area due to duplicated logic and multiplexers, the performance gain in terms of speed was
significant, making it suitable for high-speed applications where timing is critical.
Simulation Results
The 8-bit carry select adder is simulated with the supply voltage of 1.8V. Figure 10 shows the
transient response of the designed adder circuit for the following inputs:
a7 a6 a5 a4 a3 a2 a1 a0 - 11010101
b7 b6 b5 b4 b3 b2 b1 b0- 00110111
———————————————
c8 s7 s6 s5 s4 s3 s2 s1 s0 -100001100
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Figure 8: Simulation Results of 8-bit CSA
5 Conclusion
The project concluded with a successful demonstration of an 8-bit carry select adder, highlight-
ing its performance advantage over basic adder designs. By employing parallel computation
of sum and carry, the CSA significantly reduces delay without compromising the accuracy of
results. This architecture proves highly useful in ALUs and other timing-sensitive components
of digital systems. Future work could include scaling the CSA to 16-bit or 32-bit designs and
exploring hybrid adder architectures that combine carry select and carry look-ahead features.
References
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