VISVESVARAYA TECHNOLOGICAL UNIVERSITY
BELAGAVI : 590018
A Major Project Report
on
Real-Time Smart Energy Meter with Theft & Leakage
Detection
Submitted in partial fulfillment of the requirement for the award of the degree of
Bachelor of Engineering
in
Electronics and Communication Engineering
By
MAHESH K 1KT22EC034
PATIL BINDU 1KT22EC040
SANTHOSH S 1KT22EC052
VAISHNAVI D R 1KT22EC059
Under the guidance of
Dr. Chaitra A S
Professor
Dept of ECE, SKIT
SRI KRISHNA INSTITUTE OF TECHNOLOGY
Department of Electronics & Communication Engineering
2024-2025
SRI KRISHNA INSTITUTE OFTECHNOLOGY
#29, Chimney Hills, Hesaraghatta Main Road, Chikkabanavara Post, Bengaluru- 560090
(Affiliated to Visvesvaraya Technological University, Belagavi)
Department of Electronics & Communication Engineering
Certificate
Certified that the Project in BEC685 entitled “Real-Time Smart Energy Meter
with Theft & Leakage current detection” is a bonafide work carried out by Mahesh K
(1KT22EC034), Patil Bindu (1KT22EC040), Santhosh S (1KT22EC052), Vaishnavi D
R (1KT22EC059) in partial fulfillment for the award of degree of Bachelor of
Engineering in Electronics & Communication Engineering of Visvesvaraya
Technological University, Belagavi during the year 2024- 2025. It is certified that all
corrections/ suggestions indicated for internal assessments have been incorporated in the
report deposited in the departmental library. The project report has been approved as it
satisfies the academic requirements in respect of project prescribed for the Bachelor of
Engineering Degree.
Signature of Guide Signature of HOD Signature of Principal
Dr. Chaitra A S Dr. J Divya Lakshmi Dr. Mahesha K
Professor Professor & HOD Principal
Dept. of ECE, SKIT Dept. of ECE, SKIT SKIT
DECLARATION
We, Mahesh K (1KT22EC034), Patil Bindu (1KT22EC040), Santhosh S
(1KT22EC052), Vaishnavi D R (1KT22EC059) students of Bachelor of Engineering,
Electronics & Communication Engineering, Sri Krishna Institute of Technology,
Bengaluru- 90, hereby declare that the project entitled “Real-time Smart Energy Meter
with Theft & Leakage current Detection" is an authentic record of our own work carried
out under the supervision and guidance of Dr Chaitra A S , Professor, Department of
Electronics & Communication Engineering, Sri Krishna Institute of Technology,
Bengaluru. We have not submitted the matter embodied to any other University or Institution
for the award of any other degree.
Mahesh K (1KT22EC034)
Patil Bindu (1KT22EC040)
Santhosh S (1KT22EC052)
Vaishnavi D R (1KT22EC059)
ACKNOWLEDGEMENT
We express our gratitude to our institution and management for providing us with
good infrastructure, laboratory, facilities and inspiring staff, and whose gratitude was of
immense help in completion of this report successfully.
We are deeply indebted to Dr. Mahesha K, Principal, Sri Krishna Institute of
Technology, Bangalore, who has been a constant source of enthusiastic inspiration to steer
us forward.
We heartily thank Dr. J Divya Lakshmi , HOD, Department of Electronics &
Communication Engineering, Sri Krishna Institute of Technology Bangalore, for her
valuable support and for rendering us resources for this project work.
We specially thank Dr. Chaitra A S , Professor, Department of Electronics &
Communication Engineering, Sri Krishna Institute of Technology who guided us with
valuable suggestions in completing this project at every stage.
Also, we wish to express deep sense of gratitude for project coordinator Mr. Sathish
S , Assistant Professor, Department of Electronics & Communication Engineering, Sri
Krishna Institute of Technology for her support and advice during the course of this pre-final
year project.
We would like to express our sincere thanks and heartfelt gratitude to our
beloved Parents, Respected Professors, Classmates, Friends, and juniors for their
indispensable help at all times.
Last but not the least our respectful thanks to the Almighty.
Mahesh K (1KT22EC034)
Patil Bindu (1KT22EC040)
Santhosh S (1KT22EC052)
Vaishnavi D R (1KT22EC059)
ABSTRACT
In recent years, the increasing demand for electricity and the rising concerns over energy
theft and wastage have made it necessary to upgrade conventional energy metering systems.
The traditional meters lack capabilities like real-time monitoring, prepaid control, theft
detection, and remote communication. To address these challenges, this project presents a
“Real-Time Smart Energy Meter with Theft & Leakage Current Detection” system that
integrates advanced features such as prepaid billing, GSM-based alerts, leakage current
detection, and unauthorized usage prevention.
The proposed system is built around the ESP32 microcontroller, which serves as the brain of
the smart meter. This data is used to deduct the energy cost from the prepaid balance. The
GSM module (SIM800L) sends SMS alerts to the user regarding low balance, power
disconnection, recharge status, theft detection, and leakage current.
The system incorporates theft detection by comparing input (grid) and output (load) currents.
If a significant difference is found, it triggers an alert. Similarly, leakage current is identified
by comparing live and neutral currents any mismatch suggests current is flowing through an
unintended path, posing a safety risk. The energy usage, remaining balance, and system
status are displayed in real time on a 16x2 LCD screen. Recharge of the meter can be done
via SMS commands, RFID tags, or UPI-based QR code systems, making the platform
flexible and user-friendly. In addition, the system integrates a relay module to automatically
disconnect the power when the balance reaches zero, and reconnects after a successful
recharge.
For enhanced sustainability, the system is also designed to work with a solar power module,
allowing partial energy usage from renewable sources. Cloud-based platforms such as
Firebase or Thingspeak can be used to store and visualize live energy data for remote
monitoring. This smart metering solution offers a robust, cost-effective, and energy-efficient
platform for both domestic and industrial applications. By enabling automated billing, fault
detection, and secure communication, it promotes responsible energy usage and supports the
vision of smart grid and smart city development.
.
i
CONTENTS
[Link] Chapter Name [Link]
i Abstract i
ii Contents ii
1 Chapter 1-Introduction 1
1.1 Problem Statemnet 2
1.2 Objectives 2
2 Chapter 2- Literature Survey
2.1 Perfomance Evaluation of 6T SRAM 3
Cell Using 90nm Technology
2.2 Improving the SRAM Layout Design 3
using Cadence Technology
2.3 6T SRAM cell design using CMOS at 3
different technology nodes
2.4 Design and performance analysis of 6T, 4
8T, 10T SRAM cells in 45nm technology
2.5 Design and performance analysis of 6T 4
SRAM cell in different technologies and
nodes
2.6 Design of 6T SRAM cell 4
2.7 Design and comparative analysis of 6T 5
SRAM bitcell using 45nm, 90nm, and
180nm technology
2.8 Novel low power cross-coupled FET- 5
based sense amplifier design for high-speed
SRAM circuits
2.9 Perfomance optimization of fabricated 5
nanosheet GAA CMOS transistor and 6T-
SRAM cells via source/drain doping
engineering
2.10 Design of high-speed, low-power 6
sensing circuits for nano-scale embedded
memory
2.11 Summary 6
CHAPTER 1
INTRODUCTION
VLSI Design of SRAM
CH
A
P
T
E
R
1
INTRODUCTION
In the rapidly changing world of semiconductor technology, memory design remains a key component in
creating efficient digital systems. Among the various types of memory, Static Random Access Memory
(SRAM) stands out due to its high speed, low latency, and compatibility with CMOS technology. SRAM
is widely utilized in cache memory, register files, and embedded memory blocks found in
microprocessors and system-on-chip (SoC) architectures. As the demand for portable, battery-operated,
and high-performance devices grows, there is a pressing need to develop SRAM cells that are not only
power-efficient and area-optimized but also stable and reliable under diverse environmental and
electrical conditions. The 6-transistor (6T) SRAM cell is a popular choice in VLSI memory design,
thanks to its balanced trade-offs regarding stability, performance, and silicon area. This structure consists
of two cross-coupled inverters for data storage and two access transistors that facilitate read and write
operations. However, as technology continues to scale and performance demands become more
aggressive, ensuring the robust operation of SRAM cells while minimizing power consumption and area
presents significant challenges. Key factors such as power dissipation, leakage currents, access time, and
static noise margin (SNM) are crucial in assessing the effectiveness of an SRAM design. This project
focuses on designing, simulating, and analyzing a 6T SRAM cell using the Cadence Virtuoso design
suite, specifically utilizing the gpdk180nm and gpdk90nm CMOS technology nodes. The work
encompasses schematic-level design, circuit-level simulations (both DC and transient), power analysis,
layout implementation, and SNM evaluation through the butterfly curve technique. Additionally, the
design process investigates methods like the stacking effect to minimize leakage and dynamic power,
thereby enhancing overall energy efficiency. Employing Cadence Virtuoso offers a professional-grade
environment to grasp and execute real-world VLSI design flows, which include schematic entry,
simulation using the Analog Design Environment (ADE), layout generation, DRC/LVS checks, and
performance evaluation. By comparing the characteristics of the same SRAM design across gpdk180 and
gpdk90, the project aims to analyze the effects of scaling on power consumption, layout area, and noise
resilience. Ultimately, this project will deliver a comprehensive understanding of low-power SRAM
design, transistor-level optimization, and the behavior of CMOS memory cells. It also lays the
groundwork for future developments, such as array implementation or advanced memory
characterization, while providing students with practical experience in industry-relevant tools and
methodologies.
[Link], SKIT
1 2024-2025
VLSI Design of SRAM
1. PROBLEM STATEMENT
Design and implement an optimized SRAM cell using Cadence and Synopsys tools, focusing on low
power consumption, high-speed operation, and improved stability for VLSI applications.
2. OBJECTIVES
Design and analyze a 6T SRAM cell using gpdk180nm and gpdk90nm in Cadence Virtuoso.
To evaluate power, area, and SNM performance across both technology nodes.
[Link], SKIT 2 2024-2025
CHAPTER 2
LITERATUR
E SURVEY
VLSI Design of SRAM
CHAPTER 2
LITERATURE SURVEY
In seeking to improve performance and power saving in memory design, several authors have
suggested enhancements to the structure and behavior of the 6T SRAM cell based on alternative
CMOS technology nodes. Each paper discussed here contributes to knowledge regarding the power-
performance-area-stability trade-offs, all of which are considerations relevant to design choices for
this project.
2.1. Performance Evaluation of 6T SRAM Cell Using 90nm Technology
The study by Dr. M. Premalatha and V. Lavanya (2022) significantly influences the direction of our
project by highlighting the importance of Static Noise Margin (SNM) analysis using butterfly curves
in 6T SRAM cell evaluation. Their approach demonstrates how SNM serves as a critical metric for
understanding cell stability during both read and hold operations. By adopting their methodology, we
are able to structure our simulation workflow in Cadence ADE more effectively.
Takeaway for our project: The present work affects our approach directly towards applying SNM
analysis by using butterfly curves. Their evaluation method of read and hold stability enables us to
establish our simulation strategy in ADE.
2.2. Improving the SRAM Layout Design using Cadence Virtuoso
The study by Nandhini R. N., Venkat A. K., and Bitan De M. (2025) focuses on improving SRAM
layout design using Cadence Virtuoso. The authors discuss techniques to optimise the layout for
better performance and reduced area, making effective use of the Cadence tool’s features. Their
approach highlights the impact of layout efficiency on overall SRAM performance, guiding our own
layout strategy to prioritise area optimisation and design rule compliance within the Virtuoso
environment.
Takeaway for our project: By implementing strategic transistor sizing, power grid optimization, and
efficient routing as suggested in the paper, we can significantly enhance our SRAM design using
Cadence Virtuoso, achieving reduced area, lower power leakage, and improved performance.
2.3. 6T SRAM Cell Design Using CMOS at Different Technology Nodes
The study titled 6T SRAM Cell Design Using CMOS at Different Technology Nodes (2024),
published in the Journal of Engineering Sciences, presents the design and analysis of a 6T SRAM cell
using 180nm, 90nm, and 45nm CMOS technologies. The results show that while the 45nm node
offers reduced power consumption and area, the 180nm node provides better Static Noise Margin
(SNM), contributing to higher stability. Based on their observations, the authors recommend 90nm as
a balanced technology node, offering a trade-off between power efficiency, area, and stability. This
analysis supports our decision to focus on the 90nm node, as it aligns with our goal of achieving both
reliable operation and design efficiency in our SRAM implementation.
.
[Link], SKIT 3 2024-2025
VLSI Design of SRAM
Takeaway for our project: This paper confirms our choice to develop and compare 6T SRAM cells
at both 90nm and 180nm, with the flexibility to assess power vs. stability trade-offs and select the best
node to use in low-power, reliable memory design.
2.4. Performance Analysis of 6T, 8T, and 10T SRAM Cells in 45nm Technology
The study by Navin, S., Kiruthika, M., and Deepan (2024) analyzes the performance of 6T, 8T, and
10T SRAM cells implemented in 45nm technology. Their results show that the 6T cell excels in read
power efficiency, whereas the 10T cell outperforms in write power, delay, and overall performance
metrics. Additionally, the authors verify design rule checks (DRC) and layout versus schematic (LVS)
to ensure the correctness of the designs. This comparison provides valuable insights for our project by
highlighting the trade-offs between different SRAM topologies, informing our focus on optimizing
power and speed while maintaining design integrity.
Takeaway for our project: Although our design remains centered on the 6T architecture, this research
encourages us to look at performance-improving methods such as stacking, while enjoying the area-
performance trade-off.
2.5. Design and Performance Analysis of 6T SRAM Cell in Different Technologies
and Nodes
The study by Uma Maheshwar and Y. Sharvani (2022) compares 6T SRAM cell designs implemented
using different technologies—CMOS, FinFET, CNTFET, and GNRFET—across technology nodes
ranging from 16nm to 32nm. Their analysis reveals that CNTFET and GNRFET based SRAM cells
outperform traditional CMOS designs in terms of Static Noise Margin (SNM) and power consumption,
indicating their strong potential for future low-power, high-performance SRAM applications. This work
provides valuable insights for our project by highlighting alternative device technologies that could
enhance SRAM stability and efficiency beyond conventional CMOS approaches.
Takeaway for our project: Even though we are working on planar CMOS right now, this paper gives
us directions for the future that we can explore in later stages. It also highlights the significance of
SNM and low leakage, which are important parameters for evaluation in our Cadence design.
2.6. Design of 6T SRAM Cell
The paper by Nayana K. S. and Vijay B. M. (2022) presents the design of a 6T SRAM cell using
180nm, 90nm, and 45nm CMOS technologies within the Cadence Virtuoso environment. Their
analysis covers key performance parameters such as delay, power consumption, and Static Noise
Margin (SNM). The results indicate that smaller technology nodes, particularly 45nm, offer
improvements in speed and power efficiency, although trade-offs related to stability are also observed.
This study informs our project by providing a clear comparison across technology nodes, helping us
understand the benefits and challenges associated with scaling SRAM designs.
Takeaway for our project: This article serves as the basis for our choice to use both gpdk180 and
gpdk90 within Cadence Virtuoso in order to analyze performance trade-offs. Their SNM and power
observations inform the way we will seek to optimize stability and efficiency in our design.
[Link], SKIT 4 2024-2025
VLSI Design of SRAM
2.7. Design and Comparative Analysis of 6T SRAM Bitcell Using 45nm, 90nm, and
180nm Technology
The study by Prasanta Kumar Panda and Manish Kumar Rout (2021) presents a design and
comparative analysis of a 6T SRAM bitcell across 45nm, 90nm, and 180nm technology nodes.
Additionally, the authors propose a 10T SRAM cell architecture aimed at achieving lower power
consumption and higher stability compared to the traditional 6T design. Their exploration of
alternative SRAM topologies provides valuable insights for low-power design strategies, making this
work relevant to our project as it highlights potential approaches to enhance both power efficiency
and reliability in SRAM cells.
Takeaway for our project: This supports our proposal to simulate our 6T SRAM design on both
gpdk180 and gpdk90 nodes. We will keep an eye on write delay, leakage, and VDD sensitivity in our
simulations, as indicated in this paper.
2.8. Novel Low Power Cross-Coupled FET-Based Sense Amplifier
Design for High-Speed SRAM Circuits
The paper by G. Lakshmi Priya, Puneet Saran, and Shikhar Kumar Padhy (2023) introduces a novel
low- power, high-speed cross-coupled FET-based sense amplifier designed for SRAM circuits,
implemented and simulated using LTSpice at the 180nm technology node. The authors apply various
power reduction techniques to significantly improve sensing delay and reduce power consumption,
enhancing the overall efficiency of SRAM read operations. This work provides useful insights for our
project by demonstrating effective methods to optimize sense amplifier performance, which is critical
for achieving fast and energy-efficient SRAM designs..
Takeaway for our project: Provides a practical design approach for improving SRAM read speed and
reducing power, useful for optimizing 180nm and 90nm SRAM cells in your project
2.9. Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors
and 6T-SRAM Cells via Source/Drain Doping Engineering
The study by Xuexiang Zhang, Qingkun Li, and Lei Cao (2025) focuses on the performance
optimization of gate-all-around (GAA) nanosheet CMOS transistors and 6T SRAM cells through
advanced source/drain doping engineering techniques, specifically Spacer-Based Doping Formation
(SBF) and Lightly Doped Drain (LDD) methods. Their results demonstrate a notable 14.9%
improvement in Static Noise Margin (SNM) alongside a significant reduction in leakage current,
highlighting the effectiveness of these doping strategies in enhancing both stability and power
efficiency. This research offers valuable guidance for our project by showcasing how precise doping
engineering can be leveraged to optimize the reliability and performance of advanced SRAM designs.
Takeaway for our project: Demonstrates how device-level doping engineering can enhance SRAM
stability and reduce power, important for future scaling and performance improvements
[Link], SKIT 5 2024-2025
VLSI Design of SRAM
2.10. Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded
Memory
The study by Sangheon Lee, Gwanwoo Park, and Hanwool Jeong (2024) reviews high-speed, low-
power sensing circuits tailored for nanoscale embedded SRAM memories. The authors emphasize the
importance of reducing offset voltage (VOS) in sense amplifiers to enhance both speed and power
efficiency during SRAM read operations. In particular, the paper discusses the use of Schmitt trigger-
based sense amplifiers, which provide improved stability and low-power performance. These insights
are valuable for our project as they highlight effective sensing circuit designs that can contribute to
faster, more reliable, and energy-efficient SRAM read functionality.
Takeaway for our project: Highlights the critical role of offset voltage reduction and sensing circuit
design for fast and low-power SRAM operation, relevant for deep-submicron technologies.
2.11. Summary
The literature review for this project is based on ten significant studies that explore various approaches
to optimizing the design and performance of 6T SRAM cells using CMOS technology across multiple
technology nodes. These studies collectively provide a comprehensive understanding of power-
performance-area-stability trade-offs that are crucial in SRAM design. Collectively, these studies
emphasize the importance of SNM analysis, power optimization, layout efficiency, and advanced
CMOS nodes for achieving robust, power-efficient SRAM designs. The findings support our objective
to implement 6T SRAM cells in 90nm and 180nm nodes using Cadence Virtuoso while exploring
power-performance trade-offs through transistor sizing, layout optimization, and SNM analysis.
[Link], SKIT 6 2024-2025
