LESSON PLAN

DEPARTMENT: ELECTRONICS AND COMMUNICATION ENGINEERING NAME OF THE STAFF : G.VIJI

SEMESTER : IV SUBJECT CODE & NAME: CS3351/DIGITAL PRINCIPLE AND
COMPUTER ORGANIZATION
ACADEMIC YEAR: 2024-2025
CUMULATI
S DATE LECTURE OBJECTIVE PERIODS MODE MEDIA VE
L NOTE REQUIRED NO OF
N PERIODS
O
0 Introduction to Course To understand the concepts of course objectives & Course Outcomes 0
Objectives & Course
Outcomes
(CO1,CO2,CO3,CO4&CO5)
UNIT- 1 TOPIC: COMBINATIONAL LOGIC TARGET DATE: PERIODS: 11
1 To implement basic logic functions (AND, 1 Lecture Chalk and board 1
Combinational Circuits OR, NOT, XOR, etc.) required in digital
systems.
2 To reduce complex Boolean functions into 2 PPT Projector 3
Karnaugh Map simpler expressions without changing the
output behavior.
3 1 Lecture Chalk and board 4
To determine what a given circuit does by
Analysis and Design
examining its structure and logic
Procedures
components.

4 1 Lecture Chalk and board 5

To ensure high-speed and accurate binary
Binary Adder
addition in real-time computing systems.

5 To minimize the number of logic gates, 1 PPT Projector 6

Subtractor – propagation delay, and power consumption
in digital subtraction circuits.
6 To produce a carry output when the sum 1 7
Decimal Adder exceeds 9, allowing multi-digit decimal
addition.
7 Magnitude Comparator To compare binary numbers of n-bits 1 Lecture Chalk and board 8
(e.g., 4-bit, 8-bit, etc.), with the ability to
 cascade comparators for larger bit sizes.
8 To decode n-bit binary input into 2ⁿ 1 Lecture Chalk and board 9
Decoder – Encoder distinct outputs, where only one output is
active at a time.
9 To select one input from multiple inputs 1 Lecture Chalk and board 10
Multiplexers - Demultiplexers
based on control (select) signals.
Revision & Discussion of 2 Possible questions 1 Discussi Chalk and board 11
1 marks and 13 marks possible ons
0 questions
UNIT- II TOPIC: SYNCHRONOUS SEQUENTIAL LOGIC TARGET DATE: PERIODS: 12
1 1 Lecture Chalk and board 12
To analyze circuits whose output changes
Introduction to Sequential
with time, based on clock signals and
Circuits
input sequences.

2 To store a single bit of binary information 1 PPT Projector 13

Flip-Flops
(either 0 or 1).
3 1 PPT Projector 14
operation and excitation
To define how a flip-flop responds to
tables,
different input combinations.
4 1 Lecture Chalk and board 15
To ensure that flip-flops change states only
Triggering of FF at specific moments, avoiding unwanted
changes.

5 2 Lecture Chalk and board 17

To determine how the circuit responds to
Analysis and design of
inputs and clock signals across different
clocked sequential circuits
time intervals.

6 To represent the behavior of systems 1 Lecture Chalk and board 18

Design – Moore/Mealy
where output depends on the sequence of
models,
inputs and states
7 state minimization, state To simplify the design by eliminating 1 Lecture Chalk and board 19
assignment, redundant or equivalent states.
8 To build a working circuit that performs 1 Discussi Chalk and board 20
the desired logic or function based on the ons
circuit implementation
design specifications.

9 To provide quick access to data compared 1 Lecture Chalk and board 21

Registers to main memory, improving processing
speed.
1 To count the number of clock pulses, 2 Lecture Chalk and board 23
0 Counters. external events, or operations occurring
over time.
UNIT- III TOPIC: COMPUTER FUNDAMENTALS TARGET DATE: PERIODS: 10
1 To accept data and instructions from 1 Lecture Chalk and board 24
Functional Units of a Digital external sources and convert them into a
Computer: form the computer can process.

2 Von Neumann Architecture 1 Lecture Chalk and board 25

To store both instructions and data in
the same memory space, simplifying
hardware design.

3 Operation and Operands of To define the actual data values or the 1 Lecture Chalk and board 26
Computer Hardware locations (registers or memory) that are to
Instruction be used in the operation.
4 To serve as a contract between the 1 Lecture Chalk and board 27
Instruction Set hardware design and the software
Architecture (ISA): (especially compilers and operating
systems).
5 To read data from a memory location and 1 Lecture Chalk and board 28
Memory Location, Address
transfer it to the CPU or register.
and Operation
6 To ensure instructions are executed in the 1 Lecture Chalk and board 29
Instruction and Instruction
correct sequence, as written in the
Sequencing
program.
7 Allow instructions to access operands from 1 Lecture Chalk and board 30
Addressing Modes, different sources: registers, memory,
constants, or immediate values.
8 1 Lecture Chalk and board 31
To represent each instruction as a binary
Encoding of Machine
pattern that the processor can decode and
Instruction
execute.

9 To allow compilers to generate optimized 1 Lecture Chalk and board 32

Interaction between Assembly
assembly code, which is then converted
and High Level Language.
into machine code.
10 Revision & Discussion of 2 Possible questions 1 Discussi Chalk and board 33
marks and 13 marks possible ons
questions
UNIT- IV TOPIC: PROCESSOR TARGET DATE: PERIODS: 9
1 1 Lecture Chalk and board 34
To convert high-level program logic into
Instruction Execution
low-level hardware operations.

2 To carry out fetch, decode, execute, 1 Lecture Chalk and board 35

– Building a Data Path memory access, and write-back
operations using dedicated hardware.
3 To generate the sequence of control 1 Lecture Chalk and board 36
Designing a Control Unit signals required to fetch, decode, and
execute each instruction correctly.
4 Hardwired Control, To achieve high-speed control signal 1 Lecture Chalk and board 37
generation through direct hardware
connections (no need to fetch
microinstructions).
5 To decode and execute machine 1 Assignm Presentation 38
Microprogrammed Control instructions through a predefined ent through Projector
sequence of micro-operations
6 To execute more instructions per unit 1 Lecture Chalk and board 39
Pipelining
time by overlapping the execution stages.
7 To minimize pipeline stalls or bubbles 1 Lecture Chalk and board 40
Data Hazard that reduce CPU performance due to
unresolved hazards.
8 To detect when a branch instruction 1 Lecture Chalk and board 41
creates uncertainty in the instruction
Control Hazards.
pipeline and apply methods to avoid or
minimize stalls.
9 Revision & Discussion of 2 Possible questions 1 Discussi Chalk and board 42
marks and 13 marks possible ons
questions
UNIT- V TOPIC: MEMORY AND I/O TARGET DATE: PERIODS: 10
1 To design systems where data flows 1 Lecture Chalk and board 43
Memory Concepts and
efficiently between different memory
Hierarchy
levels without unnecessary delays.
2 Memory Management – To provide faster access to frequently 1 Assignm Presentation 44
Cache Memories: used data, minimizing the delay caused by ent through Projector
slower main memory (RAM).
3 1 Lecture Chalk and board 45
Mapping and Replacement To provide a systematic method to map
Techniques memory addresses to cache lines.

4 1 Lecture Chalk and board 46

To enable techniques like paging and
Virtual Memory segmentation for flexible and dynamic
memory allocation.

5 To free the CPU from handling data 1 Lecture Chalk and board 47
DMA transfer tasks, allowing it to perform other
computations.
6 To free up the CPU by using efficient 1 Lecture Chalk and board 48
I/O
access methods like DMA or interrupts,
– Accessing I/O:
reducing wait times.
7 To send data bit-by-bit over a single line, 1 Lecture Chalk and board 49
Parallel and Serial Interface ideal for long-distance, low-pin-count
connections.
8 To handle multiple I/O devices 1 Lecture Chalk and board 50
Interrupt I/O efficiently, each using its own interrupt
request (IRQ) line.
 9 To provide a universal interface for 1 Lecture Chalk and board 51
Interconnection Standards:
connecting various devices to computers
USB,
and embedded systems.
10 To provide faster data rates than older 1 Lecture Chalk and board 52
SATA
technologies like PATA (Parallel ATA).

Staff Acad. Coordinator HOD VP Principal Director (Acad)