Scribd
Upload
20 views1 page

UVM Packet Sequence Class in SystemVerilog

The document contains the source code for a SystemVerilog class named 'packet_sequence' designed for use in UVM-based verification. It defines a sequence that generates a specified number of packet transactions, with methods for starting and managing the sequence. The class is licensed under the GNU Lesser General Public License and is part of a course on System and Functional Verification at UCSC Silicon Valley Extension.

Uploaded by

kaushlesh sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
20 views1 page

UVM Packet Sequence Class in SystemVerilog

The document contains the source code for a SystemVerilog class named 'packet_sequence' designed for use in UVM-based verification. It defines a sequence that generates a specified number of packet transactions, with methods for starting and managing the sequence. The class is licensed under the GNU Lesser General Public License and is part of a course on System and Functional Verification at UCSC Silicon Valley Extension.

Uploaded by

kaushlesh sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

C:\Users\kaushlesh\Downloads\ethernet_10ge_mac_SV_UVM_tb-master\scrib\packet_sequence.

sv 27 July 2025 08:18 PM


//////////////////////////////////////////////////////////////////////
// //
// File name : packet_sequence.sv //
// Author : G. Andres Mancera //
// License : GNU Lesser General Public License //
// Course : System and Functional Verification Using UVM //
// UCSC Silicon Valley Extension //
// //
//////////////////////////////////////////////////////////////////////
`ifndef PACKET_SEQUENCE__SV
`define PACKET_SEQUENCE__SV

`include "[Link]"

class packet_sequence extends uvm_sequence #(packet);

int unsigned num_packets = 100;

`uvm_object_utils(packet_sequence)

function new(input string name="packet_sequence");


[Link](name);
`uvm_info( get_name(), $sformatf("Hierarchy: %m"), UVM_HIGH )
endfunction : new

virtual task body();


repeat (num_packets) begin
`uvm_do(req);
end
endtask : body

virtual task pre_start();


if ( starting_phase != null )
starting_phase.raise_objection( this );
uvm_config_db #(int unsigned)::get(null, get_full_name(), "num_packets", num_packets);
endtask : pre_start

virtual task post_start();


if ( starting_phase != null )
starting_phase.drop_objection( this );
endtask : post_start

endclass : packet_sequence

`endif // PACKET_SEQUENCE__SV

-1-

You might also like