CHANGES MADE
4/29/2024
DC-SCI Pin Definition
The
The DC-SCI
contactconnector
sequence pinout includes
for each the single
pin indicates name in
the order (preferred
which theboard net name
pins make thatbetween
contact include functional and the
the HPM and directional
DC-SCM.nome
The
lengths, single
required to be node usages,
long pins voltage,
or 1st mate. direction, typicalPRSNT1_N
The PRSNT0_N/ usages andpins
dualand
node usage. pins are required to be short pins or 2nd
P12V_AUX
remaining pins indicated as 2nd mate can be flexibly assigned as long pins/1st mate if dictated by design or DFM requirements
Multi-function DC-SCI pins list the functions in order starting with the most typical expected usage.
When multiple voltages are listed for a signal, they map the respective alternate pin function order.
DC-SCI Signal
The following sectionsDescriptions
provide the signal descriptions of signals through the DC-SCI.
The signal names are constructed using the notation of:
function_(bus source)_(signal source)_(signal destination)_Instance#_Node#_Polarity
Node 1 omits the Node #. Functions with only 1 instance do not include 0. Polarity of active low uses the *_N naming.
Note: Follow device datasheet recommendations to appropriately terminate un-used signals on the DC-SCM.
Abbreviation Definition:
Symbol Description
_N or # Denotes active low signal
Input Input to DC-SCM
Output Output from DC-SCM
InOut At least one of the functions is a bidirectional signal
Sync to latest DC-SCI Rev 2.1 Ver 1.1 (dated 4/8/24)
HPM Common Circuit Design Spec Type 1. Scope:1-4S monolithic server; No Dual Node support
The single pin functions supported are in bold.
Pins with no function used have no function highlighted in bold. Verion 1.0 4/298/2024 Synced to
Single function pins that are not used by HPM or SCM are NC on the respective board(s).
Side A Gold Single Node Primary / Voltage Direction Single Node Lowest Side B Gold
Finger Alt function(if applicable) single/dual DC-SCM Supported Power State: Finger
view G3, Pre-STBY, STBY,
S5, S0
OA1 1 GND G3 OB1 1
OA2 0.5 PCIE_HPMROOT_SCM_HPM_0_DN / output / S0 (PCIe) OB2 0.5
USB3_SCMHOST_SCM_HPM_2_DN output S5 (BMC USB3)
S0 (Host USB3)
OA3 0.5 PCIE_HPMROOT_SCM_HPM_0_DP / output / S0 (PCIe) OB3 0.5
USB3_SCMHOST_SCM_HPM_2_DP output S5 (BMC USB3)
S0 (Host USB3)
OA4 1 GND G3 OB4 1
OA5 0.5 PCIE_HPMROOT_SCM_HPM_1_DN / PCIe / output/ S0 (PCIe) OB5 0.5
LTPI_SCM_HPM_CLK_2_DN / LTPI / output/ S5( LTPI)
DISPLAYPORT_SCM_HPM_LANE0_DN DP output S5 (DP)
OA6 0.5 PCIE_HPMROOT_SCM_HPM_1_DP / PCIe / output/ S0 (PCIe) OB6 0.5
LTPI_SCM_HPM_CLK_2_DP / LTPI / output/ S5( LTPI)
DISPLAYPORT_SCM_HPM_LANE0_DP DP output S5 (DP)
OA7 1 GND G3 OB7 1
OA8 0.5 PCIE_HPMROOT_SCM_HPM_2_DN / output / S0 (PCIe) OB8 0.5
SGMII_SCM_HPM_DN output S5 (SGMII)
OA9 0.5 PCIE_HPMROOT_SCM_HPM_2_DP / output / S0 (PCIe) OB9 0.5
SGMII_SCM_HPM_DP output S5 (SGMII)
OA10 1 GND G3 OB10 1
OA11 0.5 PCIE_HPMROOT_SCM_HPM_3_DN / PCIe / output / S0 (PCIe) OB11 0.5
LTPI_SCM_HPM_DATA_2_DN / LTPI / output/ S5 (LTPI 2)
DISPLAYPORT_SCM_HPM_LANE1_DN DP output S5(DP)
OA12 0.5 PCIE_HPMROOT_SCM_HPM_3_DP / PCIe / output / S0 (PCIe) OB12 0.5
LTPI_SCM_HPM_DATA_2_DP / LTPI / output/ S5 (LTPI 2)
DISPLAYPORT_SCM_HPM_LANE1_DP DP output S5(DP)
OA13 1 GND G3 OB13 1
OA14 0.5 PECI_HPM_SCM / GPIO 0.85-1.21 inout S0 OB14 0.5
A1 0.5 P12V_AUX input Pre-STBY B1 0.5
A2 0.5 P12V_AUX input Pre-STBY B2 0.5
A3 0.5 P12V_AUX input Pre-STBY B3 0.5
A4 0.5 P12V_AUX input Pre-STBY B4 0.5
A5 1 GND G3 B5 0.5
A6 1 GND G3 B6 0.5
A7 0.5 PRSNT1_HPM_SCM_N 0 input Pre-STBY B7 0.5
A8 0.5 JTAG_SCMCNTRL_TCK 3.3 output STBY B8 0.5
A9 0.5 JTAG_SCMCNTRL_TDO 3.3 input STBY B9 0.5
A10 0.5 JTAG_SCMCNTRL_TDI 3.3 output STBY B10 0.5
A11 0.5 JTAG_SCMCNTRL_TMS 3.3 output STBY B11 1
A12 0.5 JTAG_SCMCNTRL_TRST_N / GPIO 3.3 output / inout STBY B12 0.5
A13 0.5 SCM_HPM_STBY_RST_N 3.3 output STBY B13 0.5
A14 0.5 SCM_HPM_STBY_EN 3.3 output Pre-STBY B14 0.5
A15 0.5 I2C_3V3_0_SCL 3.3 inout Pre-STBY B15 0.5
A16 0.5 I2C_3V3_0_SDA 3.3 inout Pre-STBY B16 0.5
A17 0.5 I2C_3V3_1_SCL 3.3 inout S5 B17 0.5
A18 0.5 I2C_3V3_1_SDA 3.3 inout S5 B18 0.5
A19 1 GND G3 B19 1
A20 0.5 LTPI_SCM_HPM_DATA_DN output S5 B20 0.5
A21 0.5 LTPI_SCM_HPM_DATA_DP output S5 B21 0.5
A22 1 GND G3 B22 1
A23 0.5 LTPI_SCM_HPM_CLK_DN output S5 B23 0.5
A24 0.5 LTPI_SCM_HPM_CLK_DP output S5 B24 0.5
A25 1 GND G3 B25 1
A26 0.5 I2C_3V3_2_SCL 3.3 inout S5 B26 0.5
A27 0.5 I2C_3V3_2_SDA 3.3 inout S5 B27 0.5
A28 0.5 PCIE_HPM_SCM_PERST_N 3.3 input S0 B28 0.5
A29 1 GND G3 B29 1
A30 0.5 PCIE_HPMROOT_SCM_HPM_4_DN output S0 B30 0.5
A31 0.5 PCIE_HPMROOT_SCM_HPM_4_DP output S0 B31 0.5
A32 1 GND G3 B32 1
A33 0.5 PCIE_SCMROOT_SCM_HPM_DN / output / S5 (PCIe) B33 0.5
USB3_SCMHOST_SCM_HPM_1_DN output S5(BMC USB3) or
S0(HPM domain USB3)
A34 0.5 PCIE_SCMROOT_SCM_HPM_DP / output / "" B34 0.5
USB3_SCMHOST_SCM_HPM_1_DP output
A35 1 GND G3 B35 1
A36 0.5 PCIE_HPM_SCM_CLK_100M_0_DN input S0 B36 0.5
A37 0.5 PCIE_HPM_SCM_CLK_100M_0_DP input S0 B37 0.5
A38 1 GND G3 B38 1
A39 0.5 I2C_I3C_1V0_18_SCL / 1.0/1.2 inout S5 B39 0.5
FSI_1V2_0_SCL
A40 0.5 I2C_I3C_1V0_18_SDA / 1.0/1.2 inout S5 B40 0.5
FSI_1V2_0_SDA
A41 0.5 I2C_I3C_1V0_19_SCL / 1.0/1.2 inout S5 B41 0.5
FSI_1V2_1_SCL
A42 0.5 I2C_I3C_1V0_19_SDA / 1.0/1.2 inout S5 B42 0.5
FSI_1V2_1_SDA
A43 0.5 I2C_3V3_3_SCL 3.3 (Single) inout S5 B43 0.5
1.8 (Dual)
A44 0.5 I2C_3V3_3_SDA 3.3 (Single) inout S5 B44 0.5
1.8 (Dual)
A45 0.5 I2C_3V3_4_SCL 3.3 (Single) inout S5 B45 0.5
1.8 (Dual)
A46 0.5 I2C_3V3_4_SDA 3.3 (Single) inout S5 B46 0.5
1.8 (Dual)
A47 0.5 I2C_3V3_5_SCL 3.3 (Single) inout S5 B47 0.5
1.8 (Dual)
A48 0.5 I2C_3V3_5_SDA 3.3 (Single) inout S5 B48 0.5
1.8 (Dual)
A49 0.5 I2C_3V3_6_SCL 3.3 (Single) inout S5 B49 0.5
1.8 (Dual)
A50 0.5 I2C_3V3_6_SDA 3.3 (Single) inout S5 B50 0.5
1.8 (Dual)
A51 0.5 I2C_I3C_1V8_16_SCL 1.8 inout S5 B51 0.5
A52 0.5 I2C_I3C_1V8_16_SDA 1.8 inout S5 B52 0.5
A53 1 GND G3 B53 0.5
A54 0.5 SPI_HPMCNTRL_TPM_CLK / 1.8 input / S5 B54 0.5
I2C_I3C_1V8_10_SCL inout
A55 0.5 SPI_HPMCNTRL_TPM_CS_N / 1.8 input / S5 B55 0.5
I2C_I3C_1V8_10_SDA / inout /
QSPI_HPMCNTRL_TPM_CS_N input
A56 0.5 SPI_HPMCNTRL_TPM_DI_IO0 / 1.8 input / S5 B56 0.5
I2C_I3C_1V8_11_SCL inout
A57 0.5 SPI_HPMCNTRL_TPM_DO_IO1 / 1.8 output / S5 B57 0.5
I2C_I3C_1V8_11_SDA inout
A58 0.5 I2C_I3C_1V8_12_SCL 1.8 inout S5 B58 0.5
A59 0.5 I2C_I3C_1V8_12_SDA 1.8 inout S5 B59 0.5
A60 0.5 GPIO/ SPI_SCMCNTRL_IRQ0_N 1.8 inout / input STBY B60 0.5
(matching
Dual node
voltage
requirement)
A61 0.5 I2C_I3C_1V8_13_SCL 1.8 inout S5 B61 0.5
A62 0.5 I2C_I3C_1V8_13_SDA 1.8 inout S5 B62 0.5
A63 0.5 UART0_HPM_SCM_DATA / GPIO 3.3 input / inout Pre-STBY (Single) B63 0.5
S0 (Dual)
A64 1 GND G3 B64 1
A65 0.5 PCIE_HPMROOT_SCM_HPM_5_DN output S0 B65 0.5
A66 0.5 PCIE_HPMROOT_SCM_HPM_5_DP output S0 B66 0.5
A67 1 GND G3 B67 1
A68 0.5 PCIE_HPM_SCM_CLK_100M_1_S0_DN / input / input S0 (Host PCIe clk) B68 0.5
PCIE_HPM_SCM_CLK_100M_1_S5_DN S5 (BMC Root PCIe
Clock)
A69 0.5 PCIE_HPM_SCM_CLK_100M_1_S0_DP / input / input " " B69 0.5
PCIE_HPM_SCM_CLK_100M_1_S5_DP
A70 1 GND G3 B70 1
Note1: 3.3/BAT mean 3.3V when AC is applied and 3.0 BAT in G3
ion 1.0 4/298/2024 Synced to latest DC-SCI 2.2 Ver 1.1 RC2
Single Node Primary / Voltage Direction Single Node Lowest Supported Power
Alt function(if applicable) DC-SCM State: G3, Pre-STBY, STBY, S5, S0
view
GND G3
PCIE_HPMROOT_HPM_SCM_0_DN / S0 (PCIe)
USB3_SCMHOST_HPM_SCM_2_DN input / S5 (BMC USB3)
input S0 (Host USB3)
PCIE_HPMROOT_HPM_SCM_0_DP / S0 (PCIe)
USB3_SCMHOST_HPM_SCM_2_DP input / S5 (BMC USB3)
input S0 (Host USB3)
GND G3
PCIE_HPMROOT_HPM_SCM_1_DN / PCIe / S0 (PCIe)
LTPI2_HPM_SCM_CLK_DN / LTPI / input / S5( LTPI)
DISPLAYPORT_AUX_DN DP input / S5(DP)
inout
PCIE_HPMROOT_HPM_SCM_1_DP / PCIe / S0 (PCIe)
LTPI2_HPM_SCM_CLK_DP / LTPI / input / S5( LTPI)
DISPLAYPORT_AUX_DP DP input / S5(DP)
inout
GND G3
PCIE_HPMROOT_HPM_SCM_2_DN / input / S0 (PCIe)
SGMII_HPM_SCM_DN input S5 (SGMII)
PCIE_HPMROOT_HPM_SCM_2_DP / input / S0 (PCIe)
SGMII_HPM_SCM_DP input S5 (SGMII)
GND G3
PCIE_HPMROOT_HPM_SCM_3_DN / PCIe / S0 (PCIe)
LTPI_HPM_SCM_DATA_2_DN / LTPI / input / S5 (LTPI 2)
USB2_SCMHOST_3_DN USB2 input / S5(USB2 BMC HOST/DEVICE)
inout
PCIE_HPMROOT_HPM_SCM_3_DP / PCIe / S0 (PCIe)
LTPI_HPM_SCM_DATA_2_DP / LTPI / input / S5 (LTPI 2)
USB2_SCMHOST_3_DP USB2 input / S5(USB2 BMC HOST/DEVICE)
inout
GND G3
PECI_VREF_HPM_SCM / GPI 0.85-1.21 input S0
ESPI_HPMCNTRL_CLK 1.8 input S5
ESPI_HPMCNTRL_CS0_N 1.8 input S5
ESPI_HPMCNTRL_RESET_N 1.8 input S5
ESPI_HPMCNTRL_IO_0 1.8 inout S5
ESPI_HPMCNTRL_IO_1 1.8 inout S5
ESPI_HPMCNTRL_IO_2 1.8 inout S5
ESPI_HPMCNTRL_IO_3 1.8 inout S5
ESPI_HPMCNTRL_ALERT0_N 1.8 output S5
I2C_I3C_1V8_17_SCL / 1.8 inout / S5
ESPI0_HPMCNTRL_CS1_N input
I2C_I3C_1V8_17_SDA / 1.8 inout / S5
ESPI0_HPMCNTRL_ALERT1_N output
GND G3
QSPI_HPMCNTRL_CLK 1.8 input S5
QSPI_HPMCNTRL_CS0_N 1.8 input S5
QSPI_HPMCNTRL_IO_0 1.8 inout S5
QSPI_HPMCNTRL_IO_1 1.8 inout S5
QSPI_HPMCNTRL_IO_2 1.8 inout S5
QSPI_HPMCNTRL_IO_3 1.8 inout S5
QSPI_HPMCNTRL_CS1_N / GPIO 1.8 input / S5
GND inout G3
LTPI_HPM_SCM_DATA_DN input S5
LTPI_HPM_SCM_DATA_DP input S5
GND G3
LTPI_HPM_SCM_CLK_DN input S5
LTPI_HPM_SCM_CLK_DP input S5
GND G3
HPM_SCM_STBY_RDY 3.3 input G3
HPM_SCM_INTRUSION_N 3.3/BAT input G3
P3V0_HPM_SCM_BAT 3.0 BAT input G3
GND G3
PCIE_HPMROOT_HPM_SCM_4_DN input S0
PCIE_HPMROOT_HPM_SCM_4_DP input S0
GND G3
PCIE_SCMROOT_HPM_SCM_DN / input / S5 (PCIe)
USB3_SCMHOST_HPM_SCM_1_DN input S5(BMC USB) or
S0(HPM domain USB)
PCIE_SCMROOT_HPM_SCM_DP / input / ""
USB3_SCMHOST_HPM_SCM_1_DP input
GND G3
USB2_SCMHOST1_DN / 3.3 inout / S5 (SCMHOST=BMC root)
USB2_HPMHOST1_DN / inout S0 (HPMHOST or SCMHOST=Host
GPIO root wrapped)
USB2_SCMHOST1_DP / 3.3 inout / ""
USB2_HPMHOST1_DP / inout
GPIO
GND G3
I2C_I3C_1V8_14_SCL 1.8 inout S5
I2C_I3C_1V8_14_SDA 1.8 inout S5
I2C_I3C_1V8_15_SCL 1.8 inout S5
I2C_I3C_1V8_15_SDA 1.8 inout S5
NCSI_HPM_SCM_CLK / GPIO 3.3 input/ S5
inout
NCSI_HPM_SCM_CRS_DV / GPIO 3.3 input/ S5
inout
NCSI_SCM_HPM_TX_EN / GPIO 3.3 output/ S5
inout
NCSI_SCM_HPM_D0 / GPIO 3.3 output/ S5
inout
NCSI_SCM_HPM_D1 / GPIO 3.3 output/ S5
inout
NCSI_HPM_SCM_D0 / GPIO 3.3 input/ S5
inout
NCSI_HPM_SCM_D1 / GPIO 3.3 input/ S5
inout
VCC_SCM_HPM_FRU 3.3 output Pre-STBY
UART0_SCM_HPM_DATA / 3.3 output / Pre-STBY
PCIE_SCM_HPM_PERST_N/ GPO/ output /
NCSI2_SCM_HPM_TX_EN output
I2C_3V3_7_SCL / 3.3 inout / S5
SGPIO_CLK / output /
NCSI2_HPM_SCM_CLK output
I2C_3V3_7_SDA / 3.3 inout / S5
SGPIO_LD / output /
NCSI2_HPM_SCM_CRS_DV output
I2C_3V3_8_SCL / 3.3 inout / S5
SGPIO_DATAOUT / output /
NCSI2_SCM_HPM_D0 inout
I2C_3V3_8_SDA / 3.3 inout / S5
SGPIO_DATAIN / input /
NCSI2_SCM_HPM_D1 inout
I2C_3V3_9_SCL / 3.3 inout / S5
UART1_SCM_HPM_DATA / output /
NCSI2_HPM_SCM_D0 inout
I2C_3V3_9_SDA / 3.3 inout / S5
UART1_HPM_SCM_DATA / input /
NCSI2_HPM_SCM_D1 inout
PRSNT0_SCM_HPM_N 0 output Pre-STBY
SPI_SCMCNTRL_CS1_N / 3.3 output / STBY
GPIO inout
SPI_SCMCNTRL_CLK 3.3 output STBY
SPI_SCMCNTRL_DO_IO1 3.3 inout STBY
SPI_SCMCNTRL_DI_IO0 3.3 inout STBY
SPI_SCMCNTRL_CS0_N 3.3 output STBY
GND G3
PCIE_HPMROOT_HPM_SCM_5_DN input S0
PCIE_HPMROOT_HPM_SCM_5_DP input S0
GND G3
USB2_SCMHOST2_DN / 3.3 inout / S5 (BMC Host)
USB2_HPMHOST2_DN / inout S0 (HPM Host)
GPIO
USB2_SCMHOST2_DP / 3.3 inout / ""
USB2_HPMHOST2_DP/ inout
GPIO
GND G3
