VLSI Design

Behavioral Description
( Unit-II )

Subject In Charge
Narendra L Lokhande
Department of Electronics and Telecommunication
R C Patel Institute of Technology, Shirpur,
Dist: Dhule, Maharashtra

Email: [email protected]

Prepared By: Narendra L Lokhande 1

 Processes
• A process is a region of VHDL code that executes
SEQUENTIALLY
• Exists inside the architecture
• A process does execute continuously
• Multiple processes execute with each other
concurrently
• It is invoked when one of the signals in its
sensitivity list changes value, or has an “event”
• Sensitivity lists MUST BE COMPLETE so that all
processes execute properly!

Prepared By: Narendra L Lokhande 2

 The IF Statement
• The If statement tests a condition, and executes a different
set of statements depending on the result

• The two basic forms are the if-then and the if-then-else
statements

• Note that there is a space between the END and the If

Prepared By: Narendra L Lokhande 3

Eg. Eg.
If (clk= ‘1’) then If (clk= ‘1’) then
Temp := Temp :=
s1; s1;
Else End if ;
Temp :=
s2;
End if ;
Prepared By: Narendra L Lokhande 4
 The IF-ELSIF Statement

• The IF-ELSEIF statement allows a series of conditions

to be tested, and the first condition that is true will
cause the statements that follow to be executed
• Cannot happen for more than one branch of the
structure
• The flow then passes to the END IF statement at the
bottom

Prepared By: Narendra L Lokhande 5

If sig = ‘1’ then
Temp := s1;
Elsif sig2 = ‘1’ then
Temp := s2;
Else
Temp := s3;
End if ;

Prepared By: Narendra L Lokhande 6

 VHDL 2x1 Multiplexer Using IF-ELSE
Library IEEE; Begin
Use IEEE.STD_LOGIC_1164.ALL; if Gbar = '0' then
Entity MUX_if is
if SEL = '1' then
Port (A, B, SEL, Gbar : in std_logic;
Y : out std_logic); temp := B;
End MUX_if; else
temp := A;
end if;
Architecture MUX_bh of MUX_if is
Y <= temp;
Begin
else
process (SEL, A, B, Gbar)
Y <= 'Z';
variable temp : std_logic;
End if;
End process;

Prepared By: Narendra L Lokhande End MUX_bh; 7

 VHDL 2x1 Multiplexer Using ELSIF

Library IEEE;
Use
IEEE.STD_LOGIC_1164.ALL; Begin
Entity MUXBH is if (Gbar = '0') and (SEL = '1') then
Port (A, B, SEL, Gbar : in std_logic; temp := B;
elsif (Gbar = '0') and (SEL = '0')then
Y : out std_logic);
temp := A;
End MUXBH; else
temp := 'Z';
End if;
Architecture MUX_bh of MUXBH is Y <= temp;
Begin End process;
process (SEL, A, B, Gbar) End MUX_bh;
variable temp : std_logic;
Prepared By: Narendra L Lokhande 8
 D-Latch Using Variable-Assignment Statements

Entity DLTCH_var is
port (d, E : in bit; Q, Qb : out bit);
End DLTCH_var;

Architecture DLCH_VAR of DLTCH_var is

Begin
process (d, E)
variable temp1, temp2 : bit;
Begin
if E = '1' then
temp1 := d;
temp2 := not temp1;
End if;
Qb <= temp2;
Q <= temp1;
End process ;
End DLCH_VAR;
Prepared By: Narendra L Lokhande 9
 D-Latch Using Signal-Assignment
Entity Dltch_sig is
port (d, E : in bit;
Q : buffer bit; Qb : out bit);
End Dltch_sig;

Architecture DL_sig of Dltch_sig is

Begin
process (d, E)
Begin
if E = '1' then
Q <= d; -- signal assignment
Qb <= not Q; -- signal assignment
End if;
End process;
End DL_sig;
Prepared By: Narendra L Lokhande 10
 The CASE Statement
• The CASE statement considers all the possible values that
an object can take, and executes a different branch
depending on the current value of the object
• Values cannot be specified more than once!
• All values MUST be specified, either explicitly, or with an
“others” clause

Prepared By: Narendra L Lokhande 11

 Mux 16:1 using case
process (A, SEL)
begin
case SEL is
when "0000" => Y <= A(0);
library IEEE; when "0001" => Y <= A(1);
use IEEE.std_logic_1164.all; when "0010" => Y <= A(2);
when "0011" => Y <= A(3);
Entity SELECTOR is when "0100" => Y <= A(4);
port ( when "0101" => Y <= A(5);
A : in std_logic_vector(15 downto 0); when "0110" => Y <= A(6);
SEL : in std_logic_vector( 3 downto 0); when "0111" => Y <= A(7);
Y : out std_logic); when "1000" => Y <= A(8);
when "1001" => Y <= A(9);
End SELECTOR;
when "1010" => Y <= A(10);
when "1011" => Y <= A(11);
Architecture RTL2 of SELECTOR is when "1100" => Y <= A(12);
Begin when "1101" => Y <= A(13);
when "1110" => Y <= A(14);
when others => Y <= A(15);
end case;
end process;
end RTL2;
Prepared By: Narendra L Lokhande 12
 Positive Edge-Triggered JK Flip-Flop Using Case

Library ieee; Begin

Use ieee.std_logic_1164.all; if rising_edge (clk) then
Entity JK_FF is case JK is
port(JK : in bit_vector (1 downto 0); when "01" => temp1 := '0';
clk : in std_logic; q, qb : out bit); when "10" => temp1 := '1';
End JK_FF; when "00" => temp1 := temp1;
when "11" => temp1 := not temp1;
architecture JK_BEH of JK_FF is End case;
begin q <= temp1;
process (clk) temp2 := not temp1;
variable temp1, temp2 : bit; qb <= temp2;
end if;
clk J K Q (next state End process ;
↑ 0 0 No change(hold)
End JK_BEH;
↑ 1 0 1
↑ 0 1 0
↑ 1 1 Toggle (next state)

No + edge X X No change(hold)
Prepared By: Narendra L Lokhande 13
Excitation Table of a 3-bit counter with Synchronous Active High clear

clock clear Current state Next state

↑ H XXX 000
↑ L 000 001
↑ L 001 010
↑ L 010 011
↑ L 011 100
↑ L 100 101
↑ L 101 110
↑ L 110 111
↑ L 111 000
L X Hold

Prepared By: Narendra L Lokhande 14

 3-Bit Binary Counter Case Statement

Begin
if rising_edge (clk) then
library IEEE; if clr = '0' then
use IEEE.STD_LOGIC_1164.ALL; case temp is
Entity ctr is when "000" => temp := "001";
when "001" => temp := "010";
port (clk, clr : in std_logic; when "010" => temp := "011";
q : buffer std_logic_vector (2 downto 0)); when "011" => temp := "100";
End ctr; when "100" => temp := "101";
when "101" => temp := "110";
Architecture ctr_case of ctr is
when "110" => temp := "111";
Begin when "111" => temp := "000";
process(clk) when others => temp := "000";
variable temp : std_logic_vector (2 downto 0) := "101"; end case;
Else
temp := "000";
End if;
End if;
q <= temp;
End process;
End ctr_case;

Prepared By: Narendra L Lokhande 15

 The FOR Loop
• A FOR loop will iterate around a loop a fixed number of
times while incrementing a value through a fixed range

• In this example, the variable “i” is being incremented from

0 to 5, making 6 passes around the loop

• There is no need to declare the loop variable in any other

part of the code; it is implicitly declared when it is used in
the FOR loop

Prepared By: Narendra L Lokhande 16

• Eg
For i in 0 to 5 loop
If temp(i) = ‘1’ then
result := result + 2**i;
End if;
End loop;

Prepared By: Narendra L Lokhande 17

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Entity ex is
port (A, B, C : in std_logic_vector( 4 downto 0);
q : out std_logic_vector (4 downto 0));
End ex;

Architecture rtl of ex is
begin
process(A,B, C)
Begin
for i in 0 to 4 loop
if A(i) = ‘1’ then
q(i) <= B(i);
Else
q(i) <= C(i);
End if;
End loop;
End process;
End rtl; Prepared By: Narendra L Lokhande 18
 VHDL 4-Bit Counter with Synchronous Clear Description
Library ieee ;
Use ieee.std_logic_1164.all; -- increment result to describe a counter
Entity CNTR_LOP is result := result + 1;
-- change integer to binary
Port (clk, clr : in std_logic; q :
buffer std_logic_vector (3 downto 0)); for j in 0 to 3 loop
End CNTR_LOP; if (result MOD 2 = 1) then
temp (j) := '1';
Architecture CTR_LOP of CNTR_LOP is Else
Begin temp (j) := '0';
Process(clk) End if;
variable temp : std_logic_vector (3 downto
-- integer division by 2
0) := "0000";
variable result : integer := 0;
result := result/2;
Begin
End loop;
if rising_edge (clk) then Else
if (clr = '0') then temp := "0000";
result := 0; End if;
-- change binary to integer
q <= temp;
for i in 0 to 3 loop
if temp(i) = '1' then End if;
result := result + 2**i;
End if; End process ;
End loop; End CTR_LOP;
Prepared By: Narendra L Lokhande 19
 While- loop

• The general format of while

loop is
Eg.
While (condition) loop While (i < x ) loop
Statement1; i := i +1 ;
Statement2; z := i + z;
-------------- End loop ;
End loop ;

Prepared By: Narendra L Lokhande 20

 calculating factorial of positive Integers
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;

Entity factr is
port(N : in natural; z : out natural);
End factr;

Architecture factorl of factr is

Begin
process (N)
variable y, i : natural;
Begin
y := 1;
i := 0;
while (i < N) loop
i := i + 1;
y := y * i;
end loop;
z <= y;

End process;

End factorl; Prepared By: Narendra L Lokhande 21

 VHDL Next and Exit statement

• In VHDL next and exit are two sequential

associated with loop.

• exit causes the program to exit the loop

• next causes the program to jump to the end of the

loop, skipping all statements written between next
and end loop.

Prepared By: Narendra L Lokhande 22

 VHDL Next Exit

for i in 0 to 2 loop
---------
---------
next when z =‘ 1’;
statement1;
end loop;
statements2;

Prepared By: Narendra L Lokhande 23