MT8390 IoT APPLICATION PROCESSOR

DATASHEET

Version: 1.9
Release date: 2024-04-24

Use of this document and any information contained therein is subject to the terms and conditions set forth in
Exhibit 1 Terms and Conditions. This document is subject to change without notice.

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Document Revision History

Revision Date Description

1.0 2022-07-04 Official release
 Modified Section 1.2 Ordering information
 Modified DPTX and eDPTX speed from 8.1Gpbs to 5.4Gpbs
 Modified Section 6.2 PLL Specification
1.1 2022-09-26
 Modified Figure 4-1 Ball map diagram
 Modified Section 4.1.1 and 4.1.2 ball map tables
 Modified Table 6-1 Maximum performance ratings
 Modified Table 5-1 Absolute maximum ratings
1.2 2022-11-16
 Modified Table 5-3 Recommended operating conditions for power supply
1.3 2022-12-09  Modified Section 4.4 Reserved and Unused Pin Handling Recommendations
 Modified Figure 1-1 Functional block diagram
 Modified Section 1.2 Ordering information
1.4 2022-12-26  Modified Section [Link] CSI Timing Characteristics
 Modified Table 5-2 Storage condition
 Modified Table 5-3 Recommended operating conditions for power supply
 Replaced Table 5-16 CSI D-PHY TX electrical characteristics with CSI D-PHY RX electrical
characteristics
1.5 2023-02-16
 Modified two typos in Table 3-34 CSI0 signal descriptions and Table 5-14 DSI D-PHY TX
electrical characteristics
 Modified APU to VP6 and added MDLA 900 MHz in Table 1-1 Device features and Table 6-
1 Maximum performance ratings
 Modified DRAM-related power in Table 5-3 Recommended operating conditions for
1.6 2023-06-28
power supply
 Modified Quad-core to Dual-core and Hexa-core in Table 6-1 Maximum performance
ratings
 Removed DDR4-related information
 Modified the order# and temperature range in Table 1-2 Ordering Information
 Enhanced Chapter 3 Features Description and Section 5.5 Reset by providing additional
details
1.7 2023-09-18
 Streamlined the presentation of Section 3.6 Memory and Section 3.8 Display for
improving clarity and organization
 Modified the order# and values in Table 7-1 MT8390 AV/AZA Thermal Operating
Specifications and added Table 7-2 MT8390 IV/KZA Thermal Operating Specifications
 Revised the core numbers of CPU in Section 3.1.2 Features and Section 3.1.3 Block
Diagram
1.8 2023-11-20  Removed operating temperature from Table 3-189 Electrical Characteristics and
Operating Conditions of 1.8V Applications
 Modified the maximum capacity of DRAMC from 16GB to 8GB in Section [Link] Features

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Revision Date Description

 Modified the descriptions of Function code 1 and Function code 2 in Table 7-3 Printed
Device Reference and Decoding
 Modified “Temperature Range” to “Operating Junction Temperature” in Table 1-2
Ordering Information
 Revised “8.1Gbps” to “5.4Gbps” in Section [Link] Features and Section [Link] Features
 Revised “2 lanes” to “4 lanes” for DP_TX in Section [Link] Features
1.9 2024-04-24
 Revised “HBR3” to “HBR2” in Section 3.8.5 DisplayPort Interface (DPTX) to match the
DPTX speed of 5.4Gbps
 Revised the descriptions of USB in Section [Link] USB MAC Overview
 Added junction temperature to Table 5-1 Absolute Maximum Ratings

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Table of Contents

Document Revision History ................................................................................................................................................ 2

Table of Contents............................................................................................................................................................... 4
List of Figures ..................................................................................................................................................................7
List of Tables .................................................................................................................................................................12
1 Introduction .......................................................................................................................................................... 19
1.1 Features Overview ..............................................................................................................................................20
1.2 Ordering Information..........................................................................................................................................21
2 Preface .................................................................................................................................................................. 22
2.1 Pin Characteristics and Signal Descriptions Conventions ...................................................................................22
2.2 Timing Conventions, Parameters, and Information ...........................................................................................22
2.2.1 Timing Parameters and Information ......................................................................................................23
2.2.2 Parameter Information ..........................................................................................................................23
2.3 Abbreviations ......................................................................................................................................................24
3 Features Description.............................................................................................................................................. 38
3.1 Application Processor .........................................................................................................................................38
3.1.1 Overview ................................................................................................................................................38
3.1.2 Features .................................................................................................................................................39
3.1.3 Block Diagram ........................................................................................................................................39
3.1.4 Function Description ..............................................................................................................................39
3.1.5 Register Definition .................................................................................................................................40
3.1.6 References .............................................................................................................................................40
3.2 Graphics Accelerator ..........................................................................................................................................40
3.2.1 Overview ................................................................................................................................................40
3.2.2 Features .................................................................................................................................................40
3.2.3 Block Diagram ........................................................................................................................................41
3.3 Digital Signal Processor ......................................................................................................................................41
3.3.1 Overview ................................................................................................................................................41
3.3.2 Features .................................................................................................................................................42
3.3.3 Block Diagram ........................................................................................................................................43
3.3.4 Function Description ..............................................................................................................................43
3.3.5 Theory of Operations .............................................................................................................................45
3.3.6 Power Management...............................................................................................................................46
3.3.7 Programming Guide ...............................................................................................................................46
3.3.8 Register Definition .................................................................................................................................47
3.3.9 Reference ...............................................................................................................................................47
3.4 AI Processor Unit ................................................................................................................................................47
3.4.1 Overview ................................................................................................................................................47
3.4.2 Features .................................................................................................................................................48
3.4.3 Block Diagram ........................................................................................................................................49
3.4.4 Function Description ..............................................................................................................................49
3.4.5 Theory of Operations .............................................................................................................................53
3.4.6 Programming Guide ...............................................................................................................................53

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3.5 System Companion Processor (SCP) ...................................................................................................................53

3.5.1 Introduction ...........................................................................................................................................53
3.5.2 Features .................................................................................................................................................53
3.5.3 Block Diagram ........................................................................................................................................54
3.5.4 Clock Generation ....................................................................................................................................56
3.5.5 MCUSYS (RV55) ......................................................................................................................................58
3.5.6 JTAG .......................................................................................................................................................60
3.5.7 Internal Bus Fabric .................................................................................................................................60
3.5.8 Interrupt Controller ................................................................................................................................60
3.5.9 Timer ......................................................................................................................................................65
3.5.10 WDT........................................................................................................................................................66
3.5.11 Semaphore .............................................................................................................................................67
3.5.12 GPIO .......................................................................................................................................................67
3.5.13 UART ......................................................................................................................................................68
3.5.14 I2C and I3C .............................................................................................................................................68
3.5.15 Memory Map of SCP Subsystem ............................................................................................................68
3.6 Memory ..............................................................................................................................................................72
3.6.1 DRAMC Controller (DRAMC) ..................................................................................................................72
3.6.2 External Memory Interface (EMI) ..........................................................................................................82
3.7 Storage ................................................................................................................................................................85
3.7.1 MMC (MultiMediaCard) and SD (Secure Digital) Controller (MSDC) .....................................................85
3.7.2 Serial NOR Flash Controller (SNFC) ........................................................................................................98
3.8 Display ..............................................................................................................................................................113
3.8.1 Display Controller .................................................................................................................................113
3.8.2 Display Serial Interface (DSI)................................................................................................................117
3.8.3 Display Digital Parallel Interface (DPI) .................................................................................................138
3.8.4 Embedded DisplayPort Interface (EDPTX) ...........................................................................................140
3.8.5 DisplayPort Interface (DPTX) ...............................................................................................................148
3.8.6 High-Definition Multimedia Interface Transmitter (HDMITX) .............................................................155
3.9 Imaging .............................................................................................................................................................157
3.9.1 Camera Image Signal Processor (ISP) ..................................................................................................157
3.9.2 Face Detection (FD) .............................................................................................................................159
3.9.3 Camera Serial Interface (CSI) ...............................................................................................................161
3.10 Video .................................................................................................................................................................170
3.10.1 Video Encoder (VENC) .........................................................................................................................170
3.10.2 Video Decoder (VDEC) .........................................................................................................................172
3.11 Audio.................................................................................................................................................................172
3.11.1 Overview ..............................................................................................................................................172
3.11.2 Features ...............................................................................................................................................173
3.11.3 Block Diagram ......................................................................................................................................174
3.11.4 Function Description ............................................................................................................................174
3.12 Connectivity ......................................................................................................................................................180
3.12.1 Inter-Integrated Circuit (I2C) and Improved I2C (I3C) ..........................................................................180
3.12.2 Universal Asynchronous Receiver/Transmitter (UART) .......................................................................192
3.12.3 Serial Peripheral Interface Master (SPIM) ...........................................................................................206

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3.12.4 SuperSpeed Universal Serial Bus (SSUSB) ............................................................................................213

3.12.5 Ethernet Network Interface Controller (ENIC) ...................................................................................263
3.12.7 Peripheral Component Interconnect Express (PCIe) Controller .........................................................287
3.12.8 Keypad Scanner (Keypad) ....................................................................................................................336
3.12.9 General-purpose Input/Output (GPIO) ................................................................................................340
3.12.10 Pulse Width Modulation (PWM) ..........................................................................................................359
3.13 Miscellaneous ...................................................................................................................................................369
3.13.1 Timers and Counters ............................................................................................................................369
3.13.2 Auxiliary Analog-to-Digital Converter (AUXADC) ................................................................................381
3.13.3 Thermal Control Subsystem (TCSYS) ....................................................................................................384
3.14 Boot Flash .........................................................................................................................................................389
3.15 ROM Power Down Mode ..................................................................................................................................390
4 Ball Map .............................................................................................................................................................. 391
4.1 Quadrant Pinout ...............................................................................................................................................392
4.2 Pin Characteristics ............................................................................................................................................402
4.3 Power Rails .......................................................................................................................................................441
4.4 Reserved and Unused Pin Handling Recommendations ...................................................................................444
5 Electrical Characteristics ...................................................................................................................................... 445
5.1 Absolute Maximum Ratings ..............................................................................................................................445
5.1.1 Storage Condition ................................................................................................................................446
5.2 Recommended Operating Conditions ..............................................................................................................446
5.3 DC Electrical Specifications ...............................................................................................................................448
5.3.1 PMIC_RTC32K_CK DC Specifications ....................................................................................................448
5.3.2 SPII2CUARTIO DC Electrical Specifications ...........................................................................................449
5.3.3 I2C/I2SIO DC Specifications ..................................................................................................................449
5.3.4 I3CIO DC Specifications ........................................................................................................................449
5.3.5 eMMCIO DC Specifications ..................................................................................................................450
5.3.6 MSDC1IO DC Specifications..................................................................................................................450
5.3.7 MSDC2IO DC Specifications..................................................................................................................451
5.4 Power Management .........................................................................................................................................451
5.4.1 Power Sequence...................................................................................................................................451
5.5 Reset .................................................................................................................................................................451
5.5.1 Overview ..............................................................................................................................................451
5.5.2 Features ...............................................................................................................................................451
5.5.3 Block Diagram ......................................................................................................................................452
5.5.4 Function Description ............................................................................................................................452
5.5.5 Reset IO Signal Descriptions .................................................................................................................453
5.5.6 Theory of Operation .............................................................................................................................453
5.5.7 Programming Guide .............................................................................................................................453
5.5.8 Register Definition ...............................................................................................................................454
5.6 DSI Specifications ..............................................................................................................................................454
5.7 CSI-2 Specifications ...........................................................................................................................................455
6 Clock Characteristics ............................................................................................................................................ 456
6.1 Maximum Performance Ratings .......................................................................................................................456
6.2 PLL Spec ............................................................................................................................................................457

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6.3 Clock Squarer ....................................................................................................................................................463

6.4 Clock Signal Descriptions ..................................................................................................................................463
7 Package Information ........................................................................................................................................... 465
7.1 Thermal Specifications ......................................................................................................................................465
7.1.1 Thermal Operating Specifications ........................................................................................................465
7.2 Top Marking ......................................................................................................................................................465
7.3 Mechanical Drawing .........................................................................................................................................466
8 Legal and Support Information ............................................................................................................................ 467
8.1 Related Documents and Products ....................................................................................................................467
8.2 Trademarks .......................................................................................................................................................467
Exhibit 1 Terms and Conditions...................................................................................................................................... 469

List of Figures

Figure 1-1 Functional Block Diagram ................................................................................................................................19

Figure 3-1 Block Diagram of MCUSYS ...............................................................................................................................39
Figure 3-2 Block Diagram and Interface of MFG ...............................................................................................................41
Figure 3-3 HiFi 5 DSP Block Diagram .................................................................................................................................43
Figure 3-4 Block Diagram and Interface of APUSYS ..........................................................................................................49
Figure 3-5 VP6 Block Diagram ...........................................................................................................................................50
Figure 3-6 Key Block Diagram of MDLA .............................................................................................................................52
Figure 3-7 APU Theory of Operation Construction ...........................................................................................................53
Figure 3-8 SCP Subsystem Block Diagram .........................................................................................................................56
Figure 3-9 SCP Clock Structure ..........................................................................................................................................57
Figure 3-10 INTC Block Diagram ........................................................................................................................................60
Figure 3-11 EINT Block Diagram ........................................................................................................................................64
Figure 3-12 SCP Timer Block Diagram ...............................................................................................................................65
Figure 3-13 SCP Timer Interrupt Event ..............................................................................................................................65
Figure 3-14 SCP WDT Block Diagram.................................................................................................................................66
Figure 3-15 Semaphore Block Diagram .............................................................................................................................67
Figure 3-16 Block Diagram of Memory System .................................................................................................................73
Figure 3-17 DRAMSYS Clock and Low Power Structure ....................................................................................................74
Figure 3-18 Write Operation .............................................................................................................................................75
Figure 3-19 Read Operation ..............................................................................................................................................75
Figure 3-20 DRAM Controller Power Domain Architecture ..............................................................................................76
Figure 3-21 LPDDR4X Basic Schematic for 2 × 2 × 16-bit ..................................................................................................77
Figure 3-22 4-Channel EMI/LPDDR4 SDRAM Controller Top Connection .........................................................................83
Figure 3-23 System-level Block Diagram of MSDC ............................................................................................................86
Figure 3-24 Single Block and Multi-block Read in PIO Mode ............................................................................................87
Figure 3-25 Single Block and Multi-block Write in PIO Mode ...........................................................................................88
Figure 3-26 Single Block and Multi-block Read in DMA Mode..........................................................................................88
Figure 3-27 Single Block and Multi-block Write in DMA Mode.........................................................................................89
Figure 3-28 Voltage Switch Command ..............................................................................................................................90
Figure 3-29 MSDC Tuning Flow .........................................................................................................................................91
Figure 3-30 MSDC Timing Diagram (Default Speed mode) ...............................................................................................93

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Figure 3-31 MSDC Timing Diagram (High Speed mode)....................................................................................................94

Figure 3-32 MSDC Timing Diagram (SDR12/SDR25/SDR50/SDR104 modes) ....................................................................95
Figure 3-33 MSDC Timing Diagram (DDR50 mode) ...........................................................................................................96
Figure 3-34 MSDC Timing Diagram (HS200 mode) ...........................................................................................................97
Figure 3-35 MSDC Timing Diagram (HS400 Input Mode) ..................................................................................................98
Figure 3-36 MSDC Timing Diagram (HS400 Output Mode) ...............................................................................................98
Figure 3-37 Block Diagram of SNFC ...................................................................................................................................99
Figure 3-38 Read ID (RDID) Operation Sequence ............................................................................................................100
Figure 3-39 Sector Erase and Block Erase Operation Sequence ......................................................................................102
Figure 3-40 Chip Erase Operation Sequence ...................................................................................................................103
Figure 3-41 Programming Operation Sequence ..............................................................................................................104
Figure 3-42 Read Operation Sequence ...........................................................................................................................108
Figure 3-43 Quad Output Read Mode Sequence (Address Sent in the Single-bit Mode) ...............................................110
Figure 3-44 Quad I/O Read Mode Sequence (Address Sent in the 4-bit Mode) .............................................................110
Figure 3-45 SNOR Timing Diagram ..................................................................................................................................113
Figure 3-46 Application Position of VPPSYS inside SoC ...................................................................................................115
Figure 3-47 Possible Application Connection of SVPP-x and WPE ..................................................................................115
Figure 3-48 Possible Application Connection of DVPP-x and Display Output Interfaces ................................................116
Figure 3-49 DSI Module Block Diagram ...........................................................................................................................118
Figure 3-50 Video Mode Interface Timing Legend ..........................................................................................................120
Figure 3-51 Video Mode Interface Timing: Non-burst Mode with Sync Pulses ..............................................................120
Figure 3-52 Video Mode Interface Timing: Non-burst Mode with Sync Events ..............................................................121
Figure 3-53 Video Mode Interface Timing: Burst Mode ..................................................................................................121
Figure 3-54 Timing Chart of Initialization Sequence .......................................................................................................122
Figure 3-55 Timing Chart of Power-off Sequence ...........................................................................................................123
Figure 3-56 Registers for Data Lane Timing Parameters .................................................................................................125
Figure 3-57 Registers for Clock Lane Timing Parameters ................................................................................................126
Figure 3-58 Register for BTA Timing Parameters .............................................................................................................126
Figure 3-59 Registers for C-PHY Timing Parameters........................................................................................................127
Figure 3-60 Non-burst Transmission: Sync-pulse Mode ..................................................................................................128
Figure 3-61 Non-burst Transmission: Sync-event Mode .................................................................................................128
Figure 3-62 Burst Mode Transmission .............................................................................................................................129
Figure 3-63 DSI Command Queue Instruction Format ....................................................................................................129
Figure 3-64 D-PHY Lane Swap Mux .................................................................................................................................136
Figure 3-65 C-PHY Trio Swap Mux ...................................................................................................................................137
Figure 3-66 DPI Timing Diagram......................................................................................................................................139
Figure 3-67 DPI Block Diagram ........................................................................................................................................140
Figure 3-68 Programming Flow Diagram.........................................................................................................................140
Figure 3-69 EDP TX Block Diagram with Other IPs ..........................................................................................................142
Figure 3-70 EDP TX Encoder Block Diagram ....................................................................................................................142
Figure 3-71 DP TX Transmitter Block Diagram ................................................................................................................143
Figure 3-72 DP TX AUX Diagram ......................................................................................................................................143
Figure 3-73 DPCD Writing Flow .......................................................................................................................................146
Figure 3-74 DPCD Reading Flow ......................................................................................................................................146
Figure 3-75 I2C Writing Flow ...........................................................................................................................................147

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Figure 3-76 DP TX Block Diagram with Other IPs ............................................................................................................149

Figure 3-77 DP TX Encoder Block Diagram ......................................................................................................................149
Figure 3-78 DP TX Transmitter Block Diagram ................................................................................................................150
Figure 3-79 DP TX AUX Diagram ......................................................................................................................................150
Figure 3-80 DPCD writing flow ........................................................................................................................................153
Figure 3-81 DPCD Reading Flow ......................................................................................................................................153
Figure 3-82 I2C Writing Flow ...........................................................................................................................................154
Figure 3-83 HDMITX Block Diagram ................................................................................................................................156
Figure 3-84 Block Diagram of ISP ....................................................................................................................................158
Figure 3-85 Block Diagram of AIE2.0 ...............................................................................................................................160
Figure 3-86 Block Diagram of CSI Modules (D-PHY and C-PHY mode) ............................................................................164
Figure 3-87 CSI Programming Sequence .........................................................................................................................165
Figure 3-88 Seninf_top Basic Data Path (One Port) ........................................................................................................166
Figure 3-89 Power-On Sequence Timing .........................................................................................................................169
Figure 3-90 Block Diagram of VENC ................................................................................................................................171
Figure 3-91 Audio Interfaces Block Diagram ...................................................................................................................174
Figure 3-92 I2S Master Mode Timing Diagram ...............................................................................................................176
Figure 3-93 PCM Master Mode Timing Diagram .............................................................................................................177
Figure 3-94 PCM Slave Mode Timing Diagram ................................................................................................................177
Figure 3-95 TDM Master Mode Timing Diagram ............................................................................................................178
Figure 3-96 PDM Timing Diagram ...................................................................................................................................179
Figure 3-97 Block Diagram of I3C/I2C .............................................................................................................................182
Figure 3-98 I2C/I3C Function Description Wording Conventions ....................................................................................183
Figure 3-99 I2C Clock Stretching .....................................................................................................................................183
Figure 3-100 I2C Frame Format in SM/FM/FM+ .............................................................................................................183
Figure 3-101 I2C Write Frame Format in HS Mode .........................................................................................................184
Figure 3-102 I3C Dynamic Address Assignment (DAA) ...................................................................................................184
Figure 3-103 I3C SDR Private Write/Read .......................................................................................................................185
Figure 3-104 I3C SDR Broadcast CCC ...............................................................................................................................185
Figure 3-105 I3C SDR direct CCC .....................................................................................................................................185
Figure 3-106 Multi-user of I3C/I2C .................................................................................................................................186
Figure 3-107 I2C/I3C Single-Byte Access .........................................................................................................................187
Figure 3-108 I2C/I3C Single-Byte Access .........................................................................................................................187
Figure 3-109 Combined Write/Read with Repeated START (Direction Changed) ...........................................................188
Figure 3-110 Change Transfer Length in Write/Read Mode (No Direction Change) .......................................................188
Figure 3-111 Repeated START Multiple Transfers (Write/Read Mode) ...........................................................................189
Figure 3-112 I2C AC Timing Diagram of F/S Mode ..........................................................................................................190
Figure 3-113 I2C AC Timing Diagram of HS Mode ...........................................................................................................191
Figure 3-114 Programming Flow of I3C/I2C ....................................................................................................................191
Figure 3-115 Block Diagram of UART ..............................................................................................................................193
Figure 3-116 UART Communication Protocol..................................................................................................................195
Figure 3-117 UART Timing Diagram ................................................................................................................................203
Figure 3-118 UART Data Transmission with THRE Bit Status Polling ...............................................................................205
Figure 3-119 UART Data Reception with DR Bit Status Polling........................................................................................205
Figure 3-120 Block Diagram of SPIM ...............................................................................................................................207

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Figure 3-121 SPI Transmission Formats...........................................................................................................................210

Figure 3-122 SPI Pause Mode State Transition ................................................................................................................211
Figure 3-123 CS_N De-assert Mode ................................................................................................................................211
Figure 3-124 Four Communication Modes Waveform for SPI.........................................................................................211
Figure 3-125 SPI Transaction Format ..............................................................................................................................211
Figure 3-126 SPIM Timing Diagram .................................................................................................................................212
Figure 3-127 Block Diagram of SSUSB .............................................................................................................................214
Figure 3-128 SSUSB host architecture .............................................................................................................................215
Figure 3-129 USB2 Device Architecture ..........................................................................................................................216
Figure 3-130 Relation between Extra Defined Fields Parameters and Microframes ......................................................224
Figure 3-131 Relation between bCSCount Parameters and Microframes .......................................................................224
Figure 3-132 Standard xHCI_add_endpoint() Flow .........................................................................................................225
Figure 3-133 Patched xHCI_add_endpoint() Flow ..........................................................................................................225
Figure 3-134 Standard xHCI_drop_endpoint() Flow .......................................................................................................226
Figure 3-135 Patched xHCI_drop_endpoint() Flow .........................................................................................................226
Figure 3-136 EP0 States...................................................................................................................................................227
Figure 3-137 EP0 Idle Flow Chart ....................................................................................................................................228
Figure 3-138 EP0 Idle ......................................................................................................................................................229
Figure 3-139 EP0 TX Mode Flow Chart ............................................................................................................................230
Figure 3-140 EP0 TX Mode Flow Chart ............................................................................................................................230
Figure 3-141 EP0 RX Mode Flow Chart ...........................................................................................................................231
Figure 3-142 EP0 IDLE for RX Mode ................................................................................................................................232
Figure 3-143 GPD (USB)/BD Bus Transfer ........................................................................................................................232
Figure 3-144 GPD (USB)/BD with Extension ....................................................................................................................233
Figure 3-145 TX GPD (USB)/BD Format ...........................................................................................................................234
Figure 3-146 RX GPD (USB)/BD Format ...........................................................................................................................234
Figure 3-147 TXQ Programming Flow .............................................................................................................................236
Figure 3-148 TXQ Initialization Flow ...............................................................................................................................237
Figure 3-149 TXQ STALL Flow ..........................................................................................................................................238
Figure 3-150 TXQ Short Packet (I) Flow ...........................................................................................................................239
Figure 3-151 TXQ Short Packet (II) Flow ..........................................................................................................................240
Figure 3-152 TXQ Error Handling Flow ............................................................................................................................241
Figure 3-153 TXQ GPD (USB) Execution Flow ..................................................................................................................242
Figure 3-154 RXQ Programming Flow .............................................................................................................................243
Figure 3-155 RXQ Initialization Flow ...............................................................................................................................243
Figure 3-156 RXQ STALL Flow ..........................................................................................................................................244
Figure 3-157 RXQ Drop Packet Flow ................................................................................................................................245
Figure 3-158 RXQ Error Handling Flow ............................................................................................................................246
Figure 3-159 RXQ GPD (USB) Execution Flow..................................................................................................................247
Figure 3-160 Interrupt Architecture ................................................................................................................................248
Figure 3-161 Example Interrupt Setting ..........................................................................................................................249
Figure 3-162 QMU Interrupt Layer ..................................................................................................................................249
Figure 3-163 Interrupts Status/Mask/Mask Set/Mask Clear...........................................................................................250
Figure 3-164 Power Saving Flow: Initial ..........................................................................................................................251
Figure 3-165 Power Saving Flow: SuperSpeed ................................................................................................................252

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Figure 3-166 Power Saving Flow: High-speed and Full-speed.........................................................................................253

Figure 3-167 EPn MCU Mode TX Programming Flow ......................................................................................................256
Figure 3-168 EPn MCU Mode RX Programming Flow .....................................................................................................257
Figure 3-169 Block Diagram of USB 3.1 Gen1 PHY ..........................................................................................................258
Figure 3-170 Connection of I2C Signals ...........................................................................................................................259
Figure 3-171 Block Diagram of ENIC ...............................................................................................................................265
Figure 3-172 Ethernet Frame Format without VLAN Tag ................................................................................................267
Figure 3-173 Ethernet Frame Format with VLAN Tag ......................................................................................................267
Figure 3-174 Pause Frame Format ..................................................................................................................................267
Figure 3-175 MII Transmit Waveform .............................................................................................................................268
Figure 3-176 MII Transmit Waveform with Error Occurring ............................................................................................268
Figure 3-177 MII Receive Waveform ...............................................................................................................................269
Figure 3-178 RGMII Transmit Waveform in 1000M.........................................................................................................269
Figure 3-179 RGMII Transmit Waveform with Error Occurring in 1000M .......................................................................269
Figure 3-180 RGMII Receive Waveform in 1000M ..........................................................................................................270
Figure 3-181 RGMII Receive Waveform with Error Occurring in 1000M ........................................................................270
Figure 3-182 RGMII Transmit Waveform in 10/100M .....................................................................................................270
Figure 3-183 RGMII Transmit Waveform with Error Occurring in 10/100M ...................................................................270
Figure 3-184 RGMII Receive Waveform in 10/100M.......................................................................................................271
Figure 3-185 RGMII Receive Waveform with Error Occurring in 10/100M .....................................................................271
Figure 3-186 RMII Signal Connection between PHY and MAC ........................................................................................271
Figure 3-187 RMII Receive Waveform .............................................................................................................................272
Figure 3-188 No Preamble Case ......................................................................................................................................273
Figure 3-189 Odd Preamble Case ....................................................................................................................................273
Figure 3-190 Hash Table Set ............................................................................................................................................275
Figure 3-191 Hash Table Control Flow Chart ...................................................................................................................276
Figure 3-192 Hash Value Calculation ...............................................................................................................................277
Figure 3-193 Transmit Flow Chart ...................................................................................................................................278
Figure 3-194 ENIC MII Timing Diagram ...........................................................................................................................280
Figure 3-195 ENIC RMII Timing Diagram .........................................................................................................................281
Figure 3-196 ENIC RGMII Timing Diagram.......................................................................................................................282
Figure 3-197 ENIC MDIO Timing Diagram .......................................................................................................................282
Figure 3-198 Block Diagram of PCIe Controller ...............................................................................................................288
Figure 3-199 RC Send I/O TLP Flow .................................................................................................................................289
Figure 3-200 Transmit Message TLP Flow .......................................................................................................................291
Figure 3-201 Transmit Message TLP by Message Pool Mode .........................................................................................292
Figure 3-202 RC Received LTR Message Flow ..................................................................................................................294
Figure 3-203 RC Received Other Supported Message Flow ............................................................................................295
Figure 3-204 PCIe Reset Scheme .....................................................................................................................................297
Figure 3-205 RC Handles Received INTX Flow If ISTATUS_CTRL[3] Is 0 ...........................................................................301
Figure 3-206 RC Handles Received MSI Flow ..................................................................................................................302
Figure 3-207 RC Enters L2 State Flow ..............................................................................................................................305
Figure 3-208 RC Exits L2 State Flow ................................................................................................................................305
Figure 3-209 RC L1 Entry with and without Clock Removal ............................................................................................306
Figure 3-210 RC Receive Memory Write TLP ...................................................................................................................308

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Figure 3-211 RC Receive Memory Read TLP....................................................................................................................308

Figure 3-212 PCIe to AXI Master Address Translation for RC ..........................................................................................309
Figure 3-213 RC Initiated Memory Write ........................................................................................................................309
Figure 3-214 RC Initiated Memory Read .........................................................................................................................309
Figure 3-215 AXI Slave to PCIe Address Translation for RC .............................................................................................310
Figure 3-216 AXI Slave to PCIe Address Translation ........................................................................................................312
Figure 3-217 RC Configuration Read/Write .....................................................................................................................313
Figure 3-218 RC Access Configuration Space by Backend Interface ................................................................................315
Figure 3-219 Block Diagram of PCIe PHY .........................................................................................................................321
Figure 3-220 PCIe 100 MHz Reference Clock (REFCLK) Architecture on PCB ..................................................................321
Figure 3-221 Block Diagram of Keypad Top .....................................................................................................................337
Figure 3-222 KP1 Block Diagram .....................................................................................................................................337
Figure 3-223 2 × 2 KeyPad Matrix (8 Keys) ......................................................................................................................339
Figure 3-224 GPIO Block Diagram ...................................................................................................................................351
Figure 3-225 Block Diagram of PWM ..............................................................................................................................360
Figure 3-226 Frequency Division Generation ..................................................................................................................360
Figure 3-227 Data Sequence Generation ........................................................................................................................361
Figure 3-228 PWM Normal Mode ...................................................................................................................................361
Figure 3-229 FIFO Mode..................................................................................................................................................362
Figure 3-230 Memory Mode ...........................................................................................................................................362
Figure 3-231 Memory Mode and Stop-bit Position ........................................................................................................363
Figure 3-232 PWM Random Mode .................................................................................................................................363
Figure 3-233 Block Diagram of SYSTMR ..........................................................................................................................370
Figure 3-234 Block Diagram of APXGPT ..........................................................................................................................374
Figure 3-235 Block Diagram of AUXADC .........................................................................................................................381
Figure 3-236 Theory of AUXADC Operation ....................................................................................................................383
Figure 3-237 Thermal Control Subsystem .......................................................................................................................385
Figure 3-238 Block Diagram of System Temperature Measurement Scheme .................................................................386
Figure 3-239 Interrupt Conditions for High/Low Temperature Monitoring ....................................................................387
Figure 3-240 Finite State Machine for High/Low Temperature Monitoring ....................................................................387
Figure 3-241 Interrupt Conditions of High/Low OFFSET Monitoring ..............................................................................388
Figure 3-242 Finite State Machine for High/Low OFFSET Monitoring ............................................................................388
Figure 4-1 Ball Map Diagram ...........................................................................................................................................391
Figure 4-2 Package Quadrants Mapping .........................................................................................................................392
Figure 5-1 Block Diagram of TOPRGU .............................................................................................................................452
Figure 6-1 Device Clock Diagram .....................................................................................................................................456
Figure 7-1 Top Marking ...................................................................................................................................................465

List of Tables

Table 1-1 Device Features .................................................................................................................................................20

Table 1-2 Ordering Information ........................................................................................................................................21
Table 2-1 Column Headers Description .............................................................................................................................22
Table 2-2 Timing Parameters .............................................................................................................................................23
Table 3-1 INTC Interrupt ....................................................................................................................................................44

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Table 3-2 Debug Signals ....................................................................................................................................................45

Table 3-3 Features of a Single VP6 ....................................................................................................................................50
Table 3-4 Clock Selection Programming Outline ...............................................................................................................58
Table 3-5 MCUSYS Function Block List ..............................................................................................................................59
Table 3-6 IRQ .....................................................................................................................................................................61
Table 3-7 INTC Programming Outline ................................................................................................................................64
Table 3-8 EINT Programming Outline ................................................................................................................................64
Table 3-9 Timer Programming Outline ..............................................................................................................................66
Table 3-10 WDT Programming Outline .............................................................................................................................66
Table 3-11 GPIO Programming Outline .............................................................................................................................67
Table 3-12 SCP Memory Map ............................................................................................................................................68
Table 3-13 System Address Map from SCP View ...............................................................................................................70
Table 3-14 SCP Signal Descriptions ...................................................................................................................................70
Table 3-15 LPDDR4X DFS (Mbps).......................................................................................................................................72
Table 3-16 Voltage Support and Desciption ......................................................................................................................76
Table 3-17 DRAMC Signal Description...............................................................................................................................76
Table 3-18 LPDDR4X Device Combinations .......................................................................................................................77
Table 3-19 EMI Signal Descriptions (LPDDR4(X))...............................................................................................................78
Table 3-20 MSDC Function and Address ...........................................................................................................................86
Table 3-21 MSDC Signal Descriptions ................................................................................................................................91
Table 3-22 MSDC Signal Mapping .....................................................................................................................................92
Table 3-23 MSDC Timing Characteristics (Default Speed mode) .......................................................................................93
Table 3-24 MSDC Timing Characteristics (High Speed mode) ...........................................................................................94
Table 3-25 MSDC Timing Characteristics (SDR12/SDR25/SDR50/SDR104 modes) ...........................................................94
Table 3-26 MSDC Timing Characteristics (DDR50 mode) ..................................................................................................96
Table 3-27 MSDC Timing Characteristics (HS200 mode) ...................................................................................................96
Table 3-28 MSDC Timing Characteristics (HS400 mode) ...................................................................................................97
Table 3-29 SNFC Modules .................................................................................................................................................99
Table 3-30 Methods to Read Serial NOR Flash ................................................................................................................100
Table 3-31 Methods to Write Serial NOR Flash ...............................................................................................................100
Table 3-32 Read ID (RDID) Operation Programming Flow ...............................................................................................101
Table 3-33 Erase-command Formats ...............................................................................................................................101
Table 3-34 Sector Erase and Block Erase Operation Programming Flow ........................................................................102
Table 3-35 Chip Erase Operation Programming Flow ......................................................................................................103
Table 3-36 Methods to Program Seiral NOR Flash ..........................................................................................................104
Table 3-37 Page Program (PP) Operation Flow ...............................................................................................................104
Table 3-38 Multi-Page Program (MPP) Operation Flow ..................................................................................................105
Table 3-39 PIO Write Operation Programming Flow .......................................................................................................107
Table 3-40 PIO Read Operation Programming Flow ........................................................................................................108
Table 3-41 DMA Read Operation Programming Flow .....................................................................................................108
Table 3-42 Enter Quad-byte Address Mode Operation Programming Flow ...................................................................111
Table 3-43 Exit Quad-byte Address Mode Operation Programming Flow ......................................................................111
Table 3-44 Overall SNFC Programming Guide .................................................................................................................112
Table 3-45 SNOR Signal Descriptions ..............................................................................................................................112
Table 3-46 SNOR Timing Characteristics .........................................................................................................................113

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Table 3-47 MIPI D-PHY Initialization Programming Sequence ........................................................................................122

Table 3-48 D-PHY Power-off Programming Sequence .....................................................................................................123
Table 3-49 D-PHY Timing Parameters Register Setting ....................................................................................................124
Table 3-50 D-PHY Global Operation Timing Parameter Defined by MIPI Specification...................................................124
Table 3-51 C-PHY Global Operation Timing Parameter Defined by MIPI Specification ...................................................126
Table 3-52 Config Field Description of Main Instruction .................................................................................................130
Table 3-53 Type-0 Instruction Format .............................................................................................................................130
Table 3-54 Type-0 TX Example ........................................................................................................................................130
Table 3-55 Type-1 Instruction Format .............................................................................................................................131
Table 3-56 Type-1 TX Example ........................................................................................................................................131
Table 3-57 Type-2 Instruction Format .............................................................................................................................132
Table 3-58 Type-2 TX Example ........................................................................................................................................132
Table 3-59 Type-3 Instruction Format .............................................................................................................................132
Table 3-60 Type-3 TX Example ........................................................................................................................................133
Table 3-61 Example of Peripheral TE Signaling Detection ...............................................................................................133
Table 3-62 Example of External TE Pin Detection ...........................................................................................................134
Table 3-63 DSI Non-busy Detection by DSI_BUSY Register .............................................................................................134
Table 3-64 DSI Non-busy Detection by DSI_DONE Event ................................................................................................134
Table 3-65 DSI Non-busy Detection by VM_DONE/CM_DONE Interrupt ........................................................................135
Table 3-66 D-PHY Lane Swap Control Register ................................................................................................................135
Table 3-67 C-PHY Trio Swap Control Register ..................................................................................................................136
Table 3-68 DSI signal descriptions ...................................................................................................................................137
Table 3-68 DPI Signal Descriptions ..................................................................................................................................138
Table 3-69 DPI Timing Characteristics .............................................................................................................................139
Table 3-70 EDPTX Signal Descriptions .............................................................................................................................141
Table 3-71 DPTX Signal Descriptions ...............................................................................................................................148
Table 3-72 HDMITX Signal Descriptions ..........................................................................................................................156
Table 3-73 Camera Signal Descriptions ...........................................................................................................................159
Table 3-74 CSI0 Signal Descriptions ................................................................................................................................161
Table 3-75 CSI1 Signal Descriptions ................................................................................................................................162
Table 3-76 MIPI D-PHY RX Electrical Characteristics .......................................................................................................163
Table 3-77 Load Default Setting ......................................................................................................................................166
Table 3-78 Performance Setting ......................................................................................................................................166
Table 3-79 eFuse Reading ...............................................................................................................................................167
Table 3-80 4-Lane DPHY Cam Mode................................................................................................................................167
Table 3-81 4D1C Lane Enable Top Programming Outline ................................................................................................167
Table 3-82 4D1C Clock Lane and Data Lane Setting Top Programming Outline ..............................................................168
Table 3-83 Phy_seninf_mux_0 Setting ............................................................................................................................168
Table 3-84 Seninf1 Setting ..............................................................................................................................................168
Table 3-85 Seninf_top_mux Setting ................................................................................................................................169
Table 3-86 Seninf_mux_1 Setting....................................................................................................................................169
Table 3-87 Seninf_cam_mux Setting ...............................................................................................................................169
Table 3-88 Analog Power-On Sequence ..........................................................................................................................169
Table 3-89 Analog Power-Off ..........................................................................................................................................169
Table 3-90 CAM_CLK Pad Configuration .........................................................................................................................170

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Table 3-91 VENC Supported Formats ..............................................................................................................................170

Table 3-92 I2S Signal Descriptions...................................................................................................................................175
Table 3-93 I2S Timing Characteristics ..............................................................................................................................175
Table 3-94 PCM Signal Descriptions ................................................................................................................................176
Table 3-95 PCM Timing Characteristics ...........................................................................................................................177
Table 3-96 TDM Signal Descriptions ................................................................................................................................177
Table 3-97 TDM Timing Characteristics ...........................................................................................................................178
Table 3-98 PDM Timing Characteristics ...........................................................................................................................179
Table 3-99 DMIC Signal Descriptions ..............................................................................................................................179
Table 3-100 SPDIF Signal Descriptions ............................................................................................................................180
Table 3-101 PMIC Audio Interface Signal Descriptions ...................................................................................................180
Table 3-102 I2C/I3C Signal Descriptions ..........................................................................................................................181
Table 3-103 I3C/I2C Interrupt Control Bits and Interrupt Factors ...................................................................................185
Table 3-104 I2C AC Timing Parameters for Standard, Fast, and Fast-mode Plus .............................................................189
Table 3-105 I2C AC Timing Parameters for HS Mode ......................................................................................................190
Table 3-106 External Signals Descriptions .......................................................................................................................194
Table 3-107 DMA Signal Descriptions .............................................................................................................................195
Table 3-108 UART Interrupt Control Bits and Interrupt Factors ......................................................................................196
Table 3-109 UART Interrupt Types ..................................................................................................................................196
Table 3-110 CTS and RTS Signals Behaviors.....................................................................................................................197
Table 3-111 UART Register Map ......................................................................................................................................198
Table 3-112 UART Register Remap ..................................................................................................................................198
Table 3-113 Bit Extension Number Reference.................................................................................................................201
Table 3-114 Data Transmission Mechanism ....................................................................................................................202
Table 3-115 UART Electrical Specifications .....................................................................................................................202
Table 3-116 Suggested UART Baud Rate Setting .............................................................................................................203
Table 3-117 UART Baud Rate Setting Example ................................................................................................................204
Table 3-118 UART Hardware Initialization.......................................................................................................................204
Table 3-119 SPIM Signal Descriptions .............................................................................................................................207
Table 3-120 SPIM Signal Descriptions .............................................................................................................................207
Table 3-121 SPIM Function Descriptions .........................................................................................................................208
Table 3-122 SPIM Timing Characteristics ........................................................................................................................212
Table 3-123 USB signal descriptions................................................................................................................................214
Table 3-124 USB Host Initialization .................................................................................................................................217
Table 3-125 USB Device Initialization ..............................................................................................................................218
Table 3-126 EP0 Programming Sequence .......................................................................................................................219
Table 3-127 TX EPn Programming Sequence...................................................................................................................220
Table 3-128 RX EPn Programming Sequence ..................................................................................................................220
Table 3-129 Endpoint Context .........................................................................................................................................223
Table 3-130 Extra Defined Fields for Endpoint Context ..................................................................................................223
Table 3-131 GPD (USB) Field Description ........................................................................................................................235
Table 3-132 BD Field Description ....................................................................................................................................235
Table 3-133 Reset Sequence of USB Device Mode..........................................................................................................254
Table 3-134 USB 3.1 Spread Spectrum Clock (SSC) Electrical Characteristics .................................................................259
Table 3-135 USB 3.1 Gen1 Transmitter and Receiver Electrical Characteristics ..............................................................259

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Table 3-136 ENIC Signal Descriptions ..............................................................................................................................278

Table 3-137 ENIC MII Timing Characteristics ...................................................................................................................279
Table 3-138 ENIC RMII Timing Characteristics ................................................................................................................280
Table 3-139 ENIC RGMII Timing Characteristics ..............................................................................................................281
Table 3-140 ENIC MDIO Timing Characteristics...............................................................................................................282
Table 3-141 PCIe Layers and Components ......................................................................................................................288
Table 3-142 RC Set Address Translation Table for I/O TLP Example ................................................................................289
Table 3-143 ADT Setting Example for Transmit Message TLP .........................................................................................291
Table 3-144 ADT Setting Example for Message Pool Mode ............................................................................................292
Table 3-145 RC Handle LTR Message Interrupt Example .................................................................................................294
Table 3-146 RC Handle Other Supported Message Interrupt Example ...........................................................................295
Table 3-147 Reset Signal Description ..............................................................................................................................297
Table 3-148 Reset Control ...............................................................................................................................................297
Table 3-149 Reset Scope for Pl Exit Event .......................................................................................................................298
Table 3-150 Local Interrupt Table for RC Mode...............................................................................................................299
Table 3-151 RC Set MSI Capability Example ....................................................................................................................303
Table 3-152 RC Clear MSI Status Example .......................................................................................................................303
Table 3-153 RC L1 State Setting.......................................................................................................................................307
Table 3-154 Address Translation Table Address ..............................................................................................................310
Table 3-155 Transfer Parameter ......................................................................................................................................311
Table 3-156 Set Address Translation Table for PCIe to AXI Direction ..............................................................................311
Table 3-157 Set Address Translation Table for AXI to PCIe Direction ..............................................................................313
Table 3-158 PCIe Configuration Space Register Address for Backend .............................................................................314
Table 3-159 PCIE_CFGNUM (0x140) Bit Definition..........................................................................................................314
Table 3-160 RC Initialization Sequence ...........................................................................................................................315
Table 3-161 PCIe Module Register Mapping ...................................................................................................................318
Table 3-162 PCIe Internal Register ..................................................................................................................................319
Table 3-163 PCIe Configuration Space and PCIe Extended Configuration Space ............................................................319
Table 3-164 Loopback Mode Defined in PIPE Specification ............................................................................................322
Table 3-165 PCIe 2.5 GT/s Electrical Characteristics ........................................................................................................322
Table 3-166 PCIe 5.0 GT/s Electrical Characteristics ........................................................................................................323
Table 3-167 PCIe 100 MHz REFCLK Electrical Characteristics ..........................................................................................323
Table 3-168 Power Requirement .....................................................................................................................................324
Table 3-169 KP1 Module Description ..............................................................................................................................337
Table 3-170 Keypad Signal Descriptions ..........................................................................................................................338
Table 3-171 Keypad Setting Flow ....................................................................................................................................339
Table 3-172 GPIO Pin Control ..........................................................................................................................................340
Table 3-173 Driving Strength Control ..............................................................................................................................341
Table 3-174 General 1.8V I/O Cell ...................................................................................................................................341
Table 3-175 KP 2K I/O Cell ...............................................................................................................................................342
Table 3-176 KP 200K I/O Cell ...........................................................................................................................................343
Table 3-177 I3C I/O Cell ...................................................................................................................................................344
Table 3-178 RST I/O Cell ..................................................................................................................................................345
Table 3-179 MSDC3A18 I/O Cell ......................................................................................................................................346
Table 3-180 MSDC3A18OD33 I/O Cell .............................................................................................................................347

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Table 3-181 AGPIO General 1.8V I/O Cell ........................................................................................................................348

Table 3-182 GPIO Signal Descriptions .............................................................................................................................351
Table 3-183 Main Functions of GPIOs .............................................................................................................................356
Table 3-184 Strapping Configurations .............................................................................................................................357
Table 3-185 Strapping Configuration Register .................................................................................................................357
Table 3-186 GPIO Mode Input Programming Outline .....................................................................................................358
Table 3-187 GPIO Mode Output Programming Outline ..................................................................................................358
Table 3-188 Electrical Characteristics and Operating Conditions of 1.8V Applications ...................................................359
Table 3-189 Pulse Width Modulation (PWM) Modes .....................................................................................................359
Table 3-190 PWM Signal Descriptions ............................................................................................................................364
Table 3-191 Normal Mode Setting Procedures ...............................................................................................................364
Table 3-192 FIFO Mode Setting Procedures ....................................................................................................................365
Table 3-193 Memory Mode Setting Procedures .............................................................................................................366
Table 3-194 Random Mode Setting Procedures ..............................................................................................................367
Table 3-195 Operation Mode of GPT ..............................................................................................................................375
Table 3-196 Clock Source of GPT .....................................................................................................................................375
Table 3-197 APXGPT ONE-SHOT Mode Setting Flow .......................................................................................................376
Table 3-198 APXGPT REPEAT Mode Setting Flow ............................................................................................................377
Table 3-199 APXGPT KEEP-GO Mode Setting Flow ..........................................................................................................378
Table 3-200 APXGPT FREERUN Mode Setting Flow .........................................................................................................379
Table 3-201 GPT5 64-bit Counter Read Flow ..................................................................................................................380
Table 3-202 AUXADC Specifications ................................................................................................................................382
Table 3-203 Immediate Mode Programming Sequence ..................................................................................................383
Table 3-204 Background Detection Programming Sequence ..........................................................................................384
Table 3-205 TCSYS Signal Descriptions ............................................................................................................................385
Table 3-206 Locations Monitored by Temperature Sensors ............................................................................................388
Table 3-207 Thermal Controller Programming Guide .....................................................................................................389
Table 3-208 Boot Flash Selection ....................................................................................................................................390
Table 4-1 Ball Map-Top Left.............................................................................................................................................393
Table 4-2 Ball Map-Top Center ........................................................................................................................................394
Table 4-3 Ball Map-Top Right ..........................................................................................................................................395
Table 4-4 Ball Map-Middle Left .......................................................................................................................................396
Table 4-5 Ball Map-Middle Center ..................................................................................................................................397
Table 4-6 Ball Map-Middle Right .....................................................................................................................................398
Table 4-7 Ball Map-Bottom Left ......................................................................................................................................399
Table 4-8 Ball Map-Bottom Center ..................................................................................................................................400
Table 4-9 Ball Map-Bottom Right ....................................................................................................................................401
Table 4-10 Pin Characteristics .........................................................................................................................................402
Table 4-11 Power Rails ....................................................................................................................................................441
Table 5-1 Absolute Maximum Ratings.............................................................................................................................445
Table 5-2 Storage Condition ............................................................................................................................................446
Table 5-3 Recommended Operating Conditions for Power Supply .................................................................................446
Table 5-4 PMIC_RTC32K_CK DC Specifications ...............................................................................................................448
Table 5-5 SPII2CUARTIO DC Specifications ......................................................................................................................449
Table 5-6 I2C/I2S DC Specifications .................................................................................................................................449

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Table 5-7 I3CIO DC Specifications....................................................................................................................................449

Table 5-8 eMMCIO DC Specifications ..............................................................................................................................450
Table 5-9 MSDC1IO DC Specifications (2.8V/3.0V) ..........................................................................................................450
Table 5-10 MSDC1IO DC Specifications ...........................................................................................................................450
Table 5-11 MSDC2IO DC Specifications (2.8V/3.0V) ........................................................................................................451
Table 5-12 MSDC2IO DC ..................................................................................................................................................451
Table 5-13 Reset Signal Descriptions...............................................................................................................................453
Table 5-14 DSI D-PHY TX Electrical Characteristics ..........................................................................................................454
Table 5-15 DSI C-PHY TX Electrical Characteristics ..........................................................................................................455
Table 5-16 CSI D-PHY RX Electrical Characteristics ..........................................................................................................455
Table 6-1 Maximum Performance Ratings ......................................................................................................................456
Table 6-2 ARMPLL_LL Specifications ...............................................................................................................................457
Table 6-3 ARMPLL_BL Specifications ...............................................................................................................................458
Table 6-4 CCIPLL Specifications .......................................................................................................................................458
Table 6-5 ETHPLL Specifications ......................................................................................................................................458
Table 6-6 MSDCPLL Specifications...................................................................................................................................459
Table 6-7 TVDPLL1 Specifications ....................................................................................................................................459
Table 6-8 TVDPLL2 Specifications ....................................................................................................................................459
Table 6-9 MPLL Specifications .........................................................................................................................................460
Table 6-10 MMPLL Specifications....................................................................................................................................460
Table 6-11 MAINPLL Specifications .................................................................................................................................460
Table 6-12 IMGPLL Specifications ...................................................................................................................................460
Table 6-13 UNIVPLL Specifications ..................................................................................................................................461
Table 6-14 ADSPPLL Specifications ..................................................................................................................................461
Table 6-15 APLL1 Specifications ......................................................................................................................................461
Table 6-16 APLL2 Specifications ......................................................................................................................................462
Table 6-17 APLL3 Specifications ......................................................................................................................................462
Table 6-18 APLL4 Specifications ......................................................................................................................................462
Table 6-19 APLL5 Specifications ......................................................................................................................................462
Table 6-20 MFGPLL Specifications ...................................................................................................................................463
Table 6-21 CKSQ Specifications .......................................................................................................................................463
Table 6-22 Clock Signal Descriptions ...............................................................................................................................463
Table 7-1 MT8390 AV/AZA Thermal Operating Specifications ........................................................................................465
Table 7-2 MT8390 IV/KZA Thermal Operating Specifications .........................................................................................465
Table 7-3 Printed Device Reference and Decoding .........................................................................................................466

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1 Introduction

MT8390 is a highly integrated platform incorporating the following key features:

 Dual-core Arm® Cortex®-A78 processor  LPDDR4(X): Up to 8 GB, with memory data rate up
 Hexa-core Arm Cortex-A55 processor to LPDDR4(X)-3733
 Arm Mali™-G57 MC3 3D Graphics Accelerator (GPU)  Display output supporting 4K30 + 4K60 resolution
with Vulkan® 1.1, OpenGL ES 3.2 and OpenCL™ 2.2  Image processing: 32MP @ 30fps for single camera
 Single-core AI Processor Unit (APU) Cadence® capture; 16MP + 16MP @ 30fps for dual camera
Tensilica®VP6 processor with AI Accelerator (AIA) capture
 Single-core Cadence HiFi 5 Audio Engine DSP  Video encoding: 4K @ 30 fps with HEVC/H.264
 Video decoding: 4K @ 75 fps with
AV1/VP9/HEVC/H.264

Figure 1-1 shows the functional block diagram of the device.

MT8390
Application Processing Memory Compute Engines
Arm DynamIQ 2 × EMI HiFi 5 2D/3D GPU
(64-bit LPDDR4(X)) Audio DSP Mali-G57
Two core Six core
Arm Cortex-A78 Arm Cortex-A55 128KB On-chip Boot ROM
Single-Core APU Dual-Core SCP
64KB L1I 64KB L1D 32KB L1I 32KB L1D 192KB On-chip SRAM Vision P6 + AIA MDSP RV55

256KB L2 128KB L2 Display

DPI Video Imaging
(16-bit)
Generic Timers Generic Timers 2 × MIPI CSI
2 × MIPI DSI Video Decoder
(4-lane D-PHY) (4-lane D-PHY) FD
(4K@75fps)
(3-trio C-PHY) (3-trio C-PHY)
2MB Shared L3 HDMI TX
ISP
Video Encoder
DP Single: 32MP @ 30fps
GIC-600 DMA (4K@30fps)
eDP Dual: 16MP + 16MP @30fps

Storage Audio Miscellaneous Connectivity

4 × I2S/TDM 12-bit AUXADC GPIO
(6-channel)
3 × MSDC
eMMC/SD/SDIO 6 × SPI Master ENIC
S/PDIF In/Out PWARP
SS USB DRD
4 × UART
4 × PDM SYSTMR 2 × HS USB DRD

PCM 4 × PWM Keypad (2×2)

Serial NOR Flash Thermal Sensors

5 × I2C
HDMI/DP Audio WDT PCIe
2 × I3C

Figure 1-1 Functional Block Diagram

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1.1 Features Overview

Table 1-1 Device Features
Feature MT8390
Processors
Dual-core Arm Cortex-A78 A78 2200 MHz
Hexa-core Arm Cortex-A55 A55 2000 MHz
Graphics Accelerator Mali-G57 MC3 GPU 950 MHz
HiFi 5 Digital Signal Processor DSP 800 MHz
VP6 832 MHz
AI Processor Unit
MDLA 900 MHz
System Companion Processor SCP 832 MHz
Memory
Up to 8GB
External memory interface (LPDDR4(X)) EMI
LPDDR4(X)-3733
Storage
MSDC0 eMMC (1-/4-/8-bit)
Memory Card Controller eMMC™/SD®/SDIO MSDC1 SD/SDIO (1-/4-bit)
MSDC2 SD/SDIO Card (1-/4-bit)
Serial NOR Flash Interface SNOR Yes
Display
High-Definition Multimedia Interface Transmitter HDMITX HDMI™ 2.0b
Digital Display Parallel Interface DPI 16-bit
DisplayPort Interface DPTX Yes (DP 1.4)
Embedded DisplayPort Interface EDPTX Yes (DP 1.2)
DSI0 4-lane D-PHY, or 3-trio C-PHY
MIPI™ Display Serial Interface
DSI1 4-lane D-PHY, or 3-trio C-PHY
Imaging
Single camera: 32MP @ 30fps
Image Signal Processor ISP
Dual camera: 16MP + 16MP @ 30fps
1 × 4-lane D-PHY, or 2 × 2-lane D-PHY,
CSI0
MIPI Camera Serial Interface 2 or 1 × 3-trio C-PHY, or 2 × 2-trio C-PHY
CSI1 1 × 4-lane D-PHY, or 1 × 3-trio C-PHY
Face Detection FD Yes
Warp Engine WPE Yes
JPEG Encoder JPEG Baseline encoding and decoding (250 MP/s)
Video
Video Encoder VENC HEVC/H.264, 4K @ 30 fps
Video Decoder VDEC AV1/VP9/HEVC/H.264, 4K @ 75 fps
Audio
Inter-IC Sound I2S
4 (2 input, 2 output)
Time Division Multiplexed Interface TDM
Pulse Code Modulation PCM 1
Pulse Density Modulation (Decoder for DMIC) PDM 4 × stereo
Digital Interface SPDIF_IN 2

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Feature MT8390
SPDIF_OUT 1
I2C 5
Inter-Integrated Circuit
I3C 2(1)
Universal Asynchronous Receiver/Transmitter UART 4
Serial Peripheral Interface SPI 6 (master mode only)
USB Port 0 USB 2.0 DRD
Universal Serial Bus USB Port 1 SS USB 3.1 Gen1 DRD
USB Port 2 USB 2.0 DRD
KeyPad Scanner KeyPad 2×2
General Purpose I/O pins GPIO 177
Pulse Width Modulation PWM Up to 4
Peripheral Component Interconnect Express PCIe Gen2, 1-lane, RC mode
Gigabit Ethernet Network Interface Controller ENIC MII/RMII/RGMII
Miscellaneous
Auxiliary ADC AUXADC 12-bit, 6-channel
GPT 5 × 32-bit and 1 × 64-bit
Timers SYSTMR 64-bit
(2)
WDT Yes
Thermal Controller TCSYS Yes
1. I3C5 and I3C6 support MIPI I3C® (SDR mode only).
2. The Watchdog Timer (WDT) is part of the Top Reset Generation Unit (TOPRGU).

1.2 Ordering Information

Table 1-2 Ordering Information
Operating Junction
Order# Marking PCB Thickness (T) HDMI (RX/TX) Package
Temperature
MT8390AV/AZA See Section 7.2 Top Marking -20~95°C TJ T ≤ 1.2mm Yes MFC-VFBGA
MT8390IV/KZA See Section 7.2 Top Marking -40~105°C TJ T ≤ 1.6mm Yes MFC-VFBGA

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2 Preface

2.1 Pin Characteristics and Signal Descriptions Conventions

Table 2-1 describes the column headers in all Pin Characteristic and Signal Description tables in Section 4.2 Pin
Characteristics and Chapter 3 Features Description.

Table 2-1 Column Headers Description

Column Name Explanations
Logical name of the ball. Note that there may exist a selection of several signals for the same ball
Ball Name
(aux mode).
Ball Location Ball's physical location on the chip package
Signal Name The name of the signal for the given aux mode
Pin type when configured for the given aux mode:
 AI: Analog input
 AO: Analog output
 AIO: Analog bi-directional pin
Type  DI: Digital input
 DO: Digital output
 DIO: Digital bi-directional pin
 P: Power
 G: Ground
Description Description of the signal
Auxiliary function mode number:
Aux. Function  0 through 7 are possible alternative functions
 An empty box means Not Applicable and the ball is dedicated to one function only
Reset State Shows the Aux. function configured at the release of the SYSRSTB signal
Buffer Type Describes the associated input/output buffer type
Power Domain Indicates the voltage supply that powers the terminal IO buffers
Indicates the state of an internal pull-up or pull-down resistor at the release of the SYSRSTB signal:
 OFF: Internal pull-up and pull-down are disabled
 PU: Pull-up is enabled
PU/PD
 PD: Pull-down is enabled
 No: Pull-up and pull-down not available
 Blank cell means "No"
IO Reset Value Shows the IO state at the release of the SYSRSTB signal

2.2 Timing Conventions, Parameters, and Information

This section provides a general description of used symbols, adopted standards and terminology, and test process. All
timing characteristics are valid over the represented operating conditions unless otherwise specified.

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The interface clock frequency documented in this datasheet is the maximum clock frequency, which corresponds to the
maximum programmable frequency on the particular output clock. The frequency defines the maximum limit supported
by the device and does not consider into account any system limitation (layouts, connectors, and so forth).
The system designer should take into account these system considerations and the device timing characteristics as well and
should determine properly the maximum frequency supported to transfer the data on the corresponding interface.
The timing parameter values do not include delays by board routes. Timing values may be adjusted by
increasing/decreasing such delays. If needed, external logic hardware such as buffers may be used to compensate any
timing differences.

2.2.1 Timing Parameters and Information

Table 2-2 represents timing parameter symbols and descriptions used in the timing characteristic tables.

Table 2-2 Timing Parameters

Symbol Description
fop Operating frequency
tp Period (cycle time)
td Delay time
tdis Disable time
ten Enable time
th Hold time
tsu Setup time
Start Start bit
tt Transition time
tv Valid time
tw Pulse duration
tFALL Fall time
tRISE Rise time
VOH High level output voltage
VOL Low level output voltage
VIH High level input voltage
VIL Low level input voltage
VREF Reference voltage

2.2.2 Parameter Information

This datasheet provides timing values at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be also taken into account.
All timing requirements and switching characteristics are valid over the recommended operating conditions unless
otherwise specified.
All rise and fall transition timing parameters are referenced correspondingly to 90% and 10% of the signal logical levels,
unless otherwise specified.

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2.3 Abbreviations
A

ACP
Accelerate Coherency Port
ADC
Analog to Digital Convertor
AE
Auto Exposure
AER
Advanced Error Reporting
AES
Advanced Encryption Standard
AF
Auto Focus
AFBC
ARM Frame Buffer Compression
AHB
Advanced High-Performance Bus
AI
Artificial Intelligence
AIA
AI Accelerator
ALLM
Auto Low Latency Mode
AP
Application Processor
APB
Advanced Peripheral Bus
APC
Address Protection Controller
API
Application Programming Interface
APMCU
Application Processing Microcontroller Unit
APU
AI Processor Unit
APXGPT
Application Processor X General Purpose Timer
ASPM
Active State Power Management
ASRC
Asynchronous Sample Rate Converter
ASSR
Alternative Scrambler Seed Reset

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AUXADC
Auxiliary Analog/Digital Converter
AV
Audio Video
AVB
Audio Video Bridge
AWB
Auto White Balance
AXI
Advanced eXtensible Interface
B

BCLK
Baud Clock
BD
Buffer Descriptor
BDP
Buffer Descriptor Present
BTA
Bus Turnaround
C

CBS
Credit-based Shaper
CCC
Common Command Code
CCU
Camera Control Unit
CDR
Clock and Data Recovery
CEC
Consumer Electronics Control
CG
Clock Gating
CIC
Configuration Information Capability
CKSYS
Clock System
CKSQ
Clock Squarer
CMDE
Command Engine
CMDQ
Command Queue
CPHA
Clock Phase

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CPOL
Clock Polarity
CPU
Central Processing Unit
CPUBIU
CPU Bus Interface Unit
CRC
Cyclic Redundancy Check
CS
Complete Spilt
CSC
Color Space Conversion
CSI
Camera Serial Interface
CTS
Clear to Send
CTSI
Clear to Send Interrupt
CV
Computer Vision
D

DA
Destination Address
DAA
Dynamic Address Assignment
DDC
Display Data Channel
DDR
Dual Data Rate
DFS
Dynamic Frequency Scaling
DLL
Divisor Latch LS (Least Significant Bit)
DLM
Divisor Latch MS (Most Significant Bit)
DMA
Direct Memory Access
DMIC
Digital Microphone
DO
Digital Output
DP
DisplayPort
DP TX
DisplayPort Transmitter

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DP TX AUX
DisplayPort Transmitter Auxiliary Channel
DPI
Display Parallel Interface
DRAM
Dynamic Random Access Memory
DRD
Dual-Role-Device
DRE
Dark Region Enhancement
DRM
Digital Rights Management
DSC
Display Stream Compression
DSD
Direct Stream Digital
DSI
Display Serial Interface
DSP
Digital Signal Processor
DSU
DynamicIQ Shared Unit. Also referred to as the “CPU cluster” or “cluster” in this document.
DVFS
Dynamic Voltage and Frequency Scaling
DVI
Digital Visual Interface
E

ECC
Error Correction Code/Error Checking and Correction
ECRC
Endpoint Cyclic Redundancy Check
ED
Endpoint
EDID
Extended Display Identification Data
EDMA
External Data Memory Access
eDP
Embedded DisplayPort
EEE
Energy Efficient Ethernet
EINT
External Interrupt
ELSI
Enable Line Status Interrupt

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EMI
External Memory Interface
eMMC
Embedded MultiMediaCard
ENIC
Ethernet Network Interface Controller
EOL
End of List
ERBFI
Enable RX Buffer Full Interrupt
ETBEI
Enable TX Buffer Empty Interrupt
F

FCR IIR
FIFO Control Register/Interrupt Identification Register
FD
Face Detection
FIFO
First In First Out
FHD
Full High-Definition
FLADJ
Frame Length Adjustment Register
FM
Fast Mode
FM+
Fast Mode Plus
FPU
Floating Point Unit
FSM
Finite State Machine
G

GIC
Generic Interrupt Controller
GPGPU
General Purpose computing on GPU
GPIO
General-purpose Input/Output
GPT
General-Purpose Timer
GPU
Graphics Processing Unit
H

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HCI
Host Controller Interface
HCLK
Hopping Clock
HDCP
High-bandwidth Digital Content Protection
HDMI
High Definition Multimedia Interface
HDMITX
High Definition Multimedia Interface Transmitter
HDR
High Dynamic Range
HEIF
High Efficiency Image File
HLG
Hybrid Log Gamma
HLOS
High-Level Operating System
HP
Half Precision
HPD
Hot Plug Detect
HSYNC
Horizontal Sync
HWO
Hardware Ownership
I

I2C
Inter-Integrated Circuit
I2S
Inter-IC Sound
I3C
Improved Inter-Integrated Circuit
ICE
In-Circuit Emulator
IECR
Interrupt Enable Clear Register
IER
Interrupt Enable Register
IESER
Interrupt Enable Set Register
IMODI
Interrupt Moderation Interval
INTC
Internal Interrupt Controller

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IoC
Interrupt On Completion
IoT
Internet of Things
IPC
Inter-Processor Communication
IPG
Inter-Packet Gap
IPPC
IP Power Control
IRQ
Interrupt Request
ISA
Instruction Set Architecture
ISP
Image Signal Processor
ISR
Interrupt Service Routine
J

JTAG
Joint Test Action Group
K

KP
Keypad
L

L1PMSS
L1 Power Management Substates
L2TCM
L2 Tightly-Coupled-Memory
LCD
Liquid-Crystal Display
LCR
Line Control Register
LFPS
Low Frequency Periodic Signaling
LPM
Lower power management
LSB
Least Significant Bit
LSR
Line Status Register
LTR
Latency Tolerance Reporting

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LTSSM
Link Training and Status State Machine
LVTS
Low Voltage Thermal Sensor
M

MAC
Multiply-Accumulate/Media Access Control
MBIST
Memory Built-In Self-Test
MBOX
Mailbox
MCR
Modem Control Register
MCU
Microcontroller Unit
MDC
Management Data Clock
MDIO
Management Data Input/Output
MDLA
MediaTek Deep Learning Accelerators
MFG
MediaTek Flexible Graphics
MII
Media Independent Interface
MIPI
Mobile Industry Processor Interface
MISO
Master in slave out
MMU
Memory Management Unit
MOSI
Master out slave in
MPP
Multi-Page Program
MPS
Maximum Packet Size
MPU
Memory Protection Unit
MSA
Main Stream Attribute
MSB
Most Significant Bit
MSDC
MMC (MultiMediaCard) and SD (Secure Digital) Controller

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MSI
Message Signaled Interrupt
MSR
Modem Status Register
MTL
MAC Transaction Layer
MTT
Multiple Transaction Translator
MUX
Multiplexer
N

NN
Neural Network
O

OTG
On-The-Go
P

PCIe
Peripheral Component Interconnect Express
PCLK
Peripheral Clock
PCM
Pulse Code Modulation
PDM
Pulse Density Modulation
PHY
Physical Layer
PHYA
Analog PHY
PHYD
Digital PHY
PIF
Processor Interface
PIO
Programmed Input/Output
PIPE
PHY Interface for PCI Express
PLL
Phase-Locked Loop
PMIC
Power Management Integrated Circuit
PMSS
Power Management Substates

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POR
Power-On-Reset
PP
Page Program
PPB
Private Peripheral Bus
PPS
Pulse-Per-Second
PVT
Process, Voltage, and Temperature
PWM
Pulse Width Modulation
PQ
Perceptual Quantizer
Q

QE
Quad Enable
QMU
Queue Management Unit
QoS
Quality of Service
R

RBR
RX Buffer Register
RC
Root Complex
RGMII
Reduced GMII
RH
Relative Humidity
RL
Read Latency
RMII
Reduced MII
RMS
Root Mean Square
RPU
Region Protection Unit
RQS
Receive Queue Size
RSF
Receive Store and Forward
RTC
Real Time Clock

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RTOS
Real Time Operating System
RTS
Request to Send
RTSI
Request to Send Interrupt
RX
Receiver
S

SA
Source Address
SAR
Successive Approximation Register
SCK
Serial Clock
SCL
Serial Clock Line
SCP
System Companion Processor
SCR
Scratch Register
SDA
Serial Data Line
SDIO
Secure Digital Input/Output
SDK
Software Development Kit
SDM
Sigma-Delta Modulation
SDR
Single Data Rate/Standard Dynamic Range
SDRAM
Synchronous Dynamic Random-Access Memory
SFD
Start of Frame Delimiter
SIMD
Single Instruction Multiple Data
SM
Standard Mode
SMI
Smart Multimedia Interface
SNFC
Serial NOR Flash Controller
SoC
System on Chip

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SP
Single Precision
SPDIF
Sony/Philips Digital Interface Format
SPI
Serial Peripheral Interface
SPM
System Power Management
SRAM
Static Random Access Memory
SRC
Sampling Rate Converter
SSC
Spread Spectrum Clocking
SSUSB
SuperSpeed Universal Serial Bus
SYSTMR
System Timer
SW
Software
SYSRAM
System Static Random Access Memory
T

TCM
Tightly Coupled Memory
TCSYS
Thermal Control Subsystem
TDM
Time Division Multiplexing
TE
Tearing Effect
THR
TX Holding Register
THRE
TX Holding Register Empty
TLP
Transaction Layer Packet
TMDS
Transition-Minimized Differential Signaling
TOPRGU
Top Reset Generation Unit
TOPS
Tera Operations Per Second
TQS
Transmit Queue Size

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TRB
Transfer Request Block
TSMCU
Thermal Sensing Micro Circuit Unit
TSN
Time-Sensitive Networking
TT
Transaction Translator
TTC
Transmit Threshold Control
TU
Transfer Unit
TX
Transmitter
TXQEN
Transmit Queue Enable
U

UART
Universal Asynchronous Receiver/Transmitter
UI
Unit Interval
USB
Universal Serial Bus
UTMI
USB2.0 Transceiver Macrocell Interface
V

VBID
Vertical Blanking ID
VC
Virtual Channel
VDEC
Video Decoder
VENC
Video Encoder
VIC
Vectored Interrupt Controller
VLIW
Very Long Instruction Word
VP6
Tensilica Vision Processor 6
VPP
Video Processing Pipe
VRR
Variable Refresh Rate

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VSYNC
Vertical Synchronization
W

WDT
Watchdog Timer
WEL
Write Enable Latch
WIP
Write in Progress
WPE
Warp Engine
WRR
Weighted Round Robin
X

xHCI
Extensible Host Controller Interface
XIP
eXecute in Place
XOFF
Transmit Off
XON
Transmit On
Z

ZLP
Zero Length Packet

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3 Features Description

The MT8390 device is a highly-integrated, powerful platform designed for a wide range of Artificial Intelligence (AI) and
Internet of Things (IoT) use cases requiring high-performance edge processing, advanced multimedia and connectivity
capabilities, multiple high-resolution cameras, connected touchscreen displays, and use of a multi-tasking High-Level
Operating System (HLOS).

The highly-capable octa-core application processor utilizes the Arm® DynamIQ™ technology by combining high-
performance Cortex-A78 and power-efficient Cortex-A55 cores, equipped with Arm Neon™ engine. The application
processor offers the necessary processing power to support the latest OpenOS, along with its demanding applications such
as web browsing, email and games. This content can be enhanced by the 2D/3D graphics accelerator (Arm Mali-G57 MC3
GPU) and then visualized on a high-resolution touchscreen display. To provide advanced multimedia applications and
services such as streaming audio and video, the device features multi-standard video encoder and decoder engines, and an
advanced audio subsystem.

The AI Processor Unit (APU) enables deep learning, Neural Network (NN) acceleration, and Computer Vision (CV)
applications. The latter, combined with the up to 32MP camera, can clearly and accurately perform AI-vision functions such
as facial recognition, object identification, scene analysis, optical character recognition and much more.

An extensive set of interfaces, connectivity, flexible storage and memory options further enhance the capabilities of the
device and give product designers freedom to customize.

3.1 Application Processor

3.1.1 Overview
The MCUSYS (the application processor subsystem) is responsible for running the operating system and application
programs, providing different levels of power efficiency and computing power to satisfy a wide range of system power and
performance requirements. It is composed of:

 A local bus fabric (CPUBIU, Central Processing Unit (CPU) Bus Interface Unit)
 An interrupt controller (GIC-600)
 A CPU cluster (DSU with the CA78 and CA55 cores)

The Cortex-A55 cores are specifically optimized for power efficiency to minimize the power consumption for daily usage
scenarios and lightweight applications, while the Cortex-A78 cores are designed for performance-driven applications, and
providing the best user experiences for heavy tasks.

The MCUSYS supports the DVFS (Dynamic Voltage Frequency Scaling) technology to allow the CPU to run at different
frequencies and voltage configurations depending on the application requirements. Additionally, the power of each CPU
core can be individually turned off when not in use. In the standby mode, the MCUSYS can be completely shut down to
further reduce power consumption.

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3.1.2 Features

 6 × Arm Cortex-A55 cores with 32KB I/D cache and 128KB L2 cache
 2 × Arm Cortex-A78 cores with 64KB I/D cache and 256KB L2 cache
 2MB L3 cache
 Interrupt controller, Arm GIC (Generic Interrupt Controller)-600
 Advanced DVFS mechanism

3.1.3 Block Diagram

MCUSYS

2.0GHz 2.0GHz 2.0GHz 2.0GHz 2.0GHz 2.0GHz 2.4GHz 2.4GHz

CA55 CA55 CA55 CA55 CA55 CA55 CA78 CA78
32KB I/D L1 32KB I/D L1 32KB I/D L1 32KB I/D L1 32KB I/D L1 32KB I/D L1 64KB I/D L1 64KB I/D L1
128KB L2 128KB L2 128KB L2 128KB L2 128KB L2 128KB L2 256KB L2 256KB L2

1.7GHz MCU
DynamIQ CFG
APB
2MB L3

128 128

S1 1.7GHz S0
CPUBIU GIC-600
AXI
M1 M2 M0

128 128
128 64

emi emi infra

Figure 3-1 Block Diagram of MCUSYS

 The MCUSYS consists of

 6 Arm Cortex-A55 cores
 2 Arm Cortex-A78 CPU cores
 The cores are integrated into the DynamicIQ Shared Unit (DSU), also known as the “CPU cluster” or “cluster”.
 The DSU has a snoop control unit to manage data coherency, while a 2MB L3 cache is shared with the CPU cores.
 The GIC-600 manages interrupts between the CPU cores and systems.
 The Accelerate Coherency Port (ACP) interface provides coherent transactions support between the MCUSYS and
other execution engines such as the GPU (Graphics Processing Unit). The debug APB (Advanced Peripheral Bus)
interface connects to the MCUSYS debug logic providing the debug functions.
 The MCUSYS utilizes the AXI (Advanced eXtensible Interface) to access system memory and devices.

3.1.4 Function Description

The CPU cluster service application execution and operation systems collaborate with the advanced DVFS mechanism to
achieve a balance between power and performance for a wide range of workloads.

The CPUBIU routes transactions to dedicated memory channels, reducing path latency and improving access performance,
but it does not support coherency functions. The GIC-600 supports and manages interrupts in the MCUSYS for interrupt
masking, prioritization, and security. Additionally, the debug logic of the MCUSYS supports static debugging to connect to

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the system via certain interfaces (e.g. via the JTAG), allowing cross-triggering of internal and external trigger events for
debugging.

3.1.5 Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

3.1.6 References

 Arm® Cortex®-A55 Core Technical Reference Manual

 Arm® Cortex®-A78 Core Technical Reference Manual
 Arm® DynamIQ™ Shared Unit Revision: r4p1 Technical Reference Manual
 Arm® CoreLink GIC-600 Generic Interrupt Controller Technical Reference Manual

3.2 Graphics Accelerator

3.2.1 Overview
MFG (MediaTek Flexible Graphics) contains the Mali-G57 Graphics Processing Unit (GPU) and clock/reset control logic. The
Mali-G57 series of GPUs process extremely complicated graphics and perform general processing tasks assigned by the
main application processor.

3.2.2 Features
The Mali-G57 GPU includes the following features:

 A programmable architecture.
 An API feature set with support for shader-based and fixed-function graphics Application Programming Interfaces
(APIs).
 Anti-aliasing capabilities.
 An effective core for General-Purpose Computing on GPU (GPGPU) applications.
 High memory bandwidth and low power consumption for 3D graphics content.
 Performance leading 3D graphics.
 Arm AMBA® 1 AXI slave interface for GPU configuration.
 1 x 256-bit Arm AMBA 1 AXI master interface for external memory access.
 Easy integration.
 Latency tolerance.
 Compressed texture formats.
 Configurable per-core power management for enabling the optimal power and performance combination for each
application.
 Coherency aware interconnects for system memory and resource sharing.
 Arm Frame Buffer Compression (AFBC) 1.3.
 8-bit, 10-bit, and 16-bit YUV input and output formats.

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 Secure processing of Digital Rights Management (DRM)-protected content.

 Level-2 cache
 1 × 512KB
 4-way set associative
 The GPU supports these compute API standards
 OpenCL up to 2.2
 The GPU supports these graphics API standards
 OpenGLES 1.1, 2.0, and 3.2
 Vulkan 1.0 and 1.1

3.2.3 Block Diagram

This diagram shows the main components and interfaces of MFG.

Figure 3-2 Block Diagram and Interface of MFG

3.3 Digital Signal Processor

3.3.1 Overview
The Digital Signal Processor (DSP) is responsible for running the operating system and application programs. It comprises:

 Single-core Cadence HiFi 5 Audio Engine DSP

 AXI3 bus interface unit (in-house MediaTek bus)
 System Power Management Controller (SPMC)

The Cadence HiFi 5 DSP is a highly optimized audio processor geared for efficient execution of audio and voice codecs and
pre- and post-processing modules.

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The HiFi 5 DSP is a five-slot VLIW (Very Long Instruction Word) machine that can execute up to eight 32x32-bit MACs,
sixteen 32x16-bit MACs, and sixteen 16x16-bit MACs per cycle. It has the ability to issue two 128-bit loads per cycle, or one
load and one store of 128 bits per cycle for the parallel loads and stores of the operand and results. The HiFi 5 DSP offers
the additional floating-point precision support for enhanced audio and voice processing through an optional Single
Precision Floating Point Unit (SP FPU), which can perform eight single precision IEEE-754 floating-point MACs per cycle.
Since the audio and voice processing at the front-end is conducted in the frequency domain, both the floating-point and
fixed-point MAC operations in the HiFi 5 DSP are enhanced to operate on complex data types.

For supporting neural network-based speech recognition algorithms, the HiFi 5 DSP provides a Neural Network Extension
option that enables the hardware to perform up to thirty-two 8x16, 4x16, and 8x8-bit MACs per cycle. The multiplication
operations support both signed and unsigned operands as well as operands with 4-bit precision. A few speech neural
network implementations also use half-precision floating-point variables. For such networks, the HiFi 5 DSP offers a HP
(Half Precision) FPU option that provides up to 16 half-precision IEEE-754 floating point MACs per cycle. The instruction set
is designed to address both dot products and convolution operations to cover several types of neural network
implementations used in the speech recognition.

3.3.2 Features
 Single-core Cadence HiFi 5 DSP operates at 720 MHz (0P75V), including:
 64KB L1 I-cache
 128KB L1 D-cache
 Data retention not supported by Pre-fetch buffer, I-cache, D-cache, ITag, and DTag JTAG (Joint Test Action Group)
 25 interrupts configurable by intc
 Supports the SPM to control power sequence.

 Peripheral:
 512KB L2TCM
 One UART
 Five mailboxes
 Ten semaphores
 One system timer
 One watchdog timer

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3.3.3 Block Diagram

System
signal Interrupt

ADSP SYS

HiFi5 Core
BReset Master AXI
Reset
Synchronizer
JTAG
interface
Access DSP AUDIO
Port Xtensa LX WDT DSP_CFG
UART SYS

DReset
Debug
Trace Module Slave AXI
Memory

ICache

DCache

Prefetch

System
Perisys
RAM

Figure 3-3 HiFi 5 DSP Block Diagram

3.3.4 Function Description

[Link] Pipeline Stages

The DSP consists of a seven-stage pipeline with two-cycle latency for both the instruction-memory fetch and the data-
memory fetch.

 Pipeline length 7
 Instruction memory fetch latency 2
 Cycle of execute stage 1
 Cycle of modify stage 3
 Cycle of write-back stage 4

[Link] Layer 1 Cache Controller

The host processor of the DSP includes a cache controller that has a 64KB instruction cache and a 128KB data cache
implemented to improve the code/data fetch performance.

To further enhance cache performance, the data cache supports write-back operations. Additionally, the data cache can be
switched programmatically between write-back and write-through modes.

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Both the instruction cache and data cache support dynamic-cache-way-disable. This feature allows for the independent
disabling and re-enabling of cache ways in both caches. It also facilitates power saving, as you can clean cache ways before
disabling them and initialize cache ways when enabling them. When a cache way is disabled, the cache memory block from
service is removed, and therefore the total cache capacity is reduced by “1/(number of ways in service)”.

 Instruction cache details

 Instruction cache size in bytes 65536
 Instruction cache ways 4
 Instruction cache line size bytes 128
 Dynamic way disable Supported

 Data cache details

 Data cache size in bytes 131072
 Data cache ways 4
 Data cache line size bytes 128
 Data cache write-back Supported
 Dynamic way disable Supported

[Link] Memory Management

The Memory Protection Unit (MPU) provides memory protection functionality with a smaller footprint than the Linux-
compatible Memory Management Unit (MMU) while offering greater flexibility and features than the Region Protection
Unit (RPU).

The features of MPU are as follows:

 A configurable number (16 or 32) of entries that determine the regions

 A configurable address granularity (minimum: 4KB)
 12 choices of access-rights settings per region
 More than 200 different memory-type choices per region, including the ability to specify the internal L1 cache
behavior, which is different from an external, AXI or PIF (Processor Interface), cache behavior (attributes)
 Identity map implementation: No address translation
 Runtime modifiable foreground memory map
 Static background memory map
 Unified instruction and data memory maps

[Link] Interrupt

The DSP supports 32 maskable interrupts with four priority levels.

Table 3-1 INTC Interrupt

Interrupt Type Level BInterrupt Pin Note
0 Level 1 0 UART
1 Level 1 1 spm2adsp_wakeup

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Interrupt Type Level BInterrupt Pin Note

2 Level 1 2 Mailbox
3 Level 1 3 dsp_timer_irq[1]
4 Level 1 4 dsp_timer_irq[2]
5 Level 1 5 sw_int 0
6 Edge 1 6 sw_int NEW
7 Edge 1 7 sw_int 2
8 Level 2 8 I2c_irq
9 Level 2 9 asrc0_irq
10 Level 2 10 asrc1_irq
11 Level 2 11 asrc2_irq
12 Level 2 12 asrc3_irq
13 Level 2 13 os_timed_irq
14 Level 2 14 DMA irq
15 Level 2 15 audiosys_irq
16 Level 3 16 HiFi5_wdt_int
17 Level 3 17 no used
18 Level 3 18 Timer_merge_irq
19 Level 3 19 scp_irq
20 Level 4 20 no used
21 Level 4 21 latency_moniter_irq
22 Level 4 22 bus_tracker_irq
23 Edge 3 23 wakeup_source_irq
24 Edge 3 24 infra_bus_hang_timeout_irq

3.3.5 Theory of Operations

 HiFi 5 DSP User Guide

 Xtensa LX7 Microprocessor Data Book

[Link] Debug Monitor Register

The DSP contains a set of debug monitor registers that enable the monitoring of the internal signals within the DSP core for
debugging purposes. For more information, please refer to Xtensa Debug Guide.

Table 3-2 Debug Signals

Signal I/O Description Dsp0cfg_reg
PDebugEnable Input Trace enable PDebugBus0[0]
PDebug_latch_en PDebugBus0[4]
PDebugData[31:0] Output Trace debug data PDebugData
Inbound PIF transaction
PDebugInbPIF[ 7:0] Output PDebugBus1[31:24]
information

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Signal I/O Description Dsp0cfg_reg

Outbound PIF transaction
PDebugOutPIF[ 7:0] Output PDebugBus1[23:16]
information
PDebugInst[31:0] Output Instruction information PDebugInst
PDebugLS0Stat Output LSU0 status PDebugLS0Stat
PDebugLS1Stat Output LSU1 status PDebugLS1Stat
PDebugPC Output Trace program counter PDebugPC
PDebugPrefetchL1Fill[3:0] Output Prefetch L1 fill information PDebugBus0[19:16]
PDebugPrefetchLookup[7:0] Output Prefetch lookup information PDebugBus1[15:8]
PDebugStatus[7:0] Output Trace status information PDebugBus1[7:0]

3.3.6 Power Management

[Link] Constraint to Access DSP Configuration Register

The DSP configuration register is in the Always-On power domain.

[Link] Sleep and Wakeup

1. After the WAITI instruction is completed, the DSP sets the interrupt level in the [Link] register to the value
encoded by the instruction.
2. The processor then waits for all processor memory interfaces to become idle and asserts the DSP_PWaitMode signal.
3. During this time, all processor operations are suspended until a non-masked interrupt occurs.

Note:
 Please refer to Xtensa LX7 Microprocessor Data Book 22.5.

3.3.7 Programming Guide

[Link] Basic Setting

 HiFi 5 DSP User Guide

 Xtensa LX7 Microprocessor Data Book

[Link] Basic Setting Flow

Basic Setting

1. Load instruction code and data code to 0x10D0_0000~0x10D7_FFFF (512KB L2TCM)

2. Change the DSP clock to an at-speed clock, with the default speed of 26 MHz.
a. CLK_CFG_17[3:0] = 0x0; *CLK_CFG_UPDATE2[4] = 0x1; change clock from DSPPLL. (DSPPLL_CON1 can modify
DSPPLL frequency)
3. PWR ON DSP PWR

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4. Set AltResetVec to the value 0x4E100000 (If needed)

5. Set Initial Setting
a. Set StatVectorSel (0x10B8_B00C[0]0) to 1
b. Keep RunStall (0x10B8_000C[31]) to 1 (default)
c. Set DReset_sw (0x10B8_0000[4]) to 1
d. Set BReset_sw (0x10B8_0000[0]) to 1
6. Set Initial Setting
a. Keep StatVectorSel (0x10B8_B00C[0]) to 1
b. Keep RunStall (0x10B8_000C[31]) to 1 (default)
c. Set DReset_sw (0x10B8_0000[4]) to 0
d. Set BReset_sw (0x10B8_0000[0]) to 0
7. Set Reset_sw = 0x10
a. Keep Set StatVectorSel (0x10B8_B00C[0]) to 1
b. Set RunStall (0x10B8_000C[31]) to 1 (release run_stall)
c. Keep DReset_sw (0x10B8_0000[4]) to 0
d. Keep BReset_sw (0x10B8_0000[0]) to 0

3.3.8 Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

3.3.9 Reference

 HiFi 5 DSP User Guide

 Xtensa LX7 Microprocessor Data Book
 Xtensa Debug Guide

3.4 AI Processor Unit

3.4.1 Overview
The MediaTek AI Processor Unit System (APUSYS) significantly enhances multimedia performance by exhibiting remarkable
computing capabilities. The key components of the APUSYS are:

 Single-core programmable Tensilica Vision Processor 6 (VP6), for both the traditional Computer Vision (CV) algorithms
and Neural Network (NN) algorithms.
 Single-core MediaTek Deep Learning Accelerators (MDLA), for the NN algorithms.

The hardware design is specifically optimized for job allocation between the NN (MDLA) and CV (VP6) engines, resulting in
efficient performance. The External Direct Memory Access (EDMA) engine supports data movement and format
conversion.

For external interface parts, there are four AXI buses to access the external DRAM. The APUSYS exchanges data with other
subsystems through the external DRAM.

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3.4.2 Features
 The VP6 supports both the AI and CV.
 Per core configuration
 L1 Instruction memory per core: 64 KB + 128 KB cache
 L1 data memory per core: 128 KB + 128 KB
 vFPU to support high-precision requirement applications
 Top performance:
 Fix 8: 0.43 TOPS
 Fix 16: 0.11 TOPS
 FP16: 0.05 TOPS
 FP32: 0.03 TOPS

 The MDLA supports high-computation demands NN applications.

 Peak power reduction
 Top performance:
 8(A) x 8(W) : 3.6 TOPS
 16(A) x 16(W): 0.9 TOPS
 FP16 : 0.9 TOPS
 Simultaneous pipelined hardware function block (CONV/ACT/POOL/EWE/BILINEAR)
 Enhancement of layer fusion to further reduce DRAM memory bandwidth
 Supports Android NN asymmetric quantized data format.
 Supports compressed weight to reduce DRAM bandwidth.
 Supports Android NN asymmetric quantized data format.
 Supports compressed weight to reduce DRAM bandwidth.

 The EDMA supports data movement and data format conversion.

 Format conversion and data movement between memories

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3.4.3 Block Diagram

APMCU
(Cortex-A)

APUSYS

VP6 MDLA

APU NoC

IOMMU eDMA

Post Bus Fabric

EMI

DRAM

Figure 3-4 Block Diagram and Interface of APUSYS

3.4.4 Function Description

[Link] VP6

[Link].1 Overview

The Tensilica Vision-P6 DSP (VP6) is a programmable AI processor unit with high-performance and high-flexibility for vision
applications. There is one VP6 in APUSYS.

Each VP6 has a 5-slot Very Long Instruction Word (VLIW) architecture. To achieve high-performance computing, it utilizes
the multiply-accumulate (MAC) unit to compute up to 256 8 bits x 8 bits MACs in one cycle. To achieve high-throughput
bandwidth for computing, it uses up to “2-slot 64-byte loads” or “1-slot 64-byte load and 1-slot 64-byte store” to access
128-byte data bandwidth in one cycle.

Each VP6 is a vector Single Instruction Multiple Data (SIMD) DSP. For high-flexibility programming, it supports 64-way 8-bit
operations, 32-way 16-bit operations, and 16-way 32-bit operations in fixed-point format. It also supports 16-way single-
precision operations and 32-way half-precision operations in floating-point format.

Each VP6 supports special features. The Scatter/Gather operations enhance random accessing to local Data RAM, and the
histogram operations accelerate binning function.

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[Link].2 Features

Table 3-3 shows the features of a single VP6.

Table 3-3 Features of a Single VP6

Feature Configuration
Instruction RAM 64KBytes
Instruction Cache 128KBytes
Data RAM 256KBytes
8 bits x 8 bits: 256 (64-way multiply or multiply-accumulate quad operations)
Number of MACs 8 bits x 16bits: 128 (64-way multiply or multiply-accumulate pair operations)
in fixed-point operations 16bits x 16bits: 64 (32-way multiply or multiply-accumulate pair operations)
32 bits x 16 bits: 16 (16-way multiply or multiply-accumulate operations)
Number of MACs 16 bits x 16 bits: 32 (32-way multiply or multiply-accumulate operations)
in floating-point operations 32 bits x 32 bits: 16 (16-way multiply or multiply-accumulate operations)
Half-precision operations 32-way half precision vector FPU
Single-precision operations 16-way single precision vector FPU
Histogram operations Native histogram instructions
Scatter/Gather operations 32-way 16-bit vector elements accessing to local Data RAM
iDMA 64 outstanding re-order buffers
User TIE MTK_TIE2APB: Accessing ability to APB (Advanced Peripheral Bus)
Note:
 TIE denotes “Tensilica Instruction Extension”.
 The User TIE “MTK_TIE2APB” is used to support APB master in Vision-P6 DSP. The programmer can use API functions such as
“IPU_SendAPBWrite(data,addr)” and “IPU_SendAPBRead(data,addr)” to use APB transaction to access configuration registers.

[Link].3 Block Diagram

Confidential A
Figure 3-5 shows the block diagram of a single VP6.

DMEM0 DMEM1
Bank0 Bank1 Bank0 Bank1

512b 512b 512b 512b

Mux
512b x2 512b x2 512b
128b L/S
IMEM

128b
core iDMA
I$

128b 128b 128b

Mux
AXI Slave AXI Master
S 128b M 128b

Figure 3-5 VP6 Block Diagram

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[Link] MDLA

[Link].1 Overview

The MediaTek Deep Learning Accelerator (MDLA) comprises three primary components and handles the following tasks:

 Command engine (CMDE): Decodes commands and maps them to the corresponding registers. It receives input
commands and converts them into a format that is interpretable by other components of the MDLA.
 Convolutional engines and non-convolutional engines: Operate on the input to efficiently generate the desired tensor
data.

[Link].2 Features

 Convolutional engine
 Convolutional 2D
 Depth-wise convolutional
 Fully connected
 Transpose convolutional
 Dilated convolutional
 Element-wise engine
 Element-wise functions:
 BN, Mul, Add, Sub, Max, Min, Abs, Neg, Sqr, IN_sub
 Activation functions:
 ReLu, ReLu1, ReLu6, PreLu, Sigmoid, Tanh, Elu, GeLu, Exp, Rcp, Sqrt, Mish, Rsqrt
 Pool engine
 Pooling functions:
 Global pooling, Local pooling
 Resize function
 Resize bilinear, resize nearest (nearest-neighbor interpolation), resize nearest floor
 Transpose engine
 C-W transpose
 Depth2Space
 Space2Depth
 Store engine: Reshape

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[Link].3 Block Diagram

MDLA
Conv. Engine

Element-wise Engine

CMDE
Pool Engine

Transpose Engine

Store Engine

Figure 3-6 Key Block Diagram of MDLA

[Link] EDMA

[Link].1 Overview

The External Direct Memory Access (EDMA) serves the exchange and conversion of data formats between the
APUSYS and other subsystems or engines. This allows the computing engines, such as the MDLA and VP6, to
avoid the negative effects of inconsistent data formats from other subsystems. Consequently, the exchanged data
format within the APUSYS is more uniform and efficient.

[Link].2 Features

 Normal functions:
 Data copy
 Fill constants
 Numeric conversion
 F16 to F32
 F32 to F16
 Format conversion
 RGGB to Bayer
 Bayer to RGGB

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3.4.5 Theory of Operations

APP
Intrusion detection, face recognition, ...

Public NN Framework
TensorFlow, PyTorch, ANN, ...

MediaTek Frontend/Backend SDK

CV/NN Library and Toolchain

APUSYS
MDLA VP6

EDMA

Figure 3-7 APU Theory of Operation Construction

To enable effective uses of the APU, public frameworks provide a reliable foundation, on which software can be
built. These frameworks offer a structured approach to application development and are designed to simplify the
process. Several open-source NN frameworks, including TensorFlow, PyTorch, and ANN, are used to construct
Software Development Kits (SDK), which provide APIs and libraries that allow developers to access and control
both the MDLA and VPU hardware.

3.4.6 Programming Guide

NeuroPilot is a renowned software framework developed by MediaTek. It incorporates various public frameworks for
application development, including the VPU and MDLA software stacks. Additionally, the EDMA is utilized for efficient data
transmission. While the VPU and MDLA begin their functionality through the thread dispatcher to instruction buffer or
CMDE, programming is solely possible through the MediaTek SDK. For more detailed information, please refer to the
NeuroPilot website.

3.5 System Companion Processor (SCP)

3.5.1 Introduction
System Companion Processor (SCP) is a microprocessor subsystem with a two-core MDSP RV55 processor and peripherals.
The SCP subsystem is designed to handle specific tasks for SoC, sensor control, and the future extension tasks.

3.5.2 Features
SCP includes the following features:

 32-bit MDSP RV55 microprocessor

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 Operating frequency up to 832 MHz

 Memory Protection Unit (MPU)
 Floating Point Unit (FPU)
 32KB I-Cache and 32KB D-Cache
 AXI and prefetch
 Built-in 1MB L2 Tightly-Coupled Memory (L2TCM)
 Instruction memory and data memory share the 1MB TCM.
 SCP internal bus system
 An AXI Master interface to access L2TCM and bus fabric
 An AXI Master interface to access SoC-site INFRA and DRAM
 An AXI Master interface to access ADSP shared L2TCM
 An AXI Slave interface for APMCU to access the SCP peripherals and configuration registers
 Peripheral integrated system
 There are 6 sets of 32-bit time counters (Timers) for each RV55 core. The clock source for each timer can be
configured independently.
 8 GPIO pins for external communication
 External Interrupt Controller (EINT) provides de-bounce (anti-glitch) and edge detection functions for integrating
external interrupt signals.
 Internal Interrupt Controller (INTC) provides interrupt mask, interrupt group, and asynchronous clock domain
protection for accessing RV55 VIC (Vectored Interrupt Controller).
 1 set of I2C
 1 set of I3C
 3 sets of SPI-M (master)
 2 sets of UARTs
 2 sets of DMA, which consist of 4-channel full-sized DMA
 Direct path to PMIC (Power Management IC) wrapper
 Mailbox (MBOX) and Inter-Process Communication (IPC) support for communication between SCP and APMCU.
 Watchdog Timer (WDT) for SCP exception control to inform APMCU via interrupts (e.g. After SCP WDT times out,
interrupts are asserted to APMCU, which receives WDT interrupts and then resets SCP for debugging purposes).

3.5.3 Block Diagram

Figure 3-8 shows the detailed block diagram of the SCP subsystem as well as the connection interfaces with other modules
(e.g. APMCU) or external IO pins. Some SCP major features are introduced below:

 Direct Memory Access (DMA)

 DMA is useful when CPU (RV55 or APMCU) cannot keep up with the rate of data transfer, or when CPU needs to
operate while waiting for a relatively slow I/O data transfer.
 For memory-to-memory (e.g. L2TCM ↔ L2TCM) data moving or memory-to-peripheral (e.g.L2 TCM ↔ I2C/I3C)
data transmissions.
 L2TCM
 The total size of L2TCM is 1MB. The program code and data for SCP are downloaded to L2TCM and the code is
fetched directly from this memory space.

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 It stores the data received from serial communication interface (e.g. I2C, I3C, UART, SPI, and GPIO) and loads the
data transmitted to the serial communication interface. Therefore, APMCU or RV55 can require the data by
accessing this memory space.
 Interrupt Controller (INTC and EINT)
 The INTC module is used to pre-integrate all interrupt sources into RV55 VIC, providing mask/unmask control and
polarity configuration for each interrupt signal. It can also group similar interrupts together.
 The EINT module is used for the de-bounce (anti-glitch) and edge detection functions for stabilizing the external
IO interrupt source. It is located ahead of INTC.
 Serial Communication interfaces (e.g. I2C, I3C, SPI-M, UART, GPIO)
 Several kinds of serial communication interfaces and general purpose I/O are provided to connect with external
devices or to print some information logs.
 SCP mailbox (SCP < - > APMCU)
 Virtual addresses are allocated to L2TCM physical address function in the SCP mailbox. Therefore, the APMCU can
write down the message to inform each other that the programmable task has been completed or has exchanged
data.
 While the message is present in L2TCM, write the command into the mailbox command register. This mechanism
triggers an interrupt to inform APMCU or RV55 that there are messages present in the corresponding L2TCM
(physical address).
 Clock Controller
 The controller includes clock source MUX, clock divider, and clock gate. According to the DVFS table and current
application scenario, it can be programmable to generate the SCP internal clocks.
 Timer/Watchdog Timer (WDT)
 Timer is a counter with programmable time intervals. You can set the counter initial value and enable the timer.
When the timer counts down to zero, a timeout interrupt is generated to inform RV55.
 A watchdog timer is an electronic timer that is used to detect and recover from RV55 malfunctions. During the
normal operation, the RV55 regularly resets the watchdog timer to prevent a timeout. If, due to a hardware fault
or a program error, the computer fails to reset the watchdog, the timer elapses and generates a timeout interrupt
to inform APMCU that RV55 stops working.

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RV55_Wrap ( Power down domain)

RV55v001 Core0 RV55v001 Core1

Thread x 2 Thread x 2
SCP_Peri (sensor_hub) L1$(I-32KB/D-32KB) L1$(I-32KB/D-32KB)
APB
I2C/I3C SPI DMA
slave
128 pm_axi 128 dm_axi 128 pm_axi 128 dm_axi Core_JTAG
AXI arbiter (MI)
AHB Interconnect INFRA
DebugAPB RX
AXI F2S DebugAPB TX
64 64

AXI Interconnect

128

Unified TCM (L2TCM 1024KB)

128KB 128KB AXI_bridge AXI_bridge AXI_bridge
128KB 128KB
128KB 128KB
128KB 128KB

From INFRA To INFRA To ADSP

L2TCM

Figure 3-8 SCP Subsystem Block Diagram

3.5.4 Clock Generation

[Link] Clock Structure for RV55 and Bus

The clock source of the SCP subsystem is provided by HF_FSCP_CK, CLK_32K, CLK_26M, or CLK_ULPOSC (the four clocks are
configured by the CLK_SW_SEL control register CR setting. Bus, RV55, and IP bus interface clock are controlled by the
divider selection (MUX) control register and clock gating (CG) control register The SCP clock structure is as Figure 3-9
shows.
Note:
 When switching clock sources, make sure that the destination clock source exists.

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UNIVPLL_D4_624M HF_FSCP_CLK SCP_CK_SW

(clk_sys)
MAINPLL_D6_364M
00 SCP_CLK_PRE
CLK_32K SLP_CKSW_CLK
UNIVPLL_D6_416M 1 01 00
UNIVPLL_D4_D2_312M CLK_26M 0 10 /2 01
MAINPLL_D4_D2_273M 11
/4 10 MCLK
UNIVPLL_D_832M 11
MAINPLL_D3_728M
0x107210A0 [3] /3
CLK_26M 0x10721000 [1:0]
0x10721024 [1:0]
TOPCKGEN

F_ULPOSC_CORE_CK
(clk_high_core)

UART_MAIN_CLK

/1
0
1
F_ULPOSC_CK
(clk_high)
0

0x10721040 [0]

HF_FSCP_CLK /8
00 BCLK
CLK_32K 01 CG TMR BCLK
F_ULPOSC_CK /8 10

0x10721048 [1:0]

HF_FSCP_CLK /4 00 SPI BCLK

CLK_32K 01 CG SPI0 BCLK
10
F_ULPOSC_CK /4 CG SPI1 BCLK
CG SPI2 BCLK
0x1072104C [1:0]

HF_FSCP_CLK /4
00 I3C BCLK
CLK_32K
01 CG I3C0 BCLK
F_ULPOSC_CK /4 10 CG I2C0 BCLK
11
F_ULPOSC_CK /2

0x10721050 [1:0]

CLK_26M
00
CLK_32K 01 UART BCLK
CG UART BCLK
UART_MAIN_CLK 10
F_ULPOSC_CK /1
0
0x10721044 [1:0]

CLK_26M
00
CLK_32K 01 UART1 BCLK
CG UART1 BCLK
UART_MAIN_CLK 10
F_ULPOSC_CK /1
0
0x10721044 [17:16]

Figure 3-9 SCP Clock Structure

The SCP clock control is also responsible for SCP sleep control. When RV55 enters the idle state, which means it is waiting
for interrupts, the clock controller automatically changes the SCP system clock to the slow clock of 32 kHz or 26 MHz. The
SCP system resumes operations (the clock returns to the fast clock) after the IRQ (Interrupt Request) triggers the INTC,
which is introduced in Section 3.5.8.

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[Link] Clock Structure for Low Speed Peripherals and IO

In order to comply with the low speed IO protocol, the peripherals need to operate at the special clock period, I2C bclk, I3C
bclk, SPI bclk, or UART bclk. The clock divider selection control register and the clock gating (CG) control register of low
speed peripherals and IO are shown in Figure 3-9.

[Link] Clock Structure Programming Outline

Table 3-4 Clock Selection Programming Outline
Step Sequence REG_Name REG_Value Address
1 Select SCP system clock source CLK_SW_SEL User defined SCP/AP Base Address + 0x21000
Select SCP system clock
2 CLK_DIV_SEL User defined SCP/AP Base Address + 0x21024
divider
Enable SCP system clock
3 CLK_CG_CTRL User defined SCP/AP Base Address + 0x21030
gating (default off)
I2C_BCLK_CK_SEL SCP/AP Base Address + 0xC1050(I2C)
SPI_BCLK_CK_SEL SCP/AP Base Address + 0xC104C(SPI)
4 Select peripherals clock source UART_BCLK_CK_SEL User defined SCP/AP Base Address + 0xC1044(UART)
I3C_BCLK_CK_SEL SCP/AP Base Address + 0xC1050(I3C)
TMR_BCLK_CK_SEL SCP/AP Base Address + 0xC1048(TMR)
Enable peripherals clock
5 CLK_CG_CTRL User defined SCP/AP Base Address + 0xC1030
gating (default off)

3.5.5 MCUSYS (RV55)

The MRV55E001 is a low power DSP for sensor/voice/audio applications. The ISA (Instruction Set Architecture) is based on
free and open ISA “RISC-V” and customized MediaTek proprietary DSP instructions for differentiation.
MD32RV is designed with the necessary peripherals for embedded applications. It consists of processor core, level 1
memory subsystem, and memory protection unit.

The processor features:

 32-bit integer core
 Single precision FPU
 I/D L1 cache
 Memory protection unit
 AXI bus interface
 Vectored Interrupt Controller (VIC)
 32-bit down count timer
 Performance monitor
 JTAG embedded ICE (In-Circuit Emulator)
 APB debug interface
 Debug cross-trigger interface

MD32RV core is a 32-bit integer core and single-precision FPU:

 RISC-V compatible instruction set

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 RV32 Int/Mul/Atomic/Floating
 Privilege mode
 Standard control and status registers
 Standard interrupt and exception
 Little endian
 The external interface for MD32RV processor contains:
 Instruction AXI bus and Data AXI bus (AMBA 3 AXI protocol)
 The APB interface can be used to debug the software through an on-chip bus
 Supports conventional JTAG ICE for run control and debug, and depends on configuration
 16 interrupt sources for external devices to trigger interrupt requests (need to collocate with INTC group function)

Interface:
 System Clock and Reset: CLK/RST
 Interrupt: External, Fast, SysTimer Interrupts
 Debug interface: JTAG, Debug, APB, Cross-Trigger
 Performance and Debug Monitor: Output PMU, Core status for monitor, CG/Halt status
 Pre-defined Region: Low power access TCM/CACHE
 AXI
 SRAM (Static Random-Access Memory): ICACHE/DCACHE/TBUF

Micro arc:
 6-stage pipeline, IF/PD/ID/E1/E2/WB
 3 execution pipelines (2 Integer engines and 1 FPU engine)
 Dynamic branch predication
 Dual MACs
 Single load/store
 Non-blocking hardware divider
 Halt for interrupt instruction

Table 3-5 MCUSYS Function Block List

Name MCU L2TCM SYSRAM ROM Other Features
SCP subsystem RV55x2 @832MHz Total 1MB L2TCM No No MPU, SWD, FPU

For SCP boot-up, the image must be loaded into L2TCM by other application processors (APMCU). A basic boot sequence
of SCP MCUSYS from the APMCU point of view is as follows:

1. Configure clock source and frequency for RV55 in SCP

2. Power on L2TCM of RV55
3. Download the instruction code and data of RV55 to L2TCM
4. Release RV55 software reset
5. RV55 starts to fetch code from L2TCM
6. SCP hardware initializations for submodules (e.g. UATR, DMA, I2C, I3C, SPI)

Among which:

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 Steps A to D are performed by APMCU.

 Steps E and F are performed by RV55 in SCP.

3.5.6 JTAG
SCP RV55 supports two kinds of interfaces for CM4 debugging. One is the dedicated JTAG from Pinmux, and the other is
from APMCU debug top DAP interface.

3.5.7 Internal Bus Fabric

The SCP bus fabric provides interconnection between IP cores. This system interconnect consists of the AXI bus fabric, AHB
(Advanced High-performance Bus) fabric, and APB fabric, which are shown in Figure 3-8. The AXI bus supports the AXI
master (RV55 and APMCU), while the AHB bus supports the AHB master (DMA, SPI-M) and AHB slave (APB fabric) for high
bandwidth data transfer. However, for low power applications, the peripheral and SCP control register are connected to the
APB fabric.

3.5.8 Interrupt Controller

[Link] Internal Interrupt Controller (INTC)

The Interrupt Controller (INTC) is located ahead of RV55 VIC to provide flexibility in handling interrupt requests. The SCP
clock controller also needs the Sleep IRQ to trigger the clock resume finite-state machine. There are four features shown as
below and the block diagram is illustrated in Figure 3-10.

 Enable/Disable (Mask) control for each interrupt request

Management of valid interrupts
 Configure interrupt polarity
Change the interrupt polarity to meet the polarity requirement of RV55
 Synchronize the interrupt signal in the RV55 clock domain
 Solve the clock domain crossing issue of interrupt signals
 Group module to group IRQs into 16 groups, which trigger RV55 VIC

RV55
IRQ
VIC
Group
Interrupt signals from inside IRQ
of SCP subsystem
(UART, SPI, I2C, I3C, EINT, Enable Polarity Sync
DMA, etc.) (Mask) SCP clock control

SCP clock
Sleep IRQ resumes

Figure 3-10 INTC Block Diagram

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[Link] Interrupt Source

Interrupt signals for INTC module are listed in Table 3-6.

Table 3-6 IRQ

NVIC No. Interrupt Source
0 scp_gipc_in_0
1 scp_gipc_in_1
2 scp_gipc_in_2
3 scp_gipc_in_3
4 spm2scp_irq
5 scp_cirq_event_b
6 eint_irq_core0/1
7 pmic2scp_irq
8 irq_b_u_UART
9 irq_b_u_UART1
10 irq_b_u_I3C0
11 irq_b_u_I2C0
12 TSIP_AXI_tracker_bus_dbg_tracker_irq_b
13 clk_ctrl_irq_u_CLK_CTRL
14 data_valid_irq_u_VOWIF
15 timer0_irq_u_scp_timer_core0/1
16 timer1_irq_u_scp_timer_core0/1
17 timer2_irq_u_scp_timer_core0/1
18 timer3_irq_u_scp_timer_core0/1
19 timer4_irq_u_scp_timer_core0/1
20 timer5_irq_u_scp_timer_core0/1
21 os_timer_irq_u_scp_timer_core0/1
22 uart_rx_irq_core0/1
23 uart1_rx_irq_core0/1
24 dma_irq_b_core0/1
25 scp_audio_irq_b
26 scp_misc_irq_in_vdec_int_line_cnt_irq_b
27 adsp_irq_b
28 cpu_tick_irq_u_scp_timer_core0/1
29 spi0_irq_b
30 spi1_irq_b
31 spi2_irq_b
32 new_infra_sys_cirq_b
33 dbg_irq
34 scp_misc_irq_in_gce_irq_b
35 scp_misc_irq_in_mdp_gce_irq_b
36 scp_misc_irq_in_vdec_irq_b

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NVIC No. Interrupt Source

37 wdt_irq_core0/1
38 scp_misc_irq_in_vdec_lat_irq_b
39 gce_secure_irq_b
40 gce1_secure_irq_b
41 scp_infra_irq
42 clk_ctrl_irq_core0_u_CLK_CTRL
43 clk_ctrl_irq_2_core0_u_CLK_CTRL
44 clk_ctrl_irq_2_u_CLK_CTRL
45 scp_gipc_in_4
46 peribus_timeout_irq
47 infrabus_timeout_irq
48 scp_met_irq[0]
49 scp_met_irq[1]
50 scp_met_irq[2]
51 scp_met_irq[3]
52 ap_wdt_event
53 l2tcm_sec_vio
54 cpu_tick1_irq_u_scp_timer_core0
55 vow_data_in_irq
56 i3c0_ibi_wake
57 i2c0_ibi_wake
58 scp_misc_irq_in_venc_irq_b
59 apu_engine_irq
60 mbox_irq_0
61 mbox_irq_1
62 mbox_irq_2
63 mbox_irq_3
64 mbox_irq_4
65 clk_sys_req_irq_core0/1
66 bus_req_irq_core0/1
67 apsrc_req_irq_core0/1
68 apu2scp_mbox_irq
69 devapc_TSIP_AO_wrapper_secure_vio_irq_b
70 scp_misc_irq_in_camsys_irq_b_29
71 scp_misc_irq_in_camsys_irq_b_28
72 scp_misc_irq_in_camsys_irq_b_5
73 scp_misc_irq_in_camsys_irq_b_4
74 scp_misc_irq_in_camsys_irq_b_3
75 scp_misc_irq_in_camsys_irq_b_2
76 smi_larb7_irq_b_x1
77 wpe_vpp0_wpe_int_b_x1
78 dp_tx_irq

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NVIC No. Interrupt Source

79 edp_tx_irq
80 vpp0_irq_b[0]
81 vpp0_irq_b[12]
82 vpp0_irq_b[14]
83 msdc2_irq_b
84 scp_misc_irq_jpegenc_irq_b
85 scp_misc_irq_jpegdec_irq_b
86 scp_misc_irq_hdmitx_int_x
87 scp_misc_irq_cec_int
88 i2c_irqb[7]
89 i2c_irqb[8]
90 i2c_irqb[9]
91 i2c_irqb[10]
92 i2c_irqb[11]
93 i2c_irqb[12]
94 i2c_irqb[13]
95 infra_iommu_slow_bank0
96 infra_iommu_slow_bank1
97 infra_iommu_slow_bank2
98 infra_iommu_slow_bank3
99 infra_iommu_slow_bank4
100 vdo0_top_irq_b_x1[0] (ovl0)
101 vdo0_top_irq_b_x1[1] (wdma0)
102 vdo0_top_irq_b_x1[2] (rdma0)
103 vdo0_top_irq_b_x1[8] (dsi0)
104 vdo0_top_irq_b_x1[9] (dsc_core0)
105 vdo0_top_irq_b_x1[18] (dsi1)
106 vdo0_top_irq_b_x1[19] (dsc_core1)
107 vdo0_top_irq_b_x1[21] (dpintf0)
108 vdo0_top_irq_b_x1[22] (mutex)
109 mmsys_top_irq_b_x1[0](mutex)
110 mmsys_top_irq_b_x1[1](rdma0)
111 mmsys_top_irq_b_x1[2](rdma1)
112 mmsys_top_irq_b_x1[5](rdma4)
113 mmsys_top_irq_b_x1[6](rdma5)
114 mmsys_top_irq_b_x1[25](merge4)
115 mmsys_top_irq_b_x1[29](dpi0)
116 mmsys_top_irq_b_x1[30](dpi1)
117 mmsys_top_irq_b_x1[31](dpintf)
118 vppsys1_irq_b_x1[8](rdma2)
119 vppsys1_irq_b_x1[9](rdma3)
120 vppsys1_irq_b_x1[32](wrot2)

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NVIC No. Interrupt Source

121 vppsys1_irq_b_x1[33](wrot3)
122 vppsys1_irq_b_x1[37](mutex)

[Link] INTC Programming Outline

Table 3-7 INTC Programming Outline
Step Sequence REG_Name REG_Value Address
SCP/AP Base Address +
1 Change IRQ polarity if needed IRQ_CTRL_POL User defined
0x32030/0x32034/0x32038/0x3203C
SCP/AP Base Address +
2-1 Enable IRQ to RV55 IRQ_CTRL_EN User defined
0x32020/0x32024/0x32028/0x3202C
SCP/AP Base Address +
2-2 Enable IRQ as RV55 wakeup event IRQ_CTRL_SLP User defined
0x32040/0x32044/0x32048/0x3204C
SCP/AP Base Address + 0x32080 ~
2-3 Group IRQs as RV55 IRQ (16 groups) IRQ_CTRL_GRP User defined
0x3217C

[Link] External Interrupt Controller (EINT)

There are 8 shared multi-function pins, which can be programmed as the external interrupt sensing pins for connecting
external triggering signals to the SCP EINT module. There are de-bounce (anti-glitch) and edge detection functions used to
stabilize the external interrupt source, which are located ahead of INTC. The block diagram is illustrated in Figure 3-11.

Interrupt signals from

inside of SCP subsystem
(UART, SPI, I2C, I3C, EINT,
DMA, etc.)
Interrupt signals Eint IRQ INTC
from outside of SCP Detector
Debounce Polarity Mask
subsystem (Level/Edge)
(I/O pin interrupts)

Figure 3-11 EINT Block Diagram

[Link] EINT Programing Outline

Table 3-8 EINT Programming Outline

Step Sequence REG_Name REG_Value Address
Change the pinmux function
1 N/A N/A N/A
mode to support SCP_EINT
Change EINT input polarity if
2 EINT_POL_SET User defined SCP/AP Base Address + 0x2D340
needed
Select which EINT input will be
3-1 EINT_D0EN User defined SCP/AP Base Address + 0x2D400
OR to RV55 core0
Select which EINT input will be
3-2 EINT_D1EN User defined SCP/AP Base Address + 0x2D420
OR to RV55 core1

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Step Sequence REG_Name REG_Value Address

SCP/AP Base Address + 0x2D600 ~
4 Set each EINT input debounce EINT_DBNC_SET User defined
SCP/AP Base Address + 0x2D61C
5 Enable EINT input EINT_MASK_CLR User defined SCP/AP Base Address + 0x2D100

3.5.9 Timer
Timer is a countdown counter with programmable time intervals. You can set the counter initial value. When the timer
counts to zero, it triggers a timeout interrupt to inform RV55. The block diagram is shown in Figure 3-12.

Clk_32K

Clk_26M
Clk mux

Count to Yes Timer event

Counter
zero? IRQ
Current_value
mclk
Initial value

Timer_EN

IRQ_clr

bclk

Sel
Configuration Register

APB Channel

Figure 3-12 SCP Timer Block Diagram

You can select different clock sources (32 kHz, 26 MHz mclk and bclk) to determine the clock period. You can also set the
counter initial value to create a time interval. When the timer setup is complete, CM4 can enable the timer to start the
counter. The waveform is as Figure 3-13 shows.

Timer enable
Run Run
Count Finish

Time event IRQ

IRQ_clr

3 cycles

Figure 3-13 SCP Timer Interrupt Event

While the counter counts to the stop value, the timer triggers an interrupt signal to inform CM4. CM4 needs to give an
interrupt clear command to restart the timer.

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[Link] Timer Programming Outline

Table 3-9 Timer Programming Outline

Step Sequence REG_Name REG_Value Address
Disable timer and select the Core0: SCP/AP Base Address + 0x330n0
1 TIMERn_EN User defined
clock source Core1: SCP/AP Base Address + 0x430n0
Core0: SCP/AP Base Address + 0x330n4
2 Set timer reset value TIMERn_RST_VAL User defined
Core1: SCP/AP Base Address + 0x430n4
Core0: SCP/AP Base Address + 0x330nC
3 Set timer IRQ enable TIMERn_IRQ_CTRL User defined
Core1: SCP/AP Base Address + 0x430nC
Core0: SCP/AP Base Address + 0x330n0
4 Enable timer TIMERn_EN User defined
Core1: SCP/AP Base Address + 0x430n0

3.5.10 WDT
A watchdog timer is an electronic timer that is used to detect and recover from RV55 malfunctions. During normal
operations, the RV55 regularly resets the watchdog timer to prevent a timeout. If, due to a hardware fault or program
error, the RV55 fails to reset the watchdog, the timer elapses and generates a timeout interrupt to inform APMCU that
RV55 should cease operations. Then, APMCU may trigger a software reset to place RV55 in a safe state and restore normal
system operations. The block diagram is as shown in Figure 3-14.

Count
down Zero? WDT
Clk_32K
Counter Event IRQ
WDT_kick_rst

WDT reset
Timer_EN

value

Configuration Register

APB Channel

Figure 3-14 SCP WDT Block Diagram

The purpose of enabling APMCU and setting up SCP WDT is that the APMCU needs to detect the malfunction of RV55. In
order to avoid the WDT from triggering an interrupt, RV55 needs to reset (WDT_kick_rst) WDT counter periodically.

[Link] Watchdog Timer Programing Outline

Table 3-10 WDT Programming Outline
Step Sequence REG_Name REG_Value Address
Enable WDT and set the reset
1 WDT_CFG User defined SCP/AP Base Address + 0x30034
counter value
2 CM4 kick WDT reset periodically WDT_KICK User defined SCP/AP Base Address + 0x30038
If WDT triggers, APMCU clears the
3 WDT_IRQ User defined SCP/AP Base Address + 0x30030
WDT IRQ and resets SCP

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3.5.11 Semaphore
In SCP, a register-based semaphore is designed for shared resource management between two masters (APMCU and
RV55). In real applications, the two masters (APMCU and RV55) may need to use a shared resource (e.g. I2C port in SCP),
and you can use this register-based semaphore for privilege management over the shared resources. A master can have
access to the shared resource after it takes the semaphore successfully. A master should release the taken semaphore after
it has completed the control of the shared resource. As shown in Figure 3-15, there are a total of 16-bit assigned fields for
source permission check. For example, suppose that bit 0 is defined as UART0 source permission. The RV55 can write a flag
(1’b1) to R_SEMA_H[0] if R_SEMA_M[0] is 1’b0. Otherwise, the semaphore hardware does not allow RV55 to set
R_SEMA_H[0] as 1’b1. This purpose of this process is to prevent overlapping in resource allocation.

SEMAPHORE
RV55 R_SEMA_H[0] R_SEMA_M[0] R_SEMA_H[8] R_SEMA_M[8] APMCU
R_SEMA_H[1] R_SEMA_M[1] R_SEMA_H[9] R_SEMA_M[9]

R_SEMA_H[2] R_SEMA_M[2] R_SEMA_H[10] R_SEMA_M[10]

R_SEMA_H[3] R_SEMA_M[3] R_SEMA_H[11] R_SEMA_M[11]

R_SEMA_H[4] R_SEMA_M[4] R_SEMA_H[12] R_SEMA_M[12]

R_SEMA_H[5] R_SEMA_M[5] R_SEMA_H[13] R_SEMA_M[13]

R_SEMA_H[6] R_SEMA_M[6] R_SEMA_H[14] R_SEMA_M[14]

R_SEMA_H[7] R_SEMA_M[7] R_SEMA_H[15] R_SEMA_M[15]

Figure 3-15 Semaphore Block Diagram

3.5.12 GPIO
Please refer to Section 3.12.9 General-purpose Input/Output (GPIO).

[Link] GPIO Programming Outline

Table 3-11 GPIO Programming Outline
Step Sequence REG_Name REG_Value Address
Change the pinmux
1 function mode to support NA NA NA
SCP_GPIO
Write the data to
2 SCP_GPIO_OUT User defined SCP/AP Base Address + 0x25004
GPIO_OUT register
Change the IO direction to
3 SCP_GPIO_DIR 16’hFFFF SCP/AP Base Address + 0x25000
output
Change the IO direction to
4 input to get the external SCP_GPIO_DIR 16’h0 SCP/AP Base Address + 0x25000
data
Read the data from
5 SCP_GPIO_IN User defined SCP/AP Base Address + 0x25008
GPIO_IN register

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3.5.13 UART
Please refer to Section 3.12.2 Universal Asynchronous Receiver/Transmitter (UART).

3.5.14 I2C and I3C

Please refer to Section 3.12.1 Inter-Integrated Circuit (I2C) and Improved I2C (I3C).

[Link] SPI Master

Please refer to Section 3.12.3 Serial Peripheral Interface Master (SPIM).

3.5.15 Memory Map of SCP Subsystem

The memory map of the SCP subsystem is shown in Table 3-12. Except areas of L2TCM, SCP registers and Private Peripheral
Bus (PPB), devices in other addressing areas are actually outside the SCP modules and they need further address
remapping and device APC setting (for security access) to be reached by SCP. With the help of remapping logic, the MSB
[31:28] of addressing value can be extended from 4-bit wide to 6-bit wide so that the SCP can access external devices (e.g.
other peripheral devices). Detailed definitions and examples of the re-mapping control registers are shown in Section
[Link].

Table 3-12 SCP Memory Map

SCP (CM4) view AP view
Devices
Memory Map Address Memory Map Address
L2TCM 1MB 0x0000_0000 0x000F_FFFF 0x1050_0000 0x105F_FFFF
Adsp_share_sram 0x0010_0000 0x001F_FFFF NA
EMI external Remap 0x0020_0000 0x002F_FFFF 0x0_4020_0000 0x0_402F_FFFF
EMI external Remap 0x0030_0000 0x003F_FFFF 0x0_4030_0000 0x0_403F_FFFF
EMI external Remap 0x0040_0000 0x004F_FFFF 0x0_4040_0000 0x0_404F_FFFF
EMI external Remap 0x0050_0000 0x005F_FFFF 0x0_4050_0000 0x0_405F_FFFF
EMI external Remap 0x0060_0000 0x006F_FFFF 0x0_4060_0000 0x0_406F_FFFF
EMI external Remap 0x0070_0000 0x007F_FFFF 0x0_4070_0000 0x0_407F_FFFF
EMI external Remap 0x0080_0000 0x0FFF_FFFF 0x0_4080_0000 0x0_4FFF_FFFF
INFRA external bus 0x1000_0000 0x104F_FFFF NA
L2TCM 1MB Backup 0x1050_0000 0x105F_FFFF NA
Adsp_share_sram
0x1060_0000 0x106B_FFFF NA
backup
Reserved 0x1070_0000 0x1071_FFFF NA
tmbist_ctrl 0x1072_1000 0x1072_1FFF 0x1072_1000 0x1072_1FFF
SCP Clock ctrl 0x1072_2000 0x1072_2FFF 0x1072_2000 0x1072_2FFF
SCP pmic_wrap_p2p 0x1072_3000 0x1072_3FFF 0x1072_3000 0x1072_3FFF
VOWIF 0x1072_4000 0x1072_4FFF 0x1072_4000 0x1072_4FFF
SCP_CFGREG 0x1072_5000 0x1072_5FFF 0x1072_5000 0x1072_5FFF
GPIO 0x1072_6000 0x1072_6FFF 0x1072_6000 0x1072_6FFF

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SCP (CM4) view AP view

Devices
Memory Map Address Memory Map Address
UART0 0x1072_7000 0x1072_7FFF 0x1072_7000 0x1072_7FFF
UART1 0x1072_8000 0x1072_8FFF 0x1072_8000 0x1072_8FFF
I3C0 0x1072_9000 0x1072_9FFF 0x1072_9000 0x1072_9FFF
I2C0 0x1072_A000 0x1072_AFFF 0x1072_A000 0x1072_AFFF
SPI0 0x1072_B000 0x1072_BFFF 0x1072_B000 0x1072_BFFF
SPI1 0x1072_C000 0x1072_CFFF 0x1072_C000 0x1072_CFFF
SPI2 0x1072_D000 0x1072_DFFF 0x1072_D000 0x1072_DFFF
EINT 0x1072_E000 0x1072_FFFF 0x1072_E000 0x1072_FFFF
Reserved 0x1073_0000 0x1073_0FFF 0x1073_0000 0x1073_0FFF
SCP_CFGREG_CORE0 0x1073_1000 0x1073_1FFF 0x1073_1000 0x1073_1FFF
SCP_DMA_CORE0 0x1073_2000 0x1073_2FFF 0x1073_2000 0x1073_2FFF
SCP_INTC_CORE0 0x1073_3000 0x1073_3FFF 0x1073_3000 0x1073_3FFF
SCP_TIMER_CORE0 0x1073_4000 0x1073_4FFF 0x1073_4000 0x1073_4FFF
Debug APB CORE0 0x1073_5000 0x1073_FFFF 0x1073_5000 0x1073_FFFF
Reserved 0x1074_0000 0x1074_0FFF 0x1074_0000 0x1074_0FFF
SCP_CFGREG_CORE1 0x1074_1000 0x1074_1FFF 0x1074_1000 0x1074_1FFF
SCP_DMA_CORE1 0x1074_2000 0x1074_2FFF 0x1074_2000 0x1074_2FFF
SCP_INTC_CORE1 0x1074_3000 0x1074_3FFF 0x1074_3000 0x1074_3FFF
SCP_TIMER_CORE1 0x1074_4000 0x1074_4FFF 0x1074_4000 0x1074_4FFF
Debug APB CORE1 0x1075_0000 0x1075_0FFF 0x1075_0000 0x1075_0FFF
main bus bcrm 0x1075_1000 0x1075_1FFF 0x1075_1000 0x1075_1FFF
Main bus debug 0x1075_2000 0x1075_2FFF 0x1075_2000 0x1075_2FFF
Bus tracker 0x1075_3000 0x1075_FFFF 0x1075_3000 0x1075_FFFF
Reserved 0x1076_0000 0x1077_FFFF 0x1076_0000 0x1077_FFFF
CORE0 I/D Cache 0x1078_0000 0x1079_FFFF 0x1078_0000 0x1079_FFFF
ram(Debug)
CORE1 I/D Cache 0x107A_0000 0x107A_3FFF 0x107A_0000 0x107A_3FFF
ram(Debug)
Main bus DEVAPCAO 0x107A_4000 0x107A_4FFF 0x107A_4000 0x107A_4FFF
Main bus DEVAPC 0x107A_5000 0x107A_5FFF 0x107A_5000 0x107A_5FFF
SCP_CFGREG_SEC 0x107A_6000 0x107F_A000 0x107A_6000 0x107F_A000
Reserved 0x107F_B000 0x107F_BFFF 0x107F_B000 0x107F_BFFF
SCP MailBox0 0x107F_C000 0x107F_CFFF 0x107F_C000 0x107F_CFFF
SCP MailBox1 0x107F_D000 0x107F_DFFF 0x107F_D000 0x107F_DFFF
SCP MailBox2 0x107F_E000 0x107F_EFFF 0x107F_E000 0x107F_EFFF
SCP MailBox3 0x107F_F000 0x107F_FFFF 0x107F_F000 0x107F_FFFF
SCP MailBox4 0x1072_1000 0x1072_1FFF 0x1072_1000 0x1072_1FFF
INFRA external bus 0x1080_0000 0x1FFF_FFFF 0x1080_0000 0x1FFF_FFFF

[Link] System Address Map from SCP View

The system address map from the SCP view can be configured by some register settings.

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Table 3-13 System Address Map from SCP View

SCP View Address Remap Register
[31:28] Name Address
4’h2 REMAP_CFG0::EXT_ADDR2(Default remap to 0x1) SCP Base address+0xA506C[6:0]
4’h3 REMAP_CFG0::EXT_ADDR3(Default remap to 0x1) SCP Base address+0xA506C[6:0]
4’h4 REMAP_CFG0::EXT_ADDR4(Default remap to 0x4) SCP Base address+0xA5064[6:0]
4’h5 REMAP_CFG0::EXT_ADDR5(Default remap to 0x5) SCP Base address+0xA5064[14:8]
4’h6 REMAP_CFG0::EXT_ADDR6(Default remap to 0x6) SCP Base address+0xA5064[22:16]
4’h7 REMAP_CFG0::EXT_ADDR7(Default remap to 0x7) SCP Base address+0xA5064[30:24]
4’h8 REMAP_CFG1::EXT_ADDR8(Default remap to 0x8) SCP Base address+0xA5068[6:0]
4’h9 REMAP_CFG1::EXT_ADDR9(Default remap to 0x9) SCP Base address+0xA5068[14:8]
4’hA REMAP_CFG1::EXT_ADDRA(Default remap to 0xA) SCP Base address+0xA5068[22:16]
4’hB REMAP_CFG1::EXT_ADDRB(Default remap to 0x0) SCP Base address+0xA5068[30:24]
4’hC REMAP_CFG2::EXT_ADDRC(Default remap to 0x1) SCP Base address+0xC0064[5:0]
4’hD REMAP_CFG2::EXT_ADDRD(Default remap to 0x2) SCP Base address+0xA506C[14:8]
4’hE REMAP_CFG2::EXT_ADDRE(Default remap to 0x3) SCP Base address+0xA506C[22:16]
Example: To use the SCP view “0xExxx_xxxx” to access AP view “0x3xxx_xxxx”, set REMAP_CFG2::EXT_ADDRE (SCP Base
address+0xC006C[22:16]) as 0x3. It means that the SCP real access address is “0x3xxx_xxxx” instead of the “0xExxx_xxxx”
area.

[Link].1 SCP Signal Descriptions

Table 3-14 presents SCP signal descriptions.

Table 3-14 SCP Signal Descriptions

Signal Name Type Description Ball Location
SCP_ I3C0
SCP_SCL0 DIO SCP I3C clock 0 Y4, Y2, W2, F5, H7, T9
SCP_SDA0 DIO SCP I3C data 0 W6, AA2, W1, F6, G6, T10
SCP_I2C0
SCP_SCL1 DIO SCP I2C clock 0 Y2, W2, F5, H7, T8, Y4
SCP_SDA1 DIO SCP I2C data 0 AA2, W1, F6, G6, T7, W6
SCP_SPI0
SCP_SPI0_CK DO SCP SPI0 serial clock T11
SCP_SPI0_CS DO SCP SPI0 chip select V6
SCP_SPI0_MI DI SCP SPI0 master input / slave output V8
SCP_SPI0_MO DO SCP SPI0 master output / slave input V7
SCP_SPI1_A
SCP_SPI1_A_CK DO SCP SPI1 serial clock T10
SCP_SPI1_A_CS DO SCP SPI1 chip select T9

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Signal Name Type Description Ball Location

SCP_SPI1_A_MI DI SCP SPI1 master input / slave output T7
SCP_SPI1_A_MO DO SCP SPI1 master output / slave input T8
SCP_SPI1_B
SCP_SPI1_B_CK DO SCP SPI1 serial clock AC31
SCP_SPI1_B_CS DO SCP SPI1 chip select AD30
SCP_SPI1_B_MI DI SCP SPI1 master input / slave output AB31
SCP_SPI1_B_MO DO SCP SPI1 master output / slave input AC30
SCP_SPI2
SCP_SPI2_CK DO SCP SPI2 serial clock G1
SCP_SPI2_CS DO SCP SPI2 chip select G2
SCP_SPI2_MI DI SCP SPI2 master input / slave output E2
SCP_SPI2_MO DO SCP SPI2 master output / slave input F2
SCP_UART
TP_UCTS1_AO DI SCP UART1 clear to send (active low) G5, U5
TP_UCTS2_AO DI SCP UART2 clear to send (active low) E2, AB31, AA5
TP_URTS1_AO DO SCP UART1 request to send (active low) E3, U4
TP_URTS2_AO DO SCP UART2 request to send (active low) F2, AC5, AC30
TP_URXD1_AO DI SCP UART1 receive data G3, U3, V2
TP_URXD2_AO DI SCP UART2 receive data U3, AC31, U5, G1, AB5
TP_UTXD1_AO DO SCP UART1 transmit data G4, U2, V1
TP_UTXD2_AO DO SCP UART2 transmit data U2, AD30, U4, G2, AB6
SCP_GPIO
TP_GPIO0_AO DIO SCP GPIO0 Y10, W5, AB32, AB9
TP_GPIO1_AO DIO SCP GPIO1 U10, V4, AA35, AC9
TP_GPIO2_AO DIO SCP GPIO2 Y6, V5, G4, AB8
TP_GPIO3_AO DIO SCP GPIO3 Y7, W8, G3, AC4
TP_GPIO4_AO DIO SCP GPIO4 Y8, R31, E3, R34, AB3
TP_GPIO5_AO DIO SCP GPIO5 W7, T30, G5, R33, AA8
TP_GPIO6_AO DIO SCP GPIO6 W3, T31, E4, T33, AC8
TP_GPIO7_AO DIO SCP GPIO7 W4, U32, E5, P31, AB7
SCP Command Signals
SCP_VREQ_VAO DO SCP to PMIC normal voltage request M31
Voice Wake-up
VOW_CLK_MISO DI Voice wake-up interface clock M32
VOW_DAT_MISO DI Voice wake-up interface data M30

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3.6 Memory

3.6.1 DRAMC Controller (DRAMC)

[Link] Overview

The Dynamic Random-Access Memory Controller (DRAMC) supports the DRAM bus configuration of 4 channels of
LPDDR4/4X 16-bit at 3,733 MHz (3,733 Mbps/per bit channel). When operating in the four-channel mode, this
configuration enables a maximum DRAM bandwidth of up to 29.16 GB/s.

[Link] Features

The External Memory Interface (EMI) controller schedules requests from the masters and issues commands to the DRAM
controller. It conducts flow control for the DRAM controller and masters to avoid DRAM stall or data overflow/underflow,
minimizing the latency of the processor path to enhance the performance and increase DRAM efficiency. Furthermore, it
informs clock control to gate the clock when there are no transactions to be processed.

The LPDDR4X DRAM controller supports the following features:

 Supports high-priority sideband signals for reducing the request latency

 Supports LPDDR4X with dual-rank per channel
 Maximum capacity of up to 8 GB for four channels with 16-bit data bus width
 Power-down and self-refresh for power saving
 Automatic clock stops for power saving
 DRAM I/O interface timing calibration for PVT (Process, Voltage, and Temperature) variation
 Read/write commands out of the order control
 7 shuffle frequencies
 Supports DVFS for the SoC
 A request cannot cross a page boundary

The LPDDR4X DRAM supports a maximum shuffle capacity of up to 7 frequencies, enabling it to dynamically operate at the
suitable frequency and voltage for the user’s scenario, bandwidth requirement, and low power control to achieve a
balance between performance and power. Table 3-15 displays the Dynamic Frequency Scaling (DFS) with 7 operating
frequencies in Mbps. The additional capability is programmable to fine-tune performance and production requirements.

Table 3-15 LPDDR4X DFS (Mbps)

LPDDR4X 3,733 3,200 2,400 1,866 1,600 1,200 800

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[Link] Block Diagram

Figure 3-16 Block Diagram of Memory System

[Link] Function Description

The DRAMC transmits requests from the EMI to the DRAM protocol. Configurable registers that can be programmed by the
CPU allow the DRAMC to operate in different modes.

 The requests from the EMI scheduler are pushed to the command pool to wait for execution in order.
 The bus scheduler inspects the pre-charge/active pool and command FIFO, and decides which SDRAM bus command,
for example, PRECHARGE, ACTIVE, READ or WRITE, is issued to the SDRAM bus in order to maximize the bus utilization
rate and reduce the response latency.
 The timing controller is responsible for the integrity of the SDRAM bus timing, such as pre-charge to active delay (tRP),
active to command delay (tRCD), and bus turn-around time. The bus scheduler then refers to the information and
chooses the next SDRAM bus command.
 The DDR PHY unit generates SDRAM bus commands, transmitting data and DQS to the SDRAM, and receiving data and
DQS from the SDRAM.
 The response generator produces the response signals and data to the EMI scheduler.

As Figure 3-16 shows, besides the DRAMC that consists of a lower power controller, there are also the digital physical part
(DPHY) and analog physical part (APHY).

 The low power controller responds to DRAMC low power control, such as power domain shutdown, startup, and
Dynamic Voltage Frequency Scaling (DVFS).
 The DPHY is the middle level design covering the pin-mux and calibration operations, as well as the interface protocol
between the DRAMC and APHY.
 The APHY is an analog high-speed DDRPHY responsible for the high-speed I/O design for the DDR Interface operation,
with an integrated local PLL (Phase-Locked Loop) to generate the target frequency for the local design usage.

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[Link].1 Clock

The clock source of the DRAM system (DRAMSYS) APHY is from its PLL, while the other one is from the SoC PLL, as Figure
3-17 shows. This clock structure supports the DRAMSYS in different modes, such as active, idle and DVFS, as well as
dynamic clock management for the low power design.

DRAMC
DRAMC DPHY APHY

Command
Buffer

IO
Pinmux

Arbiter Interface
Bridge
PLL
Runtime Calibration
HW/SW
Testing

Low Power

On-Chip Clock Controller

Low Power Controller

Figure 3-17 DRAMSYS Clock and Low Power Structure

[Link].2 Reset

The asynchronous reset is sourced from the SoC, while the software reset on the DRAMSYS is sourced from the internal
MediaTek low power controller.

[Link] Theory of Operations

[Link].1 Write Operation

The LPDDR4-SDRAM uses an un-matched DQS-DQ path for lower power, so the DQS-strobe must arrive at the SDRAM ball
prior to the DQ signal by the amount of Tdqs2DQ. The DQS-strobe output is driven tWPRE before the first valid rising
strobe edge. The tWPRE pre-amble should be 2xtCK. The DQS strobe must be trained to arrive at the DQ pad center-
aligned with the DQ-data. The DQ-data must be held for tDIVW (data input valid window) and the DQS must be
periodically trained to stay centered in the tDIVW to compensate for timing changes due to temperature and voltage
variation. Burst data is captured by the SDRAM on successive edges of DQS until the 16-bit or 32-bit data burst is complete.
The DQS-strobe must remain active (toggling) for tWPST (WRITE post-amble) after the completion of the burst WRITE.
After a burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the same bank can be issued.

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Figure 3-18 Write Operation

[Link].2 Read Operation

A burst read command is initiated with CS, and CA[5:0] asserted to the proper state at the rising edge of CK, as defined by
the LPDDR4 Command Truth Table. The command address bus inputs determine the starting column address for the burst.
The two low-order address bits are not transmitted on the CA bus and are implied to be “0”, so that the starting burst
address is always a multiple of four, for example, 0x0, 0x4, 0x8, 0Xc. The Read Latency (RL) is defined from the last rising
edge of the clock that completes a read command, for example, the second rising edge of the CAS-2 command, to the
rising edge of the clock, from which the tDQSCK delay is measured. The first valid data is available RL * tCK + tDQSCK +
tDQSQ after the rising edge of Clock that completes a read command. The data strobe output is driven tRPRE before the
first valid rising strobe edge. The first data-bit of the burst is synchronized with the first valid (i.e., post-preamble) rising
edge of the data strobe. Each subsequent data out appears on each DQ pin, edge-aligned with the data strobe. At the end
of a burst, the DQS signals are driven for another half cycle post-amble, or for a 1.5-cycle post-amble if the programmable
post-amble bit is set in the mode register.

Figure 3-19 Read Operation

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[Link] Power Management

The following diagram and table illustrate the power domain and voltage terms and purpose of the DRAMC. For DRAM
relative voltage constraints, refer to the JEDEC standard specification.

Figure 3-20 DRAM Controller Power Domain Architecture

Table 3-16 Voltage Support and Desciption

Voltage Supply Description
VCORE Digital circuit power domain
VMDDR Analog DDRPHY power domain
VDD1 LPDDR4X 1.8V power rail
VDD2 LPDDR4X 1.1V power rail
VDDQ IO buffer 0.6V power rail

[Link] LPDDR4X Signal Description

Table 3-17 DRAMC Signal Description

Signal Name Type Description
CK_t Input DRAM clock signal
CK_c Input DRAM clock invert signal
CKE Input DRAM clock enable
CS0/CS1 Input RANK1 to RANK0 selection signal
CA[5:0] Input Address for all memories/CA buses for LPDDR4X
DQ[15:0] I/O Data bus for LPDDR4X
DMI[1:0] Input Data mask inversion
DQS_t[1:0] I/O Data strobe
DQS_c[1:0] I/O Data strobe invert
ZQ Reference Output driving calibration
RESET_n Input Reset

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[Link].1 LPDDR4X Timing Characteristics

The EMI LPDDR4X timing characteristics are compliant with JEDEC Standard—JESD209-4D.

[Link].2 LPDDR4X Application Guidelines

Table 3-18 presents supported LPDDR4X device combinations.

Table 3-18 LPDDR4X Device Combinations

Number of Devices Device Data Width Mirrored EMI Width
2 2 × 16-bit No 64-bit

Figure 3-21 shows the schematic connections for a 64-bit interface using 2 × 2 × 16-bit devices.

Figure 3-21 LPDDR4X Basic Schematic for 2 × 2 × 16-bit

[Link] Programming Guide

Initialize the DDRPHY.

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1. Initialize the DRAMC.

2. Initialize the MediaTek low power controller.
3. Initialize the DRAM:
 Set up the DRAM AC timing parameter.
 Follow the DRAM specification to complete the DRAM initialization including mode-register programming.
 Enable the command bus training.
 Enable calibration for the DQ/DQS window.
 Set up the refresh-rate counter.
4. Operate normally.

[Link] Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

[Link] References
LPDDR4X specification: [Link]

[Link] Signal Description

Table 3-19 presents EMI signal descriptions.

Table 3-19 EMI Signal Descriptions (LPDDR4(X))

Signal Name Type Description Ball Location
EMI0—Calibration Resistor, Reset Output, Voltage Reference
EMI0_EXTR(1) AIO EMI0 DRAM output driving calibration resistor AT2
EMI0_RESET_N DO EMI0 DRAM reset output AU35
(2)
EMI0_TP AIO EMI0 DRAM command/address voltage reference AR3
EMI0 Command/Address Bus—EMI0_CA[5:0]
EMI0_CA0 DO EMI0 DRAM command/address output 0 AT22
EMI0_CA1 DO EMI0 DRAM command/address output 1 AR22
EMI0_CA2 DO EMI0 DRAM command/address output 2 AM23
EMI0_CA3 DO EMI0 DRAM command/address output 3 AM22
EMI0_CA4 DO EMI0 DRAM command/address output 4 AN21
EMI0_CA5 DO EMI0 DRAM command/address output 5 AP21
EMI0 System Bus—Command, Chip Select, Data Mask, Data Strobe, Clock Signals
EMI0_CK_T DO EMI0 DRAM clock AM20
EMI0_CK_C DO EMI0 DRAM clock invert AL20
EMI0_CKE0 DO EMI0 DRAM clock enable for rank 0 AU20
EMI0_CKE1 DO EMI0 DRAM clock enable for rank 1 AT20
EMI0_CS0 DO EMI0 DRAM chip select for rank 0 AR20

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Signal Name Type Description Ball Location

EMI0_CS1 DO EMI0 DRAM chip select for rank 1 AU22
EMI0_DMI0 DIO EMI0 DRAM data mask/inversion for DQ[7:0] AU25
EMI0_DMI1 DIO EMI0 DRAM data mask/inversion for DQ[15:8] AU31
EMI0_DQS0_T DIO EMI0 DRAM data strobe for DQ[7:0] AM27
EMI0_DQS0_C DIO EMI0 DRAM data strobe invert for DQ[7:0] AN27
EMI0_DQS1_T DIO EMI0 DRAM data strobe for DQ[15:8] AT32
EMI0_DQS1_C DIO EMI0 DRAM data strobe invert for DQ[15:8] AR32
EMI0 Data Bus—EMI0_DQ[15:0]
EMI0_DQ0 DIO EMI0 DRAM data pin 0 AU27
EMI0_DQ1 DIO EMI0 DRAM data pin 1 AT26
EMI0_DQ2 DIO EMI0 DRAM data pin 2 AL25
EMI0_DQ3 DIO EMI0 DRAM data pin 3 AP25
EMI0_DQ4 DIO EMI0 DRAM data pin 4 AL24
EMI0_DQ5 DIO EMI0 DRAM data pin 5 AN25
EMI0_DQ6 DIO EMI0 DRAM data pin 6 AT24
EMI0_DQ7 DIO EMI0 DRAM data pin 7 AT28
EMI0_DQ8 DIO EMI0 DRAM data pin 8 AU34
EMI0_DQ9 DIO EMI0 DRAM data pin 9 AN31
EMI0_DQ10 DIO EMI0 DRAM data pin 10 AP30
EMI0_DQ11 DIO EMI0 DRAM data pin 11 AN29
EMI0_DQ12 DIO EMI0 DRAM data pin12 AR29
EMI0_DQ13 DIO EMI0 DRAM data pin 13 AP31
EMI0_DQ14 DIO EMI0 DRAM data pin 14 AT30
EMI0_DQ15 DIO EMI0 DRAM data pin 15 AU29
EMI1 Command/Address Bus—EMI1_CA[5:0]
EMI1_CA0 DO EMI1 DRAM command/address output 0 AT16
EMI1_CA1 DO EMI1 DRAM command/address output 1 AR16
EMI1_CA2 DO EMI1 DRAM command/address output 2 AL15
EMI1_CA3 DO EMI1 DRAM command/address output 3 AP16
EMI1_CA4 DO EMI1 DRAM command/address output 4 AN16
EMI1_CA5 DO EMI1 DRAM command/address output 5 AL16
EMI1 System Bus—Command, Chip Select, Data Mask, Data Strobe, Clock Signals
EMI1_CK_T DO EMI1 DRAM clock AM18
EMI1_CK_C DO EMI1 DRAM clock invert AL18
EMI1_CKE0 DO EMI1 DRAM clock enable for rank 0 AU18
EMI1_CKE1 DO EMI1 DRAM clock enable for rank 1 AT18
EMI1_CS0 DO EMI1 DRAM chip select for rank 0 AR18

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Signal Name Type Description Ball Location

EMI1_CS1 DO EMI1 DRAM chip select for rank 1 AU16
EMI1_DMI0 DIO EMI1 DRAM data mask/inversion for DQ[7:0] AU13
EMI1_DMI1 DIO EMI1 DRAM data mask/inversion for DQ[15:8] AU7
EMI1_DQS0_T DIO EMI1 DRAM data strobe for DQ[7:0] AN11
EMI1_DQS0_C DIO EMI1 DRAM data strobe invert for DQ[7:0] AM11
EMI1_DQS1_T DIO EMI1 DRAM data strobe for DQ[15:8] AU5
EMI1_DQS1_C DIO EMI1 DRAM data strobe invert for DQ[15:8] AT5
EMI1 Data Bus—EMI1_DQ[15:0]
EMI1_DQ0 DIO EMI1 DRAM data pin 0 AU11
EMI1_DQ1 DIO EMI1 DRAM data pin 1 AT12
EMI1_DQ2 DIO EMI1 DRAM data pin 2 AR11
EMI1_DQ3 DIO EMI1 DRAM data pin 3 AN13
EMI1_DQ4 DIO EMI1 DRAM data pin 4 AL13
EMI1_DQ5 DIO EMI1 DRAM data pin 5 AP13
EMI1_DQ6 DIO EMI1 DRAM data pin 6 AT14
EMI1_DQ7 DIO EMI1 DRAM data pin 7 AT10
EMI1_DQ8 DIO EMI1 DRAM data pin 8 AR4
EMI1_DQ9 DIO EMI1 DRAM data pin 9 AU4
EMI1_DQ10 DIO EMI1 DRAM data pin 10 AN8
EMI1_DQ11 DIO EMI1 DRAM data pin 11 AR9
EMI1_DQ12 DIO EMI1 DRAM data pin 12 AN9
EMI1_DQ13 DIO EMI1 DRAM data pin 13 AR6
EMI1_DQ14 DIO EMI1 DRAM data pin 14 AT8
EMI1_DQ15 DIO EMI1 DRAM data pin 15 AU9
EMI2—Calibration Resistor, Reset Output, Voltage Reference
EMI2_EXTR(1) AIO EMI2 DRAM output driving calibration resistor B2
EMI2_RESET_N DO EMI2 DRAM reset output B36
EMI2_TP(2) AIO EMI2 DRAM command/address voltage reference A3
EMI2 Command/Address Bus—EMI2_CA[5:0]
EMI2_CA0 DO EMI2 DRAM command/address output 0 B16
EMI2_CA1 DO EMI2 DRAM command/address output 1 C16
EMI2_CA2 DO EMI2 DRAM command/address output 2 F15
EMI2_CA3 DO EMI2 DRAM command/address output 3 F16
EMI2_CA4 DO EMI2 DRAM command/address output 4 E17
EMI2_CA5 DO EMI2 DRAM command/address output 5 D17
EMI2 System Bus—Command, Chip Select, Data Mask, Data Strobe, Clock Signals
EMI2_CK_T DO EMI2 DRAM clock F18

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Signal Name Type Description Ball Location

EMI2_CK_C DO EMI2 DRAM clock invert G18
EMI2_CKE0 DO EMI2 DRAM clock enable for rank 0 A18
EMI2_CKE1 DO EMI2 DRAM clock enable for rank 1 B18
EMI2_CS0 DO EMI2 DRAM chip select for rank 0 C18
EMI2_CS1 DO EMI2 DRAM chip select for rank 1 A16
EMI2_DMI0 DIO EMI2 DRAM data mask/inversion for DQ[7:0] A13
EMI2_DMI1 DIO EMI2 DRAM data mask/inversion for DQ[15:8] A7
EMI2_DQS0_T DIO EMI2 DRAM data strobe for DQ[7:0] F11
EMI2_DQS0_C DIO EMI2 DRAM data strobe invert for DQ[7:0] E11
EMI2_DQS1_T DIO EMI2 DRAM data strobe for DQ[15:8] B6
EMI2_DQS1_C DIO EMI2 DRAM data strobe invert for DQ[15:8] C6
EMI2 Data Bus—EMI2_DQ[15:0]
EMI2_DQ0 DIO EMI2 DRAM data pin 0 A11
EMI2_DQ1 DIO EMI2 DRAM data pin 1 B12
EMI2_DQ2 DIO EMI2 DRAM data pin 2 G13
EMI2_DQ3 DIO EMI2 DRAM data pin 3 D13
EMI2_DQ4 DIO EMI2 DRAM data pin 4 G14
EMI2_DQ5 DIO EMI2 DRAM data pin 5 E13
EMI2_DQ6 DIO EMI2 DRAM data pin 6 B14
EMI2_DQ7 DIO EMI2 DRAM data pin 7 B10
EMI2_DQ8 DIO EMI2 DRAM data pin 8 A4
EMI2_DQ9 DIO EMI2 DRAM data pin 9 E7
EMI2_DQ10 DIO EMI2 DRAM data pin 10 D8
EMI2_DQ11 DIO EMI2 DRAM data pin 11 E9
EMI2_DQ12 DIO EMI2 DRAM data pin 12 C9
EMI2_DQ13 DIO EMI2 DRAM data pin 13 D7
EMI2_DQ14 DIO EMI2 DRAM data pin 14 B8
EMI2_DQ15 DIO EMI2 DRAM data pin 15 A9
EMI3 Command/Address Bus—EMI3_CA[5:0]
EMI3_CA0 DO EMI3 DRAM command/address output 0 B22
EMI3_CA1 DO EMI3 DRAM command/address output 1 C22
EMI3_CA2 DO EMI3 DRAM command/address output 2 G23
EMI3_CA3 DO EMI3 DRAM command/address output 3 D22
EMI3_CA4 DO EMI3 DRAM command/address output 4 E22
EMI3_CA5 DO EMI3 DRAM command/address output 5 G22
EMI3 System Bus—Command, Chip Select, Data Mask, Data Strobe, Clock Signals
EMI3_CK_T DO EMI3 DRAM clock F20

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Signal Name Type Description Ball Location

EMI3_CK_C DO EMI3 DRAM clock invert G20
EMI3_CKE0 DO EMI3 DRAM clock enable for rank 0 A20
EMI3_CKE1 DO EMI3 DRAM clock enable for rank 1 B20
EMI3_CS0 DO EMI3 DRAM chip select for rank 0 C20
EMI3_CS1 DO EMI3 DRAM chip select for rank 1 A22
EMI3_DMI0 DIO EMI3 DRAM data mask/inversion for DQ[7:0] A25
EMI3_DMI1 DIO EMI3 DRAM data mask/inversion for DQ[15:8] A31
EMI3_DQS0_T DIO EMI3 DRAM data strobe for DQ[7:0] E27
EMI3_DQS0_C DIO EMI3 DRAM data strobe invert for DQ[7:0] F27
EMI3_DQS1_T DIO EMI3 DRAM data strobe for DQ[15:8] A33
EMI3_DQS1_C DIO EMI3 DRAM data strobe invert for DQ[15:8] B33
EMI3 Data Bus—EMI3_DQ[15:0]
EMI3_DQ0 DIO EMI3 DRAM data pin 0 A27
EMI3_DQ1 DIO EMI3 DRAM data pin 1 B26
EMI3_DQ2 DIO EMI3 DRAM data pin 2 C27
EMI3_DQ3 DIO EMI3 DRAM data pin 3 E25
EMI3_DQ4 DIO EMI3 DRAM data pin 4 G25
EMI3_DQ5 DIO EMI3 DRAM data pin 5 D25
EMI3_DQ6 DIO EMI3 DRAM data pin 6 B24
EMI3_DQ7 DIO EMI3 DRAM data pin 7 B28
EMI3_DQ8 DIO EMI3 DRAM data pin 8 C34
EMI3_DQ9 DIO EMI3 DRAM data pin 9 A34
EMI3_DQ10 DIO EMI3 DRAM data pin 10 E30
EMI3_DQ11 DIO EMI3 DRAM data pin 11 C29
EMI3_DQ12 DIO EMI3 DRAM data pin 12 E29
EMI3_DQ13 DIO EMI3 DRAM data pin 13 C32
EMI3_DQ14 DIO EMI3 DRAM data pin 14 B30
EMI3_DQ15 DIO EMI3 DRAM data pin 15 A29
(1) Connect this pin through an external 60.4 Ω (1%) resistor to GND.
(2) If not used, it can be left unconnected.

3.6.2 External Memory Interface (EMI)

[Link] Overview
The External Memory Interface (EMI) controller schedules requests from the masters and issues commands to DRAMC in
an efficient way. The block conducts flow control for DRAMC and masters to avoid DRAMC stalling or data overflow or
underflow. It also minimizes the latency of processor path to enhance the performance and tries to increase the DRAMC
efficiency. The block also informs clock control to gate the clock when it does not find any transaction right now.

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[Link] Features

The EMI controller receives AXI master commands and issues them to the DRAMC. It supports all AXI transaction type
commands except for the fixed and cache commands. There are plenty of schedule options to schedule the command. The
main features are as follows:

 Comply with the AXI standard protocol

 Support SDRAM up to four channels
 Maximum size for each channel is 8GB
 Rich QoS (Quality of Service) policy, as listed in Section [Link].1

[Link] Block Diagram

The EMI connects the systems via eight 128-bit AXI ports and supports 4-channel DRAMC connection, and each channel
supports two-rank SDRAMs. In each DRAMC, register programming is performed via the APB interface to initialize SDRAM
or other parameter settings.

128 16
DRAMC LPDDR4x16

APMCU /
System 128
/

Multimedia / 128 16
System 128 DRAMC LPDDR4x16
/

GPU /
128 EMI
APU /

Peripheral 128 128 16

/ / DRAMC LPDDR4x16
System

Audio 128
/
System

128 16
DRAMC LPDDR4x16

Figure 3-22 4-Channel EMI/LPDDR4 SDRAM Controller Top Connection

[Link] Function Description

The EMI is a bridge between several systems and the DRAM controller. For Cortex Application Processing Microcontroller
Unit (APMCU) system, two 128-bit AXI ports are provided for the connection. For multimedia masters such as display,

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VENC, VDEC, and camera, two 128-bit AXI ports are provided for the connection. For the GPU and APU, two 128-bit AXI
ports are provided for the connection.

Besides, there is a 128-bit AXI port for connecting to the audio system and a 128-bit AXI port for connecting to the
peripherals.

[Link] Theory of Operations

[Link].1 QoS Policy

To ensure that each master port can own the equal bandwidth QoS, EMI provides the following QoS Policy:

 Priority
Each request from each master can be grouped into three levels, High, Normal, and Low, and EMI serves these
requests in the order of priority. Requests with ultra-signal and starvation are grouped into the High group. The
requests whose allocated bandwidth is not exceeded are assigned to the Normal group. The requests whose allocated
bandwidth is exceeded are categorized into the Low group.
 Starvation Prevention
To avoid request starvation, starvation counters are set for each master port. When the starvation counter reaches
zero, the request is promoted to the High group for prioritized execution. Also, the read/write channel has individual
starvation counter settings for either read or write latency-sensitive commands.
 Bandwidth Limiter
EMI provides the bandwidth limiter for each master port to ensure that each master has the minimum quota for
bandwidth sharing. The amount of bandwidth allocation is configurable.

[Link].2 Arbitration and Scheduling

To improve the SDRAM efficiency and minimize the latency, EMI provides several configuration options:

 Priority Code Arbitration

EMI Scheduler follows a priority code to choose the requests with the highest priority. The priority codes depend on
several domains, urgent, ultra, bandwidth limiter, page hit, and age (starvation). Age expired (with negative starvation
counters) requests always have the highest priority. The domain priority can be configured.
 Data Bus Turnaround
Frequent changes in data direction (switching between reads and writes) would lower the SDRAM bandwidth
efficiency. Therefore, the scheduler would group a batch of read or write commands in a row and send them to
DRAMC. The maximum group number can be configured.
 Page Miss Prevention and Page Hit Promotion
In order to avoid the overhead for SDRAM page miss, EMI masks the requests with page miss and promotes these
requests with page hit.

[Link] Programming Guide

To enable the EMI function, follow the steps below to program.

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1. Program the supported channel number.

2. Program the DRAM address mapping type, such as column bit number, and bank bit number.
3. Program the latency for each AXI and set the request as high priority when the age counter expires.
4. Allocate the bandwidth requirement for each AXI port and set the bandwidth limiter value.
5. Set the bandwidth regulator for each AXI port to either soft mode or hard mode.

3.7 Storage

3.7.1 MMC (MultiMediaCard) and SD (Secure Digital) Controller (MSDC)

[Link] Overview
The MMC (MultiMediaCard) and SD (Secure Digital) Controller (MSDC) offers a high throughput data transfers
while power consumption and data security between device local hosts and memory cards are taken into
consideration.

The MSDC interface fully supports:

 SD 3.0 (Secure Digital) Memory Card Specification

 SDIO 3.0 (Secure Digital Input Output) Card Specification
 eMMC 5.1 (embedded MultiMediaCard) Specification

[Link] Features
The device has integrated 3 MSDC modules, MSDC0, MSDC1, and MSDC2. MSDC0 is used as the MMC™/eMMC
interface, MSDC1 is used as the SD interface, and MSDC2 is used as the SD/SDIO interface.
Each MSDC module supports the following key features:

 32-bit access on AHB for control registers

 Basic DMA and linked-list based DMA modes

The MSDC0 controller fully supports:

 64-bit data access on AXI bus
 1-, 4-, and 8-bit data bus width for eMMC
 Backwards compatibility with legacy MMC
 High-speed Single Data Rate (SDR) mode
 High-speed Double Data Rate (DDR) mode
 HS200 mode, SDR up to 200 MBps
 HS400 mode, DDR up to 400 MBps
 eMMC boot up mode
 Command Queue (CMDQ)
 Advanced Encryption Standard (AES)

The MSDC1 and MSDC2 controllers fully support:

 32-bit data access on AHB

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 1-, 4-bit data bus width for SD card interface

 1-, 4-bit data bus width for SDIO interface (MSDC2 only)
 Default Speed mode, data rate up to 12 MBps
 High-speed mode, data rate up to 25 MBps
 SDR12 mode, data rate up to 12 MBps
 SDR25 mode, data rate up to 25 MBps
 SDR50 mode, data rate up to 50 MBps
 SDR104 mode, data rate up to 100 MBps
 DDR50 mode, data rate up to 50 MBps

[Link] Block Diagram

MSDC_TOP

AXI Master Bus/ 32b MSDC_CLKPAD SD/

MSDC_GDMA 32b
AHB Master Bus MSDC_CMDPAD SDIO/
MSDC_DATAPAD MMC/
MSDC_CORE
MSDC_DSPAD eMMC
hclk_ck
MSDC_REG 32b
AHB Slave Bus 32b

msdc_src_ck

Figure 3-23 System-level Block Diagram of MSDC

[Link] Function Description

Table 3-20 MSDC Function and Address

MSDC List Base Address Feature
MSDC0 0x11230000 eMMC5.1
MSDC1 0x11240000 SD3.0/SDIO3.0/eMMC4.5
MSDC2 0x11250000 SDIO3.0/eMMC4.5

As Figure 3-23 illustrates, the MSDC consists of three primary components: MSDC_GDMA, MSDC_CORE and MSDC_REG.

 MSDC_GDMA: The DMA engine, facilitating data transfer between the MSDC and memory.
 MSDC_CORE: The main controller of the MSDC, managing data transfer between the host and the device.
 MSDC_REG: The register to configure the MSDC.

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[Link] Theory of Operations

[Link].1 MSDC Read/Write

[Link].1.1 MSDC PIO Read

When MSDC_CFG.PIO_MODE is set, the MSDC operates in the PIO (Programmed Input/Output) mode and receives data
from the device. The software can read data from the PIO_RXDATA register when MSDC_FIFOCS.RXFIFOCNT is not 0 (data
buffer empty).

Upon transfer completion, an interrupt is generated. The software is responsible for clearing the interrupt bit after
receiving it.

Figure 3-24 Single Block and Multi-block Read in PIO Mode

[Link].1.2 MSDC PIO Write

When MSDC_CFG.PIO_MODE is set, the MSDC operates in the PIO mode and sends data to the device. The software can
write data from the PIO_TXDATA register when MSDC_FIFOCS.TXFIFOCNT is not 8’h80 (data buffer full).

Upon transfer completion, an interrupt is generated. The software is responsible of clearing the interrupt bit after receiving
it.

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Figure 3-25 Single Block and Multi-block Write in PIO Mode

[Link].1.3 MSDC DMA Read

When MSDC_CFG.PIO_MODE is not set, the MSDC operates in the DMA mode. It receives data from the device and writes
it to the target DRAM address through the MSDC_GDMA control. The software must configure the DMA_SA register with
the start address in DRAM.

Upon transfer completion, an interrupt is generated. The software is responsible of clearing the interrupt bit after receiving
it.

 SD_XFER_COMPLETE is set when the DMA controller has transferred all the data and the CRC (Cyclic Redundancy
Check) has been done.
 (DMA_CTRL.LAST_BUF = 0) DMA_DONE is set when the DMA controller has transferred all the data set in the DMA
controller.
 (DMA_CTRL.LAST_BUF = 1) DMA_DONE is set at the same time as SD_XFER_COMPLETE.

Figure 3-26 Single Block and Multi-block Read in DMA Mode

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[Link].1.4 MSDC DMA Write

When MSDC_CFG.PIO_MODE is not set, the MSDC operates in the DMA mode. It receives data from DRAM through
MSDC_GDMA control and writes it to the device. The software must configure the DMA_SA register with the start address
in DRAM.

Upon transfer completion, an interrupt is generated. The software is responsible of clearing the interrupt bit after receiving
it.

 SD_XFER_COMPLETE is set when the DMA controller has transferred all the data and the CRC has been done.
 (DMA_CTRL.LAST_BUF = 0) DMA_DONE is set when the DMA controller has transferred all the data set in the DMA
controller.
 (DMA_CTRL.LAST_BUF = 1) DMA_DONE is set at the same time as SD_XFER_COMPLETE.

Figure 3-27 Single Block and Multi-block Write in DMA Mode

[Link].2 SD 3.0 Bus Voltage Switch

[Link].2.1 Voltage Switch Command

Figure 3-28 illustrates the definition of the voltage switch command (CMD11), which can be executed (even when the card
is locked) in the ready state and does not alter the state.

A response of type R1 signifies that the card starts the voltage switch sequence. If the host detects no response, a power
cycle should be executed. There are four cases, in which the card indicates no response to CMD11:

1. The card does not support voltage switching.

2. The card supports voltage switching, but ACMD41 is received with S18R = 0.
3. The card is not in the ready state.
4. The signal level is already switched to 1.8V.

In all of the above cases, CMD11 is considered an illegal command.

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Figure 3-28 Voltage Switch Command

[Link] Programming Guide

To initiate the MSDC function, the following settings should be programmed in the prescribed manner.

[Link].1 MSDC Command Sequence

This section introduces the suggested MSDC command sequence for different scenarios.

[Link].1.1 SD Command without Response

1. Check whether SDC_STA.SDCBUSY is 0 before starting to issue this command.

2. When this command is done, check the following bits for the status.
 MSDC_INT.SD_CMDRDY
 MSDC_INT.SD_CMDTO
 MSDC_INT.SD_RESP_CRCERR

[Link].1.2 SD Command with Response

1. Check whether SDC_STA.SDCBUSY is 0 before starting to issue this command

2. When this command is done, check the following bits for the status.
 MSDC_INT.SD_CMDRDY
 MSDC_INT.SD_CMDTO
 MSDC_INT.SD_RESP_CRCERR
3. The response should be in SDC_RESP0 to SDC_RESP3.

[Link].1.3 SD Command of Data Read/Write Transfer

1. Check whether SDC_STA.SDCBUSY is 0 before starting to issue this command.

2. When this command is done, check the following bits for the phase status.
 MSDC_INT.SD_CMDRDY
 SD_CMDTO
 SD_RESP_CRCERR
3. The response should be in SDC_RESP0 to SDC_RESP3.
4. Enable DMA if needed (the DMA_CTRL register should be programmed).
5. The PIO mode enables data movement (the MSDC_FIFOCS, MSDC_RXDAT, and MSDC_TXDAT registers).
6. The PIO mode and DMA mode must not be switched for the same transfer; otherwise, the result can be unexpected.

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7. Check the following for the data phase status.

 MSDC_INT.SD_XFER_COMPLETE
 DMA_DONE
 SD_DATTO
 SD_DATA_CRCERR

[Link].1.4 SD Software Check before Issuing New Command

The software should always check SDC_STA.CMDBUSY before issuing a new command, and should also check
SDC_STA.SDCBUSY for R1b response type and data transfer commands.

[Link].2 MSDC Tuning Support

The host controller incorporates a tuning algorithm to ensure stable data sampling, command response and CRC status
from the device. Both command and data have a pad delay (pad_delay). The tuning flow is illustrated as follows.

start

pad_delay=0

send tune cmd

Store result
pad_delay++

no
pad_delay
==64?
yes

Analysis result

end

Figure 3-29 MSDC Tuning Flow

[Link] MSDC Signal Descriptions

Table 3-21 presents MSDC signal descriptions.

Table 3-21 MSDC Signal Descriptions

Signal Name Type Description Ball Location
MSDC0
MSDC0_CLK DO eMMC clock output F32
MSDC0_CMD DIO eMMC command F33

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Signal Name Type Description Ball Location

MSDC0_DAT0 DIO eMMC data 0 D33
MSDC0_DAT1 DIO eMMC data 1 F36
MSDC0_DAT2 DIO eMMC data 2 D36
MSDC0_DAT3 DIO eMMC data 3 E32
MSDC0_DAT4 DIO eMMC data 4 D35
MSDC0_DAT5 DIO eMMC data 5 F37
MSDC0_DAT6 DIO eMMC data 6 E36
MSDC0_DAT7 DIO eMMC data 7 D37
MSDC0_DSL DI eMMC data strobe input E35
MSDC0_RSTB DO eMMC reset output E34
MSDC1
MSDC1_CLK DO SD card clock output D4
MSDC1_CMD DIO SD card command D3
MSDC1_DAT0 DIO SD card data 0 D2
MSDC1_DAT1 DIO SD card data 1 D1
MSDC1_DAT2 DIO SD card data 2 C4
MSDC1_DAT3 DIO SD card data 3 C3
MSDC2
MSDC2_CLK DO SD card / SDIO clock output AD35
MSDC2_CMD DIO SD card / SDIO command AC35
MSDC2_DAT0 DIO SD card / SDIO data 0 AD37
MSDC2_DAT1 DIO SD card / SDIO data 1 AD36
MSDC2_DAT2 DIO SD card / SDIO data 2 AB37
MSDC2_DAT3 DIO SD card / SDIO data 3 AB35

[Link] MSDC Signal Mapping

The communication protocol between the controller and device is implemented through an advanced 11-signal or
6-signal bus. See Table 3-22 for more details.

Table 3-22 MSDC Signal Mapping

(3.7)(1)
No. Name Type eMMC SD/SDHC/SDXC SDIO Description
1 MSDC0/1/2_CLK DO CLK CLK CLK Clock
2 MSDC0_DSL DI DSL Data Strobe
3 MSDC0_RSTB DO RCLK Reset output
4 MSDC0/1/2_DAT0 DIO DAT0 DAT0 DAT0 Serial data line bit 0
5 MSDC0/1/2_DAT1 DIO DAT1 DAT1 DAT1 Serial data line bit 1
6 MSDC0/1/2_DAT2 DIO DAT2 DAT2 DAT2 Serial data line bit 2
7 MSDC0/1/2_DAT3 DIO DAT3 DAT3 DAT3 Serial data line bit 3

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(3.7)(1)
No. Name Type eMMC SD/SDHC/SDXC SDIO Description
8 MSDC0_DAT4 DIO DAT4 Serial data line bit 4
9 MSDC0_DAT5 DIO DAT5 Serial data line bit 5
10 MSDC0_DAT6 DIO DAT6 Serial data line bit 6
11 MSDC0_DAT7 DIO DAT7 Serial data line bit 7
12 MSDC0/1/2_CMD DIO CMD CMD CMD Command/bus state
(2)
13 SD_WP I WP Write protection
14 SD_INS(2) I INS Card insertion
(1) All embedded pull-up and pull-down resistors can be disabled by programming the corresponding control registers if
optimal pull-up or pull-down resistors are required on the system board.
(2) SD_WP and SD_INS signals are not provided by the MSDC controller. These functions can be accomplished using GPIO
pins, if needed.

[Link] MSDC Timing Characteristics

Table 3-23 and Figure 3-30 present the MSDC timing characteristics in Default Speed mode.

Table 3-23 MSDC Timing Characteristics (Default Speed mode)

No Symbol Parameter Min Max Unit
Clock CLK (CLK rise and fall times are measured by min VIH and max VIL); CCARD ≤ 10 pF
fOP Operating frequency data transfer mode 0 25 MHz
DS1
fOP_ID Operating frequency identification mode 100 400 kHz
DS2 tw_CLK_L Pulse duration, CLK low 10 ns
DS3 tw_CLK_H Pulse duration, CLK high 10 ns
DS4 tRISE_CLK Rise time, CLK 10 ns
DS5 tFALL_CLK Fall time, CLK 10 ns
Input DAT/CMD (referenced to CLK); CCARD ≤ 10 pF
DS6 tsu_DAT/CMD Setup time, DAT/CMD input 5 ns
DS7 th_DAT/CMD Hold time, DAT/CMD input 5 ns
Output DAT/CMD (referenced to CLK); CL ≤ 40 pF
DS8 td_DAT/CMD Delay time, DAT/CMD output during data transfer mode 0 14 ns
DS9 td_DAT/CMD_ID Delay time, DAT/CMD output during identification mode 0 50 ns

Figure 3-30 MSDC Timing Diagram (Default Speed mode)

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Table 3-24 and Figure 3-31 present the MSDC timing characteristics in High Speed mode.

Table 3-24 MSDC Timing Characteristics (High Speed mode)

No Parameter Min Max Unit
Clock CLK (CLK rise and fall times are measured by min V IH and max VIL); CCARD ≤ 10 pF
HS1 fOP Operating frequency data transfer mode 0 50 MHz
HS2 tw_CLK_L Pulse duration, CLK low 7 ns
HS3 tw_CLK_H Pulse duration, CLK high 7 ns
HS4 tRISE_CLK Rise time, CLK 3 ns
HS5 tFALL_CLK Fall time, CLK 3 ns
Input DAT/CMD (referenced to CLK); CCARD ≤ 10 pF
HS6 tsu_DAT/CMD Setup time, DAT/CMD input 6 ns
HS7 th_DAT/CMD Hold time, DAT/CMD input 2 ns
Output DAT/CMD (referenced to CLK)
HS8 td_DAT/CMD Delay time, DAT/CMD output(1) CL ≤ 40 pF 14 ns
(1)
HS9 th_DAT/CMD Hold time, DAT/CMD output CL ≥ 15 pF 2.5 ns
CL Total system capacitance for each line 40 pF
(1) Valid during data transfer mode.

Figure 3-31 MSDC Timing Diagram (High Speed mode)

Table 3-25 and Figure 3-32 present the MSDC timing characteristics in SDR12, SDR25, SDR50, and SDR104 modes.

Table 3-25 MSDC Timing Characteristics (SDR12/SDR25/SDR50/SDR104 modes)

No. Parameter Min Max Unit
CLK output from host
Cycle time, CLK for SDR12 40 ns
Cycle time, CLK for SDR25 20 ns
SDR121 tC
Cycle time, CLK for SDR50 10 ns
(4)
Cycle time, CLK for SDR104 4.8 ns
SDR122 tw_CLK_L Pulse duration, CLK low 10 ns
SDR123 tw_CLK_H Pulse duration, CLK high 10 ns

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No. Parameter Min Max Unit

D Duty Cycle, CLK 30 70 %
(1)
SDR124 tRISE_CLK Rise time, CLK 0.2 × SDR121 ns
(1)
SDR125 tFALL_CLK Fall time, CLK 0.2 × SDR121 ns
Host DAT/CMD input (referenced to CLK), VCT = 0.975 V
Setup time, DAT/CMD input for SDR50, CCARD = 10 pF 3 ns
SDR126 tsu_DAT/CMD
Setup time, DAT/CMD input for SDR104, CCARD = 10 pF 1.4 ns
Hold time, DAT/CMD input for SDR50, CCARD = 5 pF 0.8 ns
SDR127 th_DAT/CMD
Hold time, DAT/CMD input for SDR104, CCARD = 5 pF 0.8 ns
Host DAT/CMD output (referenced to CLK)
Delay time, DAT/CMD output for SDR12/SDR25, 14 ns
tC ≥ 20.0 ns, CL = 40 pF, using driver type B
td_DAT/CMD Delay time, DAT/CMD output for SDR50, tC ≥ 10.0
7.5 ns
SDR128 ns, CL = 30 pF, using driver type B
Delay time, DAT/CMD output for SDR104 0 2 UI(2)
Delay variation due to temperature change after
∆td_DAT/CMD -350 +1550 ps
tuning for SDR104
Hold time, DAT/CMD output for
SDR129 th_DAT/CMD 1.5 ns
SDR12/SDR25/SDR50, CL = 15 pF
SDR1210 th_DAT/CMD Hold time, DAT/CMD output for SDR104 0.6(3) UI(2)
(1) tRISE_CLK/tFALL_CLK < 0.96 ns (max) at 208 MHz, CCARD = 10 pF; tRISE_CLK/tFALL_CLK < 2 ns (max) at 100 MHz, CCARD = 10 pF. The absolute
maximum value of tRISE_CLK and tFALL_CLK is 10 ns regardless of the clock frequency.
(2) Unit Interval (UI) is one bit nominal time. For example, UI = 5 ns at 200 MHz.
(3) th_DAT/CMD = 2.88 ns at 208 MHz
(4) Maximum 208 MHz, VCT = 0.975 V

Figure 3-32 MSDC Timing Diagram (SDR12/SDR25/SDR50/SDR104 modes)

Table 3-26 and Figure 3-33 present the MSDC timing characteristics in DDR50 mode.

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Table 3-26 MSDC Timing Characteristics (DDR50 mode)

No Parameter Min Max Unit
Input DAT/CMD (referenced to CLK rising and falling edge/rising edge); C CARD ≤ 10 pF
tsu_CMD Setup time, CMD input 6 ns
DDR503
tsu_DAT Setup time, DAT input 3 ns
th_CMD Hold time, CMD input 0.8 ns
DDR504
th_DAT Hold time, DAT input 0.8 ns
Output DAT/CMD (referenced to CLK rising and falling edge/rising edge)
td_CMD Delay time, CMD output(1) CL ≤ 30 pF 13.7 ns
DDR505
td_DAT Delay time, DAT output(1) CL ≤ 25 pF 7 ns
th_CMD Hold time, CMD output CL ≥ 15 pF 1.5 ns
DDR506
th_DAT Hold time, DAT output CL ≥ 15 pF 1.5 ns
(1) Valid during data transfer mode.

Figure 3-33 MSDC Timing Diagram (DDR50 mode)

Table 3-27 and Figure 3-34 present the MSDC timing characteristics in HS200 mode.

Table 3-27 MSDC Timing Characteristics (HS200 mode)

No Parameter Min Max Unit
Clock CLK
HS2001 tC Cycle time, CLK 5 ns
(4)
HS2002 tRISE_CLK Rise time, CLK (CDevice ≤ 6 pF) 1 ns
(4)
HS2003 tFALL_CLK Fall time, CLK (CDevice ≤ 6 pF) 1 ns
D Duty Cycle, CLK 30 70 %
Input DAT/CMD; CDevice ≤ 6 pF
HS2005 tsu_DAT/CMD Setup time, DAT/CMD input 1.4 ns
HS2006 th_DAT/CMD Hold time, DAT/CMD input 0.8 ns
Output DAT/CMD
td_DAT/CMD Delay time, DAT/CMD output 0 2 UI(1)
HS2007 Delay variation due to temperature change after -350 1550
∆td_DAT/CMD (2)
ps
tuning (∆T=-20⁰C) (∆T=90⁰C)
HS2008 th_DAT/CMD Hold time, DAT/CMD output 0.575(3) UI(1)

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(1) Unit Interval (UI) is one bit nominal time. For example, UI = 5 ns at 200 MHz.
(2) Total allowable shift of output valid window (th_DAT/CMD) from last system tuning procedure ∆td_DAT/CMD is 2600 ps for ∆T from -25 °C to
125 °C during operation.
(3) The minimum value is equal to 2.88 ns at 208 MHz.
(4) The absolute maximum value of tRISE_CLK and tFALL_CLK is 10 ns regardless of the clock frequency.

Figure 3-34 MSDC Timing Diagram (HS200 mode)

Table 3-28, Figure 3-35 and Figure 3-36 present the MSDC timing characteristics in HS400 mode.

Table 3-28 MSDC Timing Characteristics (HS400 mode)

No Symbol Parameter Min Max Unit
Input CLK
HS4001 tC_CLK Cycle time, CLK (with respect to VT) 5 ns
SR Slew rate, with respect to VIH/VIL 1.125 V/ns
(1)
HS4002 tck_dd Duty cycle distortion 0 0.3 ns
HS4003 tW_CLK Pulse duration, CLK (with respect to VT) 2.2 ns
Input DAT (referenced to CLK); with respect to VIH/VIL; (CDevice ≤ 6 pF)
HS4004 tsu_DAT Setup time, DAT input 0.4 ns
HS4005 th_DAT Hold time, DAT input 0.4 ns
SR Slew rate 1.125 V/ns
Data Strobe
HS4006 tC_CLK Cycle time, CLK (with respect to VT) 5 ns

SR Slew rate (with respect to VOH/VOL and HS400 reference load) 1.125 V/ns

HS4007 tds_dd Duty cycle distortion(2) 0 0.2 ns

HS4008 tW_CLK Pulse duration, CLK (with respect to VT) 2 ns
tRPRE Read preamble 0.4 tC_CLK
tRPST Read post-amble 0.4 tC_CLK
Input DAT (referenced to Data Strobe); with respect to V OH/VOL and HS400 reference load
HS4009 tRQ Output skew 0.4 ns
HS4010 tRQH Output hold skew 0.4 ns
SR Slew rate 1.125 V/ns
(1) Allowable deviation from an ideal 50% duty cycle. With respect to VT. Includes jitter and phase noise.
(2) Allowable deviation from the input CLK duty cycle distortion (tck_dd). With respect to VT. Includes jitter and phase noise.

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Figure 3-35 MSDC Timing Diagram (HS400 Input Mode)

Figure 3-36 MSDC Timing Diagram (HS400 Output Mode)

3.7.2 Serial NOR Flash Controller (SNFC)

[Link] Overview
A Serial NOR Flash Controller (SNFC) provides convenient access to high-speed serial NOR flash devices. The SNFC
supports:

 Single-bit Serial Peripheral Interface (SPI) serial NOR flash

 High-performance dual-bit and quad-bit SPI serial NOR flash

The SPI clock speed can reach up to 52 MHz for the single-bit SPI, dual-bit SPI and quad-bit SPI. The combination of the
SNFC and the serial NOR flash is an important component of system bootup and can also replace DRAM, executing within
the NOR flash chip (XIP, eXecute in Place). SPI can also complete the access of serial NOR flash. The difference between SPI
and SNFC is that the SNFC is specifically tailored for NOR flash memory, making it more efficient.

[Link] Features

 SPI bus compatible serial interface for common serial NOR flash devices.
 Maps out a 512-byte page program buffer and supports multi-page programs.
 Supports the SPI mode (single-bit) to transfer page program and 1-byte program.
 Supports the 4-byte address mode; 3-byte address mode compatible.
 Supports single-bit read, dual output and dual I/O read, as well as quad output and quad I/O read mode.
 Reads serial NOR flash data through the direct read, PIO (Programmed Input/Output) read, or DMA read mode.

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 Supports serial NOR flash device frequency of up to 52 MHz.

 Supports serial NOR flash devices MX25U25645G and W25Q256JW.

[Link] Block Diagram

Serial NOR Flash Controller

Serial
SNFC_Prefetch NOR
Flash
APB Interface

SNFC_Regs

SNFC_Arb

SNFC_DMA Direct_Read_Map

AXI Bus Fabric

AXI Master

Figure 3-37 Block Diagram of SNFC

Figure 3-37 illustrates the block diagram of the SNFC, which includes the following.

Table 3-29 SNFC Modules

Module Description
Register control module, which allows the system master to access controller registers through the
SNFC_Regs
APB interface.
Allocates a buffer with a size of 128 x 32 bits for the reading and programming processes.
 During the reading process, data is first transferred to the buffer and then sent to the read
SNFC_Prefetch master.
 In the programming process, the entire page data should be written to the buffer, and the
SNFC delivers the data to the serial NOR flash device after the page program is triggered.
Employs an arbitration mechanism when Direct_Read_Map and SNFC_DMA access the serial NOR
SNFC_Arb
flash device simultaneously.
A hardware engine that automatically reads data from the serial NOR flash and writes data to the
SNFC_DMA SRAM through the AXI bus. The CPU must configure the source address and start and end
destination addresses through the SNFC_Regs module before the DMA, SNFC_DMA, starts.
Translates the AXI master address and serial NOR flash memory address, and is responsible for
Direct_Read_Map
returning data to the CPU through the AXI master.

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[Link] Function Description

The SNFC integrates commonly used serial NOR flash operations commands, enabling convenient access to the serial NOR
flash. Even without any configuration, it can directly read data from the serial NOR flash. In addition to the conventional
reading, the SNFC also supports writing to the serial NOR flash, and configuring serial NOR flash operations.

The SNFC handles all commands, addresses, data sequences and serial interface protocols. It allows reading of serial NOR
flash in three ways as stated in Table 3-30.

Table 3-30 Methods to Read Serial NOR Flash

Mode Description
The CPU can program the control registers, SNFC_Regs, in a specific sequence and obtain the serial
PIO read mode
NOR flash data through the APB. This mode is usually used for reading few-byte data.
DMA read mode The SNFC_DMA copies serial NOR flash data to the SRAM through the AXI bus.
Direct read mode The CPU can directly read serial flash data through the AXI bus by the address offset.

The SNFC supports the following two ways to write to the serial NOR flash.

Table 3-31 Methods to Write Serial NOR Flash

Mode Description
PIO write The CPU can control the registers in a specific order through the APB, enabling single-byte write
mode operations on the serial NOR flash. This mode is usually used for writing few-byte dates.
The CPU can write data to the SNFC buffer, which holds up to 512 bytes at a time, via the APB to write
Buff write
to a specific register and initiate the transfer. The SNFC can write all data less than 512 bytes at once
mode
to the specified address space of the serial NOR flash.

[Link] Theory of Operations

[Link].1 Read Serial NOR Flash ID

This operation reads the JEDEC ID of the serial NOR flash, including the 1-byte manufacturer ID and 2-byte device ID. The
operation sequence is illustrated in Figure 3-38, and the programming flow is in Table 3-32.

CS#

0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 28 29 30 31
SCLK
Command

SI 9Fh

Manufacturer Identification Device Identification

High-Z
SO 7 6 5 2 1 0 15 14 13 2 1 0

MSB MSB

Figure 3-38 Read ID (RDID) Operation Sequence

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Table 3-32 Read ID (RDID) Operation Programming Flow

Step Address Register Name Local Address R/W Value Description
Turn off the controller
operation protection (only set
1 SF_Base+0xc4 REG_SF_WRPORT REG_SF_WRPORT[7:0] W 8’h30
once after the controller is
reset).
Write the operation command
2 SF_Base+0x34 REG_SF_PRGDATA5 REG_SF_PRGDATA5[7:0] W 8’h9f
of RDID.
3 SF_Base+0x30 REG_SF_PRGDATA4 REG_SF_PRGDATA4[7:0] W 8’h00 Write dummy data.
4 SF_Base+0x2c REG_SF_PRGDATA3 REG_SF_PRGDATA3[7:0] W 8’h00 Write dummy data.
5 SF_Base+0x28 REG_SF_PRGDATA2 REG_SF_PRGDATA2[7:0] W 8’h00 Write dummy data.
6 SF_Base+0x04 REG_SF_CNT REG_SF_CNT[5:0] W 6’h21 Write the process cycle count.
Trigger the controller (send the
7 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] W 1’b1 RDID operation sequence to
the serial NOR flash).
When this bit is 1'b0, the
8 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] R 1’b0
controller processing is done.
Read the JEDEC ID (device ID -
9 SF_Base+0x38 REG_SF_SHREG0 REG_SF_SHREG0[7:0] R
LowByte)
Read the JEDEC ID (device ID -
10 SF_Base+0x3c REG_SF_SHREG1 REG_SF_SHREG1[7:0] R
HighByte)
Read the JEDEC ID
11 SF_Base+0x40 REG_SF_SHREG2 REG_SF_SHREG2[7:0] R
(manufacturer ID)

[Link].2 Erase Serial NOR Flash

The SNFC facilitates three erase operations, namely Sector Erase, Block Erase and Chip Erase, for serial NOR flash. These
erase operations are executed to clear the data of designated part to “1”. However, before you send the erase command, it
is important to execute a WREN (WRITE enable) instruction that sets the WEL (Write Enable Latch).

The Sector Erase command is used for a 4KB sector, while the Block Erase command is used for a 64KB block, and the Chip
Erase command for the entire serial NOR flash. The erase-command formats are as follows.

Table 3-33 Erase-command Formats

Erase Method Format Operation Sequence Programming Flow
8-bit operation code (0x20) followed by the 24-bit or
Section Erase
32-bit address.
Figure 3-39 Table 3-34
8-bit operation code (0xd8) followed by the 24-bit or
Block Erase
32-bit address.
Chip Erase 8-bit operation code (0xc7) Figure 3-40 Table 3-35

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CS#

0 1 2 3 4 5 6 7 8 9 29 30 31
SCLK
Command 24-Bit Addres s

SI 20h/D8h A23 A22 A2 A1 A0

MSB LSB

Figure 3-39 Sector Erase and Block Erase Operation Sequence

Table 3-34 Sector Erase and Block Erase Operation Programming Flow
Step Address Register Name Local Address R/W Value Description
Write the operation
8’h20 or command of
1 SF_Base+0x34 REG_SF_PRGDATA5 REG_SF_PRGDATA5[7:0] W
8’hd8 Sector Erase (0x20) or
Block Erase (0xd8).
Write erase address
bit31:bit24. This register
2 SF_Base+0x30 REG_SF_PRGDATA4 REG_SF_PRGDATA4[7:0] W addr[31:24] only needs to be set
when it is in 4-byte
address mode.
Write erase address
3 SF_Base+0x2c REG_SF_PRGDATA3 REG_SF_PRGDATA3[7:0] W addr[23:16]
bit23:bit16.
Write erase address
4 SF_Base+0x28 REG_SF_PRGDATA2 REG_SF_PRGDATA2[7:0] W addr[15:8]
bit15:bit8.
Write erase address
5 SF_Base+0x24 REG_SF_PRGDATA1 REG_SF_PRGDATA1[7:0] W addr[7:0]
bit7:bit0.
Write the process cycle
count:
6’h20 or Set 0x20 for 3-byte
6 SF_Base+0x04 REG_SF_CNT REG_SF_CNT[5:0] W
6’h28 address mode.
Set 0x28 for 4-byte
address mode.
Trigger the controller to
send the erase operation
7 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] W 1’b1
sequence to the serial
NOR flash.
When this bit is 1'b0, the
8 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] R 1’b0 controller processing is
done.
(Polling serial NOR flash
status)
9 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[1] W 1’b1 Send read flash status
command to serial NOR
flash.

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Step Address Register Name Local Address R/W Value Description

(Polling serial NOR flash
status)
Check whether the WIP
(Write in Progress) bit of
10 SF_Base+0x08 REG_SF_RDSR REG_SF_RDSR[0] R 1’b0
serial NOR flash status is
de-asserted. The erase
process is completed
when this bit is 0.

CS#

0 1 2 3 4 5 6 7
SCLK
Command

SI 60h/C7h

Figure 3-40 Chip Erase Operation Sequence

Table 3-35 Chip Erase Operation Programming Flow

Step Address Register Name Local Address R/W Value Description
Write the operation command
1 SF_Base+0x34 REG_SF_PRGDATA5 REG_SF_PRGDATA5[7:0] W 8’hc7
of Chip Erase.
2 SF_Base+0x04 REG_SF_CNT REG_SF_CNT[5:0] W 6’h08 Write the process cycle count.
Trigger the controller to send
the chip erase operation
3 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] W 1’b1
sequence to the serial NOR
flash.
When this bit is 1'b0, the
4 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] R 1’b0
controller processing is done.
(Polling serial NOR flash status.)
5 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[1] W 1’b1 Send read flash status
command to serial NOR flash
(Polling serial NOR flash status)
Check whether the WIP bit of
6 SF_Base+0x08 REG_SF_RDSR REG_SF_RDSR[0] R 1’b0 serial NOR flash status is de-
asserted. The erasing process is
completed when this bit is 0.

[Link].3 Program Serial NOR Flash

The programming command is utilized to program the memory to “0”. Prior to initiating the programming process, a WREN
command must be executed to set the WEL bit. The SNFC supports two kinds of programming operations: Page Program
and PIO Program.

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Table 3-36 Methods to Program Seiral NOR Flash

Program Method Description
The maximum data size of the programming operation is limited to the serial NOR flash page size,
Page Program
which is typically 256 bytes for most devices.
PIO Program The controller register programs one byte at a time.

Figure 3-41 shows the programming operation sequence.

CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24-Bit Addres s Data Byte 1

SI 02h A23 A22 A21 A3 A2 A1 A0 7 6 5 4 3 2 1 0

MSB MSB

CS#

2072

2073

2074

2075

2076

2077

2078

2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2 Data Byte 3 Data Byte 256

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

MSB MSB MSB

Figure 3-41 Programming Operation Sequence

Furthermore, there are three cases of the two programming operations mentioned above.

1. Entire page programming via the SNFC_Prefetch buffer (Section [Link])

2. Entire multi-page programming via the SNFC_Prefetch buffer (Section [Link])
3. Writing data to the serial flash 1 byte at a time (PIO write mode) (Section [Link])

[Link] Entire Page Programming via SNFC_Prefetch Buffer

Table 3-37 Page Program (PP) Operation Flow

Step Address Register Name Local Address R/W Value Description
Enable the SNFC_Prefetch
1 SF_Base+0x64 REG_SF_CFG2 REG_SF_CFG2[0] W 1’b1
buffer for writing.
2 SF_Base+0x10 REG_SF_RADR0 REG_SF_RADR0[7:0] W addr[7:0] Write address bit7:bit0
3 SF_Base+0x14 REG_SF_RADR1 REG_SF_RADR1[7:0] W addr[15:8] Write address bit15:bit8
4 SF_Base+0x18 REG_SF_RADR2 REG_SF_RADR2[7:0] W addr[23:16] Write address bit23:bit16
Write address bit31:bit24.
This register only needs to
5 SF_Base+0xc8 REG_SF_RADR3 REG_SF_RADR3[7:0] W addr[31:24]
be set when it is in 4-byte
address mode.

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Step Address Register Name Local Address R/W Value Description

Fill the SNFC_Prefetch
buffer by writing program
data to this register. Loop N
REG_SF_PP_DW_ REG_SF_PP_DW_DATA[ times (N indicates that data
6 SF_Base+0x98 W Data[31:0]
DATA 31:0] length imported must be an
integer multiple of 32
bytes, and the maximum
data length is 256 bytes).
Trigger page program
7 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[4] W 1’b1
controller process
When this bit is 1'b0, the
8 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[4] R 1’b0 controller processing is
done.
Polling serial NOR flash
status.
9 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[1] W 1’b1 Send read flash status
command to serial NOR
flash
Polling serial NOR flash
status.
Check whether the WIP bit
of serial NOR flash status is
10 SF_Base+0x08 REG_SF_RDSR REG_SF_RDSR[0] R 1’b0
de-asserted or not. The
page program processing is
completed when this bit is
0.

[Link] Entire Multi-Page Programming via SNFC_Prefetch Buffer

Table 3-38 Multi-Page Program (MPP) Operation Flow
Step Address Register Name Local Address R/W Value Description
Enable the SNFC_Prefetch
1 SF_Base+0x64 REG_SF_CFG2 REG_SF_CFG2[0] W 1’b1
buffer for writing.
Write program address
2 SF_Base+0x10 REG_SF_RADR0 REG_SF_RADR0[7:0] W addr[7:0]
bit7:bit0
Write program address
3 SF_Base+0x14 REG_SF_RADR1 REG_SF_RADR1[7:0] W addr[15:8]
bit15:bit8
Write program address
4 SF_Base+0x18 REG_SF_RADR2 REG_SF_RADR2[7:0] W addr[23:16]
bit23:bit16
Write program address
bit31:bit24. This register
5 SF_Base+0xc8 REG_SF_RADR3 REG_SF_RADR3[7:0] W addr[31:24] only needs to be set when
it is in 4-byte address
mode.

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Step Address Register Name Local Address R/W Value Description

Set the total number of
pages needed to be
6 SF_Base+0x72c REG_SF_PAGECNT REG_SF_PAGECNT[7:0] W page_cnt[7:0]
programed in
SNFC_Prefetch buffer
Set the page size of serial
7 SF_Base+0x730 REG_SF_PAGESIZE REG_SF_PAGESIZE[7:0] W page_size[7:0]
NOR flash
8 SF_Base+0x734 REG_MPP_EN REG_MPP_EN[0] W 1’b1 Enable MPP function
Fill the SNFC_Prefetch
buffer by writing program
data to this register. Loop
N times. (N indicates that
REG_SF_PP_DW_ REG_SF_PP_DW_DATA
9 SF_Base+0x98 W data[31:0] the data length imported
DATA [31:0]
must be an integer
multiple of 32 bytes. The
maximum data length is
512 bytes).
Address increases
automatically when
10 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[7] W 1’b1 programming; keep this
bit high during the entire
programming process
Trigger multi-page
11 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[4] W 1’b1 program controller
process
When this bit is 1'b0, the
12 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[4] R 1’b0 controller processing is
done.
Polling serial NOR flash
status.
13 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[1] W 1’b1 Send read flash status
command to serial NOR
flash
Polling serial NOR flash
status.
Confirm whether the WIP
bit of serial NOR flash
14 SF_Base+0x08 REG_SF_RDSR REG_SF_RDSR[0] R 1’b0 status is de-asserted or
not. The multi-page
program processing is
completed when this bit is
0.

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[Link] Write Data to Serial Flash of 1 Byte (PIO Write Mode)

Table 3-39 PIO Write Operation Programming Flow

Step Address Register Name Local Address R/W Value Description
One byte data needs to be
1 SF_Base+0x1c REG_SF_WDATA REG_SF_WDATA[7:0] W data[7:0]
programed.
2 SF_Base+0x10 REG_SF_RADR0 REG_SF_RADR0[7:0] W addr[7:0] Write program address bit7:bit0
3 SF_Base+0x14 REG_SF_RADR1 REG_SF_RADR1[7:0] W addr[15:8] Write program address bit15:bit8
4 SF_Base+0x18 REG_SF_RADR2 REG_SF_RADR2[7:0] W addr[23:16] Write program address bit23:bit16
Write program address bit31:bit24.
This register only needs to be
5 SF_Base+0xc8 REG_SF_RADR3 REG_SF_RADR3[7:0] W addr[31:24]
programed when in 4-byte address
mode.
6 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[4] W 1’b1 Trigger the PIO write controller.
When this bit is 1'b0, the controller
7 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[4] R 1’b0
processing is done.
Polling serial NOR flash status. Send
8 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[1] W 1’b1 read flash status command to serial
NOR flash
Polling serial NOR flash status.
Confirm whether the WIP bit of serial
9 SF_Base+0x08 REG_SF_RDSR REG_SF_RDSR[0] R 1’b0 NOR flash status is de-asserted or not.
The PIO write process is completed
when this bit is 0.

[Link].1 Read Flash

The SNFC provides three modes for reading data from the flash device:

 PIO read mode (Section [Link])

 DMA read mode (Section [Link])
 Direct read mode (Section [Link])

The standard SPI link format is combined with command, address and data bytes. The read operation format and sequence
of the single-bit SPI mode is depicted in Figure 3-42. Additionally, the controller supports dual output, dual I/O, quad
output, and quad I/O read modes. For the corresponding register configuration, refer to REG_SF_DUAL (SF_Base+0xcc) in
Section [Link].5.

For a 4-byte address, set LARGE_ADDR_EN (SF_Base+0xcc [4]) to enable the address cycle to increase from 24 bits to 32
bits.

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CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command 24-Bit Addres s

SI 03h A23 A22 A21 A3 A2 A1 A0

MSB Data out 1 Data out 2

High-Z
SO 7 6 5 4 3 2 1 0 7

MSB

Figure 3-42 Read Operation Sequence

[Link] PIO Read Mode

Table 3-40 PIO Read Operation Programming Flow
Step Address Register Name Local Address R/W Value Description
1 SF_Base+0x10 REG_SF_RADR0 REG_SF_RADR0[7:0] W addr[7:0] Write read start address bit7:bit0
Write read start address
2 SF_Base+0x14 REG_SF_RADR1 REG_SF_RADR1[7:0] W addr[15:8]
bit15:bit8
Write read start address
3 SF_Base+0x18 REG_SF_RADR2 REG_SF_RADR2[7:0] W addr[23:16]
bit23:bit16
Write read start address
bit31:bit24. This register only
4 SF_Base+0xc8 REG_SF_RADR3 REG_SF_RADR3[7:0] W addr[31:24]
needs to be programed when in
4-byte address mode.
Address increases automatically
5 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[7] W 1’b1
in the PIO mode.
Trigger the controller in the PIO
6 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[0] W 1’b1
mode.
When this bit is 1'b0, the
7 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[0] R 1’b0
controller processing is done.
Get the serial NOR flash data
8 SF_Base+0x0c REG_SF_RDATA REG_SF_RDATA[7:0] R data[7:0]
(one byte).

[Link] DMA Read Mode

The hardware engine supports copying data from the serial NOR flash to the SRAM via SNFC_DMA. Prior to triggering
SNFC_DMA, the source address, destination start address and end address must be appropriately configured. Once
initiated, the hardware engine automatically copies data from the serial NOR flash device to the designated destination
address.

Table 3-41 DMA Read Operation Programming Flow

Step Address Register Name Local Address R/W Value Description
Set the DMA source
1 SF_Base+0x71C REG_FDMA_FADR REG_FDMA_FADR[31:0] W src_addr[31:0]
address.

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Step Address Register Name Local Address R/W Value Description

Set the DMA
2 SF_Base+0x720 REG_FDMA_DADR REG_FDMA_DADR[31:4] W des_addr[31:4] destination start
address.
Set the DMA
REG_FDMA_END_ REG_FDMA_END_DADR des_end_addr
3 SF_Base+0x724 W destination end
DADR [31:4] [31:4]
address.
Trigger the DMA
4 SF_Base+0x718 REG_FDMA_CTL REG_FDMA_CTL[0] W 1’b1
module process.
Poll the trigger bit as 0
to indicate that the
5 SF_Base+0x718 REG_FDMA_CTL REG_FDMA_CTL[0] R 1’b0
DMA processing is
completed.

[Link] Direct Read Mode

The CPU can directly read serial NOR flash data through the AXI bus. For instance, the CPU can directly issue the data
address and length, and the SNFC returns the corresponding data. The application supports the following operations:

 The system executes the memory copy function via the CPU data instruction.
 The system DMA (e.g., Crypto DMA) requests serial NOR flash data.

[Link] Quad-Bit Read Mode

The SNFC supports the quad-bit SPI read mode to enhance read performance, which includes the quad output mode and
quad I/O read mode. The format is similar to the single-bit SPI link format, with the addition of a dummy cycle.
This format comprises of:

 Command
 Address (quad output single-bit; quad I/O quad-bit)
 Dummy cycle (quad output for at least eight dummy cycles; quad I/O for at least six dummy cycles)
 Data

Note that the definition of the QE (Quad Enable) bit mentioned in this section may differ based on the flash vendor. Refer
to Serial NOR Flash Datasheet for more information, such as the MX25L25635F series and the W25Q256JW series.

The differences in the address and dummy cycle format between the quad output and quad I/O are illustrated in Figure 3-43
and Figure 3-44, respectively.

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CS#

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 38 39 40 41 42 43
SCLK
Command 24-Bit Addres s Configurable Data out 1 Data out 2 Data out 3
dummy cycles
SIO0 68h A23 A22 A21 A3 A2 A1 A0 4 0 4 0 4

MSB
High-Z
SIO1 5 1 5 1 5

High-Z
SIO2 6 2 6 2 6

High-Z
SIO3 7 3 7 3 7

Figure 3-43 Quad Output Read Mode Sequence (Address Sent in the Single-bit Mode)

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Command 24-Bit Addres s Configurable Data out 1 Data out 2 Data out 3
dummy cycles
SIO0 EA/EBh 20 16 12 8 4 0 4 0 4 0 4

MSB
High-Z
SIO1 21 17 13 9 5 1 5 1 5 1 5

High-Z
SIO2 22 18 14 10 6 2 6 2 6 2 6

High-Z
SIO3 23 19 15 11 7 3 7 3 7 3 7

Figure 3-44 Quad I/O Read Mode Sequence (Address Sent in the 4-bit Mode)

[Link].1.1.1 Enter Quad-Bit Read Mode

To enter the quad-bit read mode, refer to the programming flow as below:

1. Enable the QE bit of the serial NOR flash.

2. Set REG_SF_DUAL (SF_Base+0xcc) [3] and [2] = 1b’1 to enable the SNFC quad-bit mode.

[Link].1.1.2 Exit Quad-Bit Read Mode

To exit the quad-bit read mode, refer to the programming flow as below:

1. Set REG_SF_DUAL (SF_Base+0xcc)[3] and [2] = 1b’0 to disable the SNFC quad-bit mode.
2. Disable the QE bit of the serial NOR flash.

[Link].1.2 Quad-Byte Address Mode

For most serial NOR flash devices, the default address is a 3-byte address. The following sections introduce how to enter
and exit space larger than 16MB.

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[Link].1.2.1 Enter Quad-Byte Address Mode

Table 3-42 Enter Quad-byte Address Mode Operation Programming Flow

Step Address Register Name Local Address R/W Value Description
Write the operation command
1 SF_Base+0x34 REG_SF_PRGDATA5 REG_SF_PRGDATA5[7:0] W 8’hb7 of entering quad-byte address
mode.
2 SF_Base+0x04 REG_SF_CNT REG_SF_CNT[5:0] W 6’h08 Write the process cycle count.
Trigger the controller process
3 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] W 1’b1 (send OP Code to serial NOR
flash).
When this bit is 1'b0, the
4 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] R 1’b0
controller processing is done.
Enable controller quad-byte
5 SF_Base+0xcc REG_SF_DUAL REG_SF_DUAL[4] W 1’b1
address mode

[Link].1.2.2 Exit Quad-Byte Address Mode

Table 3-43 Exit Quad-byte Address Mode Operation Programming Flow

Step Address Register Name Local Address R/W Value Description
Disable the controller quad-
1 SF_Base+0xcc REG_SF_DUAL REG_SF_DUAL[4] W 1’b0
byte address mode.
Write the operation command
2 SF_Base+0x34 REG_SF_PRGDATA5 REG_SF_PRGDATA5[7:0] W 8’he9 of exiting quad-byte address
mode.
3 SF_Base+0x04 REG_SF_CNT REG_SF_CNT[5:0] W 6’h08 Write the process cycle count.
Trigger the controller process
4 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] W 1’b1 (send OP Code to serial NOR
flash).
When this bit is 1'b0, the
5 SF_Base+0x00 REG_SF_CMD REG_SF_CMD[2] R 1’b0
controller processing is done.

[Link].1.3 Recovery Sequence

To avoid synchronization problems between the SNFC and serial NOR flash device following an entire chip reset, refer to
the planned recovery sequence as follows:

1. Release power down (OP code 0xab, SPI) to wake up the serial NOR flash device and avoid entering the power down
mode.
2. Perform a software reset of the device (OP code 0x66/0x99, SPI) to reset the serial NOR flash device.
3. Initialize the serial NOR flash device by reading the JEDEC ID and detecting the serial NOR flash type.
4. Disable the serial NOR flash protection and send WRSR (OP code 0x01) to clear the protection bit.
5. Determine whether to enter the quad-byte address mode or not (OP Code 0xb7), depending on the serial NOR flash
size (>16MB).

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6. Set the serial NOR flash operation mode (SPI/SPI-D/SPI-Q) and enable or disable the QE bit using the WRSR (OP code
0x01) operation.
7. Set the SNFC register (including the control bit and OP code setting) for SPI/SPI-D/SPI-Q modes.

[Link].2 Programming Guide

The SF_Base is a specific physical address at 0x1132C000.

Table 3-44 Overall SNFC Programming Guide

Number Purpose/Mode Programming Guide
1 Read serial nor flash ID Table 3-32
2 Erase serial NOR Flash-sector/block Table 3-34
3 Erase serial NOR Flash-chip Table 3-35
4 Program serial NOR flash-PP mode Table 3-37
5 Program serial NOR flash-MPP mode Table 3-38
6 Program serial NOR flash-PIO write mode Table 3-39
7 Read Flash-PIO read mode Table 3-40
8 Read Flash-DMA read mode Table 3-41
9 Read Flash-Direct read mode N/A
10 Enter quad-bit read mode Section [Link].1.1.1
11 Exit quad-bit read mode Section [Link].1.1.2
12 Enter quad-byte address mode Table 3-42
13 Exit quad-byte address mode Table 3-43
14 Recovery sequence Section [Link].1.3

[Link].3 SNOR Signal Descriptions

Table 3-45 presents SNOR signal descriptions.

Table 3-45 SNOR Signal Descriptions

Signal Name Type Description Ball Location
SPINOR_CK DO SNOR clock N30
SPINOR_CS DO SNOR chip select N31
SPINOR_IO0 DIO SNOR I/O data 0 (MOSI) P30
SPINOR_IO1 DIO SNOR I/O data 1 (MISO) N34
SPINOR_IO2 DIO SNOR I/O data 2 (WP) P33
SPINOR_IO3 DIO SNOR I/O data 3 (hold) P35

[Link].4 SNOR Timing Characteristics

Table 3-46 and Figure 3-45 present the SNOR timing characteristics.

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Table 3-46 SNOR Timing Characteristics

(1)
No Parameter Description Min Max Unit
SNOR01 Fck SNOR clock (SF_SCLK) frequency - 52 MHz
SNOR02 D Duty cycle, SF_SCLK 45 55 %
SNOR03 tCLQx Input setup time 5.776 - ns
SNOR04 tCLQV Input hold time -4.337 - ns
SNOR05 td Output delay - 0.288 ns
SNOR06 th Output hold time -0.011 - ns
SNOR07 tR_CS/SCLK CS low to SF_SCLK rising edge (read) 1.5/SCLK 9.5/SCLK ns
SNOR08 tR_SCLK/CS SF_SCLK falling edge to CS high (read) 3/SCLK 10/SCLK ns
(1) The specification is based on the assumed load capacity value of 30 pF.

Figure 3-45 SNOR Timing Diagram

[Link].5 Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

[Link].6 Reference

Serial NOR flash datasheets for series such as the MX25L25635F and the W25Q256JW.

3.8 Display

3.8.1 Display Controller

[Link] Overview

The Display Controller, also referred to as VPPSYS, is the abbreviation of “Video Data Processing Pipe Subsystem.” It is used
to support camera video post processing, video decoder post processing, video preprocessing for video encoder or APU
and pixel data processing for Display. The data processing includes resize, sharpen, composition, HDR (High Dynamic
Range), warpage, color, gamma, etc. VPPSYS also contains multiple video IO interfaces, including HDMI_TX, DP_TX,
eDP_TX, DSI (Display Serial Interface), and Digital video out.

VPPSYS consists of three hardware parts, SVPP, DVPP, and WPE. S stands for time-share, D stands for display, while WPE is
for image warpage. The following sections show the features of each hardware part and the operation modes.

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[Link] Features

SVPP-0 and SVPP-1:

 Read DRAM agent (Supports AFBC, Arm Frame Buffer Compressions)
 Image resizer and sharpness
 Image aspect ratio converter
 Write DRAM agent with image rotation { 90, 180, 270, left right flip } (supports AFBC)
 The max pixel throughput of each SVPP pipe is 420 Mpixels/sec

SVPP-2 and SVPP-3:

 Read DRAM agent (Supports AFBC)
 Film grain noise for supporting AV1 video
 HDR decode (HDR10, HDR10+, HLG)
 Local contrast enhancement
 Image resizer and sharpness
 Preference color enhancement
 Image aspect ratio converter
 Write DRAM agent with image rotation { 90, 180, 270, left right flip } (supports AFBC)
 The max pixel throughput of each SVPP pipe is 420 Mpixels/sec

WPE:
 Backward grid-map based image warpage
 Max map size: 640x640
 Single data processing core that can process 300 Mpixels/sec

DVPP-0:
 4-layer RGB image compositor
 One display image resizer (up-scaling)
 Preference color adjustment
 Global contrast adjustment
 Display CSC, Gamma, Dither, and Post_mask
 MIPI DSC display data compression
 Single display data processing pipe
 Max image width for each display data processor pipe is 3840 pixels
 Max pixel throughput of each display data processor pipe is 300 Mpixels/sec (Htotal*Vtotal*fps <= 300 Mpixels/s)

DVPP-1:
 Two read DRAM agents (support AFBC) that support Dolby video HDR (Dolby HDR and HDR10+)
 Two read DRAM agents (do not support AFBC) that support Dolby graphic SDR (Standard Dynamic Range) to HDR
 Two display image resizers (up-scaling)
 4-layer image compositor compliant with Dolby HDR requirements
 The max supported video definition of DVPP-1 is 4K60 (3840x2160x60fps)

Display input and output interfaces:

 HDMI_RX: N/A

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 Digital video input: N/A

 DSI_TX: MIPI DSI C(D)PHY combo. Dual link. Max lane speed: 1.6G
 eDP_TX: 2 lanes. Max 5.4 Gbps per lane. 10-bit color. Max 4K30
 DP_TX: DP1.4. 4 lanes. Max 5.4 Gbps per lane. 10-bit color. Max 4K60
 HDMI_TX: HDMI2.0 Max 4K60. Max 12-bit color. Supports VRR and HDR metadata

[Link] Block Diagram

Figure 3-46 shows the application position of VPPSYS inside the SoC. Figure 3-47 shows the possible application connection
of SVPP-x and WPE. Figure 3-48 shows the possible application connection of DVPP-x and Display output interfaces. The
best pixel throughput of each display IO interface is also shown in the diagram. Note that only the orange blocks are
included in the scope of VPPSYS documentation.

DRAM
frame buffer s VENC

DRAM
AI
Mipi CSI Camera ISP frame buffer s

DSI Else ...

VDEC DRAM
frame buffer s
VPPsys
eDP
Else ... Warp
VPP s
SVPP s DP

VPP s HDMI_TX
DVPP s

Digital video

DRAM
frame buffer s

Figure 3-46 Application Position of VPPSYS inside SoC

DRAM
frame buffer s
Warp
Slice with 512 pixel
Usage : time shared for camera data manipulation DRAM
frame buffer s
VENC
SVPP-0 ( RSZ, SHP, Rotate)
DRAM
frame buffer s
DRAM DRAM AI or Else ...
frame buffer Camera ISP frame buffer s

DRAM Slice with 512 pixel

Else ... frame buffer s Usage : time shared for video codec data. Or dedicated for Video In/Out.
DRAM
SVPP-2 ( HDR, LCE, RSZ, SHP, Color, Rotate) frame buffer s
DRAM
VDEC frame buffer s Slice with 512 pixel
Usage : time shared for video codec data. Or dedicated for Video In/Out.
DRAM
frame buffer s
SVPP-3 ( HDR, LCE, RSZ, SHP, Color, Rotate)
DVPP pipes

Figure 3-47 Possible Application Connection of SVPP-x and WPE

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Up to 4 layer blending

DRAM 2*DSI

{
frame buffer
Blender RDMA DVPP-0 ( Color, CSC, GCE, Gamma, dither )
DRAM
Video or Graphic frame buffer Single pipe: up to eDP
(Video have HDR decoded) DRAM 4K@30
frame buffer DSC
DRAM
frame buffer RSZ
Up to 4 layer blending DP
Fixed to 2 video + 2 Graphic

{
DVPP-1 HDMI_TX
Video (support Dolby, HDR10,
DRAM HDR10+, HLG videos )
(SDR or HDR) frame buffer Digital video
DRAM
frame buffer RSZ

{
DRAM
Graphic frame buffer
(SDR only) DRAM RSZ
frame buffer

Figure 3-48 Possible Application Connection of DVPP-x and Display Output Interfaces

[Link] Function Description

SVPP: It is a multipurpose image data processor. The data input could be from DRAM and WPE. The data output target is
DRAM. Main features of SVPP are image-resizer, image-sharpener, HDR decode, composition, and image rotation.

DVPP: There are two kinds of DVPP in VPPSYS. DVPP-0 is for SDR display on integrated display panel (DSI, eDP) or external
display (DP, HDMI). DVPP-1 is for HDR (Dolby HDR, HDR10+) external display (DP, HDMI). There is one display data
processor inside DVPP-0. DVPP-0 supports conventional display data processor features like color, gamma, dither, while
DVPP-1 is dedicated to standard HDR (Dolby HDR, HDR10+) display. Color or gamma tuning has to be merged with HDR
data processing.

WPE: It is a free-form image warpage accelerator. The input is the source image and a warpage map. The map is an array of
grids in a rectangle arrangement. Each grid contains a backward vector pointing out the coordinate in the source image
that needs to be warped to the new position in the destination image. The output of WPE can be an SVPP or DRAM buffer.

[Link] Theory of Operations

There are three operation modes in VPPSYS, SW mode, Video mode, and DSI-CMD mode. Each data processor hardware
(SVPP-x, WPE, DVPP-0, DVPP-1) can be operated in either one of these three operation modes.

SW mode: As the name implies, the software initiates the hardware operation (one image frame), waits for the HW job
done signal (INTR) and then updates the hardware setting of the next job and kicks off again.

Video mode: In this operation mode, the hardware operation is tied to the video timing of Video IO interfaces, including
HDMI_TX, DSI (video mode), DP_TX, and eDP_TX. The video timing generator inside these video IO blocks will create Vsync
and VDE signals for hardware data processor pipe. By these signals, the hardware automatically and repeatedly knows
when to start a new image frame. To stop and reset the hardware, the software receives the timing signal, by INTR, to
know the period that allows change of hardware settings or information read back.

DSI-CMD mode: This mode is available when using a DSI command mode display panel. A TE (Tearing Effect) signal from
the display panel is received by the SoC, which then informs the software by the INTR signal. The software, depending on
the necessary system operation, updates the hardware setting with the new image frame, which is going to replace the
image data inside the frame buffer in display panel.

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3.8.2 Display Serial Interface (DSI)

[Link] Overview
The DSI is based on MIPI Alliance Specification, supporting high-speed serial data transfer between host processor
and peripheral devices such as display modules. The device includes two DSI controllers, DSI0 and DSI1. DSI
should work with the MIPI_TX_Config module to obtain its engine clock from Analog PHY Macro. And it should
work with DMA engines in the previous stage of the display path to read out frame pixels from memory, performs
frames packing and lane distribution, and then sends the data to a dedicated MIPI D-PHY/C-PHY TX core for
serializing.

[Link] Features
Each DSI controller provides the following key features:

 Compliance with MIPI DSI Specification v01-02-00

 Supports video and command mode data transfers
 Pixel formats supported: RGB888/RGB101010/compressed pixel stream
 128-entry command queue for command transmission
 3 types of video modes: Sync-event, sync-pulse, and burst modes
 Limited high-speed residual packet transmission during video mode blanking period
 Ultra-low power mode control
 Peripheral and external Tearing Effect (TE) signals detection
 MIPI D-PHY interface, with the following features:
 1 clock lane and up to 4 data lanes, 2 ports
 Throughput up to 1.2 Gbps per data lane
 Bi-directional data transmission in Low-Power mode for data lane 0
 Uni-directional data transmission in High-Speed mode for data lanes 0 through 3
 Non-continuous high-speed transmission for clock and data lanes
 Lane swapping
 Compliance with MIPI D-PHY Specification v1.1
 MIPI C-PHY interface, with the following features:
 Single 3-trio, 2 ports
 Throughput up to 1.1 Gsps per trio
 Trio swapping
 Compliance with MIPI C-PHY Specification v1.0
 Each D-PHY/C-PHY TX core provides the following main features:
 Sigma-Delta Modulation (SDM) PLL configuration
 Spread Spectrum Clocking (SSC) control

[Link] Block Diagram

Figure 3-49 shows the block diagram of DSI modules. The whole DSI block is constructed by the DSI controller, PHY digital
controller and analog PHY macro. The DSI controller implements MIPI DSI application and protocol layers, which mainly
focus on packet format, checksum, ECC (Error Correction Code) generation, etc. The MIPI TX configuration module, or

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called MIPI_TX_Config here, is used to control MIPI TX related registers for lane swap function and analog PHY macro. Lane
swap function in MIPI_TX_Config is used to select the order of data and clock lanes. Analog PHY macro converts digital
signals to analog signals.

PHY Digital Controller

slice
MIPI TX configuration module
DSI Controller
(Display Serial
Analog PHY Macro
Interface Controller)
Lane_Swap
ANA_MIPI
TX_PAD

Async_fifo

Figure 3-49 DSI Module Block Diagram

[Link] Function Description

[Link].1 Size Control

The horizontal size of input data received by DSI is defined by DSI register DSI_WIDTH[14:0]. The unit of DSI_WIDTH[14:0]
is pixel. The vertical size of input data received by DSI is defined by DSI register DSI_HEIGHT[14:0]. The unit of
DSI_HEIGHT[14:0] is line. The payload length transferred by DSI is defined by DSI register PS_WC[14:0]. The unit of
PS_WC[14:0] is byte. The line number transferred by DSI is defined by DSI register VACT_NL[14:0]. The unit of
VACT_NL[14:0] is line.

The PS_WC[14:0] is calculated according to DSI_WIDTH[14:0] and PS_SEL[3:0]. The formula of PS_WC[14:0] are
DSI_WIDTH[14:0]*(24/8) for RGB888,
DSI_WIDTH[14:0]*(30/8) for RGB101010,
DSI_WIDTH]14:0]*(24/8) – n for compress (n=0,1,2, payload length sometimes may not be a multiple of three after DSC
compression)

[Link].2 Data Format Control

DSI supports RGB888, RGB101010 and compress mode. The data format is defined by DSI register PS_SEL[3:0](3: RGB888,
4: RGB101010, 5: compress). The compress mode is used in DSC compress.

[Link].3 Mode Control

DSI supports video and command mode, which is defined by the DSI register MODE_CON[1:0].
2’b00: command mode

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2’b01: video mode: sync-pulse mode

2’b10: video mode: sync-event mode
2’b11: video mode: burst mode

DSI also supports D-PHY or C-PHY transmission, which is defined by the DSI register CPHY_EN.
0: DPHY mode
1: CPHY mode

[Link].4 Lane Number Control

DSI supports one to four lanes for D-PHY transmission. DSI supports one to three trios for C-PHY transmission, which is
defined by DSI register LANE_NUM[3:0].
4’b0001: 1 lane or 1 trio
4’b0011: 2 lanes or 2 trios
4’b0111: 3 lanes or 3 trios
4’b1111: 4 lanes

[Link] Theory of Operations

MediaTek DSI peripherals support either of two basic modes of operation: command mode and video mode. Which mode
is used depends on the architecture and capabilities of the peripheral. The mode definitions reflect the primary intended
use of DSI for display interconnection, but they are not intended to restrict DSI from operating in other applications.

[Link].1 Command Mode

Command mode refers to an operation in which transactions primarily take the form of sending commands and data to a
peripheral, such as a display module, which incorporates a display controller. In command mode, long and short packets
can be sent to the peripheral, and data can be read/written from/to frame buffer of the peripheral. Command mode
operation requires a bidirectional interface.

[Link].2 Video Mode

Video mode refers to an operation in which transfers from the host processor to the peripheral take the form of a real-time
pixel stream. Video information should only be transmitted using HS mode. In video mode, sync-event, sync-pulse and
burst modes are supported. These terms are used throughout the following sections:

 Sync-Pulse – Enables the peripheral to accurately reconstruct original video timing, including sync pulse widths.
 Sync-Event – Similar to the one above, but accurate reconstruction of sync pulse widths is not required.
 Burst Mode – RGB pixel packets are time-compressed, leaving more time during a scan line for LP mode (saving power)
or for multiplexing other transmissions onto the DSI link.

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Figure 3-50 Video Mode Interface Timing Legend

Detailed timing and packet sequence are shown in Figure 3-51, Figure 3-52 and Figure 3-53.
Transmission packet components used in Figure 3-51, Figure 3-52, and Figure 3-53 are defined in Figure 3-50.

Figure 3-51 Video Mode Interface Timing: Non-burst Mode with Sync Pulses

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Figure 3-52 Video Mode Interface Timing: Non-burst Mode with Sync Events

Figure 3-53 Video Mode Interface Timing: Burst Mode

[Link] Programming Guide

[Link].1 Initialization

Figure 3-54 illustrates the waveform of the initialization sequence to enable the DSI analog block and power up the DSI
analog block’s PLL. Follow the steps described in Table 3-47 to achieve the initialization sequence.

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If Efuse option is realized, please read the Efuse results and write to DSI_*_RTCODE0~4 before RG_DSI_BG_CORE_EN is asserted.

Read out Efuse results 5'bXXXXX

Write to DSI_*_RTCODE0~4
5'b10000 5'bXXXXX 5'bXXXXX

RG_DSI_BG_CORE_EN >1us

RG_DSI_BG_LPF_EN

RG_DSI_PLL_SDM_PCW[31:0]

RG_DSI_PLL_SDM_PCW_CHG
Must be 1'b1 while enabling PLL
AD_DSI_PLL_SDM_PWR_ON >30ns
(controlled by RG) >1us

DA_DSI_PLL_SDM_PWR_ACK

AD_DSI_PLL_SDM_ISO_EN
(controlled by RG)

> 30ns > 20us for PLL > 30ns

RG_DSI_PLL_EN
settling time
Must have a low-to-high transition.

LPTX_PRE_OE Normal operation

(Hardware control power on & begin after PLL is settled.
normal operation)

Figure 3-54 Timing Chart of Initialization Sequence

Table 3-47 MIPI D-PHY Initialization Programming Sequence

Step Sequence R/W REG_Name REG_Value Address
0 x *00[0]~
Read out eFuse result and write it to
1 W DSI_*_RTCODE0~4 0 x *24[0]
impedance RG
*: 1~5
0 x *28[0]
2 Lane CK mode configuration W DSI_*_CKMODE_MODE 1
*: 1~5
3 Enable BG core power W RG_DSI_BG_CORE_EN 1 0 x 00c[7]
4 Wait for 1 µs
5 Enable BG LP filter W RG_DSI_BG_LPF_EN 1 0 x 00c[6]
6 Wait for 30 ns
7 Enable PLL power W AD_DSI_PLL_SDM_PWR_ON 1 0 x 028[0]
8 Enable PLL power isolation W AD_DSI_PLL_SDM_ISO_EN 1 0 x 028[1]
9 Wait for 1 µs
10 Disable PLL isolation W AD_DSI_PLL_SDM_ISO_EN 0 0 x 028[1]
11 Wait for 30 ns
12 Set SDM_PCW by data rate W RG_DSI_PLL_SDM_PCW - 0 x 02C
13 Set POST_DIV by data rate W RG_DSI_PLL_POSDIV - 0 x 030[10:8]
14 Wait for 1 µs
15 Enable PLL W RG_DSI_PLL_EN 1 0 x 030[4]
16 Wait for 20 µs
17 DSI analog block initialization is done.
Note:
 The addresses with an underline are MIPI_TX_Config REG, and the addresses without an underline are DSI REG.

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[Link].2 Power Off Sequence

If DSI goes into suspend mode or power saving mode, you can power off the DSI analog block. Figure 3-55 illustrates the
waveform of the power-off sequence to disable the DSI analog block and power off the DSI analog block’s PLL. The power-
off programming steps are listed in Table 3-48. To avoid unexpected power consumption, make sure that all registers are in
the default settings.

Normal operation
LPTX_PRE_OE ends & DSI analog
(Hardware control power off ) block power off

RG_DSI_PLL_SDM_PCW_CHG
Must be 1'b1 while enabling PLL
AD_DSI_PLL_SDM_PWR_ON > 30ns
(controlled by RG)

DA_DSI_PLL_SDM_PWR_ACK

AD_DSI_PLL_SDM_ISO_EN
(controlled by RG)

> 30ns
RG_DSI_PLL_EN > 30ns

RG_DSI_BG_CORE_EN

RG_DSI_BG_LPF_EN

Figure 3-55 Timing Chart of Power-off Sequence

Table 3-48 D-PHY Power-off Programming Sequence

Step Sequence R/W REG_Name REG_Value Address
1 Turn off all data lanes W LANE_NUM 0x0 0 x 018[5:2]
2 Wait for 30 ns
3 Disable PLL W RG_DSI_PLL_EN 0 0 x 030[4]
4 Enable PLL isolation W AD_DSI_PLL_SDM_ISO_EN 1 0 x 028[1]
5 Wait for 30 ns
6 Disable PLL power W AD_DSI_PLL_SDM_PWR_ON 0 0 x 028[0]
7 Wait for 30 ns
8 Disable BG LP filter W RG_DSI_BG_LPF_EN 0 0 x 00c[6]
9 Disable BG core power W RG_DSI_BG_CORE_EN 0 0 x 00c[7]
10 DSI analog block power off done
Note:
 The addresses with an underline are MIPI_TX_Config REG, and the addresses without an underline are DSI REG.

[Link].3 Timing Control

[Link].3.1 PHY Timing Control

All of the timing parameters defined in the MIPI specification should be properly set in the DSI controller programmable
registers for correct timing control. The written value is based on the DSI internal clock cycle period, which is related to DSI
analog block PLL clock settings through MIPI TX Config engine. And the written value cannot be zero.

For example, the D-PHY timing parameter THS-PREPARE must be between 40 ns + 4 * UI and 85 ns + 6 * UI, where UI means
time interval, which is equal to the duration of any HS state on clock lane. If the clock lane is set to 500 MHz frequency, as
well as bit-rate 1 Gbps, the UI should be 1 ns. In other words, the value of THS-PREPARE must between 44 and 91 ns. The
internal DSI clock is 8x divided by data rate, as well as 125 MHz. To satisfy THS-PREPARE, the register value DA_HS_PREP should
be 6 to 11 (see Table 3-49).

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Table 3-49 D-PHY Timing Parameters Register Setting

Timing Specification Absolute Time for UI: 1 ns DA_HS_PREP Value
THS-PREPARE 40 ns + 4 * UI~85 ns + 6 * UI 44 to 91 ns 6 to 11

[Link].3.2 D-PHY PHY Timing Control

Table 3-50 lists the D-PHY timing parameters that should be configured in the DSI registers. Note that for different bit-rate
requirements, the UI values vary. For more precise timing control, select DSI internal clock as fast as possible. However, the
faster DSI internal clock is set, the more power is wasted. A suitable clock is beneficial to the optimization of system power
consumption.

Table 3-50 D-PHY Global Operation Timing Parameter Defined by MIPI Specification
Parameter Description Min Max Unit
Timeout for receiver to detect absence of Clock transitions and
TCLK-MISS 60 ns
disable the Clock Lane HS-RX.
Time that the transmitter continues to send HS clock after the
last associated Data Lane has transitioned to LP Mode. Interval is 60 ns +
TCLK-POST ns
defined as the period from the end of THS-TRAIL to the beginning 52*UI
of TCLK-TRAIL.
Time that the HS clock shall be driven by the transmitter prior to
TCLK-PRE any associated Data Lane beginning the transition from LP to HS 8 UI
mode.
Time that the transmitter drives the Clock Lane LP-00 Line state
TCLK-PREPARE immediately before the HS-0 Line state starting the HS 38 95 ns
transmission.
Time interval during which the HS receiver should ignore any
TCLK-SETTLE Clock Lane HS transitions, starting from the beginning of TCLK- 95 300 ns
PREPARE.

Time for the Clock Lane receiver to enable the HS line Time for Dn
TCLK-TERM-EN termination, starting from the time point when Dn crosses to reach 38 ns
VIL,MAX. VTERM-EN
Time that the transmitter drives the HS-0 state after the last
TCLK-TRAIL 60 ns
payload clock bit of a HS transmission burst.
TCLK-PREPARE + TCLK- TCLK-PREPARE + time that the transmitter drives the HS-0 state prior
300 ns
ZERO to starting the Clock.
Time for the Data Lane receiver to enable the HS line Time for Dn
35 ns +
TD-TERM-EN termination, starting from the time point when Dn crosses to reach
4*UI
VIL,MAX. VTERM-EN
Transmitted time interval from the start of THS-TRAIL or TCLK-TRAIL, to 105 ns +
TEOT
the start of the LP-11 state following a HS burst. n*12*UI
THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns
Time that the transmitter drives the Data Lane LP-00 Line state
85 ns +
THS-PREPARE immediately before the HS-0 Line state starting the HS 40 ns + 4*UI ns
6*UI
transmission

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Parameter Description Min Max Unit

THS-PREPARE + time that the transmitter drives the HS-0 state prior 145 ns +
THS-PREPARE + THS-ZERO ns
to transmitting the Sync sequence. 10*UI
Time interval during which the HS receiver shall ignore any Data
Lane HS transitions, starting from the beginning of THS-PREPARE.
145 ns +
THS-SETTLE The HS receiver shall ignore any Data Lane transitions before the 85 ns + 6*UI ns
10*UI
minimum value, and the HS receiver shall respond to any Data
Lane transitions after the maximum value.
Time interval during which the HS-RX should ignore any
transitions on the Data Lane, following a HS burst. The end point 55 ns +
THS-SKIP 40 ns
of the interval is defined as the beginning of the LP-11 state 4*UI
following the HS burst.
max(n*8*UI,
Time that the transmitter drives the flipped differential state
THS-TRAIL 60 ns + ns
after last payload data bit of a HS transmission burst
n*4*UI)
TINIT Initialization period 100 µs
TLPX Transmitted length of any Low-Power state period 50 ns
Ratio TLPX Ratio of TLPX(MASTER)/TLPX(SLAVE) between Master and Slave sides 2/3 3/2
Time that the new transmitter drives the Bridge state (LP-00)
TTA-GET 5*TLPX ns
after accepting control during a Link Turnaround.
Time that the transmitter drives the Bridge state (LP-00) before
TTA-GO 4*TLPX ns
releasing control during a Link Turnaround.
Time that the new transmitter waits after the LP-10 state before
TTA-SURE 1*TLPX 2*TLPX ns
transmitting the Bridge state (LP-00) during a Link Turnaround.
Time that a transmitter drives a Mark-1 state prior to a Stop
TWAKEUP 1 ms
state in order to initiate an exit from ULPS.
Where n = 1 for Forward-direction HS mode and n = 4 for Reverse-direction HS mode

The registers of D-PHY timing parameters for data lanes and clock lane are illustrated in Figure 3-56 and Figure 3-57,
respectively. The registers for BTA (Bus Turnaround) timing are illustrated in Figure 3-58. The unit of them is the clock
period of the DSI internal clock.

Figure 3-56 Registers for Data Lane Timing Parameters

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Figure 3-57 Registers for Clock Lane Timing Parameters

Figure 3-58 Register for BTA Timing Parameters

[Link].3.3 C-PHY PHY Timing Control

Table 3-51 lists the C-PHY timing parameters that should be configured in the DSI registers. Note that for different symbol-
rate requirements, the UI values vary. For example, the UI should be 1 ns when the symbol rate is set to 1Gsps. The
internal DSI clock is 7x divided by the symbol rate, as well as 142.8571 MHz.

Table 3-51 C-PHY Global Operation Timing Parameter Defined by MIPI Specification
Parameter Description Min Max Unit
Time that the transmitter drivers the 3-wire LP-000 line state immediately before
T3-PREPARE 38 95 ns
the HS_+x line state starting the HS transmission.
The length of the first part of the preamble. T3-PREBEGIN should be adjustable at the
T3-PREBEGIN 7 448 UI
transmitter from 7 UI minimum to 448 UI maximum in increments of 7 UI.
The length of the programmable sequence section of the preamble. The length of
T3-PROGSEQ T3-PROGSEQ can be configured by CPHY_PROGSEQ_SKIP_EN (0: T3-PROGSEQ = 14 UI, 1: 0 or 14 UI
T3-PROGSEQ = 0 UI).
T3-PREEND The length of the end of the preamble. 7 UI

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Parameter Description Min Max Unit

T3-SYNC The length of the Sync Word. 7 UI
The length of the Post sequence at the end of the burst. T3-POST should be
T3-POST 7 224 UI
adjustable from 7 UI minimum to 224 UI maximum in increments of 7 UI.
THS_EXIT Time that the transmitter drives LP-111 following a HS burst. 100 ns
TLPX Transmitted length of any low-power state period 50 ns
Time that the new transmitter drives the bridge state (LP-000) after accepting
TA-GET 5*TLPX ns
control during a link turnaround
Time that the transmitter drives the bridge state (LP-000) before releasing control
TTA-GO 4*TLPX ns
during a link turnaround.
Time that the new transmitter waits after the LP-100 state before transmitting the
TTA-SURE TLPX 2*TLPX ns
bridge state (LP-000) during a link turnaround.
Time that a transmitter drives a Mark-1 state prior to a Stop state in order to
TWAKEUP 1 ms
initiate an exit from ULPS.

The registers of C-PHY timing parameters for data lanes and clock lane are illustrated in Figure 3-59. The registers for BTA
timing are illustrated in Figure 3-58. The unit of them is the clock period of the DSI internal clock.

Figure 3-59 Registers for C-PHY Timing Parameters

[Link].3.4 Video Mode Timing

DSI supports video mode traffic sequences, including sync pulse mode, sync event mode and burst mode. To facilitate the
translation of the parameters of packets, see the timing diagrams below for the corresponding register settings. The DSI
register of VSA_NL, VBP_NL, VACT_NL and VFP_NL are used to control the line numbers, and the unit is number of lines.
The ranges of HSA (HPW), HBP, and HFP are specified by DDIC, and the unit is pixel. They are controlled by the DSI register
of DSI_HSA_WC, DSI_HBP_WC and DSI_HFP_WC. The unit of DSI_*_WC is byte (8 bits).

[Link].3.4.1 Non-Burst with Sync-Pulse Mode

A non-burst sync-pulse mode enables the peripheral to accurately reconstruct original video timing, including sync pulse
widths. A timing diagram for sync-pulse mode is shown in Figure 3-60, which also shows registers mappings to lines of
VSA/VBP/VACT/VFP periods.

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VSA_NL VBP_NL VFP_NL

VACT_NL

Figure 3-60 Non-burst Transmission: Sync-pulse Mode

[Link].3.4.2 Non-Burst with Sync-Event Mode

A non-burst sync-event mode is similar to the pulse-sync mode, but accurate reconstruction of sync pulse widths is not
required. Therefore, a single sync event is substituted. The timing diagram is shown in Figure 3-61.

VSA_NL VBP_NL VFP_NL

VACT_NL

Figure 3-61 Non-burst Transmission: Sync-event Mode

[Link].3.4.3 Burst Mode

A burst mode allows RGB pixel packets to be time-compressed, leaving more time during a scan line for LP mode to save
power or for multiplexing other transmissions onto DSI link. The timing diagram is shown in Figure 3-62.

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VSA_NL VBP_NL VFP_NL

VACT_NL

Figure 3-62 Burst Mode Transmission

[Link].4 Command Mode Packet Transmission

DSI supports command mode transmission through writing commands to a dedicated command queue. By configuring
commands and triggering, the transmission can be executed sequentially.

[Link].4.1 Command Queue

DSI has a dedicated command queue that is 32-bit in width and up to 128-entry in depth, as shown in Figure 3-63. To
simplify the settings for transmitting a packet in the command mode, the command queue is designed to categorize all
possible transmission types and commands into four primary instructions and unifies all DSI specification commands into
one or several 32-bit-wide instructions. Figure 3-63 also illustrates a 32-bit instruction structure with the instruction format
of CONFG byte.

32-bit
Main instruction ( 4 bytes )
Instruction 0
Data 1 Data 0 Data ID CONFG.
Instruction 1
Instruction 2

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Conmand Queue RSV RSV TE CL HS BTA TYPE[1:0]

Figure 3-63 DSI Command Queue Instruction Format

Table 3-52 shows the descriptions of the CONFIG byte to an instruction.

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Table 3-52 Config Field Description of Main Instruction

REG_Name REG_Value Function Description
00 Type 0 Used for DSI short packet read/write command
01 Type 1 Used for DSI frame buffer write command (long packet)
Type[1:0]
10 Type 2 Used for DSI generic long packet write command
11 Type 3 Used for DSI frame buffer read command (short packet)
0 Off
BTA Turn around the DSI link after the DSI command is transmitted
1 On
0 Off Enable HS TX transmission for this packet; otherwise, transmit
HS
1 On packet via LP TX.
0 8-bit Select command length for frame buffer read/write instruction.
CL
1 16-bt Only effective for type 1 and type 3 instructions.
0 Off Enable TE request. Will only turn around the DSI link without
TE
1 On any packet transmission.
Resv - - Reserved for further use
Resv - - Reserved for further use

[Link].4.2 Type-0 Instruction

Type-0 instruction is used to transmit short packets. Table 3-53 lists the formats of type-0 instruction where (Data ID + Data
0 + Data 1) is constructed by a DSI short packet command (without ECC).

Table 3-53 Type-0 Instruction Format

Byte 3 Byte 2 Byte 1 Byte 0

Data 1 Data 0 Data ID CONFG.

To send the “Turn on Peripheral” and “Color Mode On” commands, which are transmitted via LP TX and HS TX respectively,
request a slave response after the second command is finished, and translate the descriptions into two 32-bit instructions.
See the steps illustrated in Table 3-54.

Table 3-54 Type-0 TX Example

Step Sequence R/W REG_Name REG_Value Address
1 Fill command queue entry-0 W DSI_CMDQ[0] 0 x 0000120C 0 x 200
2 Fill command queue entry-1 W DSI_CMDQ[1] 0 x 00003200 0 x 204
3 Set command count W CMDQ_SIZE 0x2 0 x 060[7:0]
4 Start command W DSI_START 0x1 0 x 000[0]
Issue interrupt and receive slave
5 R LPRX_RD_RDY_INT_FLAG 0x1 0 x 00C[0]
response
6 Clear interrupt status W LPRX_RD_RDY_INT_FLAG 0x1 0 x 00C[0]
RX_TRIG_0
RX_TRIG_1
7 Read trigger status (Acknowledge) R 0x4 0 x 088[3:0]
RX_TRIG_2
RX_TRIG_3
Respond read ack to module and go to
8 W RACK 0x1 0 x 084[0]
next commands in queue

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Step Sequence R/W REG_Name REG_Value Address

9 Issue interrupt and command done R CMD_DONE_INT_FLAG 0x1 0 x 00C[1]
10 Clear interrupt status W CMD_DONE_INT_FLAG 0x1 0 x 00C[1]

[Link].4.3 Type-1 Instruction

Type-1 command is used to write data into the frame buffer. As shown in Table 3-55, there are 4 bytes constructing this
type of instruction where Mem_start_0 and Mem_start_1 can be generic commands defined by slave vendors or DCS
commands. Mem_start_1 is optional, i.e. the memory start/continue command can be single-byte as DCS defines. It
depends on the CL bit of the CONFG. The byte indicates whether the DSI controller sends Mem_start_1 or not.

Since the length of frame butter to be updated is not constant, this type of instruction may send several long packets to
the slave. The payload data and length of each packet (excluding mem_start_0 and mem_start_1) are prepared by the
RDMA controller that couples the output of image data path or layer overlay result to the DSI controller. For the first
packet, mem_start_0 and mem_start_1 (if CL = 1) are used as the parameters to inform the slave that the host is starting to
write the frame buffer. For the remaining packets, the register value DSI_RWMEM_CONTI[15:0] will be used as the
parameters to inform the slave side to write these data following the last pixel of the previous packet. For more flexibility,
Mem_start_0, Mem_start_1, DSI_RWMEM_CONTI[15:0] and CL are all programmable.

You need to set up two registers to define the packet length and packet count for a frame-based type-1 transmission.
Frame width in bytes should be set to PS_WC, and frame height in lines should be set to DSI_VACT_NL, respectively. These
two registers are used in both video and command mode frame data transmission.

Table 3-55 Type-1 Instruction Format

Byte 3 Byte 2 Byte 1 Byte 0
Mem start 1
Mem start 0 Data ID CONFG.
(optional)

Refer to the example in Table 3-56 to write the frame buffer via DCS commands in the HS TX mode.

Table 3-56 Type-1 TX Example

Step Sequence R/W REG_Name REG_Value Address
1 Fill command queue entry-0 W DSI_CMDQ[0] 0 x 002C3909 0 x 200
2 Set command count W CMDQ_SIZE 0x1 0 x 060[7:0]
3 Set memory continue command W DSI_RWMEM_CONTI 0 x 3C 0 x 090[15:0]
4 Start command W DSI_START 0x1 0 x 000[0]
5 Issue interrupt and command done R CMD_DONE_INT_FLAG 0x1 0 x 00C[1]
6 Clear interrupt status W CMD_DONE_INT_FLAG 0x1 0 x 00C[1]

[Link].4.4 Type-2 Instruction

Type-2 instruction is used to send a long packet. As shown in Table 3-57, this type of main instruction requires several sub-
instructions that do not have CONFIG. To send a type-2 command, write a CONFIG with TYPE = 2 and packet header
information (Data ID + 2-byte word count) to entry 0, and write a series of data bytes in size of word count to the following
entries, excluding ECC and checksum. The bytes in the following entries are treated as long packet data instead of the next

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instruction until the word count size is reached. The command queue count should be set as the number of multiple
entries used.

The type-2 command is sent in LPTX mode due to memory latency in reading sub-instruction data. Besides, the type-2
command should be sent individually without the next instruction followed. For the 32-entry command queue, the
maximum word count for a long packet is 124 bytes.

Table 3-57 Type-2 Instruction Format

Byte 3 Byte 2 Byte 1 Byte 0

WC 1 WC 0 Data ID CONFG.

Data 3 Data 2 Data 1 Data 0

Data WC-1 Data WC-2

See Table 3-58 for the example of sending three parameters (0 x 33, 0 x 22, 0 x 11) by a generic long packet command with
3-byte word count.

Table 3-58 Type-2 TX Example

Step Sequence R/W REG_Name REG_Value Address
Fill command queue entry-0 (data ID and
1 W DSI_CMDQ[0] 0 x 00032902 0 x 200
word count)
2 Fill command queue entry-1 (parameters) W DSI_CMDQ[1] 0 x 00112233 0 x 204
3 Set command count W CMDQ_SIZE 0x2 0 x 060[7:0]
4 Start command W DSI_START 0x1 0 x 000[0]
5 Issue interrupt and command done R CMD_DONE_INT_FLAG 0x1 0 x 00C[1]
6 Clear interrupt status W CMD_DONE_INT_FLAG 0x1 0 x 00C[1]
Note that the RPT bit of [Link] designed for this type of instruction. It is useful for the NULL packet or blanking packet.
For example, if a null packet is to be sent, only the main instruction (entry-0 of command queue) will be needed, and the
following payload data will be sent as “0”.

[Link].4.5 Type-3 Instruction

Type-3 instruction is used for reading frame buffer. As shown in Table 3-59, the format is the same as that of type-1. When
this instruction is executed, the host first sends a short packet with memory start parameter given in byte 2 and byte 3 and
automatically issues the next packet by memory continuous parameters programmed in DSI_RWMEM_CONTI[15:0]. The
number of total packets required to be sent depends on the DSI_FRM_BC and “maximum return packet size”. For example,
to read 1,024 bytes from the frame buffer in the slave, and the “maximum return packet size” is set to “4”, there will be
another 255 short packets with memory continuous parameters to be sent successively after the first short packet
described in main instruction is sent.

Table 3-59 Type-3 Instruction Format

Byte 3 Byte 2 Byte 1 Byte 0
Men start 1
Mem start 0 Data ID CONFG.
(optional)

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See Table 3-60 for an example of using the type-3 instruction to perform the frame buffer read.

Table 3-60 Type-3 TX Example

Step Sequence R/W REG_Name REG_Value Address
1 Fill command queue entry-0 W DSI_CMDQ[0] 0 x 002E0603 0 x 200
2 Set command count W CMDQ_SIZE 0x1 0 x 060[7:0]
3 Set memory read continue command W DSI_RWMEM_CONTI 0 x 3E 0 x 090[15:0]
4 Start command W DSI_START 0x1 0 x 000[0]
Issue interrupt and receive slave
5 R LPRX_RD_RDY_INT_FLAG 0x1 0 x 00C[0]
response
BYTE0
BYTE1
6 Read receive data bytes R - 0 x 074
BYTE2
BYTE3
7 Clear interrupt status W LPRX_RD_RDY_INT_FLAG 0x1 0 x 00C[0]
Respond with read acknowledgement to
8 module and go to next commands in W RACK 0x1 0 x 084[0]
queue
9 Issue interrupt and command done R CMD_DONE_INT_FLAG 0x1 0 x 00C[1]
10 Clear interrupt status W CMD_DONE_INT_FLAG 0x1 0 x 00C[1]

[Link].5 Tearing Effect Detection

[Link].5.1 Peripheral TE

DSI has the ability to receive peripheral Tearing Effect (TE) signals via the BTA process. The TE signal is the LPTX transmitted
signal from the panel. Before starting to receive TE signals from the peripheral, make sure a DCS command of
“set_tear_on” is sent and register configuration of TE is enabled in the peripheral to avoid TE hanged issue. Here is an
example in Table 3-61 to show how to trigger TE commands by command queue.

Table 3-61 Example of Peripheral TE Signaling Detection

Step Sequence R/W REG_Name REG_Value Address
1 Fill command queue: DCS “set_tear_on” W DSI_CMDQ[0] 0 x 00351500 0 x 200
2 Fill command queue: Get TE W DSI_CMDQ[1] 0 x 00000020 0 x 204
3 Fill command queue: Type-1 command W DSI_CMDQ[2] 0 x 002C3909 0 x 208
4 Set command count W CMDQ_SIZE 0x3 0 x 060[7:0]
5 Set memory write continue command W DSI_RWMEM_CONTI 0 x 3C 0 x 090[15:0]
6 Start command W DSI_START 0x1 0 x 000[0]
7 Issue interrupt and receive TE R TE_RDY_INT_FLAG 0x1 0 x 00C[2]
RX_TRIG_0,
RX_TRIG_1,
8 Read trigger status (TE) R 0x2 0 x 088[3:0]
RX_TRIG_2,
RX_TRIG_3
9 Clear interrupt status W TE_RDY_INT_FLAG 0x1 0 x 00C[2]

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Step Sequence R/W REG_Name REG_Value Address

Response read ack to module and go to
10 W RACK 0x1 0 x 084[0]
next commands in queue
11 Issue interrupt and command done R CMD_DONE_INT_FLAG 0x1 0 x 00C[1]
12 Clear interrupt status W CMD_DONE_INT_FLAG 0x1 0 x 00C[1]

[Link].5.2 External TE

In certain cases, an external TE pin may be used instead of TE signals for some reasons. DSI supports this mechanism to
issue external TE interrupt signals. Refer to the sequences shown in Table 3-62 for detailed control information.

Table 3-62 Example of External TE Pin Detection

Step Sequence R/W REG_Name REG_Value Address
1 Enable external TE interrupt W TE_RDY_INT_EN 0x1 0 x 008[2]
2 Select external TE polarity (active-high) W EXT_TE_EDGE_SEL 0x0 0 x 018[10]
3 Enable external TE W EXT_TE_EN 0x1 0 x 018[9]
4 Issue interrupt and receive external TE R TE_RDY_INT_FLAG 0x1 0 x 00C[2]
5 Clear interrupt status W TE_RDY_INT_FLAG 0x1 0 x 00C[2]

[Link].6 Switch of Video Mode and Command Mode

The switch between video mode and command mode is controlled by MODE_CON (DSI base address + 0 x 014[1:0]). And
this switch is allowed only when DSI is not busy. Switching the mode while DSI is still busy causes DSI to hang up. There are
three ways to know if DSI is non-busy, which are shown in Table 3-63, Table 3-64, and Table 3-65.

Table 3-63 DSI Non-busy Detection by DSI_BUSY Register

Step Sequence R/W REG_Name REG_Value Address
1 Stop DSI W DSI_START 0x0 0 x 000[0]
2 Wait for DSI non-busy R DSI_BUSY 0x0 0 x 00C[31]
3 Switch mode W MODE_CON - 0 x 014[1:0]
4 Mode switch done

Table 3-64 DSI Non-busy Detection by DSI_DONE Event

Step Sequence R/W REG_Name REG_Value Address
1 Stop DSI W DSI_START 0x0 0 x 000[0]
2 Wait for DSI_DONE event
3 Switch mode W MODE_CON - 0 x 014[1:0]
4 Mode switch done

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Table 3-65 DSI Non-busy Detection by VM_DONE/CM_DONE Interrupt

Step Sequence R/W REG_Name REG_Value Address
Enable VM_DONE interrupt (video VM_DONE_INT_EN/
1 W 0x1 0 x 008[3]/[1]
mode)/CM_DONE interrupt (command mode) CM_DONE_INT_EN
2 Stop DSI W DSI_START 0x0 0 x 000[0]
Wait for VM_DONE (video mode)/CM_DONE
3
IRQ (command mode)
4 Switch mode W MODE_CON - 0 x 014[1:0]
5 Mode switch done

[Link].7 Lane/Trio Swap Function

[Link].7.1 D-PHY Lane Swap

The D-PHY lane swap function can swap the source of all lanes. The source of each lane can be chosen by MIPI_TX_*_SEL,
which is shown in Table 3-66. The schematic diagram of lane swap mux is shown in Figure 3-64.

Table 3-66 D-PHY Lane Swap Control Register

Default
REG_Name Description Address
REG_Value
MIPI_TX_PHY2_SEL Lane2 LP data P selection 4’d0 MIPI_TX_Config base address + 0 x 040[7:4]
MIPI_TX_CPHY0BC_SEL Lane2 LP data N selection 4’d1 MIPI_TX_Config base address + 0 x 040[11:8]
MIPI_TX_PHY0_SEL Lane0 LP data P selection 4’d2 MIPI_TX_Config base address + 0 x 040[15:12]
MIPI_TX_CPHY1AB_SEL Lane0 LP data N selection 4’d3 MIPI_TX_Config base address + 0 x 040[19:16]
MIPI_TX_PHYC_SEL Lanec LP data P selection 4’d4 MIPI_TX_Config base address + 0 x 040[23:20]
MIPI_TX_CPHY1CA_SEL LaneC LP data N selection 4’d5 MIPI_TX_Config base address + 0 x 040[27:24]
MIPI_TX_PHY1_SEL Lane1 LP data P selection 4’d6 MIPI_TX_Config base address + 0 x 040[31:28]
MIPI_TX_CPHY2BC_SEL Lane1 LP data N selection 4’d7 MIPI_TX_Config base address + 0 x 044[3:0]
MIPI_TX_PHY3_SEL Lane3 LP data P selection 4’d8 MIPI_TX_Config base address + 0 x 044[7:4]
MIPI_TX_CPHYXXX_SEL Lane3 LP data N selection 4’d9 MIPI_TX_Config base address + 0 x 044[11:8]
MIPI_TX_PHY2_HSDATA_
Lane2 HS data selection 4’d0 MIPI_TX_Config base address + 0 x 048[3:0]
SEL
MIPI_TX_PHY0_HSDATA
Lane0 HS data selection 4’d2 MIPI_TX_Config base address + 0 x 048[11:8]
_SEL
MIPI_TX_PHYC_HSDATA
LaneC HS data selection 4’d4 MIPI_TX_Config base address + 0 x 048[19:16]
_SEL
MIPI_TX_PHY1_HSDATA
Lane1 HS data selection 4’d6 MIPI_TX_Config base address + 0 x 048[27:24]
_SEL
MIPI_TX_PHY3_HSDATA
Lane3 HS data selection 4’d8 MIPI_TX_Config base address + 0 x 04C[3:0]
_SEL

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LANE2_HSDATA_source 0 LANE2_LPDATA_P_source 0
LANE2_LPDATA_N_source 1
LANE0_HSDATA_source 2 LANE0_LPDATA_P_source 2
LANE0_LPDATA_N_source 3
LANEC_HSDATA_source 4 LANE*_HSDATA_output LANEC_LPDATA_P_source 4 LANE*_LPDATA_output
(*: 2, 0, C, 1, 3) LANEC_LPDATA_N_source 5 (*: 2, 0, C, 1, 3)
LANE1_HSDATA_source 6 LANE1_LPDATA_P_source 6
LANE1_LPDATA_N_source 7
LANE3_HSDATA_source 8 LANE3_LPDATA_P_source 8
LANE3_LPDATA_N_source 9

MIPI_TX_*_HSDATA_SEL MIPI_TX_*_SEL

Figure 3-64 D-PHY Lane Swap Mux

[Link].7.2 C-PHY Trio Swap

The C-PHY trio swap function can swap the source of all trios. The source of each trio can be chosen by MIPI_TX_*_SEL,
which is shown in Table 3-67. The schematic diagram of trio swap mux is shown in Figure 3-65.

Table 3-67 C-PHY Trio Swap Control Register

Default
REG_Name Description Address
REG_Value
MIPI_TX_PHY2_SEL T0A LP data selection 4’d0 MIPI_TX_Config base address + 0 x 040[7:4]
MIPI_TX_CPHY0BC_SEL T0B LP data selection 4’d1 MIPI_TX_Config base address + 0 x 040[11:8]
MIPI_TX_PHY0_SEL T0C LP data selection 4’d2 MIPI_TX_Config base address + 0 x 040[15:12]
MIPI_TX_CPHY1AB_SEL T1A LP data selection 4’d3 MIPI_TX_Config base address + 0 x 040[19:16]
MIPI_TX_PHYC_SEL T1B LP data selection 4’d4 MIPI_TX_Config base address + 0 x 040[23:20]
MIPI_TX_CPHY1CA_SEL T1C LP data selection 4’d5 MIPI_TX_Config base address + 0 x 040[27:24]
MIPI_TX_PHY1_SEL T2A LP data selection 4’d6 MIPI_TX_Config base address + 0 x 040[31:28]
MIPI_TX_CPHY2BC_SEL T2B LP data selection 4’d7 MIPI_TX_Config base address + 0 x 044[3:0]
MIPI_TX_PHY3_SEL T2C LP data selection 4’d8 MIPI_TX_Config base address + 0 x 044[7:4]
MIPI_TX_PHY2_HSDATA_SEL T0A HS data selection 4’d0 MIPI_TX_Config base address + 0 x 048[3:0]
MIPI_TX_CPHY0BC_HSDATA
T0B HS data selection 4’d1 MIPI_TX_Config base address + 0 x 048[7:4]
_SEL
MIPI_TX_PHY0_HSDATA _SEL T0C HS data selection 4’d2 MIPI_TX_Config base address + 0 x 048[11:8]
MIPI_TX_CPHY1AB_HSDATA
T1A HS data selection 4’d3 MIPI_TX_Config base address + 0 x 048[15:12]
_SEL
MIPI_TX_PHYC_HSDATA _SEL T1B HS data selection 4’d4 MIPI_TX_Config base address + 0 x 048[19:16]
MIPI_TX_CPHY1CA_HSDATA
T1C HS data selection 4’d5 MIPI_TX_Config base address + 0 x 048[23:20]
_SEL
MIPI_TX_PHY1_HSDATA _SEL T2A HS data selection 4’d6 MIPI_TX_Config base address + 0 x 048[27:24]
MIPI_TX_CPHY2BC_HSDATA
T2B HS data selection 4’d7 MIPI_TX_Config base address + 0 x 048[31:28]
_SEL
MIPI_TX_PHY3_HSDATA _SEL T2C HS data selection 4’d8 MIPI_TX_Config base address + 0 x 04C[3:0]
T0 HS ctrl signal
MIPI_TX_CPHY0_HS_SEL 2’d0 MIPI_TX_Config base address + 0 x 044[25:24]
selection
T0 HS ctrl signal
MIPI_TX_CPHY1_HS_SEL 2’d1 MIPI_TX_Config base address + 0 x 044[27:26]
selection
T0 HS ctrl signal
MIPI_TX_CPHY2_HS_SEL 2’d2 MIPI_TX_Config base address + 0 x 044[29:28]
selection

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T0A_DATA_source 0
T0B_DATA_source 1 T0_HS_CTRL_source 0
T0C_DATA_source 2
T1A_DATA_source 3
T1B_DATA_source 4 T*_HS_CTRL_output
T*_DATA_output T1_HS_CTRL_source 1
T1C_DATA_source 5 (*: 0, 1, 2)
T2A_DATA_source 6 *: T0A, T0B, T0C,
T2B_DATA_source 7 T1A, TB, T1C,
T2C_DATA_source 8 T2A, T2B, T2C T2_HS_CTRL_source 2

MIPI_TX_*_SEL MIPI_TX_CPHY*_HS_SEL

Figure 3-65 C-PHY Trio Swap Mux

[Link] DSI Signal Descriptions

Table 3-68 presents DSI signal descriptions.

Table 3-68 DSI signal descriptions

Signal Name Type Description Ball Location
DSI1 D-PHY Mode C-PHY Mode
DSI1_CKN_T1C AIO DSI1 clock lane (negative) DSI1 Trio1 C AK6
DSI1_CKP_T1B AIO DSI1 clock lane (positive) DSI1 Trio1 B AK7
DSI1_D0N_T1A AIO DSI1 data lane 0 (negative) DSI1 Trio1 A AK5
DSI1_D0P_T0C AIO DSI1 data lane 0 (positive) DSI1 Trio0 C AL5
DSI1_D1N_T2B AIO DSI1 data lane 1 (negative) DSI1 Trio2 B AL6
DSI1_D1P_T2A AIO DSI1 data lane 1 (positive) DSI1 Trio2 A AL7
DSI1_D2N_T0B AIO DSI1 data lane 2 (negative) DSI1 Trio0 B AL4
DSI1_D2P_T0A AIO DSI1 data lane 2 (positive) DSI1 Trio0 B AL3
DSI1_D3N AIO DSI1 data lane 3 (negative) - AK8
DSI1_D3P_T2C AIO DSI1 data lane 3 (positive) DSI1 Trio2 C AL8
DSI1_TE DI DSI1 tearing effect control DSI1 tearing effect control Y5, AA7
DSI0 D-PHY Mode C-PHY Mode
DSI0_CKN_T1C AIO DSI0 clock lane (negative) DSI0 Trio1 C AH7
DSI0_CKP_T1B AIO DSI0 clock lane (positive) DSI0 Trio1 B AH6
DSI0_D0N_T1A AIO DSI0 data lane 0 (negative) DSI0 Trio1 A AH5
DSI0_D0P_T0C AIO DSI0 data lane 0 (positive) DSI0 Trio0 C AG5
DSI0_D1N_T2B AIO DSI0 data lane 1 (negative) DSI0 Trio2 B AH3
DSI0_D1P_T2A AIO DSI0 data lane 1 (positive) DSI0 Trio2 A AH4
DSI0_D2N_T0B AIO DSI0 data lane 2 (negative) DSI0 Trio0 B AG6
DSI0_D2P_T0A AIO DSI0 data lane 2 (positive) DSI0 Trio0 A AG7
DSI0_D3N AIO DSI0 data lane 3 (negative) - AH2
DSI0_D3P_T2C AIO DSI0 data lane 3 (positive) DSI0 Trio2 C AJ3
DSI_TE DI DSI0 tearing effect control DSI0 tearing effect control AA7, Y5

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3.8.3 Display Digital Parallel Interface (DPI)

[Link] Overview
The device includes two DPI controllers, DPI0 and DPI1, which output digital video data and timing signals. DPI0 is
used to directly interface with an external display panel, while DPI1 provides data and timings to the HDMITX
module.

[Link] Features

Each DPI controller supports the following key features:

 Flexible output data bus width and formats:

 DPI0 up to 16-bit bus: RGB565/YUV422 8-bit
 DPI1 up to 30-bit bus: RGB565/RGB 8-bit, 10bit/YUV444 8-bit, 10-bit/YUV422 8-bit, 10-bit, 12-bit
 Resolution up to 1920 × 1080 @ 60fps (for DPI0 only)
 Fixed-coefficient color space conversion
 Embedded synchronization timings for BT.656-like output format
 Dual edge output format
 YUV444 to YUV422 chroma down-sampling
 Internal pattern generator

[Link] DPI Signal Descriptions

Table 3-69 presents DPI signal descriptions.

Table 3-69 DPI Signal Descriptions

Signal Name Type Description Ball Location
DPI_CK DO DPI pixel clock AB1
DPI_D0 DO DPI data 0 AB9
DPI_D1 DO DPI data 1 AC9
DPI_D10 DO DPI data 10 AC5
DPI_D11 DO DPI data 11 AA5
DPI_D12 DO DPI data 12 AA6
DPI_D13 DO DPI data 13 AC6
DPI_D14 DO DPI data 14 AC7
DPI_D15 DO DPI data 15 AB4
DPI_D2 DO DPI data 2 AB8
DPI_D3 DO DPI data 3 AC4
DPI_D4 DO DPI data 4 AB3
DPI_D5 DO DPI data 5 AA8
DPI_D6 DO DPI data 6 AC8

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Signal Name Type Description Ball Location

DPI_D7 DO DPI data 7 AB7
DPI_D8 DO DPI data 8 AB6
DPI_D9 DO DPI data 9 AB5
DPI_DE DO DPI data enable AB2
DPI_HSYNC DO DPI horizontal synchronization AD11
DPI_VSYNC DO DPI vertical synchronization AD10

[Link] DPI Timing Characteristics

Table 3-70 and Figure 3-66 present timing characteristics for DPI in the device.

Table 3-70 DPI Timing Characteristics

No. Parameter Min Max Unit
(1)
DPI01 tc Cycle time 6.73 ns
DPI02 D Duty cycle, DPI_CK 45 55 %
DPI03 tRISE Rise time 1.374 ns
DPI04 tFALL Fall time 1.374 ns
DPI05 td Delay time, other signals to DPI_CK 1.683 ns
(1) For maximum operating clock frequency, refer to Table 6-1.

Figure 3-66 DPI Timing Diagram

[Link] DPI Block Diagram

 Timing generator (tgen): Generate timing signals like vsync, hsync, and de.
 Pattern generator (pat): Generate an internal pattern. If a pattern is enabled, the input data is replaced by the internal
pattern data.
 FIFO controller (afifo): Turn 1T1P or 1T2P to 1T1P and turn mm_clk to dpi_pixel_clk.

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 Matrix: Perform color space conversion and support 19 internal matrices as well as programmable matrix.
 Chroma low pass filter (clpf) and YUV422: Down sample YUV444 to YUV422.
 Embedded sync (embsync): Embed sync signals to data channel and support BT656-like output format.
 Outstage: Support channel swap and DDR, output video data and timing.

Figure 3-67 DPI Block Diagram

[Link] DPI Programming Guide

The following figure shows the DPI programming flow diagram. Firstly, configure each timing register based on the target
frame timing. Then, reset and enable DPI.

Figure 3-68 Programming Flow Diagram

3.8.4 Embedded DisplayPort Interface (EDPTX)

[Link] Overview

The EDPTX provides the electrical transport for video and auxiliary data between the device and an external display
module. The communication link is handled through the eDP Auxiliary Channel (EDPAUX).

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[Link] Features

The EDPTX supports the following key features:

 Compliance with eDP v1.4 standard

 Single link output port with 2 × main lanes
 Up to 5.4 Gbps per lane (HBR2)
 Hot-Plug Detect (HPD) line
 Auxiliary channel lane:
 Manchester-II coding
 Clock extracted from the data stream
 1 Mbps bit rate
 Input data formats: RGB 8-bit/10-bit, YUV444 8-bit/10-bit, YUV422 8-bit/10-bit
 RGB444 8-bit/10-bit color format
 8-bit to 10-bit encoder
 Alternative Scrambler Seed Reset (ASSR) function
 Inter-lane skew function
 Up to 2560x1600 @ 60 Hz resolution (10-bit, HBR2 without DSC)

[Link] EDPTX Signal Descriptions

Table 3-71 presents EDPTX signal descriptions.

Table 3-71 EDPTX Signal Descriptions

Signal Name Type Description Ball Location

EDP_TX_HPD DI EDPTX hot plug detect AC32, AA35, F4, AA7, Y5, K30

EDP_LN0_TXN AIO EDPTX lane 0 (negative) AG29

EDP_LN0_TXP AIO EDPTX lane 0 (positive) AG30

EDP_LN1_TXN AIO EDPTX lane 1 (negative) AF31

EDP_LN1_TXP AIO EDPTX lane 1 (positive) AF32

EDPAUXN AIO EDPTX auxiliary channel (negative) AF37

EDPAUXP AIO EDPTX auxiliary channel (positive) AF36

[Link] Block Diagram

The EDP_TX_MAC block is the main design. It supports HBR2 solution. Source video signals can come from GPU. The AUX
can be controlled by the software.

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EDP TX MAC
EDP PHY

GPU DP Encoder TX PHY

ATOP

Transmitter TX PHY
SW

AUX

Figure 3-69 EDP TX Block Diagram with Other IPs

[Link].1 EDPTX Encoder

The pixel clock and link clock serve as the main clocks in DP. Hence, the design is related to the speed limitation. The
Transfer Unit (TU) calculator generates the appropriate TU value to avoid TBC FIFO from being empty or full. The lane
arbiter splits video data into 4/2/1 DP lanes. The video data packer packages video data into DP format. Meanwhile, the
video MN GEN circuit calculates the M value, which is inserted to Vertical Blanking ID (VBID) and Main Stream Attribute
(MSA) packets. VBID includes the vblank flag, field flag, interlace flag (I mode), video mute flag, audio mute flag, HDCP sync
detect flag, and DSC flag, while MSA includes video timing information (HV_total, HV_width, etc.). Finally, the symbol mixer
contains VBID, MSA, and video data.

Pixel
Domain
VBID
Link To Transmitter
Symbol
Domain
Mixer
link_clk
Video MN Gen. MSA
stream_clk

Video
data
Video
Lane Video
Timing Gen MUX Data
Arbiter TBC FIFO
Pattern Packer TU
Gen Calculator

Figure 3-70 EDP TX Encoder Block Diagram

[Link].2 DPTX Transmitter

1. Main link data path is processed in 4P, clk_ls = link_rate/40.

2. TX Training Control generates TPS1/TPS2/TPS3/TPS4 patterns.
3. Pre-Encode MISC includes lane mux, PN swap, bit reverse and data swap.
4. Post-Encode MISC includes lane mux, PN swap, bit reverse and data swap.
5. Program/PRBS Pattern gen can generate 8/11/80-bit and PRBS test patterns.

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32 32 32 40 40 40 Lane 0 40

Pre- Program/ Post- Lane 1

8b10b
Encode Scramble PRBS Interskew Encode Lane 2
Encode
MISC PAT GEN MISC Lane 3

Lane TOP

TX Training Control

Figure 3-71 DP TX Transmitter Block Diagram

[Link].3 DPTX AUX

The software controls PHY TX to transmit AUX sequence and receive RX site reply data by PHY RX.

1. PHY TX includes Manchester encoder.

2. PHY RX includes Manchester decoder.

phy_tx

Register
control

phy_rx

Figure 3-72 DP TX AUX Diagram

[Link] General SW MAC Setting (APN)

[Link].1 MSA

dptx_reg_3030_dp_enc_4p[9:0] = 10’h3ff
dptx_reg_3010_dp_enc_4p[15:0]: htotal
dptx_reg_3014_dp_enc_4p[15:0]: vtotal
dptx_reg_3018_dp_enc_4p[15:0]: hstart
dptx_reg_301C_dp_enc_4p[15:0]: vstart
dptx_reg_3020_dp_enc_4p[15:0]: hwidth
dptx_reg_3024_dp_enc_4p[15:0]: vheigth
dptx_reg_3028_dp_enc_4p[14:0]: hsw
dptx_reg_3028_dp_enc_4p[15]: hsp
dptx_reg_302C_dp_enc_4p[14:0]: vsw

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dptx_reg_302C_dp_enc_4p[15]: vsp

[Link].2 Lane Number

The lane number control register exists in the encoder and transmitter.

4-lane: dptx_reg_3000_dp_enc_4p[1:0] = 2’b10

dptx_reg_34A4_dp_trans_4p[3:2] = 2’b10
dptx_reg_35F0_dp_trans_4p[3:2] = 2’b10

2-lane: dptx_reg_3000_dp_enc_4p[1:0] = 2’b01

dptx_reg_34A4_dp_trans_4p[3:2] = 2’b01
dptx_reg_35F0_dp_trans_4p[3:2] = 2’b01

1-lane: dptx_reg_3000_dp_enc_4p[1:0] = 2’b00

dptx_reg_34A4_dp_trans_4p[3:2] = 2’b00
dptx_reg_35F0_dp_trans_4p[3:2] = 2’b00

[Link].3 Training Pattern (1/2/3/4)

Normal mode : dptx_reg_3400_dp_trans_4p[15:12] = 4’b0000

Training Pattern 1: dptx_reg_3400_dp_trans_4p[15:12] = 4’b0001
Training Pattern 2: dptx_reg_3400_dp_trans_4p[15:12] = 4’b0010
Training Pattern 3: dptx_reg_3400_dp_trans_4p[15:12] = 4’b0100
Training Pattern 4: dptx_reg_3400_dp_trans_4p[15:12] = 4’b1000

[Link].4 CTS Pattern

CP2520 pattern 1: dptx_reg_3478_dp_trans_4p[0]

CP2520 pattern 2: dptx_reg_3478_dp_trans_4p[1]
PRBS pattern: dptx_reg_3444_dp_trans_4p[3]

[Link].5 Alternate Scrambler Seed Reset (ASSR)

Scrambler Seed Reset = hfffe

dptx_reg_3404_dp_trans_4p[1]

[Link].6 Enhanced Frame Mode

dptx_reg_3000_dp_enc_4p[4]

[Link].7 Pre-Lane Mux

dptx_reg_3404_dp_trans_4p[1:0]: Lane0 mux

dptx_reg_3404_dp_trans_4p[3:2]: Lane1 mux

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dptx_reg_3404_dp_trans_4p[5:4]: Lane2 mux

dptx_reg_3404_dp_trans_4p[7:6]: Lane3 mux

[Link].8 Post-Lane Mux

dptx_reg_3408_dp_trans_4p[9:8]: Lane0 mux

dptx_reg_3408_dp_trans_4p[11:10]: Lane1 mux
dptx_reg_3408_dp_trans_4p[13:12]: Lane2 mux
dptx_reg_3408_dp_trans_4p[15:14]: Lane3 mux

[Link].9 Post-PN Swap

dptx_reg_3406_dp_trans_4p[1]: PN swap

[Link].10 Initial Setting

RGB 30BPP: dptx_reg_303C_dp_enc_4p[14:8] = 7’h02

RGB 24BPP: dptx_reg_303C_dp_enc_4p[14:8] = 7’h03
RGB 18BPP: dptx_reg_303C_dp_enc_4p[14:8] = 7’h04
MISC0: dptx_reg_3034_dp_enc_4p[7:0], value according to DP specification.
MISC1: dptx_reg_3034_dp_enc_4p[15:8]

[Link].11 MSA Delay Line Setting

dptx_reg_32F8_dp_enc_4p_2[8]: MSA line delay function enable

dptx_reg_32F8_dp_enc_4p_2[7:0]: Line delay count

[Link].12 TU Calculation

dptx_reg_33C0_dp_enc_4p_2[6:0]: Read hardware TU number

[Link].13 AUX PHY Initial Setting

dptx_reg_367C_dp_tx_aux[12] = 1’b1
dptx_reg_3670_dp_tx_aux[10] = 1’b0
dptx_reg_3658_dp_tx_aux[10] = 1’b0

[Link].14 AUX 400us Timeout Threshold

dptx_reg_360C_dp_tx_aux[12:0]: The unit is xtal period.

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[Link].15 DPCD Write

dptx_reg_3644_dp_tx_aux[3:0]: Request command

{dptx_reg_364C_dp_tx_aux, dptx_reg_3648_dp_tx_aux[15:0]}: Request address
dptx_reg_3650_dp_tx_aux[15:12]: Request length
dptx_reg_3634_dp_tx_aux[7:0]: Request write data
dptx_reg_3630_dp_tx_aux[3]: Request ready

Command Address data_num wdata Wait 1T wdata Ready trigger

xtal …

Repeat based on data_num

Figure 3-73 DPCD Writing Flow

dptx_reg_3640_dp_tx_aux[6]: Sink reply complete IRQ

dptx_reg_3640_dp_tx_aux[0]: AUX timeout IRQ
dptx_reg_3624_dp_tx_aux[3:0]: Sink reply command

[Link].16 DPCD Read

These control registers are the same as DPCD write registers.

Command Address data_num Ready

trigger

dptx_reg_3620_dp_tx_aux[8]: The software reads data pulse.

Wait for Reply value Trigger FIFO ren Wait Clear all IRQ Complete
IRQ …

Repeat based on data_num

Figure 3-74 DPCD Reading Flow

[Link].17 I2C Write

The flow is the same as that of DPCD write.

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[Link].18 I2C Write No Length

This flow is different. Since the AUX sequence has no length, data_num and wdata can be ignored. Note that no_length has
to be cleared after the communication is completed.

dptx_reg_362C_dp_tx_aux[0]: No length setting

Command Address data_num wdata Ready

trigger

no_length

Wait for IRQ Reply value Clear all IRQ Complete Clear no_length

Figure 3-75 I2C Writing Flow

[Link].19 I2C Read

The flow is the same as that of DPCD read.

[Link].20 I2C Read No Length

The flow is the same as DPCD write no length, but it is a write command.

[Link].21 AUX PHY FIFO Status

dptx_reg_368C_dp_tx_aux[0]: RX FIFO done flag

dptx_reg_368C_dp_tx_aux[1]: Clear RX FIFO done flag
dptx_reg_368C_dp_tx_aux[2]: TX FIFO done flag
dptx_reg_368C_dp_tx_aux[3]: Clear TX FIFO done flag

When toggling dptx_reg_3620_dp_tx_aux[8], the software could poll dptx_reg_368C_dp_tx_aux[0]. If this bit is 1’b0, it will
read the next data. Before reading the next data, clear the dptx_reg_368C_dp_tx_aux[0] status by
dptx_reg_368C_dp_tx_aux[1].

When toggling dptx_reg_3634_dp_tx_aux, the software could poll dptx_reg_368C_dp_tx_aux[2]. If this bit is 1’b0, it will
write the next data to this FIFO. Before writing the next data to TX FIFO, clear the dptx_reg_368C_dp_tx_aux[2] status by
dptx_reg_368C_dp_tx_aux[3].

[Link].22 AUX TX Request Pre-charge + Preamble Number

dptx_reg_3630_dp_tx_aux[15:8]: pre-charge + preamble number

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3.8.5 DisplayPort Interface (DPTX)

[Link] Overview
The DPTX provides digital video and auxiliary data transfer between the device and an external display module.
The communication link is handled through the DP Auxiliary Channel (DPAUX).

[Link] Features

The DPTX supports the following key features:

 Compliance with DP v1.4 standard

 Single link output port with 4 × main lanes, configured as follows:
 4 × lanes with up to 5.4 Gbps per lane (HBR2)
 Hot-Plug Detect (HPD) line
 Auxiliary channel lane:
 Manchester-II coding
 Clock extracted from the data stream
 1 Mbps bit rate
 Input data formats: RGB 8-bit/10-bit, YUV444 8-bit/10-bit, YUV422 8-bit/10-bit
 Output data format: RGB444 8-bit/10-bit
 8-bit to 10-bit encoder
 Alternative Scrambler Seed Reset (ASSR) function
 Inter-lane skew function
 Up to 4K2K @ 60 Hz resolution (10-bit, HBR2 without DSC)

[Link] DPTX Signal Descriptions

Table 3-72 presents DPTX signal descriptions.

Table 3-72 DPTX Signal Descriptions

Signal Name Type Description Ball Location
DP_LN0_TXN AIO DPTX lane 0 (negative) AH35
DP_LN0_TXP AIO DPTX lane 0 (positive) AG35
DP_LN1_TXN AIO DPTX lane 1 (negative) AH31
DP_LN1_TXP AIO DPTX lane 1 (positive) AH32
DP_LN2_TXN AIO DPTX lane 2 (negative) AJ33
DP_LN2_TXP AIO DPTX lane 2 (positive) AJ34
DP_LN3_TXN AIO DPTX lane 3 (negative) AK31
DP_LN3_TXP AIO DPTX lane 3 (positive) AK32
DP_TX_HPD DI DPTX hot plug detect AB33, J31, Y9, AA11, E5
DPAUXN AIO DPTX auxiliary channel (negative) AJ37
DPAUXP AIO DPTX auxiliary channel (positive) AJ36

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[Link] Block Diagram

The DP_TX_MAC block is the main design. It supports HBR2 solution. Source video signals can come from GPU. The AUX
can be controlled by the software.

DP TX MAC
TX PHY ATOP

GPU DP Encoder TX PHY

ATOP

Transmitter TX PHY
SW

AUX

Figure 3-76 DP TX Block Diagram with Other IPs

[Link].1 DPTX Encoder

The pixel clock and link clock serve as the main clocks in DP. Hence, the design is related to the speed limitation. The
Transfer Unit (TU) calculator generates the appropriate TU value to avoid TBC FIFO from being empty or full. The lane
arbiter splits video data into 4/2/1 DP lanes. The video data packer packages video data into DP format. Meanwhile, the
video MN GEN circuit calculates the M value, which is inserted to Vertical Blanking ID (VBID) and Main Stream Attribute
(MSA) packets. VBID includes the vblank flag, field flag, interlace flag (I mode), video mute flag, audio mute flag, HDCP sync
detect flag, and DSC flag, while MSA includes video timing information (HV_total, HV_width, etc.). Finally, the symbol mixer
contains VBID, MSA and video data.

Audio RS
sample Audio Audio Encoder
SDP Packer
Packer FIFO &
CRC

link_clk
128fs_clk Audio MN Gen. and FREQ VBID
xtal_clk Symbol
To Transmitter
Mixer
link_clk
stream_clk Video MN Gen. and FREQ MSA
xtal_clk

HVDE
Video
M Lane Video
Timing Gen Data
UX Arbiter TBC FIFO
Pattern Packer TU
Gen calculator

Figure 3-77 DP TX Encoder Block Diagram

[Link].2 DPTX Transmitter

1. Main link data path is processed in 4P, clk_ls = link_rate/40.

2. TX Training Control generates TPS1/TPS2/TPS3/TPS4 patterns.
3. Pre-Encode MISC includes lane mux, PN swap, bit reverse and data swap.
4. Post-Encode MISC includes lane mux, PN swap, bit reverse and data swap.
5. Program/PRBS Pattern gen can generate 8/11/80-bit and PRBS test patterns.

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32 32 32 40 40 40 Lane 0 40

Pre- Program/ Post- Lane 1

8b10b
Encode Scramble PRBS Interskew Encode Lane 2
Encode
MISC PAT GEN MISC Lane 3

Lane TOP

TX Training Control

Figure 3-78 DP TX Transmitter Block Diagram

[Link].3 DP TX AUX

The software controls PHY TX to transmit AUX sequence and receive RX site reply data by PHY RX.

1. PHY TX includes Manchester encoder.

2. PHY RX includes Manchester decoder.

phy_tx

Register
control

phy_rx

Figure 3-79 DP TX AUX Diagram

[Link] General SW MAC Setting (APN)

[Link].1 MSA

dptx_reg_3030_dp_enc_4p[9:0] = 10’h3ff
dptx_reg_3010_dp_enc_4p[15:0]: htotal
dptx_reg_3014_dp_enc_4p[15:0]: vtotal
dptx_reg_3018_dp_enc_4p[15:0]: hstart
dptx_reg_301C_dp_enc_4p[15:0]: vstart
dptx_reg_3020_dp_enc_4p[15:0]: hwidth
dptx_reg_3024_dp_enc_4p[15:0]: vheigth
dptx_reg_3028_dp_enc_4p[14:0]: hsw
dptx_reg_3028_dp_enc_4p[15]: hsp
dptx_reg_302C_dp_enc_4p[14:0]: vsw

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dptx_reg_302C_dp_enc_4p[15]: vsp

[Link].2 Lane Number

The lane number control register exists in the encoder and transmitter.

4-lane: dptx_reg_3000_dp_enc_4p[1:0] = 2’b10

dptx_reg_34A4_dp_trans_4p[3:2] = 2’b10
dptx_reg_35F0_dp_trans_4p[3:2] = 2’b10

2-lane: dptx_reg_3000_dp_enc_4p[1:0] = 2’b01

dptx_reg_34A4_dp_trans_4p[3:2] = 2’b01
dptx_reg_35F0_dp_trans_4p[3:2] = 2’b01

1-lane: dptx_reg_3000_dp_enc_4p[1:0] = 2’b00

dptx_reg_34A4_dp_trans_4p[3:2] = 2’b00
dptx_reg_35F0_dp_trans_4p[3:2] = 2’b00

[Link].3 Training Pattern (1/2/3/4)

Normal mode : dptx_reg_3400_dp_trans_4p[15:12] = 4’b0000

Training Pattern 1: dptx_reg_3400_dp_trans_4p[15:12] = 4’b0001
Training Pattern 2: dptx_reg_3400_dp_trans_4p[15:12] = 4’b0010
Training Pattern 3: dptx_reg_3400_dp_trans_4p[15:12] = 4’b0100
Training Pattern 4: dptx_reg_3400_dp_trans_4p[15:12] = 4’b1000

[Link].4 CTS Pattern

CP2520 pattern 1: dptx_reg_3478_dp_trans_4p[0]

CP2520 pattern 2: dptx_reg_3478_dp_trans_4p[1]
PRBS pattern: dptx_reg_3444_dp_trans_4p[3]

[Link].5 Alternate Scrambler Seed Reset (ASSR)

Scrambler Seed Reset = hfffe

dptx_reg_3404_dp_trans_4p[1]

[Link].6 Enhanced Frame Mode

dptx_reg_3000_dp_enc_4p[4]

[Link].7 Pre-Lane Mux

dptx_reg_3404_dp_trans_4p[1:0]: Lane0 mux

dptx_reg_3404_dp_trans_4p[3:2]: Lane1 mux

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dptx_reg_3404_dp_trans_4p[5:4]: Lane2 mux

dptx_reg_3404_dp_trans_4p[7:6]: Lane3 mux

[Link].8 Post-Lane Mux

dptx_reg_3408_dp_trans_4p[9:8]: Lane0 mux

dptx_reg_3408_dp_trans_4p[11:10]: Lane1 mux
dptx_reg_3408_dp_trans_4p[13:12]: Lane2 mux
dptx_reg_3408_dp_trans_4p[15:14]: Lane3 mux

[Link].9 Post-PN Swap

dptx_reg_3406_dp_trans_4p[1]: PN swap

[Link].10 Initial Setting

RGB 30BPP: dptx_reg_303C_dp_enc_4p[14:8] = 7’h02

RGB 24BPP: dptx_reg_303C_dp_enc_4p[14:8] = 7’h03
RGB 18BPP: dptx_reg_303C_dp_enc_4p[14:8] = 7’h04
MISC0: dptx_reg_3034_dp_enc_4p[7:0], value according to DP specification.
MISC1: dptx_reg_3034_dp_enc_4p[15:8]

[Link].11 MSA Delay Line Setting

dptx_reg_32F8_dp_enc_4p_2[8]: MSA line delay function enable

dptx_reg_32F8_dp_enc_4p_2[7:0]: Line delay count

[Link].12 TU Calculation

dptx_reg_33C0_dp_enc_4p_2[6:0]: Read hardware TU number

[Link].13 AUX PHY Initial Setting

dptx_reg_367C_dp_tx_aux[12] = 1’b1
dptx_reg_3670_dp_tx_aux[10] = 1’b0
dptx_reg_3658_dp_tx_aux[10] = 1’b0

[Link].14 AUX 400us Timeout Threshold

dptx_reg_360C_dp_tx_aux[12:0]: The unit is xtal period.

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[Link].15 DPCD Write

dptx_reg_3644_dp_tx_aux[3:0]: Request command

{dptx_reg_364C_dp_tx_aux, dptx_reg_3648_dp_tx_aux[15:0]}: Request address
dptx_reg_3650_dp_tx_aux[15:12]: Request length
dptx_reg_3634_dp_tx_aux[7:0]: Request write data
dptx_reg_3630_dp_tx_aux[3]: Request ready

Command Address data_num wdata Wait 1T wdata Ready trigger

xtal …

Repeat based on data_num

Figure 3-80 DPCD writing flow

dptx_reg_3640_dp_tx_aux[6]: Sink reply complete IRQ

dptx_reg_3640_dp_tx_aux[0]: AUX timeout IRQ
dptx_reg_3624_dp_tx_aux[3:0]: Sink reply command

[Link].16 DPCD Read

These control registers are the same as DPCD write registers.

Command Address data_num Ready

trigger

dptx_reg_3620_dp_tx_aux[8]: The software reads data pulse.

Wait for Reply value Trigger FIFO ren Wait Clear all IRQ Complete
IRQ …

Repeat based on data_num

Figure 3-81 DPCD Reading Flow

[Link].17 I2C Write

The flow is the same as that of DPCD write.

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[Link].18 I2C Write No Length

This flow is different. Since the AUX sequence has no length, data_num and wdata can be ignored. Note that no_length has
to be cleared after the communication is completed.
dptx_reg_362C_dp_tx_aux[0]: No length setting

Command Address data_num wdata Ready

trigger

no_length

Wait for IRQ Reply value Clear all IRQ Complete Clear no_length

Figure 3-82 I2C Writing Flow

[Link].19 I2C Read

The flow is the same as that of DPCD read.

[Link].20 I2C Read No Length

The flow is the same as DPCD write no length, but it is a write command.

[Link].21 AUX PHY FIFO Status

dptx_reg_368C_dp_tx_aux[0]: RX FIFO done flag

dptx_reg_368C_dp_tx_aux[1]: Clear RX FIFO done flag
dptx_reg_368C_dp_tx_aux[2]: TX FIFO done flag
dptx_reg_368C_dp_tx_aux[3]: Clear TX FIFO done flag

When toggling dptx_reg_3620_dp_tx_aux[8], the software could poll dptx_reg_368C_dp_tx_aux[0]. If this bit is 1’b0, it will
read the next data. Before reading the next data, clear the dptx_reg_368C_dp_tx_aux[0] status by
dptx_reg_368C_dp_tx_aux[1].

When toggling dptx_reg_3634_dp_tx_aux, the software could poll dptx_reg_368C_dp_tx_aux[2]. If this bit is 1’b0, it will
write the next data to this FIFO. Before writing the next data to TX FIFO, clear the dptx_reg_368C_dp_tx_aux[2] status by
dptx_reg_368C_dp_tx_aux[3].

[Link].22 AUX TX Request Pre-charge + Preamble Number

dptx_reg_3630_dp_tx_aux[15:8]: pre-charge + preamble number

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3.8.6 High-Definition Multimedia Interface Transmitter (HDMITX)

[Link] Overview
The HDMITX module encodes video, audio, and control data into Transition-Minimized Differential Signaling (TMDS)
format for digital transmission based on HDMI Specification 2.0b and transfers the uncompressed digital data
streams to an HDMI-compatible sink device.

[Link] Features

The HDMITX supports the following video features:

 Deep Color mode: up to 16 bits

 Maximum operating frequency: up to 594 MHz
 Video color space options: RGB444, YCbCr [Link] (ITU 601 and 709), YCbCr [Link] (ITU 601 and 709), YCbCr
[Link], and xvYCC
 3D HDMI function
 SD mode resolutions:
 1440 × 480i (pixel repeat 2) @59.94/60 Hz
 720 × 480p @ 59.94/60 Hz
 1440 × 576i (pixel repeat 2) @50 Hz
 720 × 576p @50 Hz
 HD/FHD/UFHD mode resolutions:
 1280 × 720p @ 59.94/60/50 Hz
 1920 × 1080i @ 59.94/60/50 Hz
 1920 × 1080p @ 59.94/60/50 Hz
 1920 × 1080p @ 23.97/24 Hz
 1920 × 1080p @ 25 Hz
 1920 × 1080p @ 29.97/30 Hz
 3840 × 2160p @ 29.97/30 Hz
 3840 × 2160p @ 59.94/60/50 Hz

The HDMITX supports the following audio features:

 Single compressed S/PDIF IEC61937 (up to 192 kHz)

 Single LPC S/PDIF IEC60958 (up to 192 kHz and up to 24 bits), 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4
kHz, 192 kHz
 Multi-channel PCM (Pulse-Code Modulation) input (maximum 8 channels)
 DSD audio
 Compressed lossless audio according to HDMI 2.0 (Dolby TrueHD and DTS-HD)

Additionally, the HDMITX supports the following general features:

 HPD line
 Discovery by EDID

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 Compatible with DVI 1.0

 HDCP 1.4/HDCP 2.3 function
 Supports dynamic metadata up to 2KB
 I2C-based Display Data Channel (DDC) with clock stretching
 Variable Refresh Rate (VRR)/Auto Low Latency Mode (ALLM)
 CEC channel shared with HDMIRX

[Link] Block Diagram

Figure 3-83 is the HDMITX block diagram.
HDMITX_TOP

Video process
pixel_clk

vs/hs/de
rgb[47:0]
video_data[23:0] AV mix

HDCP1.X 0 xor_data[23:0]
1

data_out[39:0]
HDCP2.X

AIP
bclk
lrck/sdx
audio_data[8:0]
mclk
spdif

pll_clk

Figure 3-83 HDMITX Block Diagram

[Link] HDMITX Signal Descriptions

Table 3-73 presents HDMITX signal descriptions.

Table 3-73 HDMITX Signal Descriptions

Signal Name Type Description Ball Location
HDMITX20_CEC DIO HDMITX CEC channel AC33, T30
HDMITX20_HTPLG DI HDMITX HPD line R31, AC32
HDMITX20_PWR5V DO HDMITX power supply (+5 V) AB32, AB34
HDMITX20_SCL DIO HDMITX DDC/I2C clock T31, AD32
HDMITX20_SDA DIO HDMITX DDC/I2C data AD33, U32
HDMITX21_CH0_M AO HDMITX TMDS data lane 0 (negative) AN34

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Signal Name Type Description Ball Location

HDMITX21_CH0_P AO HDMITX TMDS data lane 0 (positive) AN35
HDMITX21_CH1_M AO HDMITX TMDS data lane 1 (negative) AM37
HDMITX21_CH1_P AO HDMITX TMDS data lane 1 (positive) AM36
HDMITX21_CH2_M AO HDMITX TMDS data lane 2 (negative) AL35
HDMITX21_CH2_P AO HDMITX TMDS data lane 2 (positive) AK35
HDMITX21_CLK_M AO HDMITX TMDS clock lane (negative) AR35
HDMITX21_CLK_P AO HDMITX TMDS clock lane (positive) AR34

[Link] Theory of Operations

Data is transmitted in the same way as described in the specification of HDMI 2.0b.

[Link] Programming Guide

To start HDMITX function, follow the sequence to program the settings:

1. HDMITX analog clock configuration

2. HDMITX pixel clock configuration
3. Deep color mode selection
4. Audio mode configuration
5. Packet content configuration
6. Optional HDCP configuration

3.9 Imaging
The Camera Imaging Subsystem (CAMSYS) is built around a feature-rich Image Signal Processor (ISP) and a deep learning
Face Detection (FD) engine. The ISP processes data received either from camera sensors through MIPI CSI-2 interface or
system DRAM.

3.9.1 Camera Image Signal Processor (ISP)

The Image Signal Processor (ISP) is responsible for processing the image data generated by the camera sensor of a device.
The ISP converts the captured data into a digital format and enhances the image quality before displaying it on the screen
or storing it in memory.

[Link] ISP Features

The ISP supports the following key features:

 3 × MIPI CSI-2 high-speed camera serial interfaces:

 Up to 4 × data lanes of MIPI D-PHY 2.5 Gbps per lane
 Up to 3 × trios of MIPI C-PHY 4.5 Gsps per trio

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 Sensor supported format:

 RAW8/RAW10/RAW12/RAW14
 YUV422 8-bit (only dump DRAM)
 Single camera capture: up to 32MP at 30fps
 Dual camera capture: up to 16MP + 16MP at 30fps
 ISP image processing capability: 400MP/sec
 Video High Dynamic Range (HDR) with stagger HDR sensor: up to 12MP at 30fps
 Full size image capture for preview
 Image processing functions:
 Auto sensor defect pixel correction
 Lens shading correction
 Edge enhancement
 Video stabilization
 Motion compensated temporal noise reduction for video recording
 Electronic image stabilization
 Multiple frame noise reduction for image capture
 Zero shutter delay image capture
 Preference color adjustment
 AE (Auto Exposure)/AWB (Auto White Balance)/AF (Auto Focus) statistics collection
 Three-frame stagger HDR fusion
 Color aberration correction
 Anti-blooming correction
 YUV frame buffer compression

[Link] ISP Block Diagram

Figure 3-84 Block Diagram of ISP

The ISP consists of 2 main engines: Pass 1 (P1) and Pass 2 (P2).
 P1 receives raw data from the camera sensor, executes lens and sensor compensation algorithms, and converts the
image into YUV format.
 P2 obtains data from P1 through DRAM and further enhances the image quality, such as noise reduction, preference
color adjustment, edge enhancement, etc.

Note:
 The block diagram only represents a typical use case. The path may differ for other scenarios, such as debugging, tuning and
engineering modes.

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[Link] Camera Signal Descriptions

Table 3-74 presents camera signal descriptions.

Table 3-74 Camera Signal Descriptions

Signal Name Type Description Ball Location
CMFLASH0 DO Camera flash strobe 0 AC7, V4, G4
CMFLASH1 DO Camera flash strobe 1 V5, G3, AB4
CMFLASH2 DO Camera flash strobe 2 AA35, J31, E3
CMFLASH3 DO Camera flash strobe 3 G5, Y11, K30,
CMMCLK0 DO Sensor reference clock 0 E4
CMMCLK1 DO Sensor reference clock 1 E5
CMMCLK2 DO Sensor reference clock 2 F4
CMVREF0 DO Camera frame sync 0 V6, AD11, W4
CMVREF1 DO Camera frame sync 1 AD10, W5, T11
CMVREF2 DO Camera frame sync 2 AB2, V7, AA11
CMVREF3 DO Camera frame sync 3 AB1, V8, Y5
CMVREF4 DO Camera frame sync 4 G36, U7, G4
CMVREF5 DO Camera frame sync 5 U8, H36, G3
CMVREF6 DO Camera frame sync 6 T9, J36, W8
CMVREF7 DO Camera frame sync 7 T10, J37, AA35

3.9.2 Face Detection (FD)

[Link] Overview
The Face Detection (FD) engine uses a convolutional neural network algorithm to detect faces on a source image and
output the detected coordinates of the face windows and their confidence values.

[Link] Features
The FD engine supports the following key features:

 Input image formats:

 YUV420: 2 planes (Y/UV)
 YUV422: 2 planes (Y/UV, Y/VU)
 YUV422: 1 plane (YUYV, YVYU, UYVY, VYUY)
 Mono 8-bit 1 plane
 YUV to RGB888 format conversion
 Image up/down-scaling
 Maximum resize width: 640 pixels
 Maximum throughput

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 800 × 600@30 FPS

[Link] Block Diagram

Figure 3-85 is the block diagram of FD.

Figure 3-85 Block Diagram of AIE2.0

[Link] Function Description

The FD is a simple DRAM access engine supporting YUV420 and mono input images and building the image pyramid by the
up/down-size resizer inside the FD. YUV2RGB is directly linked to RS (resizer) to reduce DRAM bandwidth. After converting
YUV420 to RGB888 and building an image pyramid, FD starts several face detection loops and outputs the detected
coordinates of the face window and their confidence values.

[Link] Programming Guide

Step 1: Program FDVT frame-level registers
To program the FD, the first step is programming frame-level registers by the APB interface. These registers contain the
information of configuration DRAM base address, resizer loop number, face detection loop number, etc.

Step 2: Place YUV2RGB, RS, and FD configurations to DRAM

After programming the corresponding configuration DRAM base address, place the YUV2RGB, RS, and FD configurations
into DRAM. The sequencer inside the FD goes to the corresponding address to get the configuration during different
stages.

Step 3: Trigger FDVT start register

Program the FDVT_START register.

Step 4: Wait for FDVT interrupt

Once the programming of FD is done, an interrupt is generated.

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3.9.3 Camera Serial Interface (CSI)

[Link] Overview
The CSI is based on the MIPI Alliance Specification for Camera Serial Interface 2 (MIPI CSI-2) Version 2.1. The CSI provides
high-speed serial data transfer between the ISP and external camera image sensors.

The device features two MIPI CSI-2 controllers (CSI0 and CSI1), which are fully compliant with the MIPI CSI-2 specification.
The CSI0 controller and the CSI1 controller utilize a combined MIPI D-PHY/C-PHY physical layer. The PHY layer is based on
MIPI D-PHY Specification Revision 2.1 and MIPI C-PHY Specification Revision 1.2. It acts as a physical link between the CSI
controllers and image sensors.

[Link] Features
The MIPI CSI-2 implementation in the device provides the following key features:

 Primary CSI-2 interface (CSI0), which can be used in the following configuration:
 Two 2-data lane interfaces in D-PHY mode, or
 One 4-data lane interface in D-PHY mode, or
 One 3-trio interface in C-PHY mode, or
 Two 2-trio interfaces in C-PHY mode
 D-PHY supports 2.5Gbps per lane and C-PHY supports 4.5Gsps per trio
 Secondary CSI-2 interface (CSI1), which can be used in one of the following configurations:
 One 4-data lane interface in D-PHY mode, or
 One 3-trio interface in C-PHY mode
 DPHY supports 2.5Gbps per lane and C-PHY supports 4.5Gsps per trio
 Pixel formats: RAW8/RAW10/RAW12/RAW14/YUV422 8-bit
 No support for D-PHY escape mode and bus turnaround

[Link] CSI Signal Descriptions

Table 3-75 presents CSI0 signal descriptions.

Table 3-75 CSI0 Signal Descriptions

Signal Name Type Description Ball Location
1 × D-PHY 4- 2 × D-PHY 2-lane 1 × C-PHY 3- 2 × C-PHY 2-trio
lane Mode Mode trio Mode Mode
CSI0 data lane 2 CSI0 port 0 data
CSI0A_L0N_T0B AIO CSI0 Trio0 B CSI0 port 0 Trio0 B N3
(negative) lane 0 (negative)
CSI0 data lane 2 CSI0 port 0 data
CSI0A_L0P_T0A AIO CSI0 Trio0 A CSI0 port 0 Trio0 A N2
(positive) lane 0 (positive)
CSI0 data lane 0 CSI0 port 0 clock
CSI0A_L1N_T1A AIO CSI0 Trio1 A CSI0 port 0 Trio1 A N5
(negative) lane (negative)

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Signal Name Type Description Ball Location

CSI0 data lane 0 CSI0 port 0 clock
CSI0A_L1P_T0C AIO CSI0 Trio0 C CSI0 port 0 Trio0 C N4
(positive) lane (positive)
CSI0 clock lane CSI0 port 0 data
CSI0A_L2N_T1C AIO CSI0 Trio1 C CSI0 port 0 Trio1 C N6
(negative) lane 1 (negative)
CSI0 clock lane CSI0 port 0 data
CSI0A_L2P_T1B AIO CSI0 Trio1 B CSI0 port 0 Trio1 B M6
(positive) lane 1 (positive)
CSI0 data lane 1 CSI0 port 1 data
CSI0B_L0N_T0B AIO CSI0 Trio2 B CSI0 port 1 Trio0 B P1
(negative) lane 0 (negative)
CSI0 data lane 1 CSI0 port 1 data
CSI0B_L0P_T0A AIO CSI0 Trio2 A CSI0 port 1 Trio0 A P2
(positive) lane 0 (positive)
CSI0 data lane 3 CSI0 port 1 clock
CSI0B_L1N_T1A AIO - CSI0 port 1 Trio1 A P4
(negative) lane (negative)
CSI0 data lane 3 CSI0 port 1 clock
CSI0B_L1P_T0C AIO CSI0 Trio2 C CSI0 port 1 Trio0 C P3
(positive) lane (positive)
CSI0 port 1 data
CSI0B_L2N_T1C AIO CSI0 port 1 Trio1 C P6
lane 1 (negative)
CSI0 port 1 data
CSI0B_L2P_T1B AIO CSI0 port 1 Trio1 B P5
lane 1 (positive)
Note:
 Unused CSI ports could be connected to GND or set in not connected.

Table 3-76 presents CSI1 signal descriptions.

Table 3-76 CSI1 Signal Descriptions

Signal Name Type Description Ball Location
1× D-PHY 4-lane Mode 1 × C-PHY 3-trio Mode
CSI1A_L0N_T0B AIO CSI1 data lane 2 (negative) CSI1 Trio0 B J4
CSI1A_L0P_T0A AIO CSI1 data lane 2 (positive) CSI1 Trio0 A J5
CSI1A_L1N_T1A AIO CSI1 data lane 0 (negative) CSI1 Trio1 A J3
CSI1A_L1P_T0C AIO CSI1 data lane 0 (positive) CSI1 Trio0 C J2
CSI1A_L2N_T1C AIO CSI1 clock lane (negative) CSI1 Trio1 C K6
CSI1A_L2P_T1B AIO CSI1 clock lane (positive) CSI1 Trio1 B K7
CSI1B_L0N_T0B AIO CSI1 data lane 1 (negative) CSI1 Trio2 B K3
CSI1B_L0P_T0A AIO CSI1 data lane 1 (positive) CSI1 Trio2 A K5
CSI1B_L1N_T1A AIO CSI1 data lane 3 (negative) - L4
CSI1B_L1P_T0C AIO CSI1 data lane 3 (positive) CSI1 Trio2 C L3
Note:
 Unused CSI ports could be connected to GND or set in not connected.

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[Link] CSI Timing Characteristics

The CSI timing characteristics are compliant with MIPI CSI-2 Specification v2.1, MIPI D-PHY Specification v1.2, and
MIPI C-PHY Specification v1.2.

Table 3-77 MIPI D-PHY RX Electrical Characteristics

Description Min Typ Max Unit Note
High speed date rate 80 - 2500 Mbps
High speed common point voltage 70 - 330 mV
High speed differential input high voltage - - 40 mV
High speed differential input low voltage -40 - - mV
High speed single ended input high voltage - - 460 mV
High speed single ended input low voltage -40 - - mV
High speed differential input impedance 80 100 125 Ω
Low power logic 1 input voltage 740 - - mV
Low power logic 0 input voltage - - 550 mV
Low power input hysteresis 25 - - mV
Minimum pulse width response 20 - - ns

[Link] Block Diagram

Figure 3-86 shows the block diagram of the CSI modules. The CDPHY_TOP module is for DPHY and CPHY data reception.
The seninf controller is used for unpacking the MIPI stream into pixel data format by MIPI CSI2. The seninf_top_mux is
used for selecting pixel data generated by the CSI2 controller and transferring them to seninf_mux, and the seninf_mux
selects one group or test model signal and transfers the pixel data to seninf_cam_mux. Then, each seninf_cam_mux
selects the pixel data from one of the seninf_muxes. The buffer in the seninf_mux serves as a horizontal blanking
(temporal) buffer for pixel data, and ISP reads out one or more pixel data from the buffer during the horizontal period, so
the ISP clock frequency can be reduced. CKSYS, the Clock System, is used for generating proper clocks to external camera
sensor modules (MCLK).

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ISP_CK
seninf_top_mux seninf_cam_mux
PHY_CSI0_CK
seninf1 seninf_mux_1
Sensor0 clk domain Async FIFO BUFFER
MIPI
2D sensor CDPHY_TOP phy_seninf_mux_0
seninf2
MIPI seninf_mux_2 cam1
2D sensor
Async FIFO
BUFFER

PHY_CSI1_CK seninf3 seninf_mux_3

Sensor1 clk domain
Async FIFO
BUFFER
MIPI
4D sensor CDPHY_TOP phy_seninf_mux_1

seninf4 cam3
seninf_mux_4
Async FIFO
BUFFER

cam4
seninf_mux_5

BUFFER

cam5
seninf_mux_6

BUFFER
cam6

seninf_mux_7

BUFFER
cam7

seninf_mux_8

BUFFER
cam8
VC/DT group (1st)

cam9
seninf_mux*8 (buffer*8)

VC/DT group (2nd)

cam10

Figure 3-86 Block Diagram of CSI Modules (D-PHY and C-PHY mode)

[Link] Theory of Operations

The block diagram has one DPHY_TOP module, and it can connect with a 4D1C sensor. The seninf1 is responsible for
receiving data from sensor and de-packeting the MIPI byte data to pixel data. The seninf_top_mux module can switch
different groups to different seninf_muxes. Each seninf_mux has a buffer to store the pixel data generated from seninf.

[Link] Programming Guide

 CSI programming sequence

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Sensor
init

Load default setting

CSI reg setting :

Step1. Performance setting
Step2. Efuse Reading

4-Lane D-PHY
Cam Mode

Setting Lane enable

Setting clock mux & lane mux

Analog PHY powers off Setting phy_seninf_mux

Setting seninf

Setting seninf_top_mux

Setting seninf_mux

Setting seninf_cam_mux

Analog PHY power on sequence

MIPI Sensor
Streaming out

Normal Operation

Figure 3-87 CSI Programming Sequence

 CSI basic register setting

This part takes a basic register setting as an example to show that MIPI sensor data stream can pass through
seninf_top to ISP pass1. See the red thread in Figure 3-88.

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seninf_sen0_mclk
CKSYS

seninf_top seninf_cam_mux
seninf_top_mux
seninf_mux_1

Async FIFO BUFFER

MIPI phy_seninf_mux
sensor
CDPHY_TOP seninf1
_0
seninf_mux_2
cam1
Async FIFO BUFFER

seninf_mux_3

Async FIFO BUFFER

Figure 3-88 Seninf_top Basic Data Path (One Port)

 Load default setting

Table 3-78 Load Default Setting

Step Description Register Name Register Bit Field Bit Field Value Address

1 Set CSI Register Reset TOPRGUWDT_SWSYSRST camsys_rst 1’b1 0x10007018

2 Wait for 1 µs
3 Release CSI Register Reset TOPRGUWDT_SWSYSRST camsys_rst 1’b0 0x10007018

4 Set Seninf_top Clock On CAMSYS_CG_CON 1’b0 0x16000000

5 Set Seninf_top Reset CAMSYS_SW_RST seninf_top_sw_rst 2’b11 0x160000A0

6 Wait for 1 µs
7 Release Seninf_top Reset CAMSYS_SW_RST seninf_top_sw_rst 2’b00 0x160000A0

 Performance setting

Table 3-79 Performance Setting

Bit Field
Step Description Register Name Register Bit Field Address
Value
CSI0A CSI0A_CDPHY_RX_ANA_1 RG_CSI0A_BG_LPRX_VTL_SEL[2:0] 3’b100 0x11ED0004
1 performance CSI0A_CDPHY_RX_ANA_1 RG_CSI0A_BG_LPRX_VTH_SEL[2:0] 3’b100 0x11ED0004
setting CSI0A_CDPHY_RX_ANA_1 RG_CSI0A_BG_VREF_SEL[3:0] 4’b1000 0x11ED0004
CSI0B CSI0B_CDPHY_RX_ANA_1 RG_CSI0B_BG_LPRX_VTL_SEL[2:0] 3’b100 0x11ED1004
2 performance CSI0B_CDPHY_RX_ANA_1 RG_CSI0B_BG_LPRX_VTH_SEL[2:0] 3’b100 0x11ED1004
setting CSI0B_CDPHY_RX_ANA_1 RG_CSI0B_BG_VREF_SEL[3:0] 4’b1000 0x11ED1004

 eFuse reading
Read eFuse value according to eFuse map, and set the eFuse value to the corresponding registers.

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Table 3-80 eFuse Reading

Step Description Register Name Register Bit Field Bit Field Value Address
A_CSI_0 rg_csi0a_l0p_t0a_hsrt_code[4:0] 0x11F2018C[4:0] 0x11F2018C
A_CSI_0 rg_csi0a_l0n_t0b_hsrt_code[4:0] 0x11F2018C[9:5] 0x11F2018C
A_CSI_0 rg_csi0a_l1p_t0c_hsrt_code[4:0] 0x11F2018C[14:10] 0x11F2018C
A_CSI_0 rg_csi0a_l1n_t1a_hsrt_code[4:0] 0x11F2018C[19:15] 0x11F2018C
Read eFuse A_CSI_0 rg_csi0a_l2p_t1b_hsrt_code[4:0] 0x11F2018C[24:20] 0x11F2018C
1
value A_CSI_0 rg_csi0a_l2n_t1c_hsrt_code[4:0] 0x11F2018C[29:25] 0x11F2018C
A_CSI_1 rg_csi0b_l0p_t0a_hsrt_code[4:0] 0x11F20190[4:0] 0x11F20190
A_CSI_1 rg_csi0b_l0n_t0b_hsrt_code[4:0] 0x11F20190[9:5] 0x11F20190
A_CSI_1 rg_csi0b_l1p_t0c_hsrt_code[4:0] 0x11F20190[14:10] 0x11F20190
A_CSI_1 rg_csi0b_l1n_t1a_hsrt_code[4:0] 0x11F20190[19:15] 0x11F20190
CSI0A_CDPHY_RX_ANA_2 RG_CSI0A_L0P_T0A_HSRT_CODE[4:0] rg_csi0a_l0p_t0a_hsrt_code[4:0] 0x11ED0008
CSI0A
CSI0A_CDPHY_RX_ANA_2 RG_CSI0A_L0N_T0B_HSRT_CODE[4:0] rg_csi0a_l0n_t0b_hsrt_code[4:0] 0x11ED0008
termination
CSI0A_CDPHY_RX_ANA_3 RG_CSI0A_L1P_T0C_HSRT_CODE[4:0] rg_csi0a_l1p_t0c_hsrt_code[4:0] 0x11ED000C
2 control
CSI0A_CDPHY_RX_ANA_3 RG_CSI0A_L1N_T1A_HSRT_CODE[4:0] rg_csi0a_l1n_t1a_hsrt_code[4:0] 0x11ED000C
registers
CSI0A_CDPHY_RX_ANA_4 RG_CSI0A_L2P_T1B_HSRT_CODE[4:0] rg_csi0a_l2p_t1b_hsrt_code[4:0] 0x11ED0010
setting
CSI0A_CDPHY_RX_ANA_4 RG_CSI0A_L2N_T1C_HSRT_CODE[4:0] rg_csi0a_l2n_t1c_hsrt_code[4:0] 0x11ED0010
CSI0B CSI0B_CDPHY_RX_ANA_2 RG_CSI0B_L0P_T0A_HSRT_CODE[4:0] rg_csi0b_l0p_t0a_hsrt_code[4:0] 0x11ED1008
termination CSI0B_CDPHY_RX_ANA_2 RG_CSI0B_L0N_T0B_HSRT_CODE[4:0] rg_csi0b_l0n_t0b_hsrt_code[4:0] 0x11ED1008
3 control CSI0B_CDPHY_RX_ANA_3 RG_CSI0B_L1P_T0C_HSRT_CODE[4:0] rg_csi0b_l1p_t0c_hsrt_code[4:0] 0x11ED100C
registers
CSI0B_CDPHY_RX_ANA_3 RG_CSI0B_L1N_T1A_HSRT_CODE[4:0] rg_csi0b_l1n_t1a_hsrt_code[4:0] 0x11ED100C
setting

 4-lane DPHY cam mode

Table 3-81 4-Lane DPHY Cam Mode

Step Description Register Name Register Bit Field Bit Field Value Address
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_DPHY_L0_CKMODE_EN 1’b0 0x11ED0000
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_DPHY_L0_CKSEL 1’b1 0x11ED0000
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_DPHY_L1_CKMODE_EN 1’b0 0x11ED0000
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_DPHY_L1_CKSEL 1’b1 0x11ED0000
1 Data lane setting
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_DPHY_L0_CKMODE_EN 1’b0 0x11ED1000
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_DPHY_L0_CKSEL 1’b1 0x11ED1000
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_DPHY_L1_CKMODE_EN 1’b0 0x11ED1000
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_DPHY_L1_CKSEL 1’b1 0x11ED1000
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_DPHY_L2_CKMODE_EN 1’b1 0x11ED0000
2 Clock lane setting
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_DPHY_L2_CKSEL 1’b1 0x11ED0000

 Set lane enable

CSI 4D1C lane enable top programming outline

Table 3-82 4D1C Lane Enable Top Programming Outline

Step Description Register Name Register Bit Field Bit Field Value Address
1 Configure clock lane DPHY_RX_LANE_EN dphy_rx_lc0_en 1’b1 0x11ED2000
DPHY_RX_LANE_EN dphy_rx_lc1_en 1’b0 0x11ED2000
2 Set data lane enable DPHY_RX_LANE_EN dphy_rx_ld0_en 1’b1 0x11ED2000
DPHY_RX_LANE_EN dphy_rx_ld1_en 1’b1 0x11ED2000

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Step Description Register Name Register Bit Field Bit Field Value Address
DPHY_RX_LANE_EN dphy_rx_ld2_en 1’b1 0x11ED2000
DPHY_RX_LANE_EN dphy_rx_ld3_en 1’b1 0x11ED2000
3 Disable software reset DPHY_RX_LANE_EN dphy_rx_sw_rst 1’b0 0x11ED2000

 Set clock mux and lane mux

CSI 4D1C clock lane and data lane setting top programming outline

Table 3-83 4D1C Clock Lane and Data Lane Setting Top Programming Outline
Step Description Register Name Register Bit Field Bit Field Value Address
CK_DATA Mux
1 DPHY_RX_LANE_SELECT dphy_rx_ck_data_mux_en 1’b1 0x11ED2004
enable
Configure
2 DPHY_RX_LANE_SELECT rg_dphy_rx_lc0_sel 3’h2 0x11ED2004
clock lane
DPHY_RX_LANE_SELECT rg_dphy_rx_ld0_sel 3’h1 0x11ED2004
Set data lane DPHY_RX_LANE_SELECT rg_dphy_rx_ld1_sel 3’h3 0x11ED2004
3
enable DPHY_RX_LANE_SELECT rg_dphy_rx_ld2_sel 3’h0 0x11ED2004
DPHY_RX_LANE_SELECT rg_dphy_rx_ld3_sel 3’h4 0x11ED2004
DPHY_RX_CLOCK_LANE0_HS_PARAMETER rg_dphy_rx_lc0_hs_settle_parameter 8’h28 0x11ED2010
rg_cdphy_rx_ld0_trio0_hs_settle_para
DPHY_RX_DATA_LANE0_HS_PARAMETER 8’h28 0x11ED2020
meter
rg_cdphy_rx_ld1_trio1_hs_settle_para
Configure DPHY_RX_DATA_LANE1_HS_PARAMETER 8’h28 0x11ED2024
4 meter
settle time
rg_cdphy_rx_ld2_trio2_hs_settle_para
DPHY_RX_DATA_LANE2_HS_PARAMETER 8’h28 0x11ED2028
meter
rg_cdphy_rx_ld3_trio3_hs_settle_para
DPHY_RX_DATA_LANE3_HS_PARAMETER 8’h28 0x11ED202C
meter

 phy_seninf_mux_setting

Table 3-84 Phy_seninf_mux_0 Setting

Step Description Register Name Register Bit Field Bit Field Value Address
1 Enable seninf_top D-PHY mux 0 SENINF_TOP_PHY_CTRL_CSI0 phy_seninf_mux0_dphy_en 1’b1 0x16010060

 seninf setting

Table 3-85 Seninf1 Setting

Step Description Register Name Register Bit Field Bit Field Value Address
1 Enable CSI2 SENINF_CSI2_CTRL rg_seninf_csi2_en 1’b1 0x16010210
2 Enable seninf SENINF_CTRL seninf_en 1’b1 0x16010200
csi2_lane0_en
csi2_lane1_en
3 Enable CSI2 lane numbers SENINF_CSI2_EN 4’b1111 0x16010A00
csi2_lane2_en
csi2_lane3_en
4 Assert CSI2 software reset 1’b1
SENINF_CSI2_CTRL seninf_csi2_sw_rst 0x16010210
5 De-assert CSI2 software reset 1’b0

 seninf_top_mux setting

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Table 3-86 Seninf_top_mux Setting

Step Description Register Name Register Bit Field Bit Field Value Address

1 Seninf top mux 1 input source selection SENINF_TOP_MUX_CTRL_0 rg_seninf_mux1_src_sel 4’b0000 0x16010010

 seninf_mux_1 setting

Table 3-87 Seninf_mux_1 Setting

Step Description Register Name Register Bit Field Bit Field Value Address
1 Disable seninf mux 1 seninf_mux_en 1’b0
2 Assert seninf mux 1 software reset seninf_mux_sw_rst 1’b1
3 Assert seninf mux 1 IRQ software reset SENINF_MUX_CTRL_0 seninf_mux_irq_sw_rst 1’b1 0x16010D00
4 De-assert seninf mux 1 IRQ software reset seninf_mux_irq_sw_rst 1’b0
5 De-assert seninf mux 1 software reset seninf_mux_sw_rst 1’b0
6 Select seninf mux 1 input source SENINF_MUX_CTRL_1 rg_seninf_mux_src_sel 4’b1000 0x16010D04
7 Enable seninf mux 1 SENINF_MUX_CTRL_0 seninf_mux_en 1’b1 0x16010D00

 seninf_cam_mux setting

Table 3-88 Seninf_cam_mux Setting

Step Description Register Name Register Bit Field Bit Field Value Address
1 Enable seninf cam mux 0 seninf_cam_mux0_en 1’b1
2 Disable seninf cam mux 1 SENINF_CAM_MUX_EN seninf_cam_mux1_en 1’b0 0x16010410
3 Disable seninf cam mux 2 seninf_cam_mux2_en 1’b0

 Analog PHY power on sequence

Table 3-89 Analog Power-On Sequence

Step Description Register Name Register Bit Field Bit Field Value Address
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_BG_CORE_EN 1’b1 0x11ED0000
1 BG Core Enable
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_BG_CORE_EN 1’b1 0x11ED1000
2 Wait > 30 µs
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_BG_LPF_EN 1’b1 0x11ED0000
3 BG LPF Enable
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_BG_LPF_EN 1’b1 0x11ED1000

Figure 3-89 Power-On Sequence Timing

 Analog PHY powers off

Table 3-90 Analog Power-Off

Step Description Register Name Register Bit Field Bit Field Value Address
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_BG_CORE_EN 1’b0 0x11ED0000
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_BG_CORE_EN 1’b0 0x11ED1000
1 BG Core and LPF Disable
CSI0A_CDPHY_RX_ANA_0 RG_CSI0A_BG_LPF_EN 1’b0 0x11ED0000
CSI0B_CDPHY_RX_ANA_0 RG_CSI0B_BG_LPF_EN 1’b0 0x11ED1000

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[Link] External Sensor Clock Option

This section describes the master clock option for the image sensor. In most cases, the clock system of the external image
sensor module requires a reference clock source. There are 3 master clocks named CMMCLK0, CMMCLK1 and CMMCLK2.
The master clocks can be obtained from different clock sources that are not integrated in the CSI controller. The CKSYS
provides a variety of master clock options from internal clock system. The supported clock can be
6/12/13/19.2/24/26/48/52 MHz.

Table 3-91 CAM_CLK Pad Configuration

Pin Name Aux Func.0 Aux Func.1 Aux Func.2 Aux Func.3
CMMCLK0 B:GPIO 22 O:CMMCLK0
CMMCLK1 B:GPIO 23 O:CMMCLK1
CMMCLK2 B:GPIO 24 O:CMMCLK2
In GPIO Aux function 1, these pins are connected to their clock mux.

3.10 Video

3.10.1 Video Encoder (VENC)

[Link] Overview

This Video Encoder (VENC) is a mainstream video encoder. It consists of 2 video encoders: H.264 and HEVC. The
VENC is capable of encoding 4K video at 30 frames per second (FPS) with promising superior video quality for
H.264 and HEVC. Furthermore, it supports pixel bit-depth up to 8 bits. This design also supports various encoding
methods that satisfy basic requirements of easy software controllability. Furthermore, with advanced encoding
technology, it delivers astonishing high quality video while maintaining low memory bandwidth requirements. The
VENC also considers the usage of portable devices and provides several power saving capabilities.

[Link] Features
The VENC has the following main features:

 Uses DRAM as an input, output, and working buffer

 Reads input frame buffers, executes video encoding and writes encoded bit stream to the output buffer
 Support of YUV420 two-plane scan line (NV12/NV21) and YUV420 three-plane scan line (YV12/I420) color
spaces
 Support RGB and ARGB input formats.

Table 3-92 presents the supported video formats and their capabilities.

Table 3-92 VENC Supported Formats

Format Feature Details
Profile Main (8-bit)
H.264 Encoding Level L4.1
Speed 4K@30fps

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Format Feature Details

Profile Main (8-bit)
HEVC Encoding Level L4.1
Speed 4K@30fps

[Link] Block Diagram

Figure 3-90 shows a brief overview of the IP architecture and local on-chip-bus architecture. The interface for
controlling it consists of ARM APB and MediaTek proprietary SMI (Smart Multimedia Interface) bus. It reports a
hardware event through an interrupt or software polling. In addition, it adopts several SMI ports and one APB
port. The video encoder core includes the following modules: DMA, ME, MC, TQ, DB, and EC. The input to the
video encoder is image data. After the encoding process, the bitstream is sent to DRAM by the system bus.

System Bus

DMA

APB
ME VENC
CPU
DB
EC
MC Interrupt
TQ

Figure 3-90 Block Diagram of VENC

[Link] Function Description

The video encoder is configured by software through the APB interface. As the register is configured, the sequencer sends
the corresponding control signals to trigger sub-modules.

 DMA acquires and stores back the image data and bitstream from and to memory according to the configured
address.
 ME conducts motion estimation to decide motion vector for later encoding.
 MC conducts motion compensation to give predicted pixel values.
 TQ conducts transform and quantization operations and writes reconstructed pixels to DB and quantized transformed
coefficients to EC.
 DB conducts de-blocking operations and allows DMA to store back the processed frame as the next frame’s reference
frame.
 EC conducts entropy encoding, and the coding can be variable length code, context based arithmetic code, or context
based variable length code. The encoded bitstream is written to memory by DMA.

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3.10.2 Video Decoder (VDEC)

[Link] Overview
The Video Decoder (VDEC) accelerator is designed to provide multi-standard video decoding, relieving the Central
Processing Unit (CPU) load and providing high performance video. It receives a compressed video bitstream as
input, performs the decoding process, and then sends the reconstructed video to the display.

[Link] Features

 HEVC
 Main profile 4K2K @ 75fps/160 Mbps, 8 bits
 Main 10 profile 4K2K @ 75fps/160 Mbps, 10 bits
 HEIF
 Main profile maximum resolution 16383 × 16383, 8 bits
 Main10 profile maximum resolution 16383 × 16383, 10 bits
 VP9
 Profile 0 4K2K @ 75 fps/120 Mbps, 8 bits
 Profile 2 4K2K @ 75 fps/120 Mbps, 10 bits
 AV1
 Main profile 0 4K2K @ 75 fps/120 Mbps, 8/10 bits
 AVC
 Constrained Baseline 4K2K @ 75fps/160 Mbps, 8 bits
 Main/High profile 4K2K @ 75fps/160 Mbps, 8 bits
 High 10 profile 4K2K @ 75fps/160 Mbps, 10 bits
 MPEG-4
 Simple Profile 1080p @ 60 fps/60 Mbps, 8 bits
 Advanced Simple Profile 1080p @ 60 fps/60 Mbps, 8 bits
 MPEG-2
 Main profile 1080p @ 60 fps/60 Mbps, 8 bits
 VP8
 1080p @ 60 fps/40 Mbps, 8 bits
 H.263
 Baseline profile 1080p @ 60 fps/60 Mbps

3.11 Audio

3.11.1 Overview
The MediaTek audio system allows data exchange among the AP and external components. The following
interfaces are available.

 Two I2S/Time Division Multiplexing (TDM) outputs

 Two I2S/TDM inputs
 One High-Definition Multimedia Interface (HDMI™) TX output

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 One DisplayPort (DP) TX output

 One S/PDIF input
 One S/PDIF output
 One PCM interface with Sampling Rate Converter (SRC)
 One slave 8-channel I2S input (AUDIO IN)
 Four Pulse Density Modulation (PDM) interfaces for Digital Microphone Interface Controller (DMIC)
 One proprietary audio interface for the MediaTek PMIC codec (2-channel ADC and 2-channel DAC)

3.11.2 Features
 PMIC audio CODEC playing
 Supports 8/11.025/12/16/22.05/24/32/44.1/48/96/192 kHz sampling rate playing
 PMIC audio CODEC recording
 Supports 8/16/32/48/96/192 kHz sampling rate recording
 One master I2S output (I2SO1):
 2-channel I2S output. Sampling rates from 8 kHz to 192 kHz, up to 32 bits.
 16-channel TDM output. Sampling rates from 8 kHz to 48 kHz, up to 32 bits.
 One master or slave I2S output (I2SO2):
 8-channel I2S output. Sampling rates from 8 kHz to 192 kHz, up to 32 bits
 16-channel TDM output with 48 kHz sampling rate
 One master or slave I2S input (I2SIN):
 8-channel I2S input. Sampling rates from 8 kHz to 192 kHz and resolution up to 32 bits
 16-channel TDM input. Sampling rates from 8 kHz to 48 kHz, up to 32 bits, or 16-channel direct path to memory
 One master or slave TDM input (TDMIN):
 16-channel TDM output with 48 kHz sampling rate and bit resolution up to 32 bits
 2-channel I2S input. Sampling rates from 8 kHz to 192 kHz and resolution up to 32 bits
 One master 8-channel High-Definition Multimedia Interface (HDMI™) audio output (HDMITX):
 Sampling rates from 8 kHz to 192 kHz with a resolution of up to 32 bits
 8-channel DisplayPort™ audio output with sampling rates from 8 kHz to 192 kHz, up to 24 bits

 One S/PDIF input. Sampling rates include 32, 44.1, 48, 88.2, 96, 176.4, and 192 kHz
 One S/PDIF output with 32, 44.1, 48, 88.2, 96, and 192 kHz sampling rates
 One master or slave PCM interface with Sampling Rate Converter (SRC). Supported sampling rates: 8, 16, 32,
44.1, and 48 kHz with bit resolution up to 24 bits
 One slave 8-channel I2S input (AUDIO IN) with sampling rate from 8 kHz to 192 kHz with bit resolution up to
24 bits
 4 × Pulse Density Modulation (PDM) interfaces for up to 4 stereo Digital Microphones (DMICs). Support of
one-wire and two-wire modes with 8, 16, 32, and 48 kHz PCM sampling rates and 24 bits.
 A proprietary audio interface for PMIC CODEC
 2-channel DAC. Supports up to 192 kHz sampling rate
 2-channel ADC. Supports up to 192 kHz sampling rate
 Hardware gain function and general ASRC to enhance the audio quality and flexibility of mix engine. The flexible mix
engine system for data exchange between the interfaces without CPU intervention.
 2 × stereo hardware gain

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 12 × stereo general-purpose Asynchronous Sample Rate Converters (ASRC) for sampling rate conversion and slave
mode clock tracking
 4 × stereo memory-based ASRC
 32-channel channel merge
 5 × APLL can support up to 5 clock rates at the same time
 64KB internal audio SRAM
 Voice wakeup (in MediaTek PMIC codec)

3.11.3 Block Diagram

Figure 3-91 illustrates the flexibility of the mix engine between audio interfaces.

Device

DMIC1_DAT I2SO1_D[0-11]
2 × DMIC PDM1 I2SO1

DMIC2_DAT I2SO2_D[0-7]
2 × DMIC PDM2 I2SO2

DMIC3_DAT TDMIN_D
2 × DMIC PDM3 TDM IN

DMIC4_DAT I2SIN_D[0-3]
2 × DMIC PDM4 I2S IN

PCM_DO AUD_DATA_MOSI[0-1] PIMIC CODEC

Connectivity IC PCM_DI PCM PMIC DL

AUD_DATA_MISO[0-2] PIMIC CODEC

PMIC UL
Memory IF

SPDIF_OUT
SPDIF OUT

SPDIF_IN[0-1]
MPHONE_MULTI SPDIF IN
Top Bus

AHB

SPLIN_D[0-3]
MPHONE_MULTI2 I2S AUDIO IN

HDMITX
HDMITX

DP
DPTX

Figure 3-91 Audio Interfaces Block Diagram

3.11.4 Function Description

[Link] Inter-IC Sound (I2S)

[Link].1 I2S Signal Descriptions

Table 3-93 presents I2S signal descriptions.

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Table 3-93 I2S Signal Descriptions

Signal Name Type Description Ball Location
I2SIN
I2SIN_BCK DIO I2SIN serial bit clock M33, H36, H33, U10
I2SIN_D0 DI I2SIN serial data input 0 J37, J33, M34, Y7
I2SIN_D1 DI I2SIN serial data input 1 G33, G31, N33, Y8
I2SIN_D2 DI I2SIN serial data input 2 G32, G30, M30, W7
I2SIN_D3 DI I2SIN serial data input 3 H35, H32, M32, W3
I2SIN_MCK DIO I2SIN master clock H34, K30, Y10, G36
I2SIN_WS DIO I2SIN word select (left/right audio channel) J34, M35, Y6, J36
I2SO1
I2SO1_BCK DO I2SO1 serial bit clock W7, G1, AD10, H32, M35
I2SO1_D0 DO I2SO1 serial data output 0 N33, W8, E2, AB1, H35
I2SO1_MCK DO I2SO1 master clock Y8, G2, M33, G30, AD11
I2SO1_WS DO I2SO1 word select (left/right audio channel) F2, AB2, G32, M34, W3
I2SO2
I2SO2_BCK DIO I2SO2 serial bit clock AC9, U10, H33
I2SO2_D0 DO I2SO2 serial data output 0 AC4, Y7, J33
I2SO2_D1 DO I2SO2 serial data output 1 AB3, Y8, G31
I2SO2_D2 DO I2SO2 serial data output 2 AA8, W7, G30
I2SO2_D3 DO I2SO2 serial data output 3 AC8, W3, H32
I2SO2_MCK DO I2SO2 master clock Y10, H34, AB9
I2SO2_WS DIO I2SO2 word select (left/right audio channel) Y6, J34, AB8
SPLIN (I2S AUDIO IN)
SPLIN_BCK DI SPLIN serial bit clock J36
SPLIN_D0 DI SPLIN data 0 J37
SPLIN_D1 DI SPLIN data 1 G33
SPLIN_D2 DI SPLIN data 2 G32
SPLIN_D3 DI SPLIN data 3 H35
SPLIN_LRCK DI SPLIN word select H36
SPLIN_MCK DI SPLIN master clock G36

[Link].2 I2S Timing Characteristics

Table 3-94 and Figure 3-92 present timing characteristics for the I2S modules in the device.

Table 3-94 I2S Timing Characteristics

No. Parameter Description Min Typ Max Unit
- fS Sampling frequency 8 - 192 kHz
IIS01 fc_MCK Cycle time, MCK (master clock) - - 24.576 MHz

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No. Parameter Description Min Typ Max Unit

- fOP_BCK Operation frequency, BCK 32 × fS - 64 × fS MHz
IIS03 tc_BCK Cycle time, BCK 81.38 - 3906.25 ns
IIS04 tw_BCK_H Pulse duration, BCK high - 0.5 - 1/tc_BCK
IIS05 tw_BCK_L Pulse duration, BCK low - 0.5 - 1/tc_BCK
- tLRCK LRCK period 32 - 64 1/tc_BCK
IIS06 tv_LRCK BCK negative edge to LRCK valid - - 19 ns
IIS07 tv_DO BCK negative edge to DO valid - - 19 ns
IIS08 tsu Setup time, DI 19 - - ns
IIS10 th Hold time, DI 19 - - ns

IIS01
MCK

IIS03 IIS05 IIS04

BCK
IIS06

LRCK
IIS07
DO

IIS08 IIS10
DI

Figure 3-92 I2S Master Mode Timing Diagram

[Link] Pulse Code Modulation (PCM)

[Link].1 PCM Signal Descriptions

Table 3-95 presents PCM signal descriptions.

Table 3-95 PCM Signal Descriptions

Signal Name Type Description Ball Location
PCM_CLK DIO PCM clock G1, AD30
PCM_DI DI PCM data input E2, AB31
PCM_DO DO PCM data output AC30, F2
PCM_SYNC DIO PCM synchronization AC31, G2

[Link].2 PCM Timing Characteristics

Table 3-96, Figure 3-93, and Figure 3-94 present timing characteristics for the PCM interfaces in the device.

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Table 3-96 PCM Timing Characteristics

No. Parameter Description Min Typ Max Unit
- fS Sampling frequency 8 - 48 kHz
PCM1 fCLK Serial clock frequency 0.256 - 3.072 MHz
- tSYNC Sync period 32 - 64 1/fCLK
PCM2 tw_CLK_H Pulse duration, CLK high - 0.5 - 1/fCLK
PCM3 tw_CLK_L Pulse duration, CLK low - 0.5 - 1/fCLK
PCM4 td_CLK_SYNC Delay time, output CLK low to SYNC valid - - 78 ns
PCM5 td_CLK_TX Delay time, output CLK low to TX valid - - 78 ns
PCM6 tsu Setup time, RX master mode 78 - - ns
PCM7 th Hold time, RX master mode 78 - - ns
PCM8 tsu Setup time, RX slave mode 78 - - ns
PCM9 th Hold time, RX slave mode 78 - - ns

PCM1 PCM3 PCM2

CLK
PCM4

SYNC
PCM5
TX

PCM6 PCM7
RX

Figure 3-93 PCM Master Mode Timing Diagram

PCM3 PCM2

PCM8 PCM9
RX

PCM5
TX

Figure 3-94 PCM Slave Mode Timing Diagram

[Link] Time Division Multiplexed (TDM) Interface

[Link].1 TDM Signal Descriptions

Table 3-97 presents TDM signal descriptions.

Table 3-97 TDM Signal Descriptions

Signal Name Type Description Ball Location
TDMIN_BCK DIO TDM clock AD35, W5, T10, N31, G3, H35

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Signal Name Type Description Ball Location

TDMIN_DI DI TDM receive data input AD36, V5, T7, N34, G5, H32
TDMIN_LRCK DIO TDM word select (left/right audio channel) V4, T8, P30, E3, G30, AD37
TDMIN_MCK DIO TDM receive master clock T9, N30, G4, G32, AC35, W4

[Link].2 TDM Timing Characteristics

Table 3-98 and Figure 3-95 present timing characteristics for the TDM interfaces in the device.

Table 3-98 TDM Timing Characteristics

No. Parameter Description Min Typ Max Unit
- fS Sampling frequency 8 - 192 kHz
TDM1 fMCK Master clock frequency 0.768 - 49.152 MHz
TDM2 fBCK Serial clock frequency 0.256 - 49.152 MHz
TDM3 tw_BCK_H Pulse duration, BCK high - 0.5 - 1/fBCK
TDM4 tw_BCK_L Pulse duration, BCK low - 0.5 - 1/fBCK
TDM5 td_BCK_WS Delay time, output BCK low to WS valid - - 10 ns
TDM6 td_BCK_SDOUT Delay time, output BCK low to SDOUT valid - - 10 ns
TDM7 tsu_DI Setup time, DI 10 - - ns
TDM8 th_DI Hold time, DI 10 - - ns

TDM1
MCK

TDM2 TDM4 TDM3

BCK

TDM5
WS
TDM6
SDOUT

TDM7 TDM8
SDIN

Figure 3-95 TDM Master Mode Timing Diagram

[Link] Pulse Density Modulation (PDM)

[Link].1 PDM Timing Characteristics

Table 3-99 and Figure 3-96 present timing characteristics for the PDM interface in the device.

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Table 3-99 PDM Timing Characteristics

No. Parameter Description Min Typ Max Unit
- fCLK Operating frequency, PDM CLK 0.40625 - 3.25 MHz
PDM2 tW_CLK_H Pulse duration, CLK high - 0.5 - 1/fCLK
PDM3 tW_CLK_L Pulse duration, CLK low - 0.5 - 1/fCLK
PDM4 tSU_DAT Setup time, DAT 0.2 - - 1/fCLK
PDM5 tH_DAT Hold time, DAT 0.2 - - 1/fCLK

CLK
PDM2 PDM3

PDM4 PDM5

DAT

Figure 3-96 PDM Timing Diagram

[Link].2 Digital Microphone (DMIC)

[Link].3 DMIC Signal Descriptions

Table 3-100 presents DMIC signal descriptions.

Table 3-100 DMIC Signal Descriptions

Signal Name Type Description Ball Location
DMIC1_CLK DO DMIC1 clock AB9, W3, N30
DMIC1_DAT DI DMIC1 data in one-wire mode or data left AC9, W4, N31
DMIC1_DAT_R DI DMIC1 data right AB8, W5, P30
DMIC2_CLK DO DMIC2 clock V4, N34, AC4
DMIC2_DAT DI DMIC2 data in one-wire mode or data left P33, AB3, V5
DMIC2_DAT_R DI DMIC2 data right P35, AA8, W8
DMIC3_CLK DO DMIC3 clock V6, G33, AC8, Y10
DMIC3_DAT DI DMIC3 data in one-wire mode or data left U10, T11, G32, AB7
DMIC3_DAT_R DI DMIC3 data right Y6, V7, H35, AB6
DMIC4_CLK DO DMIC4 clock Y7, V8, H36, AB5
DMIC4_DAT DI DMIC4 data in one-wire mode or data left Y8, U7, J36, AC5
DMIC4_DAT_R DI DMIC4 data right AA5, W7, U8, J37

[Link] Digital Interface (SPDIF)

[Link].1 SPDIF Signal Descriptions

Table 3-101 presents SPDIF signal descriptions.

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Table 3-101 SPDIF Signal Descriptions

Signal Name Type Description Ball Location
SPDIF_IN0 DI SPDIF input 0 AD10, W3, D4, G36
SPDIF_IN1 DI SPDIF input 1 AB2, W7, D2, P33
SPDIF_IN2 DI SPDIF input 2 D1, P35, AB1, Y8
SPDIF_OUT DO SPDIF output W8, D3, G33, AD11

[Link] Power Management Integrated Circuit (PMIC)

[Link].1 PMIC Audio Interface Signal Descriptions

Table 3-102 presents PMIC audio interface signal descriptions.

Table 3-102 PMIC Audio Interface Signal Descriptions

Signal Name Type Description Ball Location
AUD_CLK_MOSI(1) DO PMIC CODEC clock master output M33
AUD_DAT_MISO0 DI PMIC CODEC data master input 0 M30
AUD_DAT_MISO1 DI PMIC CODEC data master input 1 M32
AUD_DAT_MOSI0 DO PMIC CODEC data master output 0 M34
AUD_DAT_MOSI1 DO PMIC CODEC data master output 1 N33
AUD_SYNC_MOSI DO PMIC CODEC sync master output M35
(1) These pins should be left unconnected when unused.

3.12 Connectivity

3.12.1 Inter-Integrated Circuit (I2C) and Improved I2C (I3C)

[Link] Overview

The I3C/I2C controller is a bi-directional, two-wire serial interface that utilizes Serial Clock Line (SCL) and Serial Data Line
(SDA) signals. These signals can be driven by either the master or the slave in both I2C and I3C, with the exception that SCL
is only driven by the master in I3C. This generic controller supports the master role and conforms to the I3C/I2C
specification.

[Link] Features

 Start, repeated start and stop conditions generation

 Bus detection
 Acknowledge bit generation and detection
 7-bit/10-bit addressing
 Clock stretching
 Active drive/wired-and I/O configuration

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 I2C four operating speeds:

 I2C Standard Mode (SM) with speed up to 100 kbit/s
 I2C Fast Mode (FM) with speed up to 400 kbit/s
 I2C Fast Mode Plus (FM+) with speed up to 1 Mbit/s
 I2C High Speed (HS) Mode with speed up to 3.4 Mbit/s
 Adjustable clock speed for SM/FM/FM+/HS mode operation
 I3C 12.5 MHz Single Data Rate (SDR) mode:
 Dynamic address assignment
 Private Write/Read transfer
 Broadcast Common Command Code (CCC)
 Directed CCC
 Multi-users
 FIFO mode and DMA mode
 Multiple transfer formats:
 Multi-write per transfer
 Multi-read per transfer
 Multi-transfer per transaction
 Combined format transfer with length change capability
 Combined format transfer with direction change capability
 Multi-transfer with repeated start condition

[Link] I2C/I3C Signal Descriptions

Table 3-103 presents I2C/I3C signal descriptions.

Table 3-103 I2C/I3C Signal Descriptions

Signal Name Type Description Ball Location
I3C5
SCL5 DIO I3C5 serial clock F5
SDA5 DIO I3C5 serial data F6
I3C6
SCL6 DIO I3C1 serial clock H7
SDA6 DIO I3C1 serial data G6
I2C0
SCL0 DIO I2C0 serial clock Y4
SDA0 DIO I2C0 serial data W6
I2C1
SCL1 DIO I2C1 serial clock M36
SDA1 DIO I2C1 serial data L36
I2C2
SCL2 DIO I2C2 serial clock Y2
SDA2 DIO I2C2 serial data AA2

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Signal Name Type Description Ball Location

I2C3
SCL3 DIO I2C3 serial clock W2
SDA3 DIO I2C3 serial data W1
I2C4
SCL4 DIO I2C4 serial clock K36
SDA4 DIO I2C4 serial data K37

[Link] Block Diagram

apb_reg

APB APB scl_out

scl_oe
Interface sda_out
sda_oe
FIFO Master Bus
scl_in
sda_in

Figure 3-97 Block Diagram of I3C/I2C

The I3C/I2C master controller is composed of several sub-modules, including:

 APB interface: Facilitates communication with the host side.

 FIFO: 16-byte storage depth
 apb_reg: APB register, configuration for other sub-modules.
 Master: Read and write control, state machine, timing control, etc.
 Bus: Monitors the bus behavior and data output.

The data flow direction differs in the following two scenarios:

 When the I3C/I2C master writes data to the slave, the data flow direction is:
APB interface  FIFO  Master  Bus  Slave

 When the I3C/I2C master reads data from the slave, the data flow direction is:
Slave  Bus  Master  FIFO  APB interface

[Link] Function Description

Figure 3-98 shows the wording conventions that are used subsequently.

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Master to slave direction A Acknowledge nA nonAcknowledge T T-bit(I3C only)

Slave to master direction A Acknowledge nA nonAcknowledge T T-bit(I3C only)

Direction Repeated Start

S Start condition R P Stop condition
depends on the CCC condition

Figure 3-98 I2C/I3C Function Description Wording Conventions

[Link].1 Start, Repeated Start and Stop Conditions

In both I2C and I3C protocols, transactions begin with a Start condition (S) and are terminated by a Stop condition (P).

Transaction Description
Start condition When bus is free, a high to low transition on the SDA line while SCL is high.
Repeated Start condition When bus is busy, a high to low transition on the SDA line while SCL is high.
Stop condition When bus is busy, a low to high transition on the SDA line while SCL is high.

[Link].2 Bus Detection

The I2C master is equipped to detect the bus status. Prior to controlling the bus to transfer data, the master initiates a
detection process. If the bus is busy, the master waits until a stop condition is detected.

[Link].3 I2C Clock Stretching

SCL1(Master drive)

SCL2(Slave drive)

SCL(Bus)

Figure 3-99 I2C Clock Stretching

In certain scenarios, the master may need to communicate with the slave, but the slave may not be ready to receive or
send data. This can occur when the internal FIFO of the slave is full or empty. In such cases, after the master pulls SCL low,
the slave actively and continuously pulls down the SCL, thus enabling clock stretching.

[Link].4 I2C Standard Mode (SM), Fast Mode (FM), and Fast Mode Plus (FM+)

Master Write

S Slave Address A DATA A P

Master Read

S Slave Address A DATA nA P

Figure 3-100 I2C Frame Format in SM/FM/FM+

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Figure 3-100 illustrates the basic transfer format utilized by the SM/FM/FM+ of I2C. A more complex transfer format is
described in Section [Link].

Initially, the master sends a start condition. Following this, the master sends the 7-bit static address of the I2C slave device
with which it intends to communicate. Once the slave responds to the addressing, the master sends or receives the data.
Upon completion of the data transfer, the master sends a stop condition, and the bus returns to the free state.

[Link].5 I2C High-Speed (HS) Mode

Master Write

S Master Code nA R Slave Address A DATA A P

Master Read

S Master Code nA R Slave Address A DATA nA P

Figure 3-101 I2C Write Frame Format in HS Mode

Figure 3-101 depicts the differences between the frame formats employed by the I2C HS mode and I2C SM/FM/FM+.
Notably, the I2C HS mode introduces a fixed master code (00001XXX) that broadcasts to all slaves supporting the HS mode,
allowing them to transition to high speed. The master then sends a repeat start condition signal followed by the same
frame format as in SM/FM/FM+.

[Link].6 I3C Single Data Rate (SDR) Mode

The I3C master supports the I3C Specification v1.0 SDR mode, including:

 Dynamic Address Assignment (DAA) (Section [Link].6.1)

 Private write/read (Section [Link].6.2)
 Broadcast CCC (Section [Link].6.3)
 Direct CCC (Section [Link].6.4)

[Link].6.1 Dynamic Address Assignment (DAA)

I3C Reserved Byte Broadcast CCC

S A T
7'h7E,RnW = 0 ENTDAA

I3C Reserved Byte Read 8 Bytes Data Assign 7-bit Dynamic A/

R A
7'h7E,RnW = 1 (48-bit ID,BCR,DCR) Address to slave , PAR nA

I3C Reserved Byte Read 8 Bytes Data Assign 7-bit Dynamic A/

R A
7'h7E,RnW = 1 (48-bit ID,BCR,DCR) Address to slave , PAR nA

I3C Reserved Byte

R nA P
7'h7E,RnW = 1

Figure 3-102 I3C Dynamic Address Assignment (DAA)

The procedure of DAA is employed to assign dynamic addresses to I3C slaves, as all I3C slaves must have a dynamic address
to complete data transfer.

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[Link].6.2 Private Write/Read

Master Write

I3C Reserved Byte

S A R I3C Slave Address A DATA T P
7'h7E,RnW = 0

Master Read
I3C Reserved Byte
S A R I3C Slave Address A DATA T P
7'h7E,RnW = 0

Figure 3-103 I3C SDR Private Write/Read

SDR private write/read is a basic communication mode similar to the I2C HS mode with the frame format shown in Figure
3-103, where 7E is the I3C reserved address to indicate that this message is an I3C message.

[Link].6.3 Broadcast CCC

I3C Reserved Byte

S A I3C Broadcast CCC T Data(optional) T P
7'h7E,RnW = 0

Figure 3-104 I3C SDR Broadcast CCC

The I3C master controller supports broadcast CCC (command codes 0x00 to 0x7F) to write to all I3C slaves on the I3C bus.

[Link].6.4 Direct CCC

I3C Reserved Byte

S A I3C Directed CCC T
7'h7E,RnW = 0

R I3C Slave Address A Data T P

Figure 3-105 I3C SDR direct CCC

The master controller supports direct CCC (command codes 0x80 to 0xFE) to the specific I3C slave on the I3C Bus.

[Link] Interrupts

Table 3-104 I3C/I2C Interrupt Control Bits and Interrupt Factors

Interrupt Type Interrupt Enable Bit Interrupt Identification Interrupt Factors
After transmission is completed, the
Transmit MAS_TRANSAC_COMP TRANSAC_COMP
interrupt will be generated.
Communication When the slave sends no ack, the
MAS_ACKERR ACKERR
Error interrupt will be generated.
This status is asserted if HS master code
Communication
MAS_ HS_NACKERR HS_NACKERR NACK (Negative Ack.) error detection is
Error
enabled.
Enhancement When the I2C controller loses arbitration,
MAS_ARB_LOST ARB_LOST
Feature the interrupt is generated.

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Interrupt Type Interrupt Enable Bit Interrupt Identification Interrupt Factors

In multiple read/write with rs_stop
Enhancement transfer mode, this status is asserted
MAS_RS_MULTIPLE RS_MULTIPLE
Feature when a transfer has completed
successfully.
Enhancement This status is asserted if the I2C bus time-
MAS_TIMEOUT TIMEOUT
Feature out occurs.
Enhancement This status is asserted if the DMA hand-
MAS_ DMA_ERR DMA_ERR
Feature shake error has occurred.

[Link] Theory of Operations

[Link].1 Multi-User

Figure 3-106 Multi-user of I3C/I2C

The I3C/I2C master supports the multi-user function, enabling multiple hosts (including CCU (Camera Control Unit), AP,
SCP, etc.) to poll to control the I3C/I2C master, as illustrated in Figure 3-106. In case of using AP/SCP multi-user, it is advised
to use the FIFO mode on the non-XPU side. Moreover, if the AP multi-user is employed, the IRQ of the AP's I3C/I2C channel
2 can only be sent to the AP and CCU, and not to the SCP.

[Link].2 FIFO Mode

The I3C/I2C master controller offers a FIFO mode. Along with the slave address register, the controller integrates a 16-byte
deep FIFO. This feature enables the AP to prepare up to 16 bytes of data for a write transfer or read up to 16 bytes of data
for a read transfer.

[Link].3 DMA Mode

The AP_DMA facilitates communication between the I2C master controller and the system. To enable efficient data
transfer, configuration of the DMA settings is necessary in advance. These settings include the target memory address and
the TX/RX transfer direction and transfer length, in addition to the slave address register.

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[Link] Supported Transfer Formats

The I3C/I2C master controller is designed to be generic to support a wide range of devices that may utilize different
combinations of transfer formats. The supported formats and examples are described in the following sections.

Wording conventions:
Word Description
Transfer Anything encapsulated within a START and STOP or repeated START.
Number of bytes within the transfer (TRANSFER_LEN (I2Cn Base address +
Transfer length
0x14)/TRANSFER_LEN_AUX (I2Cn Base address + 0x6C)).
Transaction The top unit. Everything combined equals 1 transaction.
Transaction length Number of transfers to be conducted (TRANSAC_LEN (I2Cn Base address + 0x18)).

[Link].1 Single-Byte Access

The I2C master writes 1-byte data to the I2C slave or reads 1-byte data from it. The I3C master is compatible with this
transfer format.

Single Byte Write

S Slave Address A DATA A P

Single Byte Read

S Slave Address A DATA nA P

Figure 3-107 I2C/I3C Single-Byte Access

[Link].2 Multi-Byte Access

The I2C master writes N-byte data to the I2C slave or reads N-byte data from it. The I3C master is compatible with this
transfer format.

 DIR_CHANGE(I2Cn Base address + 0x10)[4] = 0

 TRANSAC_LEN(I2Cn Base address + 0x18) = 1
 TRANSFER_LEN (I2Cn Base address + 0x14) = N (N ≥ 1)

Multi Byte Write

S Slave Address A DATA A P

N (Bytes + Ack)
Multi Byte Read
A/
S Slave Address A DATA P
nA

N (Bytes + Ack/nAck)

Figure 3-108 I2C/I3C Single-Byte Access

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[Link].3 Combined Write/Read with Repeated START (Direction Changed)

The I2C master first writes N-byte data to the I2C slave. After a repeated START condition, the I2C master reads M-byte
data from the I2C slave. The I3C master is compatible with this transfer format. Note that only the “read after write
sequence” is supported; the “write after read sequence” is not supported.

 DIR_CHANGE(I2Cn Base address + 0x10)[4] = 1

 TRANSAC_LEN(I2Cn Base address + 0x18) = 2
 TRANSFER_LEN(I2Cn Base address + 0x14) = N (N ≥ 1)
 TRANSFER_LEN_AUX(I2Cn Base address + 0x6C) = M (M ≥ 1)
 RS_STOP(I2Cn Base address + 0x10)[1] = 1

Transaction (TRANSAC_LEN=2)

Combined Multi Byte Write + Multi Byte Read + Repeated Start

Slave Address Slave Address A/

S A DATA A R A DATA P
RnW=0 RnW=1 nA

N (Bytes + Ack) M(Bytes + Ack/nAck)

TRANSFER_LEN TRANSFER_LEN_AUX

Figure 3-109 Combined Write/Read with Repeated START (Direction Changed)

[Link].4 Transfer Length Change after First Transfer Completion (No Direction Changed)

Under the condition of changing the transfer length without changing the transfer direction in the write/read mode, the
I2C master first writes N-byte data to the I2C slave. After a repeated START condition, the I2C master writes/reads M-byte
data to the I2C slave. The I3C master is compatible with this transfer format.

 DIR_CHANGE(I2Cn Base address + 0x10)[4] = 0

 TRANSFER_LEN_CHANGE(I2Cn Base address + 0x10)[6] = 1
 TRANSAC_LEN(I2Cn Base address + 0x18) = 2
 TRANSFER_LEN(I2Cn Base address + 0x14) = N (N ≥ 1)
 TRANSFER_LEN_AUX(I2Cn Base address + 0x6C) = M (M ≥ 1)
 RS_STOP(I2Cn Base address + 0x10)[1] = 1

Figure 3-110 Change Transfer Length in Write/Read Mode (No Direction Change)

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[Link].5 Repeated START for Multiple Transfers

When the I2C master performs X transfers, between each two transfers, it is in the pause state and issues an interrupt. At
this time, software can change the length, slave address and direction of the next transfer and then restart the transfer.
The I3C master is compatible with this transfer format. Note that this function is only supported in the FIFO mode.

 TRANSAC_LEN(I2Cn Base address + 0x18) = X (X ≥ 1)

 TRANSFER_LEN(I2Cn Base address + 0x14) = N (N ≥ 1)
 RS_STOP(I2Cn Base address + 0x10)[1] = 1
 RS_STOP_MULTIPLE_CONFIG(I2Cn Base address + 0x24)[15] = 1
 RS_STOP_MULTIPLE_CONFIG(I2Cn Base address + 0x24)[15] = 0 before last transfer

Figure 3-111 Repeated START Multiple Transfers (Write/Read Mode)

[Link] AC Timing

Table 3-105, Figure 3-112, Table 3-106, and Figure 3-113 present timing characteristics for the I2C interfaces in in SS/FS/FS+
modes.

Table 3-105 I2C AC Timing Parameters for Standard, Fast, and Fast-mode Plus
Standard-mode Fast-mode Fast-mode Plus
Symbol Parameter Unit Remark
Min Max Min Max Min Max
Serial Clock Line (SCL)
fSCL 0 100 0 400 0 1000 kHz -
clock frequency
Hold time (repeated)
tHD;STA 4.0 - 0.6 - 0.26 - µs -
START condition
LOW period of the SCL
tLOW 4.7 - 1.3 - 0.5 - µs -
clock
HIGH period of the SCL
tHIGH 4.0 - 0.6 - 0.26 - µs -
clock
Set-up time for a
tSU;STA repeated START 4.7 - 0.6 - 0.26 - µs -
condition

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Standard-mode Fast-mode Fast-mode Plus

Symbol Parameter Unit Remark
Min Max Min Max Min Max
I2C-bus
tHD;DAT Data hold time 5.0 - 0 - 0 - µs
devices

tSU;DAT Data set-up time 250 - 100 - 50 - ns -

Rise time of both SDA

tr - 1000 20 300 - 120 ns -
and SCL signals
Fall time of both SDA 20x 20x VDD is I2C IO
tf - 300 300 120 ns
and SCL signals (VDD/5.5V) (VDD/5.5V) voltage
Set-up time for STOP
tSU;STO 4.0 - 0.6 - 0.26 - ns -
condition
tVD;DAT Data valid time - 3.45 - 0.9 - 0.45 µs -
Data valid acknowledge
tVD;ACK - 3.45 - 0.9 - 0.45 µs -
time

Figure 3-112 I2C AC Timing Diagram of F/S Mode

Table 3-106 I2C AC Timing Parameters for HS Mode

Cb = 100 pF (max) Cb = 400 pF
Symbol Parameter Unit Note
Min Max Min Max
fSCL SCL clock frequency 0 3.4 0 1.7 MHz -
Set-up time (repeated) START -
tSU;STA 160 - 160 - ns
condition

tHD;STA Hold time (repeated) START condition 160 - 160 - ns -

tLOW LOW period of the SCL clock 160 - 320 - ns -

tHIGH HIGH period of the SCL clock 60 - 120 - ns -
tHD;DAT Data hold time 0 70 0 150 ns I2C-bus devices

tSU;DAT Data set-up time 10 - 10 - ns -

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Cb = 100 pF (max) Cb = 400 pF

Symbol Parameter Unit Note
Min Max Min Max

tr Rise time of SCLH signal 10 40 20 80 ns -

tf Fall time of SCLH signal 10 40 20 80 ns

tSU;STO Set-up time for STOP condition 160 - 160 - ns -

Figure 3-113 I2C AC Timing Diagram of HS Mode

For the I3C AC timing of the SDR mode, please refer to the MIPI I3C specification.

[Link] Programming Guide

Start

Clear interrupt

SCL frequency
configuration

Transaction
configuration

Trigger start

Wait for interrupt

End

Figure 3-114 Programming Flow of I3C/I2C

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Figure 3-114 shows the programming workflow of the I3C/I2C master. To initiate transmission of register data to the
master, the AP must first clear the interrupt and then configure the frequency division factor of the SCL to correspond to
the low and high speeds (for the I2C HS mode or the I3C SDR mode). Then, the AP configures relevant registers for
transmission such as the slave address, transfer length, and transaction length. The transmission is then triggered by the
Start register. Upon completion of the transfer or in the event of an error, an interrupt is generated, which should be
cleared after the transmission is completed correctly or an error occurs.

3.12.2 Universal Asynchronous Receiver/Transmitter (UART)

[Link] Overview

The Universal Asynchronous Receiver/Transmitter (UART) is a full duplex serial communication channel between the chip
and external devices. It is designed to be compatible with a range of standard software drivers and offer M16C450 and
M16550A modes.

The UART supports word lengths from 5 to 8 bits, an optional parity bit, and one or two stop bits, all of which are fully
programmable via the CPU interface. Additionally, the UART includes:

 A 16-bit programmable baud rate generator

 An 8-bit scratch register
 Modem CTS (Clear to Send) and RTS (Request to Send) control lines
 A diagnostic loopback mode

Furthermore, the UART is equipped with two Direct Memory Access (DMA) handshake lines for indicating when the FIFOs
are ready to transfer data to the CPU and can generate interrupts from any of these sources.

After the hardware reset, the UART is in the M16C450 mode; however, it can be enabled to enter the M16550A mode,
which adds more advanced functions. These extensions are individually selectable via software control.

[Link] Features

 Provides 4 channels of UARTs

 UART1 and UART2 are 4-pin (TX, RX, CTS, RTS), while UART0 and UART3 are 2-pin channels (TX and RX) UART channels.
 Supports both M16C450 and M16550A operation modes
 Compatible with standard software drivers
 Transfer system: Asynchronous
 Data length: 5 to 8 bits
 Stop bits: 1 or 2
 Programmable parity (even, odd, and no parity)
 Hardware flow control: CTS/RTS-based automatic transmission and reception control
 Software flow control: Uses special characters, XON and XOFF for software flow control
 Baud rate programmable up to 3 Mbps
 Baud rate error: Less than 0.25%
 Baud rate accuracy compensation
 Interrupt request: Receive interrupts/transmit interrupts

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 Maskable interrupts
 Two independent 32-depth FIFOs for transmit and receive
 Data transfer: Supports DMA (Transmit/Receive) transfer
 Escape character sequence detection

[Link] Block Diagram

Baud Rate
Generator

Clock
uart_tx
TX Machine
TX FIFO

APB APB RX FIFO uart_rx

Interface RX Machine

uart_rts
Hardware
uart_cts
Flow Control

Figure 3-115 Block Diagram of UART

The figure above depicts the block diagram of UART, which consists of

 First In First Out (FIFO)

 Finite State Machine (FSM)
 Advanced Peripheral Bus (APB) interface
 Modem control

The UART supports full-duplex serial communication through its TX and RX channels, each of which contains an FSM (TX
FSM or RX FSM) and a 32-byte FIFO (TX FIFO or RX FIFO). The FSM indicates the current transfer stage of the TX or RX
channel, while the FIFOs store the data to be sent or received. The APB interface allows the system to:

 Access the configuration and status registers of UART

 Read the received data or write the data to be sent

The modem control enables the UART to support the hardware flow control.

[Link] Function Description

[Link].1 Signals

[Link].1.1 External Signals

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Table 3-107 External Signals Descriptions

Signal Name Type Description Ball Location
UART0
URXD0 DI UART0 receive data U3
UTXD0 DO UART0 transmit data U2
UART1
URXD1 DI UART1 receive data U10, G3, V2, R33, AC6
UTXD1 DO UART1 transmit data Y10, G4, V1, R34, AA6
UCTS1 DI UART1 clear to send (active low) Y7, G5, U5, P31, AD10
URTS1 DO UART1 request to send (active low) Y6, E3, U4, T33, AD11
UART2
URXD2 DI UART2 receive data U5, G1, P31, AB5
UTXD2 DO UART2 transmit data U4, G2, T33, AB6
UCTS2 DI UART2 clear to send (active low) V2, E2, R33, AA5
URTS2 DO UART2 request to send (active low) V1, F2, R34, AC5
UART3
URXD3 DI UART3 receive data AA35, U8, R30, H32, AB1
UTXD3 DO UART3 transmit data AB32, U7, P32, G30, AB2

[Link].1.2 Internal Signals

[Link].1.3 Clock

The UART has two clock input ports: Peripheral Clock (PCLK) and Baud Clock (BCLK).

 The PCLK is the APB clock with its frequency determined by the APB.
 The BCLK is the UART function clock with two levels of clock sources available for the UART to select the
adapted clock frequency, allowing flexible implementation of multiple UARTs.

[Link].1.4 Reset

The UART features one asynchronous reset input port, which can be triggered by the hardware reset, power reset,
or software reset bit, which can reset the initial values of all UART registers, FIFOs, and state machines.

[Link].1.5 Advanced Peripheral Bus (APB)

The UART is connected to the APB as an APB slave, allowing all UART registers to be programmed or read via the APB.

 Data transmitted to the outside via the TX FIFO can be written by the APB.
 Data received from the outside can be read from the APB via the RX FIFO.

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[Link].1.6 Direct Memory Access (DMA)

Table 3-108 DMA Signal Descriptions

Signal Name Signal Type Description
tx_dmareq Output TX DMA request signal to DMA for transmission data.
tx_dmaack Input TX DMA acknowledge from DMA for transmission data
rx_dmareq Output RX DMA request signal to DMA for received data.
rx_dmaack Input RX DMA acknowledge from DMA for received data

[Link].1.7 Interrupt

When there is an output interrupt request, poll the UART interrupt identification register for more information
about the interrupt, as described in Section [Link].4.

[Link].2 Communication Protocol

 The 1-bit start bit must be low.

 The data bit length is 5 to 8 bits.
 The parity check can be odd or even.
 The stop bit is 1 to 2 bit(s) long and must be high.

start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity bit stop bit stop bit

Figure 3-116 UART Communication Protocol

[Link].3 Clock Requirement

This section describes the clocks and special clocking requirements of the UART. For the definitions of PCLK and
BCLK, please refer to Section [Link].1.3.

 The PCLK is primarily used for programing registers and also plays the roles below. The PCLK must be always running
when the UART is in use.
 The write clock of a TX FIFO
 The read clock of an RX FIFO
 Synchronization of FIFO.
 The BCLK is used for all state machines, writing RX FIFOs, and reading TX FIFOs. The BCLK must always be running
when the UART is in use. To ensure a fixed baud rate when transmitting or receiving data, the BCLK must be kept in
one clock source.

Note that for the 16x oversampling of input characters, the BCLK frequency is preferably greater than or equal to 16x the
request baud rate. There is no special requirement for the PCLK.

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[Link].4 Interrupt Definition

The UART generates several types of interrupts, as detailed in Table 3-109 and Table 3-110.

Table 3-109 UART Interrupt Control Bits and Interrupt Factors

UARTn+0004h Interrupt Enable Register UARTn_IER
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CTSI RTSI XOFFI EDSSI ELSI ETBEI ERBFI
Type R/W
Reset 0
IER[3:0] are modified when LCR[7] = 0.
IER[7:4] are modified when LCR[7] = 0&EFR[4] = 1.

UARTn+0008h Interrupt Identification Register UARTn_IIR

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FIFOE ID4 ID3 ID2 ID1 ID0 NINT
Type RO
Reset 0 0 0 0 0 0 0 1
ID4 and ID3 are presented only when EFR[4] = 1.

Table 3-110 UART Interrupt Types

Interrupt
Interrupt Request Bit
Interrupt Type Identification Interrupt Factor Notes
(UARTn_IER)
(UARTn_IIR)
The RX buffer contains
ERBFI IIR[5:0] = 000100b -
data.
Received
Timeout on the character
- IIR[5:0] = 001100b -
in the RX FIFO
The TX holding register is
empty, or the contents of
Transmit ETBEI IIR[5:0] = 000010b the TX FIFO have been -
reduced to the trigger
level.
If a frame error, parity
For the detailed
error, break interrupt, or
Communication Error ELSI IIR[5:0] = 000110b interrupt status,
FIFO overrun happens,
refer to LSR[4:1].
the interrupt occurs.
For the detailed
Modem EDSSI IIR[5:0] = 000000b Modem status change interrupt status,
refer to MSR[4:1].
If a rising edge is
Enhancement Available when
CTSI IIR[5:0] = 100000b detected on the CTS, the
Feature the enhanced
interrupt occurs.

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Interrupt
Interrupt Request Bit
Interrupt Type Identification Interrupt Factor Notes
(UARTn_IER)
(UARTn_IIR)
If a rising edge is feature is
RTSI IIR[5:0] = 100000b detected on the RTS, the enabled.
interrupt occurs. (EFR[4] = 1)
When an XOFF character
XOFF1 IIR[5:0] = 010000b is received, the interrupt
occurs.

[Link].5 Enhancement Features

The UART provides more enhanced features than the industry-standard 16550. This includes hardware flow control,
software flow control, and the escape function.

[Link].5.1 Hardware Flow Control

The hardware flow control uses two dedicated signals, Clear to Send (CTS) and Request to Send (RTS) signals, to indicate
whether the UART is ready to receive data or send data.

This feature is highly advantageous in embedded applications where the Interrupt Service Routine (ISR) latency is difficult
to predict and control. The MCU is relieved from the requirement of fetching the received data within a fixed amount of
time.

Table 3-111 CTS and RTS Signals Behaviors

Signal Status Description
CTS Low The UART can start to transmit data.
CTS Active The UART is not allowed to transmit data.
RTS Low The UART FIFO in the received circuit is sufficient to receive data.
RTS High The UART is not allowed to receive data.

[Link].5.2 Software Flow Control

The software flow control uses special programmable characters, XON and XOFF, to handle the flow of data. When XOFF is
received, the UART transmission is halted and does not resume until XON is received.

Note:
 To enable any of the enhancement features, the enhanced mode bit EFR[4] must be set. If it is not set, IER[7:5], FCR[5:4], and
MCR[7:6] cannot be written, ensuring the UART is backward compatible with software written for 16C450 and 16550A devices.
 When the oversampling ratio between the UART clock and baud rate is less than 8, it is necessary to enable the guard time function
of the UART TX device to ensure the MediaTek UART RX works properly. Otherwise, frame errors could occur and the received data
could get corrupted.

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[Link].5.3 Escape Function

The Escape function can be enabled by configuring ESCAPE_EN and ESCAPE_DAT for the software flow control. The normal
character sent in the TX FIFO is escaped to its inverse code if it matches XON/XOFF/ESCAPE_DAT and the transmit state
machine sends ESCAPE_DAT before the inverse code. When the receive state machine receives the ESCAPE_DAT character,
it abandons the character and escapes the next character to its inverse code before saving it to the RX FIFO.

[Link] Theory of Operations

[Link].1 Register Remap

Table 3-112 UART Register Map

Address Name Description
UART_BASE+0x0C LCR Line Control Register (LCR)
UART_BASE+0x24 HIGHSPEED HIGH SPEED UART
UART_BASE+0x28 SAMPLE_COUNT SAMPLE_COUNT
UART_BASE+0x2C SAMPLE_POINT SAMPLE_POINT
UART_BASE+0x34 RATEFIX_AD Rate Fix Address
UART_BASE+0x3C GUARD Guard Time Added Register
UART_BASE+0x40 ESCAPE_DAT Escape Character register
UART_BASE+0x44 ESCAPE_EN Escape Enable Register
UART_BASE+0x48 SLEEP_EN Sleep Enable Register
UART_BASE+0x4C DMA_EN DMA Enable Register
UART_BASE+0x50 RXTRI_AD RX Trigger Address
UART_BASE+0x54 FRACDIV_L Fractional Divider LSB Address
UART_BASE+0x58 FRACDIV_M Fractional Divider MSB Address
UART_BASE+0x5C FCR_RD FIFO Control Register
UART_BASE+0x88 RTO_CFG Rx Time Out Configuration Register
UART_BASE+0XB4 SLEEP_REQ UART Sleep Request Register
UART_BASE+0xB8 SLEEP_ACK UART Sleep Acknowledge Register

Table 3-113 UART Register Remap

Address Name Description Name Description
Condition: LCR[7] == 0 Condition: LCR[7] == 1
UART_BASE+0x00 THR TX Holding Register/ DLL Divisor Latch (LS)
RBR RX Buffer Register
UART_BASE+0x04 IER Interrupt Enable DLM Divisor Latch (MS)
Register
Condition: LCR != 0xBF Condition: LCR == 0xBF
UART_BASE+0x08 FCR FIFO Control Register/ EFR Enhanced Feature
IIR Interrupt Identification Register
Register

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Address Name Description Name Description

UART_BASE+0x10 MCR Modem Control XON1 XON1
Register
UART_BASE+0x14 LSR Line Status Register XON2 XON2
UART_BASE+0x18 MSR Modem Status Register XOFF1 XOFF1
UART_BASE+0x1C SCR Scratch Register XOFF2 XOFF2

[Link].2 Baud Rate Generation

The DLL (Divisor Latch LS (Least Significant Bit)) and DLM (Divisor Latch MS (Most Significant Bit)) act as clock dividers to
obtain the required baud rate based on the BCLK frequency.

UARTn+0000h Divisor Latch (LS) UARTn_DLL

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLL[7:0]
Type R/W
Reset 1

UARTn+0004h Divisor Latch (MS) UARTn_DLM

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name DLM[7:0]
Type R/W
Reset 0

Note:
 The DLL and DLM can only be updated if LCR[7] is set (“1”). Note that the division by 1 generates a BAUD signal that is constantly
high. The example below shows the divider that needs to generate a given baud rate from the clock inputs of 26 MHz.

When clock source = 26 MHz and baud rate = 4800 bps

If HIGHSPEED (0x24) = 0: 26 MHz/4800/16 ~= 339 = 0x153  DLM: 0x01, DLL: 0x53
If HIGHSPEED (0x24) = 1: 26 MHz/4800/8 ~= 677 = 0x2A3  DLM: 0x02, DLL: 0xA3
If HIGHSPEED (0x24) = 2: 26 MHz/4800/4 ~= 1354 = 0x54A  DLM: 0x05, DLL: 0x4A
If HIGHSPEED (0x24) = 3: 26 MHz/4800/256 + 1 ~= 22 = 0x16  DLM: 0x00, DLL: 0x16

UARTn+0024h HIGH SPEED UART UARTn_HIGHSPEED

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SPEED [1:0]
Type R/W
Reset 0

Note:
SPEED UART sample counter base
0: Based on 16*baud_pulse, baud_rate = system clock frequency/16/{DLM, DLL}
1: Based on 8*baud_pulse, baud_rate = system clock frequency/8/{DLM, DLL}
2: Based on 4*baud_pulse, baud_rate = system clock frequency/4/{DLM, DLL}

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3: Based on sample_count * baud_pulse, baud_rate = system clock frequency/(sample_count+1)/{DLM, DLL}

UARTn+0028h SAMPLE_COUNT UARTn_SAMPLE_COUNT

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLECOUNT [7:0]
Type R/W
Reset 0

Note:
When HIGHSPEED = 3, the sample_count is the threshold value for the UART sample counter (sample_num).
Sample Count = clock source/baud rate/{DLM. DLL} - 1
For example, clock source: 26 MHz, baud rate: 4800 bps; DLM: 0x00, DLL: 0x16
If High Speed (0x24) = 0, 1 or 2: Unnecessary to set SAMPLE_COUNT
If High Speed (0x24) = 3: 26 MHz/4800/0x16 - 1 ~= 245  SAMPLE_COUNT = 245

UARTn+002Ch SAMPLE_POINT UARTn_SAMPLE_POINT

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name SAMPLEPOINT [7:0]
Type R/W
Reset 8'hff

Note:
If HIGHSPEED = 3, UART gets the input data when sample_count = sample_num.
The SAMPLE_POINT is usually ROUNDDOWN ((SAMPLE_COUNT+1)/2 - 1).
For example, if the clock source = 26 MHz, the baud rate = 4800 bps,
DLL: 0x00, and DLL: 0x16&SAMPLE_COUNT = 245
SAMPLE_POINT = ROUNDDOWN ((245+1)/2 – 1) = 122 (sample the central point to decrease inaccuracy)

[Link].3 Accuracy Compensation

FRACDIV_L and FRACDIV_M act as baud rate accuracy compensation factors to reduce baud rate errors.

UARTn+0054h Fractional Divider LSB Address UARTn_FRACDIV_L

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FRACDIV_L
Type R/W
Reset 0 0 0 0 0 0 0 0

Note:
 FRACDIV_L: Add sampling count (+1) from state data7 to state data0 in order to improve fractional divisor.

UARTn+0058h Fractional Divider MSB Address UARTn_FRACDIV_M

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name FRACDIV_M
Type R/W
Reset 0 0

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Note:
 FRACDIV_M: Add sampling count in the stop state and the parity state to improve the fractional dividers.
 FRACDIV_L/FRACDIV_M: Add one sampling period to each symbol to increase baud rate accuracy.

bit_extend register = FRACDIV_L[7:0]

FRACDIV_M[1:0]

Start d0 d1 d2 d3 d4 d5 d6 d7 Parity Stop

n n+L[0] n+L[1] n+L[2] n+L[3] n+L[4] n+L[5] n+L[6] n+L[7] n+M[0] n+M[1]

Bit extend number = ROUND ((clock source/baud rate/{DLM. DLL} – (SAMPLE_COUNT + 1))*10)
For example, if the clock source = 26 MHz, the baud rate = 4800 bps;
DLM: 0x00, DLL: 0x16, and SAMPLE_COUNT = 245.
Bit extend number = ROUND ((26 MHz/4800/0x16 – (245+1))*10) = 2
Therefore, it should compensate for 2 bits of one frame (e.g. FRACDIV_L = 0x44, FRACDIV_M = 0x00).
Refer to Table 3-114 for more details.

Table 3-114 Bit Extension Number Reference

Bit Extension Number FRACDIV_M FRACDIV_L
0 0x00 0x00
1 0x00 0x10
2 0x00 0x44
3 0x00 0x92
4 0x01 0x29
5 0x01 0xaa
6 0x01 0xb6
7 0x01 0xdb
8 0x01 0xef
9 0x01 0xff
10 0x03 0xff

[Link].4 Data Transmission

See Table 3-115 for details of the data transmission mechanism.

The software can write transmitted data into the THR by asserting transmit interrupt (IIR[5:0] = 000010b) or polling the
THRE bit status as “1” directly. When FIFOs are enabled, the transmitted data can be written into the THR. The data is
transferred to the TX FIFO directly.

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Table 3-115 Data Transmission Mechanism

FIFIO Status Condition Result
THRE bit of LSR is 1.
THR empty
FIFO disabled Transmitted data can be written in THR.
THR not empty TX starts to transmit automatically.
THRE bit of LSR is 1.
TX FIFO reduced to trigger level
FIFO enabled Transmitted data can be written in THR.
TX FIFO not empty TX starts to transmit automatically.

[Link].5 Data Reception

 When the RX Buffer is almost full or a byte is being transferred into the RX FIFO, the DR bit of the LSR is “1” and the
received data can be read by the RX Buffer Register (RBR).
 The software can read the received data either by responding to a received interrupt (IIR[5:0] = 000100b), or by
polling the DR bit status directly. If FIFOs are enabled, the received data in the RX FIFO can be read by reading RBR.

[Link] Power Management

Every UART has its own clock gating to save power. Enabling clock gating can turn off the clock once the transfer is
complete with the UART. Furthermore, the UART BCLK and PCLK share the same clock gating bit.

In special scenarios where the system needs to enter the sleep mode while the UART is either transmitting or receiving
characters, the UART hardware provides sleep_req and sleep_ack mechanisms to avoid conflicts. Set sleep_req and then
poll sleep_ack until its status becomes “1”, which indicates that the UART has entered an idle status (TX idle and RX idle).

 TX idle: The TX state machine enters an idle status.

 RX idle: The RX state machine enters an idle status and the RX data line remains idle (high) for the duration of five-bit
baud.

[Link] Electrical Specifications

Table 3-116 UART Electrical Specifications

Symbol Description Min Max Unit
TX baud rate error rate
TX_ERR (1) (3000000, 2000000, 1000000, 921600, 460800, 230400, 115200, 76800, -0.25 0.25 %
57600, 38400, 28800, 19200, 9600)
Acceptable error rate on RX baud rate
RX_ERR (2) (3000000, 2000000, 1000000, 921600, 460800, 230400, 115200, 76800, -1.5 1.5 %
57600, 38400, 28800, 19200, 9600)
(1) TX_ERR (%): The percentage of ((real TX output baud rate – target baud rate)/target baud rate).
(2) RX_ERR (%): The acceptable error rate on the RX, i.e. the percentage of ((real RX acceptable baud rate – target baud rate)/target
baud rate).

The figure below depicts the specific UART baud rate waveform.

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One character

UARTx_RX
UARTx_TX

Figure 3-117 UART Timing Diagram

[Link] Programming Guide

[Link] Baud Rate Setting and UART Initialization

The table below suggests the UART baud rate setting from a clock input of 30 MHz.

Table 3-117 Suggested UART Baud Rate Setting

Baud Rate HIGHSPEED {DLM, DLL} SAMPLE_COUNT SAMPLE_POINT FRACDIV_M FRACDIV_L

3,000,000 3 0x00, 0x01 0x09 0x04 0x0 0x0

2,000,000 3 0x00, 0x01 0x0E 0x06 0x0 0x0
1,000,000 3 0x00, 0x01 0x1D 0x0E 0x0 0x0
500,000 3 0x00, 0x01 0x3B 0x1D 0x0 0x0
250,000 3 0x00, 0x01 0x77 0x3B 0x0 0x0
153,600 3 0x00, 0x01 0xC2 0x60 0x0 0x92
115,200 3 0x00, 0x02 0x81 0x40 0x0 0x44
76,800 3 0x00, 0x02 0xC2 0x60 0x0 0x92
57,600 3 0x00, 0x03 0xAC 0x55 0x1 0xB6
38,400 3 0x00, 0x04 0xC2 0x60 0x0 0x92
28,800 3 0x00, 0x05 0xCF 0x67 0x0 0x92
19,200 3 0x00, 0x07 0xDE 0x6E 0x0 0x44
9,600 3 0x00, 0x0D 0xEF 0x77 0x1 0x92
7,200 3 0x00, 0x11 0xF4 0x79 0x1 0x01
4,800 3 0x00, 0x19 0xF9 0x7C 0x0 0x0

Use the registers below to set the baud rate.

 DLL
 DLM
 HIGHSPEED
 SAMPLE_COUNT
 SAMPLE_POINT
 FRACDIV_M
 FRACDIV_L

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Once the baud rate is set, the UART is able to start transmitting data by filling the TX FIFO and receiving data from the RX
FIFO. See Table 3-118 for an example of how to set the baud rate to 115,200 bps using a clock input of 30 MHz.

Table 3-118 UART Baud Rate Setting Example

Step Description Related Register Setting
1 Select UART sample counter base to SPEED 3. HIGHSPEED = 0x3
SAMPLE_COUNT = 0x81
SAMPLE_POINT = 0x40
2 Set sample counter.
FRACDIV_L = 0x44
FRACDIV_M = 0x0
Switch register to the divisor mode (Register MAP condition 2) to
3 execute the divisor latch setting. LCR = 0x80
UARTn_LCR[7] = 1
DLL = 0x2
4 Set the divisor latch.
DLM = 0x0
5 Set the guard time. GUARD
Switch the register to the normal mode (Register MAP condition 1).
6 LCR = 0x00
UARTn_LCR[7] = 0

Table 3-119 UART Hardware Initialization

Step Description Related Register Setting
1 Set the baud rate (refer to Table 3-118). -
LCR = 0xBF
Enable the enhanced features.
2 EFR = 0x10
(The register is accessible only when LCR = 0xBF.)
LCR = 0x00
3 Enable the FIFO control. FCR
4 Set word length (LCR[1:0]), parity (LCR[5:4]) and STOP (LCR[2]) bits. LCR
5 Enable interrupts. IER

The suggested software programming sequence is as follows:

1 DRV_WriteReg32(UART_BASE+0x24, 0x00000003); //High-speed UART
2 DRV_WriteReg32(UART_BASE+0x28, 0x00000081); //sample_count
3 DRV_WriteReg32(UART_BASE+0x2C, 0x00000040); //sample_point
4 DRV_WriteReg32(UART_BASE+0x4C, 0x00000001); //Enable RX DMA
5 DRV_WriteReg32(UART_BASE+0x54, 0x00000044); //FRACDIV_L
6 DRV_WriteReg32(UART_BASE+0x58, 0x00000000); //FRACDIV_M
7 DRV_WriteReg32(UART_BASE+0x0C, 0x000000BF); //LCR==0xBF, change to Condition 2
8 DRV_WriteReg32(UART_BASE+0x00, 0x00000002); //DLL, LS
9 DRV_WriteReg32(UART_BASE+0x04, 0x00000000); //DLM, MS
10 DRV_WriteReg32(UART_BASE+0x08, 0x00000010); //Enable enhancement features
11 DRV_WriteReg32(UART_BASE+0x0C, 0x00000000); //LCR !=0xBF, change to Condition 1
12 DRV_WriteReg32(UART_BASE+0x08, 0x00000031); //FIFO trigger threshold and enable FIFO
13 DRV_WriteReg32(UART_BASE+0x0C, 0x00000003); //8-bit word length
14 DRV_WriteReg32(UART_BASE+0x04, 0x00000001); //Enable RX interrupt

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[Link] Data Transmission and Reception

[Link].1 Data Transmission

Start
FIFO register settings:
 Enable FIFO: Set 0x08[0] to 1 b1
FIFO Control Register Settings
 TX FIFO Trigger Threshold 0x08[5:4]
(Set TX FIFO Trigger Threshold and Enable FIFOs)  2 b00: 1 byte (down to trigger)
 2 b01: 4 bytes (down to trigger)
 2 b10: 8 bytes (down to trigger)
No  2 b11: 14 bytes (down to trigger)
THRE Bit of LSR
Is 1 ?

Yes
Set Transmit Data to TX
Holding Register(THR)

Figure 3-118 UART Data Transmission with THRE Bit Status Polling

[Link].2 Data Reception

Start
FIFO register settings:
 Enable FIFO: Set 0x08[0] to 1 b1
FIFO Control Register Settings
 RX FIFO Trigger Threshold 0x08[7:6]
(Set RX FIFO Trigger Threshold and Enable FIFOs)  2 b00: 1 byte (up to trigger)
 2 b01: 6 bytes (up to trigger)
 2 b10: 12 bytes (up to trigger)
No  2 b11: register 0x50[4:0] (up to trigger)
DR Bit of LSR Is
1 ?

Yes
Set Transmit Data to RX
Buffer Register(RBR)

Figure 3-119 UART Data Reception with DR Bit Status Polling

[Link].3 Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

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[Link].4 Reference

16550 UART

3.12.3 Serial Peripheral Interface Master (SPIM)

[Link].1 SPI Master Overview

The Serial Peripheral Interface Master (SPIM) is a four-pin synchronous serial interface used for short-distance
communication, primarily in embedded systems. The device features six SPIM controllers.

[Link].2 SPI Master Features

The SPIM supports the following key features:

 Six SPIMs in PERISYS. They can support up to 52 MHz. SPIM0 is quad mode SPI, while SPIM1/SPIM2/SPIM3/SPIM4/SPIM5 is
dual mode SPI.
 Three SPIMs in SCPSYS. They can support up to 26 MHz. SCP_SPIM0/SCP_SPIM1/SCP_SPIM2 is single mode SPI.
 Two configurable transmit modes:
 TX DMA mode—the SPI controller automatically fetches the transmitted data (to be put on the MOSI (Master
Output Slave Input) line) from memory
 TX FIFO mode—the data to be transmitted on the MOSI line is written to FIFO before the start of the transaction.
 Two configurable receive modes:
 RX DMA mode—the SPI controller automatically stores the received data (from the MISO (Master Input Slave
Output) line) into memory.
 RX FIFO mode—the received data is kept in RX FIFO of the SPI controller. The processor must read back the data by
itself.
 Configurable chip-select setup, hold, and idle times
 Programmable serial clock high and low times
 Configurable transmit and receive bit order (MSB or LSB)
 Adjustable endian order from/to memory system
 Programmable byte length for transmission
 Unlimited length for transmission using dedicated pause mode
 Configurable option to control chip-select de-assertion between byte transfers
 Supports all clock polarity and phase modes
 SPIM signal descriptions

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[Link].3 SPIM Block Diagram

CSB
Control and Status CLK
APB Main SPI PAD_MACRO
Register MO
MI

DMA mode DMA mode

AHB
TX/RX FIFO
DMA Control Unit
32x8

PIO mode: write TX FIFO

or read RX FIFO

APB

Figure 3-120 Block Diagram of SPIM

The SPIM consists of the following modules:

Table 3-120 SPIM Signal Descriptions

Module Description
Control and status register Receives commands from the system
DMA control unit Communicate with SYSRAM when the SPI is set to the DMA mode
Main SPI The functional unit
TX/RX FIFO Both TX and RX have 32 x 8 bits FIFO for data storage
PAD_MACRO Controls the SPI data capture and transmission to/from the SPI

 In the FIFO mode, software can write data into the TX FIFO via SPI_TX_DATA, or read data from the RX FIFO via
SPI_RX_DATA.
 In the DMA mode, the SPI is capable of automatically retrieving data from or sending data to SYSRAM via the AHB after
the software configures the DMA parameters.

[Link].4 SPI Master Signal Descriptions

Table 3-121 presents SPIM signal descriptions.

Table 3-121 SPIM Signal Descriptions

Signal Name Type Description Ball Location
SPI0 Master
SPIM0_CLK DO SPIM0 clock T11

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Signal Name Type Description Ball Location

SPIM0_CSB DO SPIM0 chip select V6
SPIM0_MISO DIO SPIM0 data in/SPIM0 data 1 V8
SPIM0_MOSI DIO SPIM0 data out/SPIM0 data 0 V7
SPIM0_MIO2 DIO SPIM0 data 2 U7
SPIM0_MIO3 DIO SPIM0 data 3 U8
SPI1 Master
SPIM1_CLK DO SPIM1 clock T10
SPIM1_CSB DO SPIM1 chip select T9
SPIM1_MISO DIO SPIM1 data in/SPIM0 data 1 T7
SPIM1_MOSI DIO SPIM1 data out/SPIM0 data 0 T8
SPI2 Master
SPIM2_CLK DO SPIM2 clock G1
SPIM2_CSB DO SPIM2 chip select G2
SPIM2_MISO DIO SPIM2 data in/SPIM0 data 1 E2
SPIM2_MOSI DIO SPIM2 data out/SPIM0 data 0 F2
SPI3 Master
SPIM3_CLK DO SPIM3 clock W5, AC6
SPIM3_CSB DO SPIM3 chip select W4, AA6
SPIM3_MISO DIO SPIM3 data in/SPIM0 data 1 V5, AB4
SPIM3_MOSI DIO SPIM3 data out/SPIM0 data 0 V4, AC7
SPI4 Master
SPIM4_CLK DO SPIM4 clock T30, AC31
SPIM4_CSB DO SPIM4 chip select R31, AD30
SPIM4_MISO DIO SPIM4 data in/SPIM0 data 1 U32, AB31
SPIM4_MOSI DIO SPIM4 data out/SPIM0 data 0 T31, AC30
SPI5 Master
SPIM5_CLK DO SPIM5 clock U10, AC9
SPIM5_CSB DO SPIM5 chip select Y10, AB9
SPIM5_MISO DIO SPIM5 data in/SPIM0 data 1 Y7, AC4
SPIM5_MOSI DIO SPIM5 data out/SPIM0 data 0 Y6, AB8

[Link].5 SPI Master Function Description

As introduced in Section [Link].2, the following table extends further regarding the SPI features.

Table 3-122 SPIM Function Descriptions

Features Description
IO speed SPIM[0-5] support up to 52 MHz.

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Features Description
SPI_CLK = SOURCE_CLK/2n (n ∈ N*)
The default SOURCE_CLK value is 208 MHz.
SCP_SPIM[0-2] support up to 26 MHz.
 TX modes(1)
– TX DMA mode(2): The SPI controller automatically fetches
the transmitted data (to be put on the MOSI line) from
memory.
– TX FIFO mode: Data transmitted on the MOSI line is
Two configurable TX/RX modes: TX/RX DMA mode written to FIFO before the transaction starts.
and TX/RX FIFO mode  RX modes(3)
– RX DMA mode: The SPI controller automatically stores
the received data (from the MISO line) to memory.
– RX FIFO mode: Data received is stored in the RX FIFO of
the SPI controller. The processor itself must read back the
data.
Configurable chip-select setup time, hold time and
Refer to Figure 3-121.
idle time
Configurable option to control CS_N de-assert
Refer to Figure 3-123.
between byte transfers
 TX:
– In the TX DMA mode, data on the MOSI line is prepared
priorly in memory(4), and the SPI controller automatically
reads the data.
– In the TX FIFO mode, writing the SPI_TX_DATA register
means to write 4 bytes to TX FIFO, whose pointer
The depth of the TX and RX FIFO is 32 bytes. automatically moves towards the next 4 bytes.
 RX:
– In the RX DMA mode, data on the MISO line is
automatically moved by the SPI controller.
– In the RX FIFO mode, reading from the SPI_RX_DATA
register means to read 4 bytes from the RX FIFO, whose
pointer automatically moves towards the next 4 bytes.
Programmable serial clock high time and low time The high and low time can be set separately. Thus, for a given
baud rate, the serial clock with a wide range of a duty cycle is
generated.
 PACKET_LENGTH defines the number of bytes in one packet.
The number of bytes in one packet = PACKET_LENGTH+1.
 PACKET_LOOP_CNT defines the number of packets within
Programmable byte length for transmission one transaction. The number of packets in one transaction =
PACKET_LOOP_CNT+1.
 Total bytes of one transaction = (PACKET_LENGTH+1) *
(PACKET_LOOP_CNT+1)

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Features Description
Achieved by the pause mode operation.
In this mode, the CS_N signal is always active (in other modes,
Unlimited length for transmission using the
normally low) after the transmission. At this time, the SPI
dedicated pause mode
controller is in the PAUSE_IDLE state and ready to receive the
resume command. Refer to Figure 3-122 for the state transition.
 There are four communication modes: mode 0/1/2/3 (Figure
3-124).
 The modes define the SCLK edge on which the MOSI line
toggles and the master samples to the MISO line. The modes
Supports all clock polarity and phase modes
also define the SCLK steady level: clock/high/low, when the
clock is inactive.
 Each mode is formally defined with a pair of parameters
namely “Clock Polarity (CPOL)” and “Clock Phase” (CPHA).
(1) The value of SPI_TX_SRC must be 4-byte aligned.
(2) TX data must always be prepared before a transaction. In the DMA mode, TX_DMA_EN must be set to 1’b1. In the FIFO mode,
software must put data into the TX FIFO through the SPI_TX_DATA register.
(3) The value of SPI_RX_DST must be 4-byte aligned.
(4) For theory of operations, please refer to Section [Link].6.

CS_N
idle time
Data Transmission

CS_N

CS_N setup time CS_N hold time

SCK
(CPOL=0)

SCK Edge
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCK
(CPOL=1)

SAMPLE MOSI/MISO
(CPHA=0)

SAMPLE MOSI/MISO
(CPHA=1)

Figure 3-121 SPI Transmission Formats

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activate
IDLE

! (pause)

BUSY

pause

PAUSE IDLE
resume

Figure 3-122 SPI Pause Mode State Transition

CS_N

SCLK BYTE BYTE ... BYTE BYTE BYTE

Figure 3-123 CS_N De-assert Mode

Toggling edge Toggling edge

Mode 0 Mode 2
CPOL = 0 CPOL = 1
CPHA = 0 CPHA = 0
Sampling edge Sampling edge
SCLK idle level low SCLK idle level high

Toggling edge Toggling edge

Mode 1 Mode 3
CPOL = 0 CPOL = 1
CPHA = 1 CPHA = 1
Sampling edge Sampling edge
SCLK idle level low SCLK idle level high

Figure 3-124 Four Communication Modes Waveform for SPI

[Link].6 SPI Master Theory of Operations

-5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

CS_N

SCK

MOSI data0 data1 data2 dataN

MISO slv_data0 slv_data1 slv_data2 slv_dataN

Figure 3-125 SPI Transaction Format

 In the DMA mode, data to be transferred should be prepared in SYSRAM in advance.

 In the FIFO mode, the system must first push the data to be transferred into the SPI TX FIFO. Once the START command
is received, the SPI sends the data to the slave continuously while simultaneously receiving data from the slave.

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[Link].7 SPIM Timing Characteristics

Table 3-123 presents timing characteristics for the SPIM in the device.

Table 3-123 SPIM Timing Characteristics

No. Parameter Min Typ Max Unit
fOP_MCK SPI clock frequency 52 MHz
(1)
SPI02 tc Cycle time, SPI clock (SPI_CLK) 19.23 ns
SPI05 tw_CLK_L Pulse duration, SPI_CLK low 7.2 ns
SPI06 tw_CLK_H Pulse duration, SPI_CLK high 7.2 ns
SPI07 tsu_cs(4) SPI_CSB falling to SPI_SCK rising setup time 1.8 ns
SPI08 th_cs(4) SPI_SCK falling to SPI_CSB rising hold time 1.8 ns
SPI09 tsu_MOSI SPI_MO to SPI_CK rising setup time 6.6 ns
SPI10 th_MOSI SPI_SCK rising to SPI_MO hold time 6.6 ns
(2)
SPI11 tsu_MISO SPI_MI to SPI_SCKrising setup time requirement 0 ns
(3)
SPI12 th_MISO SPI_SCK rising to SPI_MI hold time requirement 0 ns
(1) For maximum operating clock frequency, refer to Table 6-1.
(2) To achieve the minimum value of tsu_MISO, the internal sample clock delay of SPIM should be adjusted.
(3) th_MISO data valid time should be one cycle of fOP_MCK.
(4) In CS GPIO mode, SPI_CSB is handled by the software. The software should pull down SPI_CSB pin before SPI starts
transferring and pull up SPI_CSB pin when SPI completes the transaction.

Figure 3-126 SPIM Timing Diagram

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[Link].8 SPIM Programming Guide

Follow the steps below to perform an SPI transmission:

1. Prepare the data in the memory with its start address to be the “source address.”
2. Set the timing and protocol for the SPI transmission (see Figure 3-122 for detailed setup parameters).
3. Fill in the “destination address,” which is the start address to place the received data, and “source address”, which is
the start address to place the data to be transmitted, into the registers SPI_RX_DST and SPI_TX_SRC, respectively.
4. Write 1 to CMD_ACT to start the transfer.
5. Get the data received from the buffer prepared starting from “destination address”.

3.12.4 SuperSpeed Universal Serial Bus (SSUSB)

[Link] USB MAC Overview

The device has three USB subsystems with integrated PHYs—one SuperSpeed (SS) USB 3.1 Gen1 DRD and two USB
2.0 Dual-Role-Devices (DRD).

 USB Port 1 supports SS USB 3.1 Gen1 DRD.

 USB Port 0 and USB Port 2 are USB 2.0 DRD ports.

The module contains a pair of U3 Gen1 PHY and U3 Gen1 MAC for SuperSpeed connection, as well as a pair of U2 PHY and
U2 MAC for High-, Full- and Low-Speed connection.

The USB2.0 dual role capability allows the port to support On-The-Go (OTG) host and peripheral functions. When operating
in the USB2.0 host role, the port is controlled by the host controller (xHC), which manages all devices connected through
its root hub ports. Conversely, when operating in the peripheral role, the port is controlled by the device (DEV) controller.

[Link] Features

 USB 3.1 SS Gen1 with 5 Gbps TX and 5 Gbps RX (USB Port 1 only)
 Embedded USB 3.1 Gen1 PHY with 32-bit @ 125 MHz PIPE interface
 U0/U1/U2/U3 states
 USB 2.0 Full-Speed (FS) 12 Mbps and High-Speed (HS) 480 Mbps
 Embedded USB 2.0 PHY with 16-bit @ 30 MHz UTMI+ interface
 Lower Power Management (LPM)
 Host role features:
 Host controller based on eXtensible Host Controller Interface (xHCI) Revision 1.1
 Dedicated DMA channel for USB 3.1 data transfer
 Support of all USB compliant data transfer types (Control/Bulk/Interrupt/Isochronous)
 Support of connection to USB 2.0/USB 3.0 Hubs
 Support of up to 15 devices
 Support of up to 64 endpoints
 Device (peripheral) role features:
 Proprietary application layer device controller

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 Embedded queue management function with scatter/gather DMA capability

 Shared endpoint and buffer hardware for USB 2.0 port
 Up to 8 OUT endpoints and 8 IN endpoints
 Up to 8 packet slots for each endpoint
 Software configurable FIFO size allocation for each endpoint
 Software configurable transfer type (Bulk/Interrupt/Isochronous) for each endpoint
 Software configurable interrupt with the following interrupt statuses: VBUS On/Off, suspend/resume, and USB
Reset
 Software configurable period from VBUS connection to D+ pull-up
 Data alignment for Device DMA descriptor: 16-byte
 Data alignment for Device data: Byte alignment

[Link] Block Diagram

Chip

TXP/TXN
U3 Gen1 EMI
U3 Gen1 PHY DEV Controller
MAC
RXP/RXN

DP/DM U2 PHY U2 MAC MCU

xHC

Figure 3-127 Block Diagram of SSUSB

[Link] USB Signal Descriptions

Table 3-124 presents USB signal descriptions.

Table 3-124 USB signal descriptions

Signal Name Type Description Ball Location
USB Port 0
USB_DP_P0 AIO USB D+ bi-directional differential data W32
USB_DM_P0 AIO USB D- bi-directional differential data W31
USB OTG ID. Cable end detector:
IDDIG DI GND: micro-A R36
Floating: micro-B
USB_DRVVBUS DO USB drive VBUS—signal to external power switch enable P36
VBUSVALID DI Digital VBUS—valid signal from external circuitry P34
USB Port 1
SSUSB_RXN AI USB SuperSpeed receive data negative W36
SSUSB_RXP AI USB SuperSpeed receive data positive W37

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Signal Name Type Description Ball Location

SSUSB_TXN AO USB SuperSpeed transmit data negative Y34
SSUSB_TXP AO USB SuperSpeed transmit data positive Y33
USB_DP_P1 AIO USB D+ bi-directional differential data U37
USB_DM_P1 AIO USB D- bi-directional differential data U36
VBUSVALID_1P DI Digital VBUS-valid signal from external circuitry AC33, T33
IDDIG_1P DI USB OTG ID. Micro-A/B cable end detector AB34, R34
USB_DRVVBUS_1P DO USB drive VBUS—signal to external power switch enable AC32, R33
USB Port 2
USB_DP_P2 AIO USB D+ bi-directional differential data V34
USB_DM_P2 AIO USB D- bi-directional differential data V35
VBUSVALID_2P DI Digital VBUS-valid signal from external circuitry AB33, R30
IDDIG_2P DI USB OTG ID. Micro-A/B cable end detector AD32, P31
USB_DRVVBUS_2P DO USB drive VBUS—signal to external power switch enable AD33, P32

[Link] Function Description

[Link].1 Host Architecture

The SSUSB is the designated application for the MediaTek USB host controllers as mentioned in Section [Link]. Each PHY
is equipped with its own MAC for protocol packet management. Figure 3-128 illustrates the architecture of the SSUSB host.

The xHCI controller manages all endpoint and device resources. Dynamic allocation of resources for different ports is
achievable by software, which can also enable or disable each port separately.

USB 3.1 USB 3.1 USB3.1

USB 3.1 TX
TXP/TXN
Gen1 Gen1 Gen
Gen11 DMA
RXP/RXN EMI
PHY MAC Scheduler
RX
xHC DMA

USB 2.0 USB 2.0 USB 2.0 USB MCU

DP/DM
PHY MAC Scheduler 2.0
DMA

Figure 3-128 SSUSB host architecture

[Link].1.1 Features

 Hardware supports USB 3.1 SuperSpeed Gen1 with 5 Gb/s TX and 5 Gb/s RX bandwidth.
 Hardware supports USB 2.0 with Full-speed 12 Mbps/High-speed 480 Mbps.
 Embedded USB 3.1 Gen1PHY with 32-bit 125 MHz PIPE interface
 Embedded USB 2.0 PHY with 16-bit/30 MHz UTMI
 AHB interface for register access
 AXI3 interface for DMA access
 Extensible xHCI Revision 1.1 based host controller

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 Lower Power Management (LPM) on USB 2.0 port

 U0/U1/U2/U3 state on USB 3.1 Gen1 port
 Dedicated DMA channel for USB 3.1 data transfer
 Supports all USB compliant data transfer types with control/bulk/interrupt/isochronous transfer
 Compatible to connect to USB 2.0/USB3.0 hubs
 Maximum 15 devices
 Maximum 32 endpoints
 Bulk stream: Not supported
 Transaction Translator (TT) (Multiple Transaction Translator (MTT) not supported)

[Link].2 Device Architecture Overview

Figure 3-129 illustrates the architecture of the USB2 device function. The USB 2.0 PHY and MAC operate independently for
different transmission lines. As only one link can connect to the USB host at a time, they share the same endpoint and
buffer management unit.

The linked-list queue of the USB2 device is inherited from the MediaTek unified USB with similar descriptor definition.

EMI
EP & Buffer Queue
Management Management DMA
Unit Unit
USB2.0 USB2.0 MCU
DP/DM
PHY MAC

Figure 3-129 USB2 Device Architecture

[Link].2.1 Features

 Hardware supports USB 3.1 Gen1 and USB 2.0 High-speed/Full-speed

 Embedded USB 3.1 PHY with 32-bit/125 MHz (Gen1) PIPE interface
 Embedded USB 2.0 PHY with 16-bit/30 MHz UTMI
 AHB interface for register access
 AXI3 interface for DMA access
 Embedded queue management function with scatter/gather DMA capability
 Proprietary application layer device controller with linked list queue and scatter/gather DMA
 Lower Power Management (LPM) on USB 2.0 port
 U0/U1/U2/U3 state on USB 3.1 Gen1 port
 Shared endpoint and buffer hardware for USB 2.0 and USB 3.1 Gen1 ports
 Hardware configurable to USB 2.0 only device
 Hardware configurable up to 8 OUT endpoints and 8 IN endpoints
 Hardware configurable up to 8 packet slots for each endpoint separately
 Software configurable FIFO size allocation for each endpoint separately
 Software configurable transfer type to Bulk/Interrupt/Isochronous for each endpoint
 Software configurable Interrupt with the following interrupt statuses: VBUS On/Off, suspend/resume, USB Reset

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 Software configurable for the period from VBUS connection to D+ pull up

 Data alignment for Device DMA Descriptor “16-byte alignment” in SDRAM
 Data alignment for Device Data: “Byte alignment”
 Bulk stream: Not supported

[Link] Theory of Operations

[Link].1 USB Host Initialization

 After Power-On-Reset (POR), USB powers down by default to save power.

 Software must execute the following steps before using USB. Refer to Table 3-125 for details.
For the MediaTek scheduling algorithm initialization, refer to the kernel drivers implemented in xhci_mtk_sch_init () of
/usb/host/mtk-xhci-sch.c file.

Table 3-125 USB Host Initialization

Step Address Register Name Local Address R/W Value Description
USB Initialization
USB Software Reset
When this bit is set, the whole USB
is reset.
ssusb_sifslv_ippc_Base Write “0” to release reset. Setting
1 SSUSB_IP_PW_CTRL0 SSUSB_IP_SW_RST [0] W 1’b0
address + 0x00000 flow:
SSUSB_IP_SW_RST [0] = “1”, delay 1
µs.
SSUSB_IP_SW_RST [0] = “0”.
This bit is USB power-down bit.
ssusb_sifslv_ippc_Base
2 SSUSB_IP_PW_CTRL1 SSUSB_IP_HOST_PDN [0] W 1’b0 Write “0” to disable USB power-
address + 0x0004
down.
Enable USB 3.1 Gen1 Port
ssusb_sifslv_ippc_Base USB 3.0 port0 disable bit.
3 SSUSB_U3_CTRL_0P SSUSB_U3_PORT_DIS [0] W 1’b0
address + 0x0030 “0”: USB 3.0 port0 is enabled.
ssusb_sifslv_ippc_Base USB 3.0 port0 power-down bit.
4 SSUSB_U3_CTRL_0P SSUSB_U3_PORT_PDN [1] W 1’b0
address + 0x0030 “0”: USB 3.0 port0 is powered on.
This bit is Host mode selection of
ssusb_sifslv_ippc_Base SSUSB_U3_PORT_HOST_SEL USB 3.0 port0.
5 SSUSB_U3_CTRL_0P W 1’b1
address + 0x0030 [2] “1”: This port is selected for Host
mode.
Enable USB 2.0 Port
ssusb_sifslv_ippc_Base USB 2.0 port0 disable bit.
6 SSUSB_U2_CTRL_0P SSUSB_U2_PORT_DIS [0] W 1’b0
address + 0x0050 “0”: USB 2.0 port0 is enabled.
ssusb_sifslv_ippc_Base USB 2.0 port0 power-down bit.
7 SSUSB_U2_CTRL_0P SSUSB_U2_PORT_PDN [1] W 1’b0
address + 0x0050 “0”: USB 2.0 port0 is powered on.
This bit is Host mode selection of
ssusb_sifslv_ippc_Base SSUSB_U2_PORT_HOST_SEL USB 2.0 port0.
8 SSUSB_U2_CTRL_0P W 1’b1
address + 0x0050 [2] “1”: This port is selected for Host
mode.
Check reference clock stability before software proceeds (i.e., Software proceeds after the following status bits are asserted)

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Step Address Register Name Local Address R/W Value Description

ssusb_sifslv_ippc_Base When this bit is 1'b1, SYSPLL for
9 SSUSB_IP_PW_STS1 SSUSB_SYSPLL_STABLE [0] R
address + 0x0010 USB is stable.
When this bit is 1'b1, it means that
ssusb_sifslv_ippc_Base
10 SSUSB_IP_PW_STS1 SSUSB_REF_RST_B_STS [8] R reset for reference clock (ref_ck)
address + 0x0010
domain is inactive.
When this bit is 1'b1, it means that
ssusb_sifslv_ippc_Base SSUSB_SYS125_RST_B_STS
11 SSUSB_IP_PW_STS1 R reset for sys125_ck domain is
address + 0x0010 [10]
inactive.
ssusb_sifslv_ippc_Base When this bit is 1'b1, it means that
12 SSUSB_IP_PW_STS1 SSUSB_XHCI_RST_B_STS [11] R
address + 0x0010 reset for xhci_ck domain is inactive.

[Link].2 USB Device Initialization

 After Power-On-Reset, USB powers down by default to save power.

 Software must perform the following steps before using USB. Refer to Table 3-126 for details.

Table 3-126 USB Device Initialization

Step Address Register Name Local Address R/W Value Description
USB Initialization
USB Software Reset.
ssusb_sifslv_ippc_Base When this bit is set, the whole
1 SSUSB_IP_PW_CTRL0 SSUSB_IP_SW_RST [0] W 1’b0
address + 0x0000 USB is reset.
Write “0” to release reset.
SSUSB IP Dev Power Down.
ssusb_sifslv_ippc_Base When this bit is set, the whole
2 SSUSB_IP_PW_CTRL2 SSUSB_IP_DEV_PDN[0] W 1’b0
address + 0x0008 CKBG can be powered down.
Write “0” to release reset.
Enable USB 3.1 Gen1 Port (If device is USB 2.0 only, please skip it.)
ssusb_sifslv_ippc_Base USB 3.0 port0 disable bit
3 SSUSB_U3_CTRL_0P SSUSB_U3_PORT_DIS [0] W 1’b0
address + 0x0030 “0”: USB 3.0 port0 is enabled.
USB 3.0 port0 power-down bit
ssusb_sifslv_ippc_Base
4 SSUSB_U3_CTRL_0P SSUSB_U3_PORT_PDN [1] W 1’b0 “0”: USB 3.0 port0 is powered
address + 0x0030
on.
This bit is Host mode selection of
ssusb_sifslv_ippc_Base SSUSB_U3_PORT_HOST_SEL USB 3.0 port0.
5 SSUSB_U3_CTRL_0P W 1’b0
address + 0x0030 [2] “0”: This port is selected for
Device mode.
Enable USB 2.0 Port
ssusb_sifslv_ippc_Base USB 2.0 port0 disable bit
6 SSUSB_U2_CTRL_0P SSUSB_U2_PORT_DIS [0] W 1’b0
address + 0x0050 “0”: USB 2.0 port0 is enabled.
USB 2.0 port0 power-down bit
ssusb_sifslv_ippc_Base
7 SSUSB_U2_CTRL_0P SSUSB_U2_PORT_PDN [1] W 1’b0 “0”: USB 2.0 port0 is powered
address + 0x0050
on.
ssusb_sifslv_ippc_Base SSUSB_U2_PORT_HOST_SEL This bit is Host mode selection of
8 SSUSB_U2_CTRL_0P W 1’b0
address + 0x0050 [2] USB 2.0 port0

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Step Address Register Name Local Address R/W Value Description

“0”: This port is selected for
Device mode.
Check reference clock stability before software proceeds (i.e., Software proceeds after the following status bits are asserted)
When this bit is 1'b1, it means
ssusb_sifslv_ippc_Base SSUSB_SYS125_RST_B_STS
9 SSUSB_IP_PW_STS1 R that reset for sys125_ck domain
address + 0x0010 [10]
is inactive.
When this bit is 1'b1, it means
that reset for mac3_mac_ck
ssusb_sifslv_ippc_Base SSUSB_U3_MAC_RST_B_STS[
10 SSUSB_IP_PW_STS1 R domain is inactive
address + 0x0010 16]
(If device is USB 2.0 only, please
skip it.).
When this bit is 1'b1, it means
ssusb_sifslv_ippc_Base SSUSB_U2_MAC_SYS_RST_B_
11 SSUSB_IP_PW_STS2 R that reset for mac2_sys_ck
address + 0x0014 STS [0]
domain is inactive.
Turn on the USB connection by speed. (USB 3.1)
ssusb_sifslv_ippc_Base SSUSB_U3_PORT_SS_SUP_SP User Users can set the register to
12 SSUSB_IP_SPARE0 W
address + 0x00c8 EED[1:0] defined force operation speed.
ssusb_usb3_mac_csr_B
13 USB3_CONFIG USB3_EN[0] W 1’b1 Enable SuperSpeed function.
ase address + 0x001c
Turn on the USB connection by speed. (USB 2.0)
ssusb_usb3_mac_csr_B
14 USB3_CONFIG USB3_EN[0] W 1’b0 Disable SuperSpeed function.
ase address + 0x001c
ssusb_usb2_csr_Base
15 POWER_MANAGEMENT HS_ENABLE[5] W 1’b1 Enable high speed function.
address + 0x0004
ssusb_usb2_csr_Base
16 POWER_MANAGEMENT SUSPENDM_ENABLE[0] W 1’b1 Enable the SUSPENDM output.
address + 0x0004
ssusb_usb2_csr_Base
17 POWER_MANAGEMENT soft_conn[6] W 1’b1 Enable D+/D- lines.
address + 0x0004
Note: On USB 3.1 Gen1/USB 2.0 port power down
 Registers in SSUSB_USB3_SYS/SSUSB_USB3_MAC cannot be read correctly when SSUSB_U3_PORT_PDN or SSUSB_U3_PORT_DIS =
1.
 Registers in SSUSB_USB2 cannot be read correctly when SSUSB_U2_PORT_PDN or SSUSB_U2_PORT_DIS = 1.
 After setting SSUSB_U*_PORT_PDN and SSUSB_U*_PORT_DIS to 0, wait until SYSPLL becomes stable (SSUSB_IPCTL
.U3D_SSUSB_IP_PW_STS1. SSUSB_SYSPLL_STABLE).

[Link].3 USB Endpoint Initialization

[Link].3.1 EP0 Initialization

 EP0 hardware should be configured properly before a successful USB enumeration.

 EP0 is controlled by USB only and software fills the correct value into EP0 CSR. The EP0 initialization is included in the
USB initial flow. And it is not recommended to modify it except for the maximum packet size.

Table 3-127 EP0 Programming Sequence

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Step Address Register Name Local Address R/W Value Description

ssusb_dev_Base address Set maximum packet size
1 EP0CSR EP0_MAXPKTSZ0[9:0] W USER DEFINED
+ 0x0100 For example, 10’d64
ssusb_dev_Base address
2 EPIESR EP0IESR[0] W 1’b1 Endpoint 0 interrupt enable setting
+ 0x0088
ssusb_dev_Base address Endpoint 0 Setup End interrupt
3 EPIESR SETUPENDIESR[16] W 1’b1
+ 0x0088 enable setting

[Link].3.2 EPn Initialization

The suggested programming sequence of TX EPn (e.g., EP1) is shown in the table below.

Table 3-128 TX EPn Programming Sequence

Step Address Register Name Local Address R/W Value Description
ssusb_dev_Base Set maximum packet size.
1 TX1CSR0 TX_TXMAXPKTSZ[10:0] W USER DEFINED
address + 0x0110 For example, 11’d64.
ssusb_dev_Base Set burst size.
2 TX1CSR1 SS_TX_BURST[3:0] W USER DEFINED
address + 0x0114
ssusb_dev_Base Set TX_MULT size.
3 TX1CSR1 TX_MULT[23:21] W USER DEFINED
address + 0x0114
Number of packets = (SS_TX_BURST+ 1) x
ssusb_dev_Base
4 TX1CSR1 TX_MAX_PKT[30:24] W USER DEFINED (TX_MULT + 1) -1 (Isochronous endpoint
address + 0x0114
only).
ssusb_dev_Base Start address of the selected TX endpoint
5 TX1CSR2 TXFIFOADDR[12:0] W USER DEFINED
address + 0x0118 FIFO
ssusb_dev_Base Set slot number of hardware.
6 TX1CSR1 TX_SLOT[13:8] W USER DEFINED
address + 0x0114
ssusb_dev_Base Set FIFO segment size of hardware layout.
7 TX1CSR2 TXFIFOSEGSIZE[19:16] W USER DEFINED
address + 0x0118 Indicate the TX FIFO size of 2^n bytes.
Select the required transfer type for the TX
endpoint.
ssusb_dev_Base
8 TX1CSR1 TXTYPE[5:4] W USER DEFINED 2'b00: Bulk
address + 0x0114
2'b01: Interrupt
2'b10: Isochronous
Interval for servicing the endpoint for data
ssusb_dev_Base
9 TX1CSR2 TXBINTERVAL[31:24] W USER DEFINED transfer. For Isochronous/Interrupt
address + 0x0118
transfer.
ssusb_dev_Base Enable EP1 DMA request for the TX
10 TX1CSR0 TX_DMAREQEN[29] W 1’b1
address + 0x0110 endpoint.
ssusb_dev_Base Enable EP1 TX QMU Done interrupt.
11 QIESR0 TXQ_DONE_IESR[1] W 1’b1
address + 0x0708

The suggested programming sequence of RX EPn (e.g.,EP2) is shown in the table below.

Table 3-129 RX EPn Programming Sequence

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Step Address Register Name Local Address R/W Value Description

Set the maximum packet
ssusb_dev_Base USER
1 RX2CSR0 RX_RXMAXPKTSZ[10:0] W size.
address + 0x0220 DEFINED
For example, 11’d64
ssusb_dev_Base USER Set burst size.
2 RX2CSR1 SS_RX_BURST[3:0] W
address + 0x0224 DEFINED
ssusb_dev_Base USER Set RX_MULT size.
3 RX2CSR1 RX_MULT[23:21] W
address + 0x0224 DEFINED
Number of packets =
ssusb_dev_Base USER (SS_RX_BURST+ 1) x
4 RX2CSR1 RX_MAX_PKT[30:24] W
address + 0x0224 DEFINED (RX_MULT + 1) -1
(Isochronous endpoint only).
ssusb_dev_Base USER Start address of the selected
5 RX2CSR2 RXFIFOADDR[12:0] W
address + 0x0228 DEFINED Rx endpoint FIFO.
ssusb_dev_Base USER Set slot number of
6 RX2CSR1 RX_SLOT[13:8] W
address + 0x0224 DEFINED hardware.
Set FIFO segment size of
ssusb_dev_Base USER hardware layout. Indicate
7 RX2CSR2 RXFIFOSEGSIZE[19:16] W
address + 0x0228 DEFINED the RX FIFO size of 2^n
bytes.
Select the required transfer
type for the RX endpoint.
ssusb_dev_Base USER
8 RX2CSR1 RX_TYPE[5:4] W 2'b00: Bulk
address + 0x0224 DEFINED
2'b01: Interrupt
2'b10: Isochronous
Interval for servicing the
ssusb_dev_Base USER endpoint for data transfer.
9 RX2CSR2 RXBINTERVAL[31:24] W
address + 0x0228 DEFINED For Isochronous/Interrupt
transfer
ssusb_dev_Base Enable EP2 DMA request for
10 RX2CSR0 RX_DMAREQEN[29] W 1’b1
address + 0x0220 the RX endpoint.
ssusb_dev_Base Enable EP2 QMU Done
11 QIESR0 TXQ_DONE_IESR [18] W 1’b1
address + 0x0708 interrupt.

[Link] Programming Guide

[Link].1 USB Host

There are certain differences between the MediaTek Host Controller (xHC) and the standard xHCI.

 The MediaTek xHC does not implement completion codes because some TRB (Transfer Request Block) types are
defined in xHCI specification. A detailed description is in Section [Link].1.1.
 The MediaTek xHC proposes a scheduling mechanism for synchronous endpoints to simplify the hardware design. The
mechanism is described in Section [Link].1.2.

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 Interrupt moderation Interval (IMODI): The standard xHCI interval is 250 ns, while the MediaTek xHC interval is 2 µs.
 Only one of the xHCI extended capability codes, “Supported Protocol” (ID code = ’d2), is implemented in the MediaTek
xHC.
 Configuration Information Capability (CIC) feature
 The following features are not implemented in the MediaTek xHC:
 Frame Length Adjustment Register (FLADJ)
 The latency tolerance messaging LTV, LTM, and BEL
 The BUS_INTERVAL_ADJUSTMENT_MESSAGE notification packet

[Link].1.1 Unsupported TRB Types and Completion Codes

The following TRB types are not implemented in the MediaTek xHC:
 Force event command TRB (TRB Type = 18, optional normative)
 Negotiate bandwidth command TRB (TRB Type = 19, optional normative)
 Set latency tolerance value command TRB (TRB Type = 20, optional normative)
 Get port bandwidth command TRB (TRB Type = 21)
 Bandwidth request event TRB (TRB Type = 35)
 Doorbell event TRB (TRB Type = 36)

The following completion codes are not implemented in MediaTek xHC:

 Data buffer error (error value = 2)
 Bandwidth error (error value = 8)
 VF event ring full error (error value = 16)
 Bandwidth overrun error (error value = 18)
 Incompatible device error (error value = 22)
 Max exit latency too large error (error value = 29)
 Event lost error (error value = 32)
 Undefined error (error value = 33)
 Secondary bandwidth error (error value = 35)
 Split transaction error (error value = 36)
 Vendor defined error (error value = 192 to 223)
 Vendor defined info (error value = 224 to 255)

[Link].1.2 Scheduling of Synchronous Endpoint

To simplify the hardware design for bandwidth calculation and scheduling on synchronous endpoints, a proprietary
scheduling algorithm is proposed. To implement this algorithm for the MediaTek Host Controller Driver (xHCD), it is
necessary to patch the standard Linux xHCD driver. The patch includes the following two steps:

1. Calculate whether there is enough bandwidth reserved for the endpoint(s) to be added.
2. Determine a set of parameters specifying the scheduling for synchronous endpoint(s) to be added.

 Bandwidth Calculation
Due to offloading of bandwidth calculation by the xHCD, the MediaTek xHC is able to process the following xHCI commands
with greater ease:

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1. Reset the device

2. Configure the endpoint (with DC = 1 of Drop Flag(s) = 1)
3. Disable the slot command

In addition, the get port bandwidth command TRB is never replaced on the command ring for the MediaTek xHC because
all bandwidth information is directly visible to the xHCD.
 Decide the Software Scheduling Parameters
The xHCD implements the proprietary scheduling algorithm to enable easy scheduling of synchronous endpoints by the
xHC. Prior to issuing the configure endpoint TRB, a set of parameters is defined for each device slot and its related
synchronous endpoint. To incorporate these proprietary parameters into the MediaTek xHC, certain reserved fields of the
endpoint context are utilized to store their values.

The extra software scheduling parameters are implemented through the commands specified in the xHCI specification, as
some reserved DWs in the endpoint context are still available. These additional fields are exclusively reserved for
synchronous endpoints, such as isochronous and interrupt endpoints. Table 3-130 shows the modified endpoint context,
with the extra defined fields highlighted in orange, and Table 3-131 lists the definitions.

Table 3-130 Endpoint Context

Table 3-131 Extra Defined Fields for Endpoint Context

Field Name Location Definition
Number of packets to be transferred in the scheduled microframes
bPkts[6:0] DW5[6:0]
(Unit: microframe 125 µs)
 Host will trigger the number of Complete Spilt (CS).
 This field is only for Split Transaction at Full-speed/Low-speed.
 For full-speed/low-speed isochronous IN and interrupt EPs, this represents the
bCSCount[2:0] DW5[10:8]
pre-defined number of CS to be in a service interval.
 For full-speed/low-speed isochronous OUT EPs, this represents the pre-defined
number of SS (Start Spilt) to be in a service interval.
bBM  Burst mode for scheduling
DW5[11]
(bBurstmode)  Normal burst mode is used by default.

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Field Name Location Definition

 0: Normal burst mode. Distribute the bMaxBurst+1 packets for a single burst
according to bPkts and bRepeat, and repeat the burst multiple times.
 1: Distribute the (bMaxBurst+1)*(Mult+1) packets according to bPpkts and
bRepeat.
Which microframe of the interval that is transferred should be scheduled at the first
DW6[15:0]
bOffset[17:0] time within the interval
DW5[13:12]
(Unit: microframe 125 µs)
The time gap between two microframes, in which transfer USB packets are scheduled
DW6[31:16]
bRepeat[17:0] within an interval
DW5[15:14]
(Unit: microframe 125 µs)

The relation between the extra defined field parameters and microframes is illustrated in the figure below.
For example: EP5 parameters, mult = 0, maxburst = 6, interval = 4

1. EP5 service interval = 2^(4 - 1) = 8 microfames. EP5 total pkts = (mult + 1) x (maxburst + 1) = 7
2. The parameters of the extra defined fields can be scheduled as the following figure shows.

Figure 3-130 Relation between Extra Defined Fields Parameters and Microframes

The relation between the extra defined field parameters and microframes for split transaction at full-speed/low-speed is
illustrated in the figure below.
For example: Split IN Transaction for FS/LS. If EP internal = 1 (1ms)

1. Service Interval = 8 microframes.

2. The parameter of the extra defined fields bCScount value is as shown below.

Figure 3-131 Relation between bCSCount Parameters and Microframes

The software flow of “xhci_add_endpoint” configuration by a standard xHCI driver is illustrated in Figure 3-132. To add
extra defined field parameters to endpoint context, a sub-flow is patched. This patched sub-flow is marked by red dash line
in Figure 3-133.

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Figure 3-132 Standard xHCI_add_endpoint() Flow

Figure 3-133 Patched xHCI_add_endpoint() Flow

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The software flow of “xhci_drop_endpoint” configured by a standard xHCI driver is illustrated in Figure 3-134. To drop
software recording extra defined field parameters, a sub-flow is patched. This patched sub-flow is marked by red dash line
in Figure 3-135.

Figure 3-134 Standard xHCI_drop_endpoint() Flow

Figure 3-135 Patched xHCI_drop_endpoint() Flow

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Refer to the Linux standard xHCI kernel driver (version 4.5 or later) in drivers/usb/host/mtk-xhci-sch.c file for more details
about the extra defined field parameters for endpoint scheduling.

[Link].2 USB Device

[Link].3 EP0 Top Programming Outline

The EP0 control is a state machine with three state modes:

 Idle mode
 TX mode
 RX mode
Sequence 3

IDLE
Sequence 1 Sequence 2

TX Mode RX Mode

Figure 3-136 EP0 States

 EP0 interrupt is generated when
 [Link] bit is set after a data packet has been received and stored into FIFO0;
 Data packet in FIFO0 has been sent to host successfully;
 [Link] bit is set after the host receives STALL;
 [Link] bit is set after SETUP transaction is received in the DATA/STATUS phase.

 [Link] indicates that the current control transfer is aborted.

 Set when
 IN transaction is received after [Link] is set to leave the TX mode (STATUS phase).
 OUT transaction is received after [Link] is set to leave the RX mode (STATUS phase).
 SETUP transaction is received in the TX mode or RX mode (DATA phase).
 Cleared when
 Software sets [Link].
 Software can unload FIFO and decode the new command.
 [Link] indicates that data phase has finished.
 Set by software when
 In the TX mode or RX mode, the amount of data required by host is sent/received.
 In the TX mode, a smaller amount of data required by the host is sent. The device has to notify the host by
sending a short packet.
 In the RX mode, a short packet is received.
 Cleared by hardware when
 (Normal) Status phase finishes successfully.
 (Error) [Link] is set.

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[Link].3.1 Idle Mode

Upon power-on or reset, EP0 goes into the “IDLE” mode. After receiving a SETUP transaction:
 [Link] is set.
 [Link] is cleared.
 An interrupt is generated to notify software.

The software unloads FIFO and decodes the command which, depending on the type, enables the software to do the
following:
 (Sequence 1/IN DATA) W1C [Link] and set [Link].
EP0 goes to TX mode.
 (Sequence 2/OUT DATA) W1C [Link].
EP0 goes to RX mode.
 (Sequence 3/NO DATA) process command. Then, W1C [Link] and set [Link] (or set
[Link]) simultaneously.
EP0 stays in “IDLE” state.

IDLE

SetupPktRdy Set?
No
(Interrupt)

Yes Return

Unload FIFO (8 bytes)

Decode Command

Has Data Phase? No Process command

W1C SetupPktRdy & Set

DataEnd (or SendStall)
Yes

Return

W1C SetupPktRdy & Set

Data Phase = IN? Yes
DPHTX

No

State -> TX Mode

W1C SetupPktRdy

Return
State -> RX Mode

Return & means registers are set simultaneously

Figure 3-137 EP0 Idle Flow Chart

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Sequence 3

Idle (No Data Stage)

Interrupt
IN Status
Setup IN Status
(ACK or
(NAK)
STALL)

Command
SW Actions Process
Latency
W1C SetupPktRdy & Set
Unload command DataEnd or SendStall

& means registers are set simultaneously

Figure 3-138 EP0 Idle

[Link].3.2 TX Mode

 Normal Flow
 Software loads data packet (<=EP0CSR.MaxPktSz0) to FIFO0, and sets [Link] to send it to the host.
 If [Link] is set, software only needs to set [Link] for the last data packet (a short packet).
 After sending data packet to the host, [Link] is cleared and an interrupt is generated to notify software.
 Software repeats the previous step until the required amount of data is sent, and set [Link] to leave
DATA phase.

 Error Cases
 If a SETUP transaction is received in TX mode (DATA phase), [Link] is set and an interrupt is
generated. Software aborts the current command and moves on to decode the new command.

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TX Mode

Write ≤ MaxPktSz0 bytes to

FIFO0

AutoSet &
No Data Length == Yes
MaxPktSz0

Set TxPktRdy (by SW) Set TxPktRdy (by HW)

Yes
FIFOFull?

No

Protocol Error? No Last Packet No

Yes Yes

Set SendStall Set DataEnd

State -> IDLE

Return

Figure 3-139 EP0 TX Mode Flow Chart

Sequence 1

Idle TX Mode Idle

OUT
Interrupt

Interrupt

Interrupt

Interrupt

OUT
Status
Setup IN Data IN Data IN Data Status
(ACK or
(NAK)
STALL)

SW Actions
Set TxPktRdy
Set TxPktRdy Set TxPktRdy Set DataEnd or
Load FIFO
Load FIFO Load FIFO SendStall
W1C SetupPktRdy &
Set DPHTX
Unload command & means registers are set simultaneously

Figure 3-140 EP0 TX Mode Flow Chart

[Link].3.3 RX Mode

 Normal flow
 After receiving data packet (<=EP0CSR.MaxPktSz0), hardware sets [Link] and generates an interrupt.
 Software unloads data packet (<=EP0CSR.MaxPktSz0) from FIFO0 and W1C [Link].

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 If [Link] is set, [Link] is cleared automatically after data packet is unloaded, unless the
data packet is of a size of 0. Software needs to W1C [Link] under this condition.
 Software repeats the previous step until the required amount of data is received or a short packet is received, and
set [Link] to leave the DATA phase.

 Error cases
 If a SETUP transaction is received in the RX mode (DATA phase), [Link] is set and an interrupt is
generated. Software aborts the current command and moves on to decode the new command.

RX Mode

RxPktRdy
Set? No
(interrupt)

Yes

Read RxCount0
(value = N)

N>0

N=0
Read N bytes from
FIFO0

AutoClear
No Yes
Set?

W1C RxPktRdy (by SW) W1C RxPktRdy (by HW)

Protocol Error? No Last Packet No

Yes Yes

Set SendStall Set DataEnd

State -> IDLE

Return

Figure 3-141 EP0 RX Mode Flow Chart

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Sequence 2

Idle RX Mode Idle

Interrupt

Interrupt

Interrupt

Interrupt
IN Status
IN Status
Setup OUT Data OUT Data OUT Data (ACK or
(NAK)
STALL)

SW Actions
W1C SetupPktRdy W1C RxPktRdy W1C RxPktRdy W1C RxPktRdy Set DataEnd or
SendStall
Unload FIFO Unload FIFO Unload FIFO
Unload command

Figure 3-142 EP0 IDLE for RX Mode

[Link].4 QMU Top Programming Outline

The Queue Management Unit (QMU) is designed to unload software effort to serve DMA interrupts. By preparing GPD
(USB) and the Buffer Descriptor (BD), software links data buffers and triggers the QMU to send/receive data to the
host/from the device at a time.

[Link].4.1 GPD (USB) and BD Introduction

Figure 3-143 GPD (USB)/BD Bus Transfer

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Figure 3-144 GPD (USB)/BD with Extension

Item Description
 Must contain a pointer pointing to a data buffer.
BD  Capable of linking to another BD.
 Capable of extension. Data is placed in memory immediately after this BD.
 Must contain a pointer pointing to a data buffer if this GPD (USB) does not link to any BD.
 Capable of linking to several BDs.
 Capable of extension. Data is placed in memory immediately after this GPD (USB).
 Maps to a transfer on the USB. Data buffers are concatenated and transferred on the USB,
data packet by data packet. Each data packet is smaller than Maximum Packet Size (MPS).
GPD (USB)  The order data buffers are concatenated.
– GPD (USB) extension
– GPD (USB) data buffer
 For each BD in the chain
– BD extension
– BD data buffer

This section provides a brief description of BD and GPD (USB), with a comprehensive descriptor format presented in the
following section for a more thorough understanding.

[Link].4.2 TX GPD (USB)/BD Format

Figure 3-145 shows the format of TX GPD (USB)/BD. For detailed description, refer to Section [Link].4.4 and [Link].4.5.

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Bit B B B B B
Location 31 24 16 8 0 offset
I B B H
NGPDP[35:32] DBBDP[35:32] GPD Check Sum O P D W 0x00
C S P O

Next GPD Pointer (NGPDP[31:0]) 0x04

BDP=0: Data Buffer (DBBDP[35:32]) 0x08

BDP=1 : BD Pointer
Z
L GPD Extension Length Data Buffer Length 0 x0C
P

Bit B B B B B
Location 31 24 16 8 0 offset
E
NBDP[35:32] DBP[35:32] BD Check Sum O 0x00
L

Next BD Pointer (NBDP[31:0]) 0x04

Data Buffer (DBP[31:0]) 0x08

BD Extension Length Data Buffer Length 0 x0C

Figure 3-145 TX GPD (USB)/BD Format

[Link].4.3 RX GPD (USB)/BD Format

Figure 3-146 shows the format of RX GPD (USB)/BD. For detailed description, refer to Section [Link].4.4 and [Link].4.5.

Bit B B B B B
Location 31 24 16 8 0 offset
I B B H
Allow Data Buffer Length GPD Check Sum O P D W 0x00
C S P O

Next GPD Pointer (NGPDP [31:0]) 0x04

BDP =0: Data Buffer

(DBBDP[31:0]) 0x08
BDP =1: BD Pointer

NGPDP DBBDP
Transferred Data Length 0x 0 C
[35:32] [35:32]

Bit B B B B B
Location 31 24 16 8 0 offset
E
Allow Data Buffer Length
BD Check Sum O 0x00
(DWORD Aligned )
L

Next BD Pointer (NBDP[31:0]) 0x04

Data Buffer (DBP[31:0]) 0x08

NBDP DBP
Transferred Data Length 0x 0 C
[35:32] [35:32]

Figure 3-146 RX GPD (USB)/BD Format

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[Link].4.4 GPD (USB) Field Description

Table 3-132 GPD (USB) Field Description

Field Description
Indicates the current ownership of this GPD, the associated BD(s) and the
associated data buffer(s).
Hardware Ownership (HWO)
 0: Software has the ownership.
 1: Hardware has the ownership.
 0: DWORD@0x8 points to a data buffer.
Buffer Descriptor Present (BDP)
 1: DWORD@0x8 points to a BD.
 0: Hardware does not skip this GPD if HWO = 1.
Bypass (BPS)
 1: Hardware skips this GPD if HWO = 1.
 0: Hardware does not issue an interrupt when this GPD (and the associated
BDs) is completed.
Interrupt On Completion (IOC)
 1: Hardware issues an interrupt when this GPD (and the associated BDs) is
completed.
Validates the contents of this GPD (USB).
 If TXQ_CS_EN/RXQ_CS_EN bit is set, an interrupt is issued when checksum
validation fails.
GPD (USB) Checksum
 Q_CS16B_EN decides the way in which the checksum value is calculated.
– 0: Over the first 12 bytes of this GPD (USB)
– 1: Over the first 16 bytes of this GPD (USB)
(RX only) Allow Data Buffer Length Indicates the length of the assigned data buffer.
 Value! = 0, pointing to the next GPD (USB).
Next GPD(USB) Pointer
 Value = 0, not pointing to any GPD (USB).
Data Buffer/BD Pointer Refer to BDP description.
(TX only) Data Buffer Length Indicates the length of the assigned data buffer.
 After receiving a transfer, the total length of data is written to this field.
(RX only) Transferred Data Length  If the total length of data is over 64 K, ‘0’ is written to this field. Software has to
sum up all BD “Transferred Data Length” to get the total length of data.
 0: Not to use the GPD (USB) extension feature.
(TX only) GPD (USB) Extension  1-255: Specifies the GPD (USB) extension buffer size. GPD (USB) extension
Length buffer is placed in memory immediately after this GPD (USB).
 Zero Length Packet (ZLP)

[Link].4.5 BD Field Description

Table 3-133 BD Field Description

Field Description
 0: Not the last BD in the chain. The next BD is pointed by “Next BD Pointer”.
End of List (EOL)
 1: The last BD in the chain.
B Checksum Validates the contents of this BD.

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Field Description
 If TXQ_CS_EN / RXQ_CS_EN bit is set, an interrupt is issued when checksum
validation fails.
 Q_CS16B_EN decides the way that checksum value is calculated.
– 0: Over the first 12 bytes of this BD.
– 1: Over the first 16 bytes of this BD.
(RX only) Allow Data Buffer
Indicates the length of the assigned data buffer.
Length
Next BD Pointer Point to the next BD. Refer to EOL description.
Data Buffer Point to data buffer
(TX only) Data Buffer Length Indicates the length of the assigned data buffer.
After receiving a transfer, the length of data transferred to the data buffer is written
(RX only) Transferred Data Length
to this field.
 0: Not to use BD extension feature.
(TX only) BD Extension Length  1-255: Specifies the BD extension buffer size. BD extension buffer is placed in
memory immediately after this BD.

[Link].5 TXQ Programming Flow

TX Mode
Async Stop Queue request

Software Software
Stop Queue TXQ Initialization

Attach GPD
Return Restart
(TXQCSRn.TXQ_START=1)

Hardware
TX Error(s) Interrupt
Execute GPD

Tx Empty Interrupt
Async Request

Attach GPD Additional Software

Yes
(TXQCSRn.TXQ_RESUME=1) Request? TX Error Handling

No

Return

Figure 3-147 TXQ Programming Flow

[Link].5.1 TXQ Initialization Flow

Refer to “MT8390 Register Map” for detailed register descriptions.

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Figure 3-148 TXQ Initialization Flow

[Link].5.2 TXQ Stop Queue Flow

During the operation of TXQ, certain scenarios may arise that require the software to halt the current transfer. In such
cases, there are two notification methods employed to inform the host.

 The first method involves explicitly notifying the host by STALLing EP.
 The second method involves implicitly notifying the host by sending a short packet to terminate the current transfer.

Regardless of the chosen notification method, it is essential for the host to perform error handling, and the device side
must initiate the TXQ restart procedure based on the specific application requirements.

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[Link].5.3 TXQ STALL (Recommended)

Start

Set [Link] to
notify host

Set TXQCSRn.TXQ_STOP to
stop TXQ

TXQCSRn.
No
TXQ_ACTIVE=0?

Yes

Use
EP_RST.EP_OUT_RST[n]
(EPCTRL) to reset EP

Attach GPD and restart TXQ

by TXQCSR n.TXQ_START
(Depend on Application)

Return

Figure 3-149 TXQ STALL Flow

[Link].5.4 TXQ Short Packet (I)

In this scenario, the host receives a ZLP, leading to the termination of the IN transfer. As EPOUT_RST is not utilized, data is
fetched before the TXQ is halted. Upon the resumption of the TXQ, the data may be transmitted to the host as required.

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Start

Set TXQCSR N.TXQ_STOP

to stop TXQ

TXQCSRn.
No
TXQ_ACTIVE=0?

Yes

Set [Link]=0

[Link]? Yes

Set [Link]=1

1st Set
[Link]
Yes
= 1 after Stop
Queue

No

Set [Link]=1

Restart TXQ by
TXQCSRn.TXQ_START

Return

Figure 3-150 TXQ Short Packet (I) Flow

[Link].5.5 TXQ Short Packet (II)

In this scenario, the device software must ensure that the short packet aligns with the description specified in GPD (USB)
to allow the host to receive the short packet and terminate the IN transfer. As EPOUT_RST is not employed, the data is
fetched before the TXQ is halted. Upon the resumption of the TXQ, the data may be transmitted to the host as required.

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Start

Set TXQCSR N.TXQ_STOP

to stop TXQ

TXQCSRn.
No
TXQ_ACTIVE=0?

Yes

[Link]? Yes

Set [Link]=0

Set [Link]=1

Set [Link]=1

Add short packet in GPD

and restart TXQ by
TXQCSRn.TXQ_START

Return

Figure 3-151 TXQ Short Packet (II) Flow

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[Link].5.6 TXQ Error Handling Flow

Start

Receive Error Interrupt

Set TXQCSRn.TXQ_STOP to
stop TXQ

Wait TXQCSR N.
No
TXQ_ACTIVE = 0?

Yes

Software Checks Error Type

&
Clear Error flag

Use
EP_RST.EP_OUT_RST[n]
(EPCTRL) to reset EP

Attach GPD and restart TXQ

by TXQCSR n.TXQ_START
(Depend on Application)

Return

Figure 3-152 TXQ Error Handling Flow

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[Link].5.7 TXQ GPD (USB) Execution Flow

TXQn empty interrupt

TXQn done interrupt. Base on IOC

TXQn checksum error interrupt

TXQn length error interrupt Start

TXQn endpoint error interrupt

Follow GPD
Get GPD
NextGPDPtr Any Bus Transaction Errors

Update GPD
HWO=0 &&
Execute IOC
No GPD HWO=1? Software
(*2)
TX Error Handling

Yes

Return Comments:
No (*1): When BDP = 0, length error interrupt asserts if GPD ExtLen
= 0 & BufLen = 0
Yes GPD BPS=1? (*2): Interrupt asserts after HWO is cleared
(*3): length error interrupt asserts if BD ExtLen = 0 & BufLen = 0
(*D): Data will be concatenated, split into data packets (size <=
TxMaxPktSz), and transferred

GPD checksum &

length correct? (*1) Follow GPD BDPtr

Yes

No GPD ExtLen=0? Yes Get BD

Transfer GPD ExtLen Bytes

of Data, starting from GPD Yes
address+0x10 to buffer
(*D)

BD checksum &
No
GPD BD=1? length correct? (*3)

Software
No Yes
TX Error Handling

BD ExtLen!=0? Yes
Yes GPD BufLen=0?

Transfer BD ExtLen Bytes of

No No Data, starting from BD
address+0x10 to buffer (*D)

Transfer BD BufLen Bytes of

Data from BD BufPtr to
Transfer GPD BufLen Bytes
buffer(*D)
of Data from GPD BufPtr to
buffer(*D)

Yes BD EOL=1? No

Follow BD NextBDPtr

Figure 3-153 TXQ GPD (USB) Execution Flow

Note that if a "bus transaction error" occurs, the TXQn endpoint error interrupt is asserted. The bus transaction error shall
not occur in the normal case.

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[Link].6 RXQ Programming Flow

RX Mode
Async Stop Queue request

Software Software
Stop Queue RXQ Initialization

Attach GPD/BD
Return Restart
(RXQCSRn.RXQ_START=1)

Hardware
RX Error(s) Interrupt
Execute GPD

Rx Empty Interrupt
Async Request

Attach GPD/BD Additional Software

Yes
(RXQCSRn.RXQ_RESUME=1) Request? RX Error Handling

No

Return

Figure 3-154 RXQ Programming Flow

Refer to “MT8390 Register Map” for detailed register descriptions.

Figure 3-155 RXQ Initialization Flow

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[Link].6.1 RXQ Stop Queue Flow

During the operation of RXQ, certain scenarios may arise that require the software to halt the current transfer. In such
cases, there are two notification methods employed to inform the host.

 The first method involves explicitly notifying the host by STALLing EP.
 The second method involves silently dropping packets.

In the first case, the host must perform error handling. Upon the resumption of the RXQ, the device side initiates the
restart procedures based on the specific application requirements.

[Link].6.2 RXQ STALL (Recommended)

Start

Set [Link] to
notify host

Set RXQCSRn.RXQ_STOP to
stop RXQ

RXQCSRn.
No
RXQ_ACTIVE=0?

Yes

Use EP_RST.EP_IN_RST[n]
(EPCTRL) to reset EP

Attach GPD and restart RXQ

by RXQCSR n.RXQ_START
(Depend on Application)

Return

Figure 3-156 RXQ STALL Flow

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[Link].6.3 RXQ Drop Packet

The device may experience reception errors due to the interruption and resumption of RXQ while the host is engaged in an
OUT transfer. During this process, some packets may be dropped, thereby corrupting the received data. To mitigate this
issue, the device must perform error handling procedures.

Start

Set RXQCSR.RXQ_STOP to
stop RXQ

RXQCSRn.
No
RXQ_ACTIVE=0?

Yes

[Link]
Yes
Y?

W1C [Link]

Restart RXQ by
RXQCSRn.RXQ_START

Return

Figure 3-157 RXQ Drop Packet Flow

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[Link].6.4 RXQ Error Handling Flow

Start

Receive Error Interrupt

Set RXQCSRn.RXQ_STOP to
stop RXQ

Wait RXQCSR N.
No
RXQ_ACTIVE = 0?

Yes

Software Checks Error Type

&
Clear Error flag

Use EP_RST.EP_IN_RST[n]
(EPCTRL) to reset EP

Attach GPD and restart RXQ

by RXQCSR n.RXQ_START
(Depend on Application)

Return

Figure 3-158 RXQ Error Handling Flow

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[Link].6.5 RXQ GPD (USB) Execution Flow

RXQn empty interrupt

RXQn done interrupt. Base on IOC

RXQn checksum error interrupt

RXQn length error interrupt

Start

RXQn endpoint error interrupt

Follow GPD
Get GPD
NextGPDPtr Any Bus Transaction Errors

Update GPD
HWO=0 &&
Execute IOC Software
(*1) No GPD HWO=1? RX Error Handling

Return Comments:
Yes (*1): Interrupt asserts after HWO is cleared
No (*2): BD Transfer Length <= BD AllowLen
(*3): Update GPD Transfer Length with 0, if Total Transfer Length
Yes GPD BPS=1? > 65535
(*D): Data receiving is terminated if
I. Short packet is received, or
II. Received Total Data Length / Data Length reaches GPD / BD
No AllowLen

GPD checksum
Follow GPD BDPtr
correct?

Yes
Yes

GPD BDP=1? Get BD

Software
No RX Error Handling

BD checksum No
Yes GPD AllowLen=0? correct & BD
AllowLen!=0?
Data length > GPD AllowLen
Software &
RX Error Handling No Yes BD EOL=1

Total Data length > Transfer GPD AllowLen Transfer BD AllowLen Bytes
GPD AllowLen Bytes of Data to GPD BufPtr of Data to BD BufPtr
(*D) (*D)
Follow BD
NextBDPtr
Total Data length=GPD AllowLen Data length=BD AllowLen
or or
Short Packet Received Short Packet Received
Update Total
Transfer Length to
GPD Update Transfer
Short Packet Data length=
(*3) Length to BD
Received BD AllowLen
(*2)

Yes BD EOL=1? No

Figure 3-159 RXQ GPD (USB) Execution Flow

Note that if a "bus transaction error" occurs, the RXQn endpoint error interrupt is asserted. The bus transaction error shall
not occur in the normal case.

[Link] Interrupt Top Programming Outline

1. Adopt the multi-level interrupt architecture.

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Figure 3-160 Interrupt Architecture

Refer to “MT8390 Register Map” for interrupt occurrence conditions.

Generally, there are two kinds of interrupt occurrence conditions:

Condition Description
For the USB device, each EP has its own independent interrupt status bit, in order
Endpoint TX/RX INT (0x80)
to indicate which EP interrupt occurs.
The USB device does the transfer by QMU block. At QMU, software needs to fill
GPD (USB) or BD to queue transfer.
TXQ Err INT (0x780,0x790):
TXQ Err INT (0x780,0x790),  TX Queue GPD (USB)/BD Checksum Error
RXQ Err INT(0x7c0,0x7d0)  TX Queue GPD (USB) Data Buffer Length Error
 RXQ Err INT (0x7c0,0x7d0):
 RX Queue Generic Packet Descriptor Checksum Error
 RX Queue Generic Packet Descriptor Data Buffer Length Error

2. ISR (USB)

 Only ISR (USB) in “leaf” node can be W1C; ISR (USB) in “non-leaf” node is RU.
 “Leaf” node ISR (USB) should be W1C to clear ISR (USB) in “non-leaf” node after the corresponding events are served.

3. IER (Interrupt Enable Register)

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The IER can be set/cleared by writing 1 to Interrupt Enable Set Register (IESER)/Interrupt Enable Clear Register (IECR),
except for MAC2_INTR/MAC3_INTR/EP_CTRL_INTR.

 If the low level IER is not set, when an event happens, it is reflected in the low level ISR (USB), but not the high level ISR
(USB) (as shown in the left side of the figure below).
 If the low level IER is set, when an event happens, it is reflected in the low level ISR (USB) and high level ISR (USB) (As
shown in the right side of the figure below)

Level-2 Interrupt is not

Level-2 Interrupt is Enabled
Enabled

Level-1 Int Event 0 Level-1 Int Event 1

Level-2 Int Event 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Level-2 Int Event 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Level-2 Int Enable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Level-2 Int Enable 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Figure 3-161 Example Interrupt Setting

[Link].1 Queue Management Unit (QMU) Interrupt Architecture

Figure 3-162 QMU Interrupt Layer

A queue has different behaviors for different TX/RX interrupts.

Interrupt Behavior
 A queue does not stop when
 A queue is completed when GPD is done with IOC = 1.
TX  A queue stops when
 A queue is empty.
 There is a queue, checksum, or length error.
 A queue does not stop when
 A queue is completed when GPD is done with IOC = 1.
 There is a queue or ZLP error.
RX
 A queue stops when
 A queue is empty.
 There is a queue, checksum, or length error.

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The figure below depicts the related status/mask/mask set/mask clear registers for each group.

31 0
0x700
QISAR0
(RU/W1C) Bitwise QMU Group 0
0x704 AND
QIER0
(RO)

0x708 W1S
0x70C W1C

31 0
0x710
QISAR1
(RU/W1C) Bitwise QMU Group 1
0x714 AND
QIER1
(RO)

0x718 W1S
0x71C W1C

31 0
0x740
QEMIR
(RU/W1C) Bitwise QMU Group 2
0x744 AND
QEMIER
(RO)

0x748 W1S
0x74C W1C

QMU Group 3
31 0
0x780
TQERRIR0
(RU/W1C) Bitwise
0x784 AND
TQERRIER0
(RO)

0x788 W1S
0x78C W1C

QMU Group 4
31 0 31 0
0x7C0 0x7D0
RQERRIR0 RQERRIR1
(RU/W1C) (RU/W1C) Bitwise
0x7C4 0x7D4 AND
RQERRIER0 REQERRIER1
(RO) (RO)

0x7C8 W1S 0x7D8 W1S

0x7CC W1C 0x7DC W1C

Figure 3-163 Interrupts Status/Mask/Mask Set/Mask Clear

[Link] Power Saving Scenario

In order to conserve power, USB provides registers for software to power down the unnecessary hardware parts.

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Figure 3-164 Power Saving Flow: Initial

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Figure 3-165 Power Saving Flow: SuperSpeed

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Figure 3-166 Power Saving Flow: High-speed and Full-speed

[Link].1 LPM Recommended Setting

 lpm_mode = 0 and lpm_hrwe = 0: Normal LPM mode, enable hardware remote wakeup.

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 SSUSB_DEV.MAC_U2_EN_CTRL [20:16] = 0x1f: Enable LPM to accept check and accept LPM request when all QMU/EP
are inactive.

For Bulk transfer:

 OUT EPs: Enable L1_EXIT_EP_OUT_CHK and L1_EXIT_EP_OUT_FC_CHK.
 IN EPs: Enable L1_EXIT_EP_IN_CHK and L1_EXIT_EP_IN_FC_CHK.
 EP0: Enable L1_EXIT_EP0_CHK and L1_EXIT_EP0_FC_CHK.

Therefore, the device can resume the bus as long as EP FIFO is ready, and the flow control assures that the EP has data to
transfer or accept.

For periodic (isochronous/interrupt) EPs, the host can easily predict the point to send/receive data. Therefore, it is better
for the host to determine the time point to resume the bus and process transfers. It is suggested to disable
L1_EXIT_EP_OUT_CHK and L1_EXIT_EP_IN_CHK for periodic EPs.

[Link] USB Device Reset Mode

Table 3-134 Reset Sequence of USB Device Mode

Step Address Register Name Local Address R/W Value Description
Toggle USB software reset
USB Software Reset.
ssusb_sifslv_ippc_Base When this bit is set, the whole USB is
1 SSUSB_IP_PW_CTRL0 SSUSB_IP_SW_RST [0] W 1’b1
address + 0x0000 reset.
Write “0” to release reset.
2 Delay 1µs
USB Software Reset.
ssusb_sifslv_ippc_Base When this bit is set, the whole USB is
3 SSUSB_IP_PW_CTRL0 SSUSB_IP_SW_RST [0] W 1’b0
address + 0x0000 reset.
Write “0” to release reset.
Check reset status
When this bit is 1'b1, it means that
ssusb_sifslv_ippc_Base SSUSB_U2_MAC_SYS_RST_
1 SSUSB_IP_PW_STS2 R reset for mac2_sys_ck domain is
address + 0x0014 B_STS [0]
inactive.
When this bit is 1'b1, it means that
ssusb_sifslv_ippc_Base SSUSB_U3_MAC_RST_B_ST
2 SSUSB_IP_PW_STS1 R reset for mac3_mac_ck domain is
address + 0x0010 S [16]
inactive.
When this bit is 1'b1, it means that
ssusb_sifslv_ippc_Base SSUSB_DEV_QMU_RST_B_
3 SSUSB_IP_PW_STS1 R reset for device QMU sys_ck domain is
address + 0x0010 STS [1]
inactive.
When this bit is 1'b1, it means that
ssusb_sifslv_ippc_Base SSUSB_DEV_BMU_RST_B_
4 SSUSB_IP_PW_STS1 R reset for device BMU sys_ck domain is
address + 0x0010 STS [2]
inactive.
When this bit is 1'b1, it means that
ssusb_sifslv_ippc_Base
5 SSUSB_IP_PW_STS1 SSUSB_DEV_RST_B_STS [3] R reset for device excluding BMU and
address + 0x0010
QMU sys125_ck. domain is inactive.

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[Link].1 Address Reset

When the following conditions happen, the device address is reset to 0.

 USB 2.0
 Upon receiving bus reset
 USB 3.1 Gen1
 When entering the “Polling” state
 When receiving a warm Reset, and then entering the “Polling” state.
 When receiving a hot reset.

[Link].2 EP Reset

The EPs are reset by hardware when the following conditions happen.

 USB 2.0
 Upon receiving bus reset
 Reset
 Data toggle
 FIFO pointer (FIFO address register is not touched)
 EP flow control status
 USB 3.1 Gen1
 When entering the “Polling” state
 When receiving a warm reset, and then entering the “Polling” state.
 When receiving a hot reset.
 Reset
 EP sequence number
 EP flow control status
 EP packet pending status
 EP packet counter
 EP active status
 FIFO pointer (FIFO address register is not touched.)

The following commands may affect the EP application and its configuration.
 SET_CONFIGURATION
 SET_INTERFACE
 CLEAR_FEATURE ENDPOINT_HALT

Therefore, the software can do the following operations before EP re-configuration:

 Use bits in the register of EP_RST to reset each EP.
 Stop the corresponding queue(s).

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[Link] EPn MCU Mode Top Programming Outline (BULK Interrupt Mode Only)

[Link].1 EPn MCU Mode TX Programming Flow

 [Link] defines the maximum packet size (in bytes). Software can load data into FIFOn at a time.
 IN transfer flow
a. Software checks whether FIFOn is full. If not, software loads a data packet to FIFOn, and sets [Link].
b. After a data packet is sent to the host, an interrupt is generated to notify software to repeat the operation until all
data is sent to the host.

TX Mode

FIFOFull? Yes

No

Protocol Error? Yes Set SendStall

No

Write ≤ TxMaxPktSz bytes

to
FIFOn
(n = 1~15)

SW Set TxPktRdy

Yes More Data?

No

Return

Figure 3-167 EPn MCU Mode TX Programming Flow

[Link].2 EPn MCU mode RX Programming Flow

 [Link] defines the maximum packet size (in bytes). Software can load data from FIFOn at a time.
 OUT transfer flow:
1. [Link] is set and an interrupt is generated to notify software.
2. Software reads RXnCSR3.EP_RX_COUNT, unloads RXnCSR3.EP_RX_COUNT bytes from FIFOn and W1C
[Link].
3. Software repeats operation until there is no more data.

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RX Mode

RxPktRdy Set?
No
(Interrupt)

Yes

Read EP_RX_COUNT
(value=M)

M>0

Read M bytes from

M=0
FIFOn
(n = 1 ~ 8)

SW W1C RxPktRdy

Protocol Error? Yes

Set SendStall
No

Return

Figure 3-168 EPn MCU Mode RX Programming Flow

[Link] Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

[Link] References

 Protocol
 Universal Serial Bus 3.1 Specification, Revision 1.0, July 26, 2013
 Universal Serial Bus Specification, Revision 2.0, April 27, 2000
 Extensible Host Controller Interface (xHCI) for Universal Serial Bus, Revision 1.1,12/20/2013
 PHY
 PHY Interface for the PCI Express, SATA, and USB 3.1 Architectures, Version 4.3
 UTMI+ Specification, Revision 1.0, February 25th, 2004
 Bus
 AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite, 28 October 2011

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[Link] USB 3.1 PHY Overview

The PHY is responsible for managing the low-level protocol and signaling functions. This includes data serialization and de-
serialization, 8b/10b encoding/decoding (5 Gbps), analog buffers, elastic buffers and receiver detection.

The controller interfaces with the PHY via a PIPE (SuperSpeedPlus) interface. The PIPE supports 32 bits * 125 MHz (5 Gbps).

[Link] Features

 Fully compliant with USB 3.1 Specification

 Electrical sub-blocks support 5.0 GT/s operation, which is compliant with USB 3.1 electrical specification.
 Fully compliant with PHY interface for the USB Architectures (PIPE), Version 4.3
 Utilizes the 32-bit parallel interface for 5.0 GT/s.

[Link] Block Diagram

USB3.1 MAC

PIPE Interface

8b/10b 128b/132b 8b/10b

Encoder Encoder Decoder

Gen1 Elastic Gen2 Elastic

Buffer Buffer

Block Align
Symbol Lock 128b/132b Decoder

Parallel to
Serial Serial to
Parallel

CDR

RX Receiver
TX Driver
and Equalizer

TXP TXN RXP RXN

AHB I2C

Figure 3-169 Block Diagram of USB 3.1 Gen1 PHY

Figure 3-169 displays the USB3.1 PHY block diagram, which comprises two main sub-modules: the Physical Layer Analog
Block (PHYA) and the Physical Layer Digital Block (PHYD).

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 The PHYA includes:

 The TX driver, which outputs differential pair signals.
 The RX front-end, which receives differential pair data.
 The CDR, which recovers timing information from the serial data stream.
 Serializer and de-serializer, which convert data between the serial and parallel data interfaces in each direction.

 The PHYD includes:

 8b/10b encoder and decoder (for 5.0 GT/s)
 Elastic buffers, which compensate for differences in frequencies between bit rates at the ends of a link.

For the FT/debug mode, the I2C interfaces (sif_scl, sif_sdin, sif_sdout, and sif_sden) of the PEXTP_PHY_TOP connection
should be verified and controlled through the pin. In addition, in the FT/debug mode, the Schmitt trigger should be
enabled at the pads of I2C SDA/SCL. Refer to Figure 3-170 for the I2C signal connection.

PAD I2C SDA

sif_sdin

sif_sdout

sif_sden

Figure 3-170 Connection of I2C Signals

[Link] Electrical Characteristics

The SSUSB electrical characteristics are compatible with USB 3.1 Specification Revision 1.1.

Table 3-135 USB 3.1 Spread Spectrum Clock (SSC) Electrical Characteristics
Description Min. Typ. Max. Unit
SSC modulation rate 30 - 33 kHz
SSC deviation +0/-4000 (Gen 1) - +0/-5000(Gen 1) ppm
Note:
 Refer to USB 3.1 Specification Revision 1.1, Section 6.5.4, Table 6-17.

Table 3-136 USB 3.1 Gen1 Transmitter and Receiver Electrical Characteristics
Description Min. Typ. Max. Unit
Transmitter Parameters
Data rate 10 GT/s
Unit interval* 199.94 (Gen 1) - 200.06 (Gen 1) ps
TX differential peak to peak voltage swing 0.8 1 1.2 V
TX eye width 0.625 (Gen 1) - - UI

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Description Min. Typ. Max. Unit

DC differential TX impedance 72 - 120 Ω
TX AC common mode voltage active - - 100 mV
SSC maximum slew rate - - 10 ms/s
Receiver Parameters
LFPS detect threshold 100 - 300 mV
DC differential RX impedance 72 - 120 Ω
Note:
 Do not account for SSC caused variations. Refer to USB 3.1 Specification Revision 1.1, Section 6.7.1, Table 6-18, Table 6-19.

[Link] Interface Signal

[Link].1 Analog Pads

Signal Name Input/Output Description

PAD_SSUSB_RXN_P1/2 Inout Analog PAD, Lane0/1 RX-
PAD_SSUSB_RXP_P1/2 Inout Analog PAD, Lane0/1 RX+
PAD_SSUSB_TXN_P1/2 Inout Analog PAD, Lane0/1 TX-
PAD_SSUSB_TXP_P1/2 Inout Analog PAD, Lane0/1 TX+
PAD_XTP_GLB_CKP Inout Analog PAD, Ref 100MHz CK+
PAD_XTP_GLB_CKN Inout Analog PAD, Ref 100MHz CK-

[Link].2 Clock and Testing

Signal Name Input/Output Description Note

ANA_OLT Input Stress test mode Reserved. Tied to 0.
ANA_SCAN Input Analog scan signal
Monitor analog signal
AD_XTP_GLB_*_OLT_* Output
by LED
DA_XTP_GLB_*_SCAN_* Analog scan signals
Analog LDO reference Provide HTOL VREF if needed. Otherwise,
ADA_XTP_GLB_LDO_VREF Input
voltage for HTOL. connect to ADA_XTP_GLB_TIELO_12.
Analog low signal for
ADA_XTP_GLB_TIELO_12 Output unused input-type
ADA_*.
ADA_XTP_GLB_MOUNT Inout Analog debug signal
Analog power-on
ADA_XTP_GLB_POR_RSTB_15 Inout 1.5V power domain.
reset
Provide 26 MHz clock if needed.
Ref 26 MHz CK from
ADA_CKM_XTAL_CK Input Otherwise, connect to
analog module
ADA_XTP_GLB_TIELO_12.

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Signal Name Input/Output Description Note

Ref 26 MHz CK from Provide 26 MHz clock if needed.
DA_CKM_XTAL_CK Input
digital module Otherwise, tie 0.
 1: Scan mode.
scan_mode Input Scan Related
 0: Function mode.
scan_500m_ck Input Scan 500 MHz clock 500 MHz clock for ATPG test.
scan_312p5m_ck Input Scan 312.5 MHz clock 312.5 MHz clock for ATPG test.
scan_625m_ck Input Scan 625 MHz clock 625 MHz clock for ATPG test.
scan_enable Input Scan related Scan shift enabled.
scan_enable_cg Input Scan related Clock gating enable during scan shifting.
System reset. It should be combined with
ext_pwr_rst_b Input Power on reset
software reset.
Reference clock type
(ref_ck)
3’d0: 20 MHZ
sspxtp_sys_ck_type Input 3’d1: 24 MHZ
3’d1: 25 MHZ
3’d2: 26 MHZ
3’d3: 27 MHZ
Reference clock,
should follow
ref_ck Input
sspxtp_sys_ck_type
setting frequency.
sspxtp_ckm_en Output CKM control signal
sspxtp_ckm_intck_req Output CKM request signal
sspxtp_ckm_padck_req Output CKM request signal
USB low power state
sspxtp_sleep Output
signal
 For debug mode: Confirm whether
sspxtp_dig_top/sspxtp_probe[15:0] can
SSUSB probe out be output correctly.
sspxtp_probe[15:0] Output
signal  For FT mode: Confirm whether
sspxtp_dig_top/sspxtp_probe[15:0] can
be output correctly.

[Link].3 I2C

Signal Name Input/Output Description Note

SSUSB register control mode
 Should be 1’b0 by default in normal
selection
sspxtp_i2c_mode Input mode. Should be controlled by the chip.
 1'b0: AHB mode
 Should be set to 1'b1 in FT mode.
 1'b1: I2C mode

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Signal Name Input/Output Description Note

Request I2C device address. Device address
sspxtp0_saddr[6:0] Input I2C device address
is 7’h51.
sspxtp0_sclk Input I2C SCLK
sspxtp0_sdin Input I2C SDIN
Refer to Figure 3-170.
sspxtp0_sdout Output I2C SDOUT
sspxtp0_sden Output I2C SDEN

[Link].4 AHB

Signal Name Input/Output Description Note

mcu_bus_ck Input AHB interface clock for SSUSB Connected to the CPU bus
sspxtp_phy_slv_hsel Input AHB interface Connected to the CPU bus
sspxtp_phy_slv_hwrite Input AHB interface Connected to the CPU bus
sspxtp_phy_slv_htrans[1:0] Input AHB interface Connected to the CPU bus
sspxtp_phy_slv_hsize[1:0] Input AHB interface Connected to the CPU bus
sspxtp_phy_slv_haddr[31:0] Input AHB interface Connected to the CPU bus
sspxtp_phy_slv_hwdata[31:0] Input AHB interface Connected to the CPU bus
sspxtp_phy_slv_hready_in Input AHB interface Connected to the CPU bus
sspxtp_phy_slv_hresp Output AHB interface Connected to the CPU bus
sspxtp_phy_slv_hready Output AHB interface Connected to the CPU bus
sspxtp_phy_slv_hrdata[31:0] Output AHB interface Connected to the CPU bus

[Link].5 PHY to MAC PIPE Interface

Signal Name Input/Output Description Note

sspxtp_pipe0_rst_b Input PIPE signal Connect to USB MAC

sspxtp_pipe0_disable Input PIPE signal Connect to SUB MAC
sspxtp_pipe0_rate Input PIPE signal Connect to USB MAC
sspxtp_pipe0_powerdown[1:0] Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_detectrx Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_elecidle Input PIPE signal Connect to USB MAC

sspxtp_pipe0_rx_term Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_deem[17:0] Input PIPE signal Connect to USB MAC

sspxtp_pipe0_enc_dec_bypass Input PIPE signal Connect to USB MAC

sspxtp_pipe0_block_align_ctrl Input PIPE signal Connect to USB MAC

sspxtp_pipe0_rx_eq_training Input PIPE signal Connect to USB MAC

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Signal Name Input/Output Description Note

sspxtp_pipe0_rx_polarity Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_oneszeros Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_data_valid Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_sync_header[3:0] Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_start_block Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_datak[3:0] Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_data[31:0] Input PIPE signal Connect to USB MAC

sspxtp_pipe0_tx_data[31:0] Input PIPE signal Connect to USB MAC

sspxtp_pipe0_phystatus Output PIPE signal Connect to USB MAC

sspxtp_pipe0_rx_valid Output PIPE signal Connect to USB MAC
sspxtp_pipe0_rx_elecidle Output PIPE signal Connect to USB MAC
sspxtp_pipe0_rx_status[2:0] Output PIPE signal Connect to USB MAC
sspxtp_pipe0_sync_header[3:0] Output PIPE signal Connect to USB MAC
sspxtp_pipe0_rx_data_valid Output PIPE signal Connect to USB MAC
sspxtp_pipe0_rx_start_block Output PIPE signal Connect to USB MAC
sspxtp_pipe0_rx_data[31:0] Output PIPE signal Connect to USB MAC
sspxtp_pipe0_rx_datak[3:0] Output PIPE signal Connect to USB MAC

3.12.5 Ethernet Network Interface Controller (ENIC)

[Link] Overview
Ethernet Network Interface Controller (ENIC) enables a host to transmit and receive data over Ethernet in compliance with
the IEEE 802.3-2015.

[Link] Features

The device features one ENIC, supporting the following key features:

Standard compliance:
 MII/RMII/RGMII
 IEEE 802.3-2015 for Ethernet MAC
 IEEE 1588-2008 for precision networked clock synchronization
 IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic
 IEEE 802.1Qbv-2015, 802.1Qbu-2016, and 802.1AS-Rev D5.0 for Time-Sensitive Networking (TSN) traffic
 IEEE 802.3az-2010 for Energy Efficient Ethernet (EEE)
MAC features:
 10/100/1000 Mbps speed mode
 Half-duplex operation:

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 Support of CSMA/CD protocol

 Support of flow control using backpressure
 Full-duplex flow control operation (IEEE 802.3x pause packets and priority flow control)
 Receive:
 Automatic pad and CRC stripping options
 Preamble and Start Frame Delimiter (SFD) deletion
 Option to disable automatic CRC checking
 Flexible address filtering modes:
 Up to 31 additional 48-bit destination address filters with masks for each byte
 Up to 31 x 48-bit source address comparison check with masks for each byte
 256-bit hash filter for multicast and unicast destination addresses
 Option to pass all multicast addressed packets
 Promiscuous mode to pass all packets without any filtering for network monitoring
 Additional packet filtering:
 VLAN tag-based: Perfect match and hash-based filtering. Filtering based on either outer or inner VLAN tag is
possible.
 Layer 3 and Layer 4-based: TCP or UDP over IPv4 or IPv6
 Extended VLAN tag based with 4 filters selection
 Transmit:
 Automatic pad and CRC generation control ability on a per-packet basis
 Preamble and start of packet data insertion
 Programmable packet length to support standard or jumbo Ethernet packets of up to 16 KB
 Programmable inter packet gap (40-bit to 96-bit times in steps of 8)
 IEEE 802.3x flow control automatic transmission of zero-quanta pause packet when the flow control input
transitions from assertion to de-assertion (in full-duplex mode)
 Source address field insertion or replacement, and VLAN insertion, replacement, and deletion in transmitted
packets with per-packet or static-global control
 Insertion, replacement, or deletion of up to two queue/channel-based VLAN tags

MAC Transaction Layer (MTL) features:

 Receive:
 16KB RX FIFO and 4 RX queues
 Transmit:
 16KB TX FIFO and 4 TX queues
 Store-and-forward mechanism or threshold mode (cut-through) for transmission to the MAC
 Calculate and insert IPv4 header checksum and TCP, UDP, or ICMP checksums
 Scheduling algorithms:
 Weighted Round Robin (WRR)
 Strict Priority (SP)
 Credit-Based Shaper (CBS) when audio-video bridging is enabled
Clause 22 and Clause 45 MDIO master interface for PHY configuration and management

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[Link] Block Diagram

This section provides a block diagram to illustrate the main components and functions of the module. An AXI Master
interface is connected to all DMA channels. The DMA arbiter provides help in arbitration of all the paths (Transmit and
Receive) in all channels. Each channel has a separate set of Control and Status registers (CSR) for managing the Transmit
and Receive functions, descriptor handling, and interrupt handling.

Figure 3-171 Block Diagram of ENIC

[Link] Function Description

[Link].1 Functions of IP

 AXI Master Interface

The AXI is designed to integrate with AMBA AXI bus on the application side. The AXI transfers the data to and from the
system memory through AXI master interface.

 APB Slave Interface

The host CPU uses the APB slave interface to access the Control and Status registers (CSRs) of ETHER_QOS.

 PHY Interface
ETHER_QOS supports the following PHY interfaces:
 Reduced GMII (RGMII)
 Media Independent Interface (MII)
 Reduced MII (RMII)

 DMA
The DMA has independent TX and RX engines, and a CSR space. The TX engine transfers data from the system memory
to the device port (MTL), whereas the RX engine transfers data from the device port to the system memory. The DMA

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engine uses descriptors to efficiently move data from source to destination with minimal application CPU intervention.
The DMA is designed for packet-oriented data transfers such as packets in Ethernet. The DMA controller can be
programmed to interrupt the application CPU for situations such as Packet Transmit and Receive Transfer completion,
and other normal or error conditions.

The DMA and the application communicate through the following two data structures:

 Control and Status registers (CSR)

 Descriptor lists and data buffers

The DMA supports up to 4 TX and 4 RX Descriptor lists (or DMA channels). The base address of each list is written to
the respective TX Descriptor List Address register and RX Descriptor List Address register. The descriptor list is forward
linked and the next descriptor is always considered at a fixed offset to the current one. The offset is controlled by the
DSL field of DMA_Ch[n]_Control register. The number of descriptors in the list is programmed in the respective TX (or
RX) Descriptor Ring Length register. Once the DMA processes the last descriptor in the list, it automatically jumps back
to the descriptor in the List Address register to create a descriptor ring. Note that the 4 TX and 4 RX queues can be
controlled by multiple CPUs. The application should set access right protection in APMIXED.

The descriptor lists reside in the physical memory address space of the application. Each descriptor can point to a
maximum of two buffers in the system memory. This enables two buffers to be used, physically addressed, rather than
contiguous buffers in memory.

A data buffer resides in the application physical memory space and consists of an entire packet or part of a packet but
cannot exceed a single packet. Buffers only contain data. Buffer status is maintained in the descriptor. Data chaining
refers to packets that span multiple data buffers. However, a single descriptor cannot span multiple packets. The DMA
skips to the data buffer of the next packet when EOP is detected.

 Transaction Layer (MTL)

The MAC Transaction Layer (MTL) provides the FIFO memory interface to buffer and regulate the packets between the
application system memory and the MAC. It also enables the data to be transferred between the application clock and
MAC clock domains. The MTL layer has two data paths: Transmit path and Receive path.

 MAC
The MAC supports RGMII/MII/RMII towards the PHY chip. The PHY interface can be selected only once after reset.

[Link] Theory of Operations

[Link].1 Ethernet Frame Formats

The IEEE 802.3 standard defines the Ethernet frame format as follows: An Ethernet frame has a minimum length of 64
bytes and a maximum length of 1518 bytes, excluding the preamble and the SFD bytes. An Ethernet frame consists of the
following fields:

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Figure 3-172 Ethernet Frame Format without VLAN Tag

Optional MAC frames can be VLAN tagged with an additional 4-bytes field (VLAN tag and VLAM info) inserted between the
MAC Source Address and the Length/Type Field. VLAN tagging is defined by the IEEE P802.1q specification.

VLAN Tagged Ethernet Frame Format is as follows.

Figure 3-173 Ethernet Frame Format with VLAN Tag

[Link].2 Pause Frames

The IEEE 802.3 defined pause frame has the following format:

Figure 3-174 Pause Frame Format

There is no Payload Length field found within a pause frame and a pause frame is always padded with 42 bytes (0x00).
If a pause frame with a pause value greater than zero (XOFF Condition) is received, the MAC stops transmitting data as
soon as the current frame transfer is completed. The MAC stops transmitting data for the value defined in pause quanta.
One pause quanta fraction refers to 512-bit times.

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If a pause frame with a pause value of zero (XON Condition) is received, the transmitter is allowed to send data
immediately.

[Link].3 Line Interfaces

The Core implements an MII for 10/100 Mbps, an RMII for 10/100 Mbps, and an RGMII for 10/100/1000 Mbps mode of
operation.

[Link].4 MII for 10M/100M MAC

On Transmit, all data transfers are synchronous to tx_clk rising edge. The MII data enable signal txen_o is asserted to
indicate the start of a new frame and remains asserted until the last byte of the frame is present on txd_o(3:0) bus.
Between frames, txen_o remains de-asserted.

Figure 3-175 MII Transmit Waveform

If a frame experiences internal errors the frame is subsequently transmitted with the MII mii_txer error signal for one
clock cycle at any time during the packet transfer.

Figure 3-176 MII Transmit Waveform with Error Occurring

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On receive, all signals are sampled on the rx_clk rising edge. The MII data enable signal rxdv_i is asserted by the
PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on rxd_i(3:0)
bus. Between frames, rxdv_i remains de-asserted.

Figure 3-177 MII Receive Waveform

If the PHY detects an error on the frame received from the line, the PHY asserts the MII error signal, rxer_i, for at least
one clock cycle at any time during the packet transfer.

[Link].5 RGMII for 10M/100M/1000M

On Transmit for 1000M, all data transfers are synchronous to tx_clk rising edge or tx_clk falling edge. The GMII data
enable signal txen_o is asserted to indicate the start of a new frame and remains asserted until the last byte of the
frame is present on txd_o(3:0) bus. Between frames, txen_o remains de-asserted.

Figure 3-178 RGMII Transmit Waveform in 1000M

If a frame experiences internal errors, the frame is subsequently transmitted with txen_o de-asserting synchronous to
tx_clk rising edge or tx_clk falling edge at any time during the packet transfer.

Figure 3-179 RGMII Transmit Waveform with Error Occurring in 1000M

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On receive for 1000M, all signals are sampled on rx_clk rising edge or rx_clk falling edge. The RGMII data enable
signal rxdv_i is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the
frame is present on rxd_i(3:0) bus. Between frames, rxdv_i remains de-asserted.

Figure 3-180 RGMII Receive Waveform in 1000M

If the PHY detects an error on the frame received from the line, the PHY asserts the RGMII error signal, rxdv_i, for at
least half clock cycle at any time during the packet transfer.

Figure 3-181 RGMII Receive Waveform with Error Occurring in 1000M

On Transmit for 10/100M, all data transfers are synchronous to tx_clk rising edge. The GMII data enable signal
txen_o is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present
on txd_o(3:0) bus. Between frames, txen_o remains de-asserted. Note that the frequency of tx_clk is 25M in 100M
mode and 2.5M in 10M mode.

Figure 3-182 RGMII Transmit Waveform in 10/100M

If a frame experiences internal errors, the frame is subsequently transmitted with txen_o de-asserting synchronous to
tx_clk rising edge or tx_clk falling edge at any time during the packet transfer.

Figure 3-183 RGMII Transmit Waveform with Error Occurring in 10/100M

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On receive for 10/100M, all signals are sampled on rx_clk rising edge. The RGMII data enable signal rxdv_i is
asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on
rxd_i(3:0) bus. Between frames, rxdv_i remains de-asserted. Note that the frequency of rx_clk is 25M in 100M
mode and 2.5M in 10M mode.

Figure 3-184 RGMII Receive Waveform in 10/100M

If the PHY detects an error on the frame received from the line, the PHY asserts the RGMII error signal, rxdv_i, for at
least half clock cycle at any time during the packet transfer.

Figure 3-185 RGMII Receive Waveform with Error Occurring in 10/100M

[Link].6 RMII for 10/100 MAC

The RMII specification reduces the data interfaces from 4-bit (nibble) data to 2-bit (di-bit) data. In addition, control is
reduced to 3 signals and one clock. Thus, the total signal connection is reduced to 8 pins.

The following figure shows the RMII mode connection between a MAC and an RMII Ethernet Transceiver.

Figure 3-186 RMII Signal Connection between PHY and MAC

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 TX signals:
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. TX_EN shall be asserted
synchronously with the first nibble of the preamble and shall remain asserted while all di-bits to be transmitted are
presented. The MAC should assert TX_EN negated prior to the first REF_CLK rising edge following the final di-bit of a
frame.

TX_EN shall transition synchronously with respect to REF_CLK.

TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY.

In 10Mbps operation, as the REF_CLK frequency is 10 times the data rate in 10Mb/s mode, the value on TXD[1:0] must
be stable for 10 clocks, allowing the PHY to sample every 10th cycle.

 RX signals:
CRS_DV shall be asserted by the PHY when the receive medium is non-idle. CRS_DV is asserted asynchronously on
detection of carrier due to the criteria relevant to the operating mode.

The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is
asynchronous relative to REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place.

The following figure shows CRS_DV formation.

Figure 3-187 RMII Receive Waveform

As the REF_CLK frequency is 10 times the data rate in 10 Mbps mode, the value on RXD[1:0] may be sampled every 10th
cycle by the MAC.

[Link].7 MAC Receive

The MAC receive engine performs the following tasks:

 Check Frame Framing

 Remove Frame preamble and Frame SFD field
 Terminate Pause Frames
 Support 9 (8 of them are optional) configurable DA to check received DA. If not matching, the packet will be dropped.

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 Drop processing of oversized frame and short frame.

 Calculate and verify CRC-32
 Write received frames in the Core receive FIFO
 IP and TCP/UDP checksum
 DMA to write packet data from receive FIFO to external memory.
 DMA interface transfer to AXI

1. Preamble Processing
MAC Core checks for the start frame delimiter (SFD) byte. Before the SFD, a 0- to 7-byte preamble is acceptable. The
following shows cases of no preamble and odd preamble.

Figure 3-188 No Preamble Case

0 1 2 3 4 5 6 7 8 9 10 11

RXCLK

RXDV

RXD 5 5 5 5 D DA DA DA DA

odd preamble
Figure 3-189 Odd Preamble Case

2. Frame Length/Type Verification

The NIC does not check the correction of length field. An internal counter is used to calculate frame length. If
calculated length < 64 bytes, then drop as a runt packet. If calculated length > 1518 (or 1522, 1536, by configuration),
then assert oversize indication in frame information and this packet will be optionally dropped in DMA.

Control and VLAN frames (Frame Length/Type field 0x8808 and 0x8100 respectively) are processed by the Core as
described in the two following sections.

The NIC supports 802.1q tag-based VLAN ingress check, and it can support up to 4 VLANs, set in registers, where
these VLAN IDs can be any in 4K VLAN space. Internally, the controller uses 4 bits of "My VLAN ID Control Register" to
enable VLAN ingress check for each pre-defined VLAN ID. When at least one of the pre-defined VLAN ID is enabled,
RX MAC will compare the pre-defined VLAN ID with the tagged VID of the received packet. If one of them is matched,
the packet will be received; otherwise, it will be dropped, and the relevant MIB counter will be increased by 1
accordingly.

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Please note that VLAN ingress check has no effect on non-VALN tagged packets. When a received packet is VLAN-
tagged, the tag can be stripped from the packet or retained with the packet. No matter VLAN tag is stripped or not,
the VLAN tag information will be stamped at RX Descriptor.

3. Pause Frame Processing

Pause frames are not transferred to the receive FIFO.
A pause frame is valid only if all the following conditions are valid:
 Length/Type is set to 0x8808
 The Opcode immediately following the Length/Type field is 0x0001
 The frame MAC destination address is either the configured unicast address (Registers MAC_ADDR_0 and
MAC_ADDR_1) or the control frame multicast address 01-80-c2-00-00-01
 The frame has a valid CRC
 The frame has a length of 64 octets
Check if the received packet is a pause frame and generate a signal to pause TX (pause_tx) when receiving a pause
frame.

4. CRC
The CRC-32 field is always checked in the received side. The CRC polynomial, as specified in the 802.3 Standard, is:
FCS(X) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X 1 +1

The 32 bits of the CRC value are placed in the FCS field so that the X31 term is the right-most bit of the first octet.
The CRC bits are thus received in the following order: X31, X30,..., X1, X0.
If a CRC-32 error is detected, the frame is marked invalid and the frame status bit 1 indicating a CRC error is set to
“1”.

5. Frame Padding
In receive, the MAC does not remove the padding octets even if the Payload length is less than 46 bytes (42 bytes for
VLAN tagged frames)

6. Frame Truncation
Since NIC does not do length field checking, so that function of frame truncation is not implemented.

7. Hash Table
A 256-bit Hash table is implemented for multicast and unicast addresses filter function. It operates as follows.
First, on receiving a multicast MAC address frame, it calculates a 8-bit Hash Value from destination MAC address of
the frame.

Next, it compares the calculated Hash Value with the SelectBit_n(n = 0 to 255) references of the MAC Address Hash
Filter Table.

Last, it decides whether to forward the frame to memory or to deny it.

If a Hash Value of RX frame MAC address becomes n and the SelectBit_n is 0, the RX frame is denied. Otherwise, if
the SelectBit_n is 1, the RX frame is forwarded to memory.

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The Hash Value results are aggregated form CRC32 calculation from when CRC32 is used in the following generator
polynomial to degenerate the destination MAC address (48 bits).
Generator Polynomial: = x32+ x26+ x 23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x1+ 1

The 8-bit hash value can be generated from reversed CRC

{r_crc[31],r_crc[30],r_crc[29],r_crc[28],r_crc[27],r_crc[2],r_crc[1],r_crc[0]}

The following shows a 256-bit hash table and the process of hash value generation.

Figure 3-190 Hash Table Set

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Figure 3-191 Hash Table Control Flow Chart

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Figure 3-192 Hash Value Calculation

8. Magic Packet Detection

Wake-on-LAN ("WOL") is implemented using a specially designed packet called a magic packet.

The magic packet is a broadcast frame containing anywhere within its payload 6 bytes of all 255 (FF FF FF FF FF FF in
hexadecimal), followed by sixteen repetitions of the target computer's 48-bit MAC address, for a total of 102 bytes.

When Wake-on-LAN is enabled, TX MAC powers down and RX MAC only scans Magic Packet and does not forward
any packet to the system memory. After detecting the Magic Packet, MAC asserts an WOL interrupt to the CPU and
wakes up the CPU accordingly.

[Link].8 MAC Transmit

Ethernet Frame transmission starts when the Transmit FIFO holds enough data. Once a transfer has started, the transmit
engine performs the following tasks:

 Convert word to byte

 Generate Preamble and SFD field before Frame transmission
 When in Link Pause Mode, generate Pause frames if the Receive FIFO reports a congestion or if the pause generation
pin back_pressure on gtx_main is asserted
 When in Link Pause Mode, suspend Ethernet Frame transfer (XOFF) if a non-zero Pause Quanta is received from the
MAC receive path (optional)

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 Calculate and replace CRC-32 to the transmitted frame (optional)

 Send Frames with correct Inter-Packet Gap (IPG)

1G/100M/10M mode default stop TX when link status of PHY is deasserted.

The following figure shows the TX transmit flow chart.

Send Preamble

Send SFD

Send Pause Frame Send Destination Address

Send Source Address

Send Payload

Send Padding
(Option to add padding by MAC)

Send CRC
(Option to replace CRC by MAC)

Figure 3-193 Transmit Flow Chart

[Link] Signal Descriptions

Table 3-137 presents ENIC signal descriptions.

Table 3-137 ENIC Signal Descriptions

Signal Name Type Description Ball Location
ENIC Receive Data Bus—GBE_RXD[3:0]

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Signal Name Type Description Ball Location

GBE_RXD0 DI Gigabit Ethernet RX data 0 AB7
GBE_RXD1 DI Gigabit Ethernet RX data 1 AC8
GBE_RXD2 DI Gigabit Ethernet RX data 2 AA8
GBE_RXD3 DI Gigabit Ethernet RX data 3 AB3
ENIC Transmit Data Bus—GBE_TXD[3:0]
GBE_TXD0 DO Gigabit Ethernet TX data 0 AC4
GBE_TXD1 DO Gigabit Ethernet TX data 1 AB8
GBE_TXD2 DO Gigabit Ethernet TX data 2 AC9
GBE_TXD3 DO Gigabit Ethernet TX data 3 AB9
ENIC Command, Status, Clock and Interrupt Signals
GBE_COL DI Gigabit Ethernet collision detected AD11
GBE_INTR DI Gigabit Ethernet interrupt from external PHY AD10
GBE_RXC DI Gigabit Ethernet RX clock AB5
GBE_RXDV DI Gigabit Ethernet RX data valid AC5
GBE_RXER DI Gigabit Ethernet RX error AB4
GBE_TXC DIO Gigabit Ethernet TX clock AB6
GBE_TXEN DO Gigabit Ethernet TX data valid AA5
GBE_TXER DO Gigabit Ethernet TX error AC7
ENIC Management Bus
GBE_MDC DO Gigabit Ethernet MDC AA6
GBE_MDIO DIO Gigabit Ethernet MDIO AC6
Ethernet Auxiliary Snapshot and Pulse-Per-Second Signal
GBE_AUX_PPS0 DIO Ethernet Auxiliary Snapshot Input 0 / Pulse-Per-Second Output 0 AB2
GBE_AUX_PPS1 DIO Ethernet Auxiliary Snapshot Input 1 / Pulse-Per-Second Output 1 AB1
GBE_AUX_PPS2 DIO Ethernet Auxiliary Snapshot Input 2 / Pulse-Per-Second Output 2 AC7
GBE_AUX_PPS3 DIO Ethernet Auxiliary Snapshot Input 3 / Pulse-Per-Second Output 3 AB4

[Link] ENIC Timing Characteristics

Table 3-138 and Figure 3-194 present timing characteristics for the ENIC MII in the device.

Table 3-138 ENIC MII Timing Characteristics

No. Parameter Min Typ Max Unit
MII1 tc_TXC_RXC Cycle time, TXC/RXC 40 ns
MII2 td_TX Delay time, transmission 9.764 ns
MII3 td_TXC Delay time, TXC 1.323 2.273 ns
MII4 td_TXD Delay time, TXD/TXEN/TXER 4.149 7.491 ns
MII5 td_RXC Delay time, RXC 1.514 2.654 ns
MII6 td_RXD Delay time, RXD/RXDV/RXER 2.041 4.021 ns

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No. Parameter Min Typ Max Unit

MII7 tsu_RX Setup time, RXD/RXDV/RXER 3.507 ns
MII8 th_RX Hold time, RXD/RXDV/RXER 0.473 ns
D Duty cycle, TXC/RXC 40 50 60 %
MII10 tRISE Rise time, TXC/RXC (20% ~ 80%) 0.75 ns
MII11 tFALL Fall time, TXC/RXC (20% ~ 80%) 0.75 ns

Figure 3-194 ENIC MII Timing Diagram

Table 3-139 and Figure 3-195 ENIC RMII Timing Diagram present timing characteristics for the ENIC RMII in the device.

Table 3-139 ENIC RMII Timing Characteristics

No. Parameter Min Typ Max Unit
RMII1 tc_REFCLK Cycle time, REFCLK 20 ns
RMII2 td_TX Delay time, transmission 7.235 ns
RMII3 td_TXC Delay time, REFCLK (when transmitting) 1.144 2.2 ns
RMII4 td_TXD Delay time, TXD/TXEN 2.8 5.035 ns
RMII5 td_RXC Delay time, REFCLK (when receiving) 1.798 3.071 ns
RMII6 td_RXD Delay time, RXD/RXDV 1.925 3.469 ns
RMII7 tsu_RX Setup time, RXD/RXDV 2.671 ns
RMII8 th_RX Hold time, RXD/RXDV 0.873 ns
D Duty cycle, REFCLK 45 50 55 %
RMII10 tRISE Rise time, REFCLK (20%~80%) 0.75 ns
RMII11 tFALL Fall time, REFCLK (20%~80%) 0.75 ns

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Figure 3-195 ENIC RMII Timing Diagram

Table 3-140 and Figure 3-196 ENIC RGMII Timing Diagram present timing characteristics for the ENIC RGMII in the device.

Table 3-140 ENIC RGMII Timing Characteristics

No. Parameter Min Typ Max Unit
RGMII1 tTXC_RXC Cycle time, TXC/RXC (10M/100M/1000M) 400/40/8 ns
(1)
RGMII2 td_TX Delay time, transmission 4.1 + K ns
RGMII3 td_TXC Delay time, TXC 3.489 8.169 ns
RGMII4 td_TXD Delay time, TXD/TX_CTL 4.141 7.491 ns
RGMII5 td_RXC Delay time, RXC 1.998 3.575 ns
RGMII6 td_RXD Delay time, RXD/RX_CTL 1.913 3.548 ns
(2)
RGMII7 tsu_RX Setup time, RXD/RX_CTL 2.55 - Q ns
(2)
RGMII8 th_RX Hold time, RXD/RX_CTL 1.085 + Q ns
Duty cycle, TXC/RXC (1000M) 45 50 55 %
D
Duty cycle, TXC/RXC (10M/100M) 40 50 60 %
RGMII10 tRISE Rise time, TXC/RXC (20%~80%) 0.75 ns
RGMII11 tFALL Fall time, TXC/RXC (20%~80%) 0.75 ns
(1) K is programmable MAC internal delay (32-levels). The maximum delay is from 12.6001 ns to 28.5724 ns.
(2) Q is programmable MAC internal delay (32-levels). The maximum delay is from 12.6001 ns to 28.5724 ns.

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Figure 3-196 ENIC RGMII Timing Diagram

Table 3-141 and Figure 3-197 present timing characteristics for the ENIC MDIO in the device.

Table 3-141 ENIC MDIO Timing Characteristics

No. Parameter Min Typ Max Unit
MDIO1 tc_MDC Cycle time, MDC 400 ns
MDIO4 -
MDIO2 td_MDO Delay time, MDIO output ns
MDIO3
MDIO3 td_MDC Delay time, MDC 3.631 9.043 ns

MDIO4 td_MDO_ MAC Delay time, MDIO output (MAC to PHY) 4.804 11.479 ns

MDIO5 td_MDI Delay time, MDIO input 1.92 4.203 ns

1 + MDIO5 +
MDIO6 tsu_MDI Setup time, MDIO input ns
MDIO3
1 - MDIO5 -
MDIO7 th_MDI Hold time, MDIO input ns
MDIO3

Figure 3-197 ENIC MDIO Timing Diagram

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[Link] Programming Guide

 Initializing DMA
Complete the following steps to initialize the DMA:

1. Provide a software reset. This resets all of the MAC internal registers and logic. (bit 0 of DMA_Mode).
2. Wait for the completion of the reset process (poll bit 0 of the DMA_Mode, which is only cleared after the reset
operation is completed).
3. Program the following fields to initialize the DMA_SysBus_Mode Register:
a. AAL
b. Fixed burst or undefined burst
c. Burst mode values in the case of the AHB interface, OSR_LMT in the case of the AXI bus interface.
d. If fixed length value is enabled, select the maximum burst length possible on the AXI bus (bits [7:1])
4. Create a descriptor list for TX and RX. In addition, ensure that the RX descriptors are owned by DMA (set bit 31 of
descriptor TDES3/RDES3).
5. Program the TX and RX Ring length registers (DMA_CH(#i)_TxDesc_Ring_Length (for i = 0; i <=
DWC_EQOS_NUM_DMA_TX_CH-1) and DMA_CH(#i)_RxDesc_Ring_Length (for i = 0; i <=
DWC_EQOS_NUM_DMA_RX_CH-1)). The ring length must be programmed to at least 4.
6. Initialize RX and TX descriptor list addresses with the base address of the TX and RX descriptor
(DMA_CH(#i)_TxDesc_List_Address (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1),
DMA_CH(#i)_RxDesc_List_Address (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)). Also, program the TX and
RX tail pointer registers indicating to the DMA about the available descriptors (DMA_CH(#i)_TxDesc_Tail_Pointer
(for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1) and DMA_CH(#i)_RxDesc_Tail_Pointer (for i = 0; i <=
DWC_EQOS_NUM_DMA_RX_CH-1)).
7. Program the settings of the following registers for the parameters like maximum burst-length (PBL) initiated by
DMA, descriptor skip lengths, OSP in the case of TxDMA, RBSZ in the case of RxDMA, and so on:
 DMA_CH(#i)_Control (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
 DMA_CH(#i)_TX_Control (for i = 0; i <= DWC_EQOS_NUM_DMA_TX_CH-1)
 DMA_CH(#i)_RX_Control (for i = 0; i <= DWC_EQOS_NUM_DMA_RX_CH-1)
8. Enable the interrupts by programming the DMA_CH(#i)_Interrupt_Enable (for i = 0; i <=
DWC_EQOS_NUM_DMA_TX_CH-1) register.
9. Start the RX and TX DMAs by setting SR (bit 0) of the DMA_CH(#i)_RX_Control (for i = 0; i <=
DWC_EQOS_NUM_DMA_RX_CH-1) and ST (bit 0) of the DMA_CH(#i)_TX_Control (for i = 0; i <=
DWC_EQOS_NUM_DMA_TX_CH-1) register to 10. Repeat steps 4 to 9 for all the TX DMA and RX DMA selected
channels in the hardware.
10. Repeat steps 4 to 9 for all the TX DMA and RX DMA channels selected in the hardware.

 Initializing MTL Registers

Complete the following steps to initialize the MTL Registers:

1. Program the TX Scheduling (SCHALG) and Receive Arbitration Algorithm (RAA) fields in MTL_Operation_Mode to
initialize the MTL operation in the case of multiple TX and RX queues.
2. Program the RX Queue to DMA mapping in MTL_RxQ_DMA_Map0 and MTL_RxQ_DMA_Map1 registers.
3. Program the following fields to initialize the mode of operation in the MTL_TxQ0_Operation_Mode register
a. Transmit Store And Forward (TSF) or Transmit Threshold Control (TTC) in the case of threshold mode
b. Transmit Queue Enable (TXQEN) to value 2‘b10 to enable Transmit Queue0

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c. Transmit Queue Size (TQS)

4. Program the following fields to initialize the mode of operation in the MTL_RxQ0_Operation_Mode register:
a. Receive Store and Forward (RSF) or RTC in the case of Threshold mode
b. Flow Control Activation and De-activation thresholds for MTL Receive FIFO (RFA and RFD)
c. Enable Error Packet and undersized good Packet forwarding (FEP and FUP)
d. Receive Queue Size (RQS)
5. Repeat previous two steps for all MTL TX and RX queues selected in the configuration

 Initializing MAC
The following MAC initialization operations can be performed after DMA initialization. If the MAC initialization is
completed before the DMA is configured, enable the MAC RX (last step in the following sequence) only after the DMA
is active. Otherwise, received frames will fill in the RX FIFO and overflow.

1. Provide the MAC address registers: MAC_Address0_High and MAC_Address0_Low. If more than one MAC address
is enabled in your configuration (during configuration in the coreConsultant), program the MAC addresses
appropriately.
2. Program the following fields to set the appropriate filters for the incoming frames in the MAC_Packet_Filter
register:
a. Receive All
b. Promiscuous mode
c. Hash or Perfect Filter
d. Unicast, multicast, broadcast, and control frames filter settings
3. Program the following fields for proper flow control in the MAC_Q0_Tx_Flow_Ctrl register:
a. Pause time and other Pause frame control bits
b. Transmit Flow control bits
c. Flow Control Busy
4. Program the MAC_Interrupt_Enable register as required, and if applicable, for your configuration.
5. Program the appropriate fields in the MAC_Configuration register, for example, Inter-packet gap, while
transmission and jabber are disabled.
6. Set bits 0 and 1 in MAC_Configuration registers to start the MAC TX and RX.

 Performing Normal Receive and Transmit Operation

For normal operation, complete the following steps:

1. For normal TX and RX interrupts, read the interrupt status. Then, poll the descriptors, reading the status of the
descriptor owned by the Host (either TX or RX).
2. Set appropriate values for the descriptors, ensuring that TX and RX descriptors are owned by the DMA to resume
the transmission and reception of data.
3. If the descriptors are not owned by the DMA (or no descriptor is available), the DMA goes into the SUSPEND state.
The transmission or reception can be resumed by freeing the descriptors and writing the descriptor tail pointer to
TX/RX tail pointer register (DMA_CH[n]_TxDesc_Tail_Pointer and DMA_CH[n]_RxDesc_Tail_Pointer).
4. The values of the current host TX or RX descriptor address pointer can be read for the debugging process
(DMA_CH[n]_Current_App_TxDesc and DMA_CH[n]_Current_App_RxDesc).
5. The values of the current host transmit buffer address pointer and receive buffer address pointer can be read for
the debugging process (Register DMA_CH[n]_Current_App_TxBuffer and DMA_CH[n]_Current_App_RxBuffer).

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 Stopping and Starting Transmission

Complete the following steps to pause the transmission for some time:

1. Disable the TX DMA (if applicable) by clearing Bit 0 (ST) of DMA_CH(#i)_TX_Control (for i = 0; i <=
DWC_EQOS_NUM_DMA_TX_CH-1) Register.
2. Wait for all the previous frame transmissions to complete. Check this by reading the appropriate bits of
MTL_TxQ0_Debug Register (TRCSTS is not 01 and TXQSTS=0).
3. Disable the MAC TX and MAC RX by clearing Bit (RE) and Bit 1 (TE) of the MAC_Configuration Register.
4. Disable the RX DMA (if applicable) after making sure that the data in the RX FIFO is transferred to the system
memory (by reading the appropriate bits of MTL_TxQ0_Debug Register, PRXQ=0 and RXQSTS=00).
5. Make sure that both TX Queue and RX Queue are empty (TXQSTS is 0 in MTL_TxQ0_Debug Register and RXQSTS is
0 in MTL_RxQ0_Debug Register).
6. To restart the operation, first start the DMAs, and then enable the MAC TX and RX.

 Programming Guidelines for Multi-Channel Multi-Queuing

 Transmit

1. Program the TX queue size in the TQS field of MTL_TxQ[n]_Operation_Mode register. The size of the queue is
determined based on the value programmed in TQS field. In the Transmit operation, the number of channels is
equal to the number of the queues. For this reason, the Channel to Queue mapping is fixed.
2. For a queue to be used, the queue needs to be enabled in TXQEN in the corresponding
MTL_TxQ[n]_Operation_Mode Register. In DMA configurations, ST bit of DMA_CH[n]_Tx_Control Register and the
corresponding TXQEN in MTL_TxQ[n]_Operation Mode Register need to be enabled.
3. The scheduling method needs to be programmed in SCHALG of MTL_Operation_Mode register.
4. Program the MTL_TxQ[n]_Quantum_Weight for generic or DCB queue as per the selected algorithm. In case of
CBS algorithm in AVB queues, the MTL_TxQ[n]_ETS_Control, MTL_TxQ[n]_SendSlopeCredit, MTL_TxQ[n]_HiCredit
and MTL_TxQ[n]_LoCredit registers also need to be programmed as required.
5. If DCB is enabled and PFC function is required, program MAC_TxQ_Prty_Map0 Register to assign a fixed priority to
the queue. This assigned priority is used to determine whether the corresponding queue should stop transmitting
packet based on the received PFC packet.

 Receive

1. Program the Receive queue size in the RQS field of MTL_RxQ[n]_Operation_Mode Register. Based on the value
programmed in RQS field, the size of the queue is determined.
2. Enable the Receive Queues 0 to 7 in the fields RXQ0EN to RXQ7EN in MAC_RxQ_Ctrl0 Register for AV or DCB. In
DMA configurations, SR bit of statically or dynamically mapped DMA_CH[n]_Rx_Control Register and
corresponding RXQ[n]_EN in MAC_RxQ_Ctrl0 Register needs to be enabled.
3. The MAC routes the RX packets to the RX Queues based on following packet types:
a. AV PTP Packets: Based on the programming of AVPTPQ in MAC_RxQ_Ctrl1 Register.
b. AV Untagged Control packets: Based on the programming of AVCPQ in MAC_RxQ_Ctrl1 Register.
c. Data Center Bridging (DCB) related Link Layer Discovery Protocol (LLDP) packets. Program DCBCPQ in
MAC_RxQ_Ctrl1 Register to indicate to MAC which queue should get the DCB packets.
d. VLAN Tag Priority field in VLAN Tagged packets: Program PSRQ7-0 of the MAC_RxQ_Ctrl2 and MAC_RxQ_Ctrl3
Register for the routing of tagged packets based on the USP (user Priority) field of the received packets to the
RX Queues 0 to 7.

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e. The AV tagged control and data packets are also routed based on PSRQ field of the MAC_RxQ_Ctrl2 and
MAC_RxQ_Ctrl3 registers.
4. If multiple RX DMA channels are enabled, the following programming should be done for proper arbitration and
mapping:
a. Program the RAA field of MTL_Operation_Mode register to select the arbitration algorithm to decide which
RxQ is read out from the RxFIFO memory.
b. Program the MTL_RxQ[n]_Control to decide the weights and the packet arbitration for each RxQ.
c. If static mapping is programmed in MTL_RxQ_DMA_Map[n] register (RXQ[n]DADMACH is reset to 0), bits
RXQx2DMA and others need to be programmed to select the channel for which each queue is mapped.
d. Set RXQ[n]DADMACH bit in MTL_RxQ_DMA_Map0 Register to select dynamic mapping of packets in each
RxQueue.
e. In dynamic channel mapping, the routing of a packet to a specific RxDMA channel is decided by the value of
DCS field in the lowest MAC Address Register.

 Programming Guidelines for IEEE 1588 Timestamping

 Initialization Guideline for System Time Generation

You can enable the timestamp feature by setting Bit 0 of the MAC_Timestamp_Control Register. However, it is
essential that the timestamp counter should be initialized after this bit is set. Complete the following steps during
DWC_ether_qos initialization:

1. Mask the Timestamp Trigger interrupt by clearing Bit 16 of MAC_Interrupt_Enable Register.

2. Set Bit 0 of MAC_Timestamp_Control Register to enable timestamping.
3. Program MAC_Sub_Second_Increment Register based on the PTP clock frequency.
4. If the Fine Correction approach is used, program MAC_Timestamp_Addend and set Bit 5 of the
MAC_Timestamp_Control Register.
5. Poll the MAC_Timestamp_Control Register until Bit 5 is cleared.
6. Program Bit 1 of MAC_Timestamp_Control Register to select the Fine Update method (if required).
7. Program MAC_System_Time_Seconds_Update Register and MAC_System_Time_Nanoseconds_Update
Register with the appropriate time values.
8. Set Bit 2 in MAC_Timestamp_Control Register. The timestamp counter starts operation as soon as it is
initialized with the value written in the Timestamp Update registers. If one-step timestamping is enabled:
a. To enable one-step timestamping, program Bit 27 of the TDES3 Context Descriptor.
b. Program registers MAC_Timestamp_Ingress_Asym_Corr and MAC_Timestamp_Egress_Asym_Corr to
update the correction field in PDelay_Req PTP messages.
9. Enable the MAC RX and TX for proper timestamping.

 System Time Correction

To synchronize or update the system time in one process (coarse correction method), complete the following
steps:

1. Set the offset (positive or negative) in the Timestamp Update registers (MAC_System_Time_Seconds_Update
and MAC_System_Time_Nanoseconds_Update).
2. Set Bit 3 (TSUPDT) of the MAC_Timestamp_Control Register. The value in the Timestamp Update registers is
added to or subtracted from the system time when the TSUPDT bit is cleared.

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To synchronize or update the system time to reduce system-time jitter (fine correction method), complete the
following steps:

1. With the help of the algorithm explained in “System Time Register Module”, calculate the rate by which you
want to make the system time increment slower or faster.
2. Update the MAC_Timestamp_Addend with the new value and set Bit 5 of the MAC_Timestamp_Control
Register.
3. Wait for the time for which you want the new value of the Addend register to be active. You can do this by
enabling the Timestamp Trigger interrupt after the system time reaches the target value.
4. Program the required target time in MAC_PPS[n]_Target_Time_Seconds Register and
MAC_PPS[n]_Target_Time_Nanoseconds Register.
5. Enable the Timestamp interrupt in bit 12 of MAC_Interrupt_Enable register.
6. Set Bit 4 in Register MAC_Timestamp_Control.
7. When this trigger causes an interrupt, read MAC_Interrupt_Status Register.
8. Reprogram MAC_Timestamp_Addend Register with the old value and set Bit 5 again.

3.12.7 Peripheral Component Interconnect Express (PCIe) Controller

[Link] Overview
The PCIe controller adheres to the Intel® PIPE (PHY interface for the PCIe) interface, facilitating seamless
integration with PIPE-compliant PHY. Moreover, the controller conforms to the AMBA® AXI4 specifications. It
supports differential bus speeds of PCIe Gen1 (2.5 Gbps), PCIe Gen2 (5.0 Gbps).

[Link] Features

 Supports Root Complex (RC) mode

 Supports x1 link
 Supports link rate of 2.5 GT/s, 5.0 GT/s
 PCIe Base Specification Revision 3.0 compliant
 PIPE 4.0 compliant
 Supports memory, I/O, configuration, and message transactions.
 Supports maximum payload size: 256 bytes
 Supports maximum read request size: 256 bytes
 Supports 1 VC (Virtual Channel)
 AER (Advanced Error Reporting)
 ECRC (End to End Cycle Redundancy Check) generation and check support
 Lane reversal
 Polarity inverse
 Legacy PCI power management
 Native ASPM (Active State Power Management) L0s and L1 states
 L1PMSS (L1 Power Management Substates) with CLKREQ#
 LTR (Latency Tolerance Reporting)
 MSI (Message Signaled Interrupt) per function up to 32 and INT x (legacy interrupts)
 AHB and AXI interfaces:

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 1 AHB slave interface for bridge configuration

 1 AXI master interface, supporting outstanding requests write (10)/read (12)
 1 AXI slave interface, supporting outstanding requests write (4)/read (6)
 128-bit data support for AXI master and slave interfaces

[Link] Block Diagram

The PCIe consists of 4 different layers: PCIe layer, Bridge layer, AXI layer and Physical layer, as depicted in the figure below.

PHY MAC

Physical Layer PCI Express Layer Bridge Layer AXI Layer

AXI
PCIe Internal
AXI Master
TX/RX Register

PCIe Link PIPE Interface AXI

PCIe PCIe Address
PHYA PHYD AXI Slave
Controller Config Translator

PCIe AHB/APB AHB/APB Interface

Interconnect
MISC Slave

Figure 3-198 Block Diagram of PCIe Controller

Table 3-142 PCIe Layers and Components

Layer Components
 A PCIe controller, which is a PCIe core IP
 A PCIe TX/RX interface between the bridge and the PCIe controller
PCIe layer
 A PCIe configuration interface to give the bridge layer access to the PCIe configuration space
 A PCIe misc. interface to allow the bridge to manage low-power, interrupts, etc.
 The internal registers of the PCIe controller
 Address translator modules to convert between the AXI and PCIe interfaces
 When transferring PCIe received requests to the AXI master, the address translator adds the
Bridge layer corresponding AXI base address and forwards the request to the desired AXI master interface
 The address translation method is similar when transferring AXI receive requests to the PCIe
interface
 An interconnect module to interconnect and arbitrate between input and output flow
 An AXI master interface, which manages requests and completions from the bridge layer to AXI
AXI layer  An AXI slave interface, which manages requests and completions from AXI to the bridge layer
 An AHB or APB slave interface for bridge configuration

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Layer Components
Physical layer Refer to Section [Link]

[Link] Function Description

[Link].1 I/O TLP (Transaction Layer Packet) Transfer

[Link].1.1 Transmitting I/O TLP

When operating in root port mode, the PCIe controller enables the local processor to send an I/O request TLP via the AXI4
slave interface by configuring the address translation table appropriately.

 In cases where the target address of a write request from the AXI slave matches the address translation table for I/O
TLP, the PCIe controller will transmit an I/O write TLP.
 Similarly, if the target address of a read request from the AXI slave matches the address translation table for I/O TLP,
the PCIe controller will transmit an I/O read TLP.

Set AXI Slave Address Translation

Table

Access target address by

AXI4 Slave Interface read or write
request

Send I/O TLP if AXI address matches

the table

Figure 3-199 RC Send I/O TLP Flow

Table 3-143 RC Set Address Translation Table for I/O TLP Example
For AXI slave0 Table0: 0x0800 to 0x081F
Offset Register Name Bit Location Action Value Description
0x800 ATR_IMPL [0] W 1’b1 The table is enabled.
ATR_SIZE [6:1] W 6’d19 Table Size is 2^ (19+1) = 1MB
SRC_ADDR[ATR_SIZE:0] will be ignored to align
SRC_ADDR_LSB [31:12] W 20’b0
the Table size
Any AXI address in 0xCCCCCCCC_00000000 to
0x804 SRC_ADDR_MSB [31:0] W 32’hCCCCCCCC
0xCCCCCCCC_000FFFFF range will match table0.

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For AXI slave0 Table0: 0x0800 to 0x081F

Offset Register Name Bit Location Action Value Description
AXI address matching the table will be translated
0x808 TRSL_ADDR_LSB [31:12] W 20’h05500 to IO Requested TLP with address 0x05500000 to
0x055FFFFF
The IO TLP does not need high 32-bit translated
0x80C TRSL_ADDR_MSB [31:0] W 32’h0
address.
0x810 TRSL_ID [3:0] W 4’d1 To the PCIe IO interface
TRSF_PARAM [18:16] W 3’d2 IO TLP
TRSF_PARAM [19] W 1’b0 NW flag is 0
TRSF_PARAM [22:20] W 3’b0 No snoop
TRSF_PARAM [23] W 1’b0 ECRC is not forwarded.
TRSF_PARAM [26:24] W 3’b0 TC is 0.

[Link].2 Message TLP Transfer

The local processor is capable of transmitting message TLP via the AXI4 slave interface by configuring the address
translation table accordingly. Once the PCIe controller receives a specific message TLP, it will notify the local processor via
an [Link] message TLP.

[Link].2.1 Original Message Mechanism

In the default PLDA mode, the local processor sends a message via an AXI slave transaction, which is equivalent to a full
message TLP. This includes the 4DW header that specifies the message code and routing information, as well as the
payload if the message TLP contains data.

For instance, if the AXI slave transaction contains 12DW data, the first 4DW is the message header, while the last 8DW is
reserved for message data. The local processor must ensure that the contents are properly prepared, including header
format, message code, and message payload, within the 12DW data from the AXI slave.

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Set AXI Slave Address Translation

Table

Access target address by

AXI4 Slave Interface Write Request

Send Message TLP if AXI address

matches the Address Translation
Table for Message

Figure 3-200 Transmit Message TLP Flow

Table 3-144 ADT Setting Example for Transmit Message TLP

For AXI slave0 Table0: 0x0800 to 0x081F
Offset Register Name Bit Location Action Value Description
0x800 ATR_IMPL [0] W 1’b1 The table is enabled
ATR_SIZE [6:1] W 6’d11 Table Size is 2^ (11+1) =4KB
SRC_ADDR[ATR_SIZE:0] will be ignored to
SRC_ADDR_LSB [31:12] W 20’b0
align the table size
Any AXI address in
0xDDDDDDDD_00000000 to
0x804 SRC_ADDR_MSB [31:0] W 32’hDDDDDDDD
0xDDDDDDDD_00000FFF range will match
table0.
Message TLP does not need translated
0x808 TRSL_ADDR_LSB [31:12] W 20’h0
address
Message TLP does not need translated
0x80C TRSL_ADDR_MSB [31:0] W 32’h0
address
0x810 TRSL_ID [3:0] W 4’d0 To PCIe TX/RX interface
TRSF_PARAM [18:16] W 3’d4 Message TLP
TRSF_PARAM [19] W 1’b0 NW flag is 0
TRSF_PARAM [22:20] W 3’b0 No snoop
TRSF_PARAM [23] W 1’b0 ECRC is not forwarded
TRSF_PARAM [26:24] W 3’b0 TC is 0

[Link].2.2 Message Pool Mechanism

In the message pool mode, the local processor sends a message, and the PCIe controller can aggregate several AXI slave
transactions to form a complete Message TLP if those transactions match the Address Translation Table for Message. In
this mode, the maximum length for a Message TLP is 8DW, including the 4DW header and a maximum of 4DW data.

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For instance, suppose the local processor intends to send a message TLP with a length of 6DW, but a single AXI slave
transaction contains a maximum of 2DW. In that case, the local processor can activate the message pool mode register and
issue three AXI transactions, each with a length of 2DW, to transmit a 6DW message TLP.

Set AXI Slave Address Translation

Table

Set Message Pool Register

Access target address by

AXI4 Slave Interface Write Request

PCIe Controller will collect several

AXI transactions until the total
length meets Message Pool Length

Figure 3-201 Transmit Message TLP by Message Pool Mode

Table 3-145 ADT Setting Example for Message Pool Mode

Offset Register Name Bit Location Action Value Description
For AXI slave0 Table0: 0x0800 to 0x081F
0x800 ATR_IMPL [0] W 1’b1 The table is enabled
ATR_SIZE [6:1] W 6’d11 Table Size is 2^ (11+1) =4KB
SRC_ADDR[ATR_SIZE:0] will be ignored to align
SRC_ADDR_LSB [31:12] W 20’b0
the Table size
Any AXI address in 0xDDDDDDDD_00000000 to
0x804 SRC_ADDR_MSB [31:0] W 32’hDDDDDDDD 0xDDDDDDDD_00000FFF range will match
table0.
0x808 TRSL_ADDR_LSB [31:12] W 20’h0 Message TLP does not need translated address
0x80C TRSL_ADDR_MSB [31:0] W 32’h0 Message TLP does not need translated address
0x810 TRSL_ID [3:0] W 4’d0 To PCIe TX/RX interface
TRSF_PARAM [18:16] W 3’d4 Message TLP
TRSF_PARAM [19] W 1’b0 NW flag is 0
TRSF_PARAM [22:20] W 3’b0 No snoop
TRSF_PARAM [23] W 1’b0 ECRC is not forwarded
TRSF_PARAM [26:24] W 3’b0 TC is 0
For Message Pool Register: 0x01A8

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Offset Register Name Bit Location Action Value Description

0x1A8 MSG_POOL_EN [4] W 1’b1 Enable Message Pool mode
Message Data Payload length is 2DW and total
MSG_POOL_DLEN [7:5] W 3’d2
length is 4DW+2DW = 6DW

[Link].2.3 Receiving Message TLP

The system can transmit incoming messages from the PCIe interface to either an internal register or an AXI master,
depending on the message type and reception message register settings. To activate this message forwarding functionality,
the software must properly configure the "PMSG_RECEPTION_SETTINGS" register, which ranges from 0x3F0 to 0x3FF.

The messages below are supported by the PCIe controller and forwarded to a dedicated destination.

 Unlock Message
 ATS Message
 LTR Message
 Optimized Buffer Flush/Fill
 Vendor Defined Type0
 Vendor Defined Type1

In the case of an LTR message, it is imperative that the message is forwarded to the internal register, and it must be
directed to a fixed destination address of 0x1A4. Therefore, LTR_DEST_ADDR register of “PMSG_RECEPTION_SETTINGS1
(0x3F4)” must be fixed to 0x1A4.

For other supported messages, there is flexibility in whether they are forwarded to the internal register or the AXI master
interface.

Field Register Description

PMSG_RECEPTION_SETTINGS0 Enables the configuration of supported message types.
PMSG_SUPPORT_RX
(0x3F0)
PMSG_RECEPTION_SETTINGS1 Enables selection of either the AXI master interface or internal
PMSG_DEST_ID
(0x3F4) register that will be used to forward messages.
Allow for specifying the address when targeting an AXI master
interface or internal register.
 If "PMSG_DEST_ID" is set to the Internal Register (5'd12),
PMSG_RECEPTION_SETTINGS2
then "PMSG_DEST_ADDR" must be fixed at 64'hCE0, and the
(0x3F8)
PMSG_DEST_ADDR PCIe controller can only support Message TLP with at most
PMSG_RECEPTION_SETTINGS3
8DW length.
(0x3FC)
 If "PMSG_DEST_ID" is set to the AXI master interface (5'd4
to 5'd7), then the 12 LSBs of this address should be equal to
12'b0 and there are no limitations on the message length.

For other supported messages, there is the option to forward them either to the internal register or the AXI master
interface.

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Field Register Description

PMSG_RECEPTION_SETTINGS0
PMSG_SUPPORT_RX Enables the configuration of supported message types.
(0x3F0)
PMSG_RECEPTION_SETTINGS1 Enables selection of either the AXI master interface or internal
PMSG_DEST_ID
(0x3F4) register to be utilized for message forwarding.
Allow for specifying the address when targeting an AXI master
interface or internal register.
 If "PMSG_DEST_ID" is set to Internal Register (5'd12), then
PMSG_RECEPTION_SETTINGS2
"PMSG_DEST_ADDR" must be fixed at 64'hCE0. Additionally,
(0x3F8)
PMSG_DEST_ADDR the PCIe controller can only support Message TLP with at
PMSG_RECEPTION_SETTINGS3
most 8DW length.
(0x3FC)
 If "PMSG_DEST_ID" is set to the AXI master interface (5'd4 to
5'd7), then the 12 LSBs of this address should be set to 12'b0,
and there are no limitations on the message length.

Once the PCIe controller receives an LTR message TLP, the message contents will be written into the internal register
"PCIE_LTR_VALUES" (0x1A4), and the status register "LTR_MSG_RECEIVED" (0x14C [0]) will be set. This setting generates a
Local Interrupt to notify the local processor.

PCIe Controller received a LTR

Message

Forward to Internal Register

PCIE_LTR_VALUE (0x1A4)

Set status register in

LTR_MSG_RECEIVED (0x14C[0])

Generate Interrupt if Mask Bit of

IMASK_LOCAL is 1 (0x180[28])

Figure 3-202 RC Received LTR Message Flow

Table 3-146 RC Handle LTR Message Interrupt Example

Clear RC LTR Message Interrupt
Offset Register Name Bit Location Action Value Description
Check whether local interrupt status and
0x184 ISTATUS_LOCAL [31:0] R 32’h1000_0000
Message TLP are received

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Clear RC LTR Message Interrupt

Offset Register Name Bit Location Action Value Description
0x14C PCIE_MISC_STATUS [31:0] R 32’h0000_0001 Check what kind of Message is received
0x1A4 PCIE_LTR_VALIE [31:0] R 32’hxxxx_xxxx Check LTR Value
After checking LTR value and performing
0x14C PCIE_MISC_STATUS [31:0] W 32’h0000_0001 requisite action, local processor can clear
LTR status
0x184 ISTATUS_LOCAL [31:0] W 32’h1000_0000 Clear local status to de-assert local interrupt

When the PCIe controller receives a supported message TLP and the "PMSG_DEST_ID" is set to internal register, the entire
message TLP contents, comprising both the header and data, are written into the internal register
"PCIE_RECEIVED_MESSAGE" (0xCE0 to 0xCFF). Additionally, the status register "PCIE_MSG_RECEIVED" (0x14C [1]) is set.
This setting generates a local interrupt to notify the local processor.

PCIe Controller received a Supported

Message

Forward to Internal Register

PCIE_RECEIVED_MESSAGE (0xCE
0~0xCFF) if PMSG_DEST_ID is
Internal Register.

Set status register in

PCIE_MSG_RECEIVED (0x14C[1])

Generate Interrupt if Mask Bit of

IMASK_LOCAL (0x180[28]) is 1

Figure 3-203 RC Received Other Supported Message Flow

Table 3-147 RC Handle Other Supported Message Interrupt Example

Clear RC LTR Message Interrupt
Offset Register Name Bit Location Action Value Description
Check whether local interrupt status
0x184 ISTATUS_LOCAL [31:0] R 32’h1000_0000
and message TLP are received
Check what kind of message is
0x14C PCIE_MISC_STATUS [31:0] R 32’h0000_0002
received
0xCE0 to
PCIE_RECEIVED_MESSAGE [31:0] R 32’hxxxx_xxxx Check message header and data
0xCFF

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Clear RC LTR Message Interrupt

Offset Register Name Bit Location Action Value Description
After checking message type and
0x14C PCIE_MISC_STATUS [31:0] W 32’h0000_0002 performing requisite action, local
processor can clear message status
Clear local status to de-assert local
0x184 ISTATUS_LOCAL [31:0] W 32’h1000_0000
interrupt

[Link].3 Reset

The PCIe controller features two reset input ports: the power on reset and the PERST#, which is a fundamental reset
defined in the PCIe specification. Additionally, the controller provides a software reset controller register, "PCIE_RST_CTRL"
(0x148), which can be utilized to reset various modules within the PCIe controller.

There are several PCIe link state transitions referred to as "Pl Exit Events." When a "Pl Exit Event" occurs, the PCIe
controller automatically resets certain logic to clear the register back to its default value. The following describes the state
transitions associated with the "Pl Exit Event":

Exit Description
LTSSM exits the Disable state or the link is unexpectedly down; then, LTSSM returns to the [Link]
Dl Up Exit
State.
Hot Reset Exit LTSSM exits the Hot Reset State and returns to the [Link] state.
L2 Exit LTSSM exits the L2 state and returns to the [Link] state.
LTSSM Exit LTSSM enters the [Link] state from any state except the upper state.

 In Rootport mode, if a "Pl Exit Event" occurs, the PCIe controller will reset the PHY, physical layer, data link layer, and
transaction layer, with the exception of the configuration space.

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ahb_apb_rstn AHB/APB Slave

Power On Reset axi_rstn AXI Layer

Internal
br_reg_rstn
PERST# Register

br_rstn Bridge & PCIe IF Layer

ResetBRG
Configuration
Reset tl_crstn
Control Space
ResetMAC
Reference
ref_rstn
Timer
ResetPHY
tl_rstn Transaction Layer
PL Exit Event Physical & Data Link Layer
pl_rstn

pl_pipe_rstn PHY

Figure 3-204 PCIe Reset Scheme

Table 3-148 Reset Signal Description

Reset Signal Name Description
ahb_apb_rst_b Clear AHB or APB slave logic in the AXI layer
axi_rstn Clear AXI slave and AXI master logic in the AXI layer
br_reg_rstn Clear internal register in the Bridge layer
br_rstn Clear Bridge layer logic except the internal register
tl_crstn Clears all configuration registers in the transaction layer, except sticky registers
tl_rstn Clears all logic in the transaction layer except configuration registers and reference timer
ref_rstn Clear reference timer
pl_rstn Clears the physical and data-link layer logic
pl_pipe_rstn Clear PHYD logic

Table 3-149 Reset Control

Power PERST# ResetBRG ResetMAC ResetPHY
Pl Exit Event
on Reset (Only for EP) (PCIE_RST_CTRL[2]) (PCIE_RST_CTRL[0]) (PCIE_RST_CTRL[1])

Depend on Depend on
ahb_apb_rstn Yes Yes No No
PCIE_RST_CTRL[9] PCIE_RST_CTRL[8]
Depend on Depend on
axi_rstn Yes Yes No No
PCIE_RST_CTRL[9] PCIE_RST_CTRL[8]
Depend on
br_reg_rstn Yes No No No No
PCIE_RST_CTRL[10]

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Power PERST# ResetBRG ResetMAC ResetPHY

Pl Exit Event
on Reset (Only for EP) (PCIE_RST_CTRL[2]) (PCIE_RST_CTRL[0]) (PCIE_RST_CTRL[1])

Depend on Depend on
br_rstn Yes Yes No No
PCIE_RST_CTRL[9] PCIE_RST_CTRL[8]
Depend on
Depend on
tl_crstn Yes PCIE_RST_CTRL[6] No Yes No
PCIE_RST_CTRL[11]
(only for EP)
Depend on Depend on
tl_rstn Yes No Yes No
PCIE_RST_CTRL[7] PCIE_RST_CTRL[6]
Depend on Depend on
ref_rstn Yes No Yes No
PCIE_RST_CTRL[7] PCIE_RST_CTRL[6]
Depend on Depend on
pl_rstn Yes No Yes No
PCIE_RST_CTRL[5] PCIE_RST_CTRL[14]
Depend on Depend on
pl_pipe_rstn Yes No No Yes
PCIE_RST_CTRL[4] PCIE_RST_CTRL[12]

Table 3-150 Reset Scope for Pl Exit Event

Role Dl Up Exit Hot Reset Exit L2 Exit
Pl_rstn Pl_rstn Pl_rstn
RC
Tl_rstn Tl_rstn Tl_rstn

[Link].4 Handling Interrupts

The ISTATUS_LOCAL (located at PCIE_MAC Base address + 0x0184) register reports the interrupt source in bits 31 to 0 when
any of the following events occurs. The host processor has the ability to enable or mask each interrupt source
independently by setting or clearing the corresponding bit in the IMASK_LOCAL (located at PCIE_MAC Base address +
0x0180) register. PCIe has the capability to generate interrupts to the Local processor for the following events:

Bit Description
Bit [31] System error signaled
Bit [30] PM/LTR/Hotplug event for RC
Bit [29] AER Event for RC
Bit [28] Message TLP received except LTR and PTM
Bit [27] Asserted when PCI interrupt line D is asserted
Bit [26] Asserted when PCI interrupt line C is asserted
Bit [25] Asserted when PCI interrupt line B is asserted
Bit [24] Asserted when PCI interrupt line A is asserted
Bit [23] L2 Wakeup: Asserted when L2 wakeup event happened
Bit [22]: PCIe discard error: Asserted to signal a completion timeout on a PCIe read request
Bit [21]: PCIe fetch error: Asserted to indicate that an error occurred on a PCIe read request
Bit [20]: PCIe post error: Asserted to indicate that an error occurred on a PCIe write request
Bit [19]: PCIe PTM message received: Asserted to indicate that a precise time message was received
Bit [18]: AXI discard error: Asserted to signal a completion timeout on an AXI read request

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Bit Description
Bit [17]: AXI fetch error: Asserted to indicate that an error occurred on an AXI read request
Bit [16]: AXI post error: Asserted to indicate that an error occurred on an AXI write request
Bit [15:8]: Multiple MSI received: Report MSI events to the local processor. Bit number i corresponds to
function number i
Bit [7:0] Reserved for RC mode because DMA engines are not implemented

The occurrence of any of these events leads to the reporting of the interrupt source in the "ISTATUS_LOCAL (0x184)"
register. The Host processor has the ability to enable or mask each interrupt source independently by setting or clearing
the corresponding bit in the "IMASK_LOCAL (0x180)" register. For detailed information about these registers, refer to
“MT8390 Register Map”.

When an interrupt source is active and not masked, an interrupt is generated on the AXI domain and reported through the
"pcie_interrupt_out" output port. The processing of this interrupt upon receipt by the Local processor is application-
specific. However, in general, the local processor:

 Reads the “ISTATUS_LOCAL (0x184)” register to determine the source of the interrupt.
 Reads any other bridge configuration space status registers if required.
 Reads any PCIe configuration space registers if required.
 Reads any PCIe device status registers if required.
 Performs the requisite actions.
 Clears the “ISTATUS_LOCAL (0x184)” interrupt source by writing 1 to the corresponding bit.

Table 3-151 Local Interrupt Table for RC Mode

Bit Interrupt Source Level2 Mark Level2 Status Level1 Mark Level1 Status
0 Internal DMA0 End N/A Internal DMA0 Status (0x420) 0x180[0] 0x184[0]
1 Internal DMA1 End N/A Internal DMA1 Status (0x460) 0x180[1] 0x184[1]
2 Internal DMA2 End N/A Internal DMA2 Status (0x4A0) 0x180[2] 0x184[2]
3 Internal DMA3 End N/A Internal DMA3 Status (0x4E0) 0x180[3] 0x184[3]
4 Internal DMA4 End N/A Internal DMA4 Status (0x520) 0x180[4] 0x184[4]
5 Internal DMA5 End N/A Internal DMA5 Status (0x560) 0x180[5] 0x184[5]
6 Internal DMA6 End N/A Internal DMA6 Status (0x5A0) 0x180[6] 0x184[6]
7 Internal DMA7 End N/A Internal DMA7 Status (0x5E0) 0x180[7] 0x184[7]
Internal DMA0 Error N/A Internal DMA0 Status (0x420)
8 Receive MSI for MSI MSI Function0 Mark 0x180[8] 0x184[8]
MSI Function0 Status (0xC04)
Funciton0 (0xC08)
Internal DMA1 Error N/A Internal DMA1 Status (0x460)
9 Receive MSI for MSI MSI Function1 Mark 0x180[9] 0x184[9]
MSI Function1 Status (0xC14)
Funciton1 (0xC18)
Internal DMA2 Error N/A Internal DMA2 Status (0x4A0)
10 Receive MSI for MSI MSI Function2 Mark 0x180[10] 0x18410]
MSI Function2 Status (0xC24)
Funciton2 ((0xC28)
11 Internal DMA3 Error N/A Internal DMA3 Status (0x4E0) 0x180[11] 0x184[11]

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Bit Interrupt Source Level2 Mark Level2 Status Level1 Mark Level1 Status
Receive MSI for MSI MSI Function3 Mark
MSI Function3 Status (0xC34)
Funciton3 (0xC38)
Internal DMA4 Error N/A Internal DMA4 Status (0x520)
12 Receive MSI for MSI MSI Function4 Mark 0x180[12] 0x184[12]
MSI Function4 Status (0xC44)
Funciton4 (0xC48)
Internal DMA5 Error N/A Internal DMA5 Status (0x560)
13 Receive MSI for MSI MSI Function5 Mark 0x180[13] 0x184[13]
MSI Function5 Status (0xC54)
Funciton5 (0xC58)
Internal DMA6 Error N/A Internal DMA6 Status (0x5A0)
14 Receive MSI for MSI MSI Function6 Mark 0x180[14] 0x184[14]
MSI Function6 Status (0xC64)
Funciton6 (0xC68)
Internal DMA7 Error N/A Internal DMA7 Status (0x5E0)
15 Receive MSI for MSI MSI Function7 Mark 0x180[15] 0x184[15]
MSI Function7 Status (0xC74)
Funciton7 (0xC78)
ADT to Local Mark
AXI ADT Event: Post Error AXI ADT Status (0x1E0~0x1EF)
16 (0x1AC[24]) 0x180[16] 0x184[16]
N/A N/A N/A
AXI ADT Event: Fetch ADT to Local Mark
AXI ADT Status (0x1E0~0x1EF)
17 Error (0x1AC[25]) 0x180[17] 0x184[17]
N/A N/A N/A
AXI ADT Event: Discard ADT to Local Mark
AXI ADT Status (0x1E0~0x1EF)
18 Error (0x1AC[26]) 0x180[18] 0x184[18]
N/A N/A N/A
ADT to Local Mark
AXI ADT Event: Doorbell AXI ADT Status (0x1E0~0x1EF)
(0x1AC[27])
19 0x180[19] 0x184[19]
Precise Time Message
N/A PTM Register (0xD80~0xD93)
Received
PCIe ADT Event: Post ADT to Local Mark PCIe ADT Status
20 Error (0x1AC[28]) (0x1D8~0x1DF) 0x180[20] 0x184[20]
N/A N/A N/A
PCIe ADT Event: Fetch ADT to Local Mark PCIe ADT Status
21 Error (0x1AC[29]) (0x1D8~0x1DF) 0x180[21] 0x184[21]
N/A N/A N/A
PCIe ADT Event: Discard ADT to Local Mark PCIe ADT Status
22 Error (0x1AC[30]) (0x1D8~0x1DF) 0x180[22] 0x184[22]
N/A N/A N/A
ADT to Local Mark PCIe ADT Status
PCIe ADT Event: Doorbell
23 (0x1AC[31]) (0x1D8~0x1DF) 0x180[23] 0x184[23]
L2 Remote Wakeup N/A N/A
Interrupt line A is
24 N/A N/A 0x180[24] 0x184[24]
asserted

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Bit Interrupt Source Level2 Mark Level2 Status Level1 Mark Level1 Status
Interrupt line B is
25 N/A N/A 0x180[25] 0x184[25]
asserted
Interrupt line C is
26 N/A N/A 0x180[26] 0x184[26]
asserted
Interrupt line D is
27 N/A N/A 0x180[27] 0x184[27]
asserted
Message Status Register
Message Received N/A
(0x14C)
28 0x180[28] 0x184[28]
Message Status Register
LTR Message Received N/A
(0x14C)
29 AER Event N/A N/A 0x180[29] 0x184[29]
30 Receive PME Message N/A N/A 0x180[30] 0x184[30]
Reset Event N/A N/A
31 0x180[31] 0x184[31]
System Error N/A N/A

[Link].4.1 Receiving INTX Message

In the root port mode, the PCIe controller is capable of generating a local interrupt to inform the local processor when it
receives an INTX message from an endpoint. Upon receiving an ASSERT INTX message, the PCIe controller sets the
"INT_EVT" bit in the "ISTATUS_LOCAL (0x184)" register, and this status remains asserted until the Root Complex (RC)
receives a DEASSERT INTX message from the endpoint.

 If "ISTATUS_CTRL[3] (0x1AC)" equals 0, the local processor is responsible for clearing the corresponding "INT_EVT"
status bit to complete the INTX handle flow.
 If "ISTATUS_CTRL[3] (0x1AC)" equals 1, the hardware automatically clears the corresponding "INT_EVT" status bit upon
receiving a DEASSERT INTX message from the endpoint.

Root Complex
Set enable bit in IMASK_LOCAL
(0x180)

Received ASSERT INTx message and

generate local interrupt

After performing requisite actions.

RC should receive DEASERT INTx
message then local processor clears
ISTATUS_LOCAL
(0x184)

Figure 3-205 RC Handles Received INTX Flow If ISTATUS_CTRL[3] Is 0

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[Link].4.2 Receiving MSI Message

In Root port mode, the PCIe Controller has the capability to support up to eight MSI capture addresses, and the local
processor can set them to the "IMSI_LO_ADDR (0xC00 + 0x10N, N = 0 to 7)" and "IMSI_HI_ADDR (0xC80 + 0x04N, N = 0 to
7)" registers.

Whenever the core receives a memory write request at any of these addresses, it signals in the "ISTATUS_LOCAL (0x184)"
register that an MSI has been received, and logs the received message number in the "ISTATUS_MSI (0xC04 + 0x10*N, N =
0 to 7)" register.

Root Complex
Set MSI Capture
Address IMSI_LO_ADDR_F0 and
IMSI_HI_ADDR_F0
(0x0C00 and 0x0C80)

According to EP MSI Number,

Set RC IMASK_MSI_F0
(0xC08)

Enable RC MSI Capture Capability

RC_MSI_EN
(0x190[0])

Enable EP MSI Capability and set MSI

control register properly on EP
Configuration Space

When receiving MSI message from

EP, RC will generate local interrupt
and record MSI status on
ISTATUS_MSI_F0"
(0xC04)

After performing requisite actions.

Local Procesor can clear
ISTATUS_MSI_F0 (0xC04) then
clear ISTATUS_LOCAL (0x184[8])
to de-assert local interrupt

Figure 3-206 RC Handles Received MSI Flow

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Table 3-152 RC Set MSI Capability Example

Set RC Function 0 MSI
Offset Register Name Bit Location Action Value Description
MSI address must be DW alignment; software must
0xC00 IMSI_LO_ADDR_F0 [31:14] W 32’hAAAABBB0
set bit[1:0] to 0.
MSI capture address is 64’hFFFFFFFF_AAAABBB0.
When MAC receives memory write TLP and its address
0xC80 IMSI_HI_ADDR_F0 [31:0] W 32’hFFFFFFFF
is 64’hFFFFFFFF_AAAABBB0, MAC will write MSI data
to 0xC04 of internal register.
0xC08 IMASK_MSI_ F0 [31:0] W 32’h0000_000F Support 4 MSI numbers.
0x190 RC_MSI_EN [0] W 1’b1 Enable RC Function0 MSI capture capability.
Set the local interrupt enable bit to generate a local
0x180 IMASK_LOCAL [8] W 1’b1
interrupt when receiving a Function0 MSI.

Table 3-153 RC Clear MSI Status Example

Clear RC Function 0 MSI
Offset Register Name Bit Location Action Value Description
Check whether local interrupt status and MSI
0x184 ISTATUS_LOCAL [31:0] R 32’h0000_0100
message for function 0 are received.
0xC04 ISTAUS_MSI_F0 [31:0] R 32’h0000_0004 Check MSI Status and received MSI number is 2.
After performing IRQ process, local processor
0xC04 ISTAUS_MSI_F0 [31:0] W 32’h0000_0004
can clear MSI status.
0x184 ISTATUS_LOCAL [31:0] W 32’h0000_0100 Clear local status to de-assert local interrupts

[Link] Power Management

The PCIe controller offers multiple low power modes, including L0s, L1, L1PM (L1 Power Management), L1SS (L1 Power
Management Sub-State), and L2, to cater to various application and scenario requirements.

[Link].1 ASPM L0s Low Power

The ASPM L0s low-power state can be initiated by both the endpoint and rootport cores. This state does not require any
application action, as it is automatically handled by the core.

 The core enters the ASPM L0s state after a pre-defined period of PCIe transmit inactivity, which is set by the ASPM L0s
entry delay (in steps of 256ns from 1 - 31) defined by the "PCIE_PEX_SPC2 (0x0D8)" register.
 The core exits the ASPM L0s state as soon as a packet needs to be transmitted to the PCIe.

[Link].2 ASPM L1 Low Power

The core automatically handles the low-power state without requiring any action from the application.

 The core enters ASPM L1 after a specific period of inactivity, which is determined by the ASPM L1 entry delay. This
delay is set by the "PCIE_PEX_SPC2 (0x0D8)" register and can be adjusted in increments of 256ns between 1 and 31.

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 The core exits ASPM L1 when it needs to transmit a packet to the PCIe or when its link partner exits the low-power
state.

Only endpoint cores can initiate the entry to the ASPM L1 low-power state.
 The endpoint core enters ASPM L1 after a specific period of inactivity, determined by the ASPM L1 entry delay set by
the "PCIE_PEX_SPC2 (0x0D8)" register.
 The Rootport core enters ASPM L1 when requested by its link partner and there are no packets to be transmitted to the
PCIe.
 Both cores exit ASPM L1 when a packet needs to be transmitted to the PCIe or when the link partner exits the low-
power state.

Note:
If the downstream port (Rootport) declines the core’s request to enter ASPM L1 after the specified period of activity, the link will remain
in its full operational state. In this case, the endpoint waits for 10μs before requesting ASPM L1 entry again, following the guidelines of
the PCIe Specification.

[Link].3 L1 Low Power

Only an endpoint core can initiate the entry to the L1 low-power state, but only when its legacy low-power state is not D0.
The core automatically handles this low-power state and does not require any action from the application.

 To enter L1, an endpoint core must set its legacy low-power state to D1, D2, or D3, as indicated by the
"PCIE_ISTATUS_PM (0x19C)" register. Any changes to the legacy power state are reported by the "PM_EVT" bit of the
"ISTATUS_LOCAL (0x184)" register.
 The endpoint core enters L1 when there are no more packets to be transmitted. On the other hand, a Rootport core
enters L1 when its link partner requests entry and there are no packets to be transmitted to the PCIe.
 Both cores exit L1 as soon as a packet needs to be transmitted.
 An endpoint core exits L1 either when directed to do so by its link partner or by setting the "Send_PME" bit in the
"PCIE_ICMD_PM (0x198)" register. This sends a power management event to request that the link partner changes its
legacy power state.

[Link].4 L2 Low Power

The L2 low-power state enables the PCIe link to be completely turned off, but it can only be initiated by a Rootport core.

 To enter the L2 state, a Rootport core disables the link as soon as its link partner is ready and the application sets the
"Turn_Off_Link" bit in the "PCIE_ICMD_PM (0x198)" register.
 The Rootport core exits the L2 state and re-enables the link when the application clears the "Turn_Off_Link" bit in the
"PCIE_ICMD_PM (0x198)" register.
 In contrast, an endpoint core automatically enters the L2 state when directed to do so by its link partner. It can only
exit L2 if directed to do so by its link partner or by setting the "WAKE_N" bit in the "PCIE_MISC_CTRL (0x348)" register.
The latter option sends a request to the link partner to re-enable the link.

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Root Complex
Sets Turn_Off_Link bit in
the PCIE_ICMD_PM (0x198)

Send PME_Turn_Off Message TLP

Receive PME_TO_Ack Message TLP

from Endpoint

LTSSM Enters L2 State and Changes

Power Mode to P2

Figure 3-207 RC Enters L2 State Flow

Root Complex received L2 Wakeup

interrupt or initiate L2 Exit

Clear Turn_Off_Link bit in

the PCIE_ICMD_PM (0x198)

LTSSM Exit L2 State and Enter

[Link] State

Reset Physical Layer and Transaction

Layer including Configuration Space

Transmit Signal to Wake up Endpoint

Figure 3-208 RC Exits L2 State Flow

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[Link].5 Implementing Power Management with CLKREQ#

CLKREQ# is an optional side-band pin that may be available in certain form factors, and is utilized to reduce power
consumption. This feature is supported by the clock power management and L1 PM substates with CLKREQ# features. It
should be noted that only one of these power-saving techniques can be used at any given time.

The functionality of CLKREQ# is implemented through the link capability and link control registers present in the
configuration space. When multiple functions are enabled, each function must be capable of utilizing CLKREQ#.

When CLKREQ# is employed to manage power consumption in the L2 state, the MAC transitions from the P0 to the P2 low
power state to halt the reference clock, and subsequently deasserts CLKREQ#.

In the event that bit [8] of the “PCIE_ICMD_PM (0x198)” register for RC (RC CLKREQ# Clock control) is set to 1 upon entry
into the L1 state, the MAC transitions directly from P0 to P2, bypassing P1. Upon exiting the L1 or L2 states, CLKREQ# is
asserted to restart the Reference Clock.

The waveform below demonstrates an L1 entry where the application does not allow clock removal (bit [8] of the
“PCIE_ICMD_PM (0x198)” register = 0), followed by an L1 entry where clock removal is permitted (bit [8] of the
“PCIE_ICMD_PM (0x198)” register = 1).

Figure 3-209 RC L1 Entry with and without Clock Removal

[Link].5.1 L1PM Sub-States with CLKREQ#

L1 PM sub-states (L1SS) is an extension to the PCIe Specification that permits further power savings in the L1 and ASPM L1
states. This feature is configured through the L1 PM sub-states capability and the T_POWEROFF parameter found in bits
[7:5] of the “PCIE_PEX_L1SS (0x0E0)” register.

If any L1PM Substate enable bit in the configuration space is set to 1 while the core is in the L1 state, it has the ability to
transition to the L1.1 or L1.2 sub-states if all the necessary conditions for this transition are met.

In the event that the L1PM Substate enable bit in the configuration space is set to 0 upon L1 entry, the core will remain in
the L1.0 state. The core's present state is indicated by bits [10:8] of the “PCIE_ISTATUS_PM (0x19C)” register (l1pm_sm).

The PIPE clock (PL_PCLK) may be halted when the core is in the L1.1 or L1.2 sub-states. However, the Transaction Layer
clock (TL_CLK) must continue to operate, albeit at a very low frequency, so that any traffic on the transaction layer transmit
interface will prompt the core to assert CLKREQ# and exit low-power mode.

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If the PCIe registers (PCIe configuration space registers or bridge registers) are accessed via the PCIe link while the core is in
L1, L1.1, or L1.2, the core must exit the low power states. Conversely, if the registers are accessed via the AXI, the core
does not need to exit low power mode.

Table 3-154 RC L1 State Setting

RC CLKREQ# Clock Control L1PM Sub-State Enable Root Complex
L1 Power State
0x198[8] 0x1118[3:0] Power State and CLKREQ# Status
LTSSM = L1
Power State = P1
L1 with P1 0x198[8]==0 0x1118[3:0]==0
L1PM State = L1.0
CLKREQ# Asserted (CLKREQ# is 0)
L1 with P2 (L1PM) LTSSM = L1
(L1 with clock Power State = P2
0x198[8]==1 0x1118[3:0]==0
power L1PM State = L1.0
management) CLKREQ# De-asserted (CLKREQ# is 1)
LTSSM = L1
Power State = P2
L1SS 0x198[8]==0 0x1118[3:0]!=0
L1PM State = L1.1 or L1.2
CLKREQ# De-asserted (CLKREQ# is 1)
LTSSM = L1
Power State = P2
L1SS 0x198[8]==1 0x1118[3:0]!=0
L1PM State = L1.1 or L1.2
CLKREQ# De-asserted (CLKREQ# is 1)

[Link] Theory of Operations

[Link].1 Address Translation Mechanism

The PCIe controller adopts address translation to:

 Convert PCIe read and write requests to any AXI4 master interface read and write transaction.
 Convert any AXI4 slave interface read and write transaction to PCIe read and write requests.
 Convert an address between PCIe domain and AXI domain.

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[Link].1.1 Address Translation for PCIe to AXI Direction

Figure 3-210 RC Receive Memory Write TLP

Figure 3-211 RC Receive Memory Read TLP

[Link].1.1.1 RC mode

In the Root port mode, the core allows the implementation of up to sixteen translation tables.

During the transfer of PCIe received requests to the AXI master, the bridge performs a windows match utilizing the PCIe 64-
bit address. Once a match is detected, the Bridge proceeds to forward the request to the intended AXI4 master interface,
along with the corresponding AXI base address.

For instance, in the diagram below, if a write request is received at address 64’hBBBBBBBB_00020140, the bridge matches
the address with the PCIe window's tables. Upon finding a match in Table 2, the request is forwarded to the AXI4-Master
#0 interface located at address 64’hCCCCCCCC_00000000 + 17’h0140.

The diagram below illustrates the PCIe to AXI4 master address translation in the root port mode.

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PCIe Address Space AXI4 Master #0 Address Space

PCIe Win 0
IO CCCCCCCC_00000000
A1F0 0000 Space #0 Table 0 Table #4
A1F0 7FFF CCCCCCCC_0001FFFF

MEM32 DDDDDDDD_00000000
AAA0 0000
AAA1 FFFF
Space #1 Table 1 Table #1
DDDDDDDD_0001FFFF

Prefetchable PCIe Win 1 AXI4 Master #1 Address Space

BBBBBBBB_00000000 Memory
Space #2 Table 0
Table #0 EEEEEEEE_00000000
Space #3 PFM Table 1 EEEEEEEE_00007FFF

Space #4 PFM Table 2

BBBBBBBB_0003FFFF FFFFFFFF_00000000
Table #1 FFFFFFFF_0000FFFF
Table #2 FFFFFFFF_00010000
FFFFFFFF_0001FFFF

Figure 3-212 PCIe to AXI Master Address Translation for RC

[Link].1.2 Address Translation for AXI to PCIe Direction

Figure 3-213 RC Initiated Memory Write

Figure 3-214 RC Initiated Memory Read

The address translation method utilized for transferring AXI receive requests to the PCIe interface is comparable. The core
allows for up to eight translation tables to be implemented per implemented AXI4-slave interface.

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The following diagram illustrates the AXI4 slave to PCIe address translation.

PCIe Address Space AXI4 Slave #0 Address Space

00000 AAAAAAAA_00000000
Table 0 Space #0
1FFFF AAAAAAAA_0001FFFF

00000 BBBBBBBB_00000000
ABF0 0000
ABF1 FFFF
SLV0 - Table #1 Table 1 Space #1
1FFFF BBBBBBBB_0001FFFF

DDDDDDDD_00000000
DDDDDDDD_0000FFFF SLV1 - Table #0 AXI4 Slave #1 Address Space
0000
Table 0 Space #0 CCCCCCCC_00000000
CCCCCCCC_0000FFFF
FFFF
BBBBBBBB_00000000
SLV0 - Table #0
BBBBBBBB_0001FFFF

Figure 3-215 AXI Slave to PCIe Address Translation for RC

[Link].1.2.1 Set Address Translation Table

[Link].[Link] Address Translation Register

The address translation registers are categorized into six sections based on the internal bus slave port to be translated, as
presented in Table 3-155.

Address translation settings allow for specification of the following parameters:

 Implementation or disablement of the table.

 Table size, ranging from 4 Kbytes to 16 Exabytes (2^64 bytes). If the table size is set to 16 Exabytes, no address
conversion is performed since window matching is always successful. This setting is useful when address translation is
required outside of the bridge.
 Source address, defining the offset address of the table inside the PCIe or AXI slave Window.
 Translated interface, specifying the interface to which the read or write request should be transferred. It can be set to
PCIe, AXI4-Master, or AXI4-Stream.
 Transfer parameters, enabling definition of specific PCIe or AXI attributes or parameters per table.

Table 3-155 Address Translation Table Address

Byte Address Read/Write (R/W) Description
0x0600 – 0x06FF Read only (RO) or RW ATR_PCIE_WIN0: PCIe window 0 address translation tables 0-7
0x0700 – 0x07FF RO or RW ATR_PCIE_WIN1: PCIe window 1 address translation tables 0-7
0x0800 – 0x08FF RO or RW ATR_AXI4_SLV0: AXI4 slave 0 address translation tables 0-7
0x0900 – 0x09FF RO or RW ATR_AXI4_SLV1: AXI4 slave 1 address translation tables 0-7
0x0A00 – 0x0AFF RO or RW ATR_AXI4_SLV2: AXI4 slave 2 address translation tables 0-7
0x0B00 – 0x0BFF RO or RW ATR_AXI4_SLV3: AXI4 slave 3 address translation tables 0-7

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Table 3-156 Transfer Parameter

Targeted Interface Target ID Description
 Bit [2:0]: TLP type
– 3’b000: Memory
– 3’b001: Memory locked
– 3’b011: Translation request
– 3’b101: Memory translated request
– 3’b010: I/O
– 3’b100: Message
– Other values are reserved.
PCIe 4’h0  Bit [3]: Translation request no write (NW) flag (must be 0b when the TLP type is
different from 3’b011).
 Bit [6:4]: TLP attributes
– Bit 4: No snoop
– Bit 5: Relaxed ordering
– Bit 6: ID-based ordering
 Bit [7]: ECRC forward
 Bit [10:8]: Traffic class
 Bit [11]: Reserved
 Bit [3:0]: ACACHE
 Bit [4]: ALOCK
AXI4-Master 4’h4 4’h7
 Bit [7:5]: APROT
 Bit [11:8] AQOS
 Bit [7:0]: TID
AXI4-Stream 4’h8 4’hB
 Bit [11:8]: TDEST

[Link].1.2.2 Programming Address Translation Table (PCIe to AXI Master Direction)

Table 3-157 Set Address Translation Table for PCIe to AXI Direction
For Table0: 0x0600 to 0x061F
Offset Register Name Bit Location Action Value Description
0x600 ATR_IMPL [0] W 1’b1 The table is enabled.
ATR_SIZE [6:1] W 6’d14 Table Size is 2^ (14+1) =32KB.
SRC_ADDR[ATR_SIZE:0] will be ignored to align
SRC_ADDR_LSB [31:12] W 20’b0
the Table size.
Any memory address in 0x00000000_00000000
0x604 SRC_ADDR_MSB [31:0] W 32’b0 to 0x00000000_000007FFF range will match
table0.

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For Table0: 0x0600 to 0x061F

Offset Register Name Bit Location Action Value Description
If the device has multiple functions, it is
necessary to set dedicated BAR number for the
0x608 SRC_BAR [3:0] W 4’d0 table.
If the device has only a single function, the
register would be ignored by the bridge.
If the device has multiple functions, it is
necessary to set dedicated function number for
0x608 SRC_FUNC [8:4] W 5’d0 the table.
If the device has only one single function, the
register would be ignored by the bridge.
TRSL_ADDR[ATR_SIZE:0] will be ignored to align
0x608 TRSL_ADDR_LSB [31:12] W 20’b0
the table size
Any memory address hit table0 is mapped to
0x60C TRSL_ADDR_MSB [31:0] W 32’hEEEEEEEE 0xEEEEEEEE_00000000 to
0xEEEEEEEE_000007FFF.
0x610 TRSL_ID [3:0] W 4’d4 To AXI master 0
TRSF_PARAM [19:16] W 4’d0 AXI master ACACHE value is 0.
TRSF_PARAM [20] W 1’b0 AXI master ALOCK value is 0.
TRSF_PARAM [23:21] W 3’b0 AXI master APROT value is 0.
TRSF_PARAM [27:24] W 4’b0 AXI master AQOS value is 0.

[Link].1.2.3 Programming Address Translation Table (AXI slave to PCIe Direction)

AXI slave0 uses 2 tables to map to 2 destinations.

 Space0 start address: 0xAAAAAAAA_00000000

 As the table0 size of AXI slave0 is 17 bits,
if AXI slave0 address range is between 0xAAAAAAAA_00000000 and 0xAAAAAAAA_0001FFFF, it will match table 0 and
be translated to new memory addresses 0xBBBBBBBB_00000000 to 0xBBBBBBBB_0001FFFF.

PCIe Address Space AXI4 Slave #0 Address Space

00000 AAAAAAAA_00000000
Table 0 Space #0
1FFFF AAAAAAAA_0001FFFF

00000 BBBBBBBB_00000000
ABF0 0000
ABF1 FFFF
SLV0 - Table #1 Table 1 Space #1
1FFFF BBBBBBBB_0001FFFF

DDDDDDDD_00000000
DDDDDDDD_0000FFFF SLV1 - Table #0 AXI4 Slave #1 Address Space
0000
Table 0 Space #0 CCCCCCCC_00000000
CCCCCCCC_0000FFFF
FFFF
BBBBBBBB_00000000
SLV0 - Table #0
BBBBBBBB_0001FFFF

Figure 3-216 AXI Slave to PCIe Address Translation

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Table 3-158 Set Address Translation Table for AXI to PCIe Direction
For AIX Slave0 Table0: 0x0800 to 0x081F
Offset Register Name Bit Location Action Value Description
0x800 ATR_IMPL [0] W 1’b1 The table is enabled.
ATR_SIZE [6:1] W 6’d16 Table Size is 2^ (16+1) =128KB.
SRC_ADDR[ATR_SIZE:0] is ignored to align the
SRC_ADDR_LSB [31:12] W 20’b0
table size.
Any AXI address between
32’hAAAAAAA
0x804 SRC_ADDR_MSB [31:0] W 0xAAAAAAAA_00000000 to
A
0xAAAAAAAA_00001FFFF will match table0.
TRSL_ADDR[ATR_SIZE:0] will be ignored to
0x808 TRSL_ADDR_LSB [31:12] W 20’b0
align the Table size.
Any AXI address hits table0 will be mapped to
0x80C TRSL_ADDR_MSB [31:0] W 32’hBBBBBBBB 0xBBBBBBBB_00000000 to
0xBBBBBBBB_000001FFFF.
0x810 TRSL_ID [3:0] W 4’d0 To PCIe interface
TRSF_PARAM [18:16] W 3’d0 Memory TLP
TRSF_PARAM [19] W 1’b0 NW flag is 0
TRSF_PARAM [22:20] W 3’b0 No snoop
TRSF_PARAM [23] W 1’b0 ECRC is not forwarded.
TRSF_PARAM [26:24] W 3’b0 TC is 0.

[Link].2 Access Configuration Space and Configure TLP Transfer

The CPU located in a specific locality can access its own configuration space, as well as the configuration space of other
devices (in RC mode). This can be achieved through the utilization of the AHB/AXI4-Lite Slave interface or the AXI4 Slave
interface.

[Link].3 Access Configuration Space via AHB/AXI4-Lite Slave Interface

Figure 3-217 RC Configuration Read/Write

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In order to access the PCIe controller register within the range of addresses 0x1000 to 0x1FFF, the accesses are routed
through the PCIe controller backend configuration space interface. This allows a local processor to effectively read from or
write to the PCIe controller configuration space.

Table 3-159 PCIe Configuration Space Register Address for Backend

Byte Address Read/Write (R/W) Description
0x1000 – 0x10FF RO/RW PCI configuration space
0x1100 – 0x1FFF RO/RW PCIe extended configuration space

To access the desired function's configuration Space, it is necessary to appropriately configure the "PCIE_CFGNUM
(0x140)" register prior to accessing the configuration space. See below for the definitions.

Table 3-160 PCIE_CFGNUM (0x140) Bit Definition

Bit Definition
Bit [2:0] FUNC_NUMBER (physical function number)
Bit [7:3] DEVICE_NUMBER
Bit [15:8] BUS_NUMBER
Bit [19:16] BYTE_EN (configuration byte enabled)
Bit [20] FORCE_BE
In situations where the target is the R1C register and the AHB/APB/AXI4-Lite protocol lacks a read strobe,
the byte enables of the CFG read or write request should be set to the "BYTE_EN" field value. This will be
enforced even in cases where the AHB/APB/AXI4-Lite strobes are absent.
Bit [30:24] VFUNC_NUMBER (virtual function number)

In the root port mode, the PCIe controller allows the local processor to access bridge configuration Space and send CFG
read and write requests via the PCIe interface. To accomplish this, the local processor should configure the "PCIE_CFGNUM
(0x140)" register accordingly and access the desired register.

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Set target Bus/Dev/Function

Number in PCIE_CFGNUM
(0x140)

Access desired register address by

AHB/APB/AXI4-Lite Slave Interface

Bus Num == RC Bus Num

&&
Dev Num == RC Dev Num

1. Send CFG TLP (Type0 or Type1) to

Access self Configuration Space access other device configuration
space or
2. Return as Unsupported Request
Completion

Figure 3-218 RC Access Configuration Space by Backend Interface

[Link] Programming Guide

Table 3-161 RC Initialization Sequence
Step Address Register Name Local Address R/W Value Description
PCIe Controller Initialization
Port Type must be chosen as
Rootport.
PCIE_MAC
Please set bit 0 of GEN_SETTINGS
1 Base address port_type GEN_SETTINGS[0] W 1’b1
register (PCIE_MAC Base Address
+0x0080
+0x0080) if the default value is
not as expected.
Reset Setting
PCIE_MAC ResetMAC PCIE_SW [0] 1’b1
Software reset
2 Base address ResetPHY PCIE_SW [1] W 1’b1
PCIE_SW[2:0](PCIE_MAC Base
+0x0148 ResetBRG PCIE_SW [2] 1’b1
Address +0x148) may be
PCIE_MAC ResetMAC PCIE_SW [0] 1’b0
asserted and de-asserted for
3 Base address ResetPHY PCIE_SW [1] W 1’b0
safety purposes.
+0x0148 ResetBRG PCIE_SW [2] 1’b0
PERST# (PCIE_SW[3] (PCIE_MAC
PCIE_MAC Base Address +0x148)) must be
4 Base address ResetPE PCIE_SW [3] W 1’b0 de-asserted for the link
+0x0148 sequence. Please refer to the
reset scenario description.

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Step Address Register Name Local Address R/W Value Description

Misc. Setting
PCIE_MAC The Vendor ID, Device ID,
Base address DeviceID PCIE_PCI_IDS_0[31:16] Appropriate Revision ID, Classcode can be set
5 W
+0x0098 VendorID PCIE_PCI_IDS_0[15:0] value by filling the new value to the
PCIE_PCI_IDS_0 register
(PCIE_MAC Base Address
PCIE_MAC +0x0098), PCIE_PCI_IDS_1
Classcode PCIE_PCI_IDS_1[31:8] Appropriate
6 Base address W register (PCIE_MAC Base Address
RevisionID PCIE_PCI_IDS_1[7:0] value
+0x009C +0x009C) if the default value is
not as expected.
Interrupt enable setting
Enable the corresponded
PCIE_MAC interrupt by setting
Appropriate
8 Base address IMASK_LOCAL[31:0] W IMASK_LOCAL register
value
+0x0180 (PCIE_MAC Base
address+0x0180)
Address Translation setting
PCIE_MAC Set PCIe Address Translation
Base address window for I/O memory,
ATR_PCIE_WIN0
+0x0600~0x07 SRC_ADDR_LSB prefetchable and non-
ATR_PCIE_WIN1
FF SRC_ADDR_MSB prefetchable memory resource.
ATR_AXI_SLV0 Appropriate
9 PCIE_MAC TRSL_ADDR_LSB W Set the address transaction
ATR_AXI_SLV1 value
Base address TRSL_ADDR_MSB window to remap PCIe bus
ATR_AXI_SLV2
+0x0800~0x0B TRSL_PARAM address if there is demand from
ATR_AXI_SLV3
FF the user.

Set 3’b11 to bit 3:2 of

PCIE_BAR_WIN (PCIE_MAC Base
PFWIN_64B address+0x00FC) if Prefetchable
PCIE_MAC
PFWIN_IMPL Appropriate memory resource is needed.
10 Base address PCIE_BAR_WIN[3:0] W
IOWIN_32B value Set 3’b11 to bit 1:0 of
+0x00FC
IOWIN_IMPL PCIE_BAR_WIN (PCIE_MAC Base
address+0x00FC) if IO resource is
needed.
Configuration space setting
Bus_Master_Enable and
MEM_ENABLE should be
asserted by writing 3’b11 to bit
IO_Enable
PCIE_MAC PCIE_CONF_HDR1[0] 1’b1 2:1 of the PCIE_CONF_HDR1
MEM_ENABLE
11 Base address PCIE_CONF_HDR1[1] W 1’b1 register (PCIE_MAC Base
Bus_master_enabl
+0x1004 PCIE_CONF_HDR1[2] 1’b1 address+0x1004), and set IO
e
Enable by writing 1 to bit 0 of the
PCIE_CONF_HDR1 register
(PCIE_MAC Base

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Step Address Register Name Local Address R/W Value Description

address+0x1004) if IO
transaction is needed.
The field of BARX register
(PCIE_MAC Base
PCIE_MAC address+0x1010~) for RC internal
PCIE_CONF_HDR4
Base address Appropriate register accessing via PCIe Host
12 Bar0~Bar1 PCIE_CONF_HDR5 W
+0x1010~0x10 value should be filled with a proper
17 value.
It will be filled up by native driver
during Host boot-up.
It is recommended to give an
effective Subordinate Bus
Number, Secondary Bus Number,
PCIE_CONF_HDR6_TYPE and Primary Bus Number by
1[7:0] writing appropriate values to bit
PCIE_MAC Prim_Bus_Num
PCIE_CONF_HDR6_TYPE Appropriate 23 to 16, bit 15 to 8, and bit 7 to
13 Base address Sec_Bus_Num W
1[15:8] value 0 of the
+0x1018 Sub_Bus_Num
PCIE_CONF_HDR6_TYPE PCIE_CONF_HDR6_TYPE1
1[23:16] register (PCIE_MAC Base
address+0x1018). It will be filled
up by native driver during Host
boot-up.
IO_Base and IO_Limit should be
specified according to the
downstream device I/O Range to
PCIE_CONF_HDR7_TYPE
bit 15 to 12 and bit 7 to 4 of the
PCIE_MAC 1[7:4]
PCIE_CONF_HDR7_TYPE1
Base address IO_Base PCIE_CONF_HDR7_TYPE
register (PCIE_MAC Base
+0x101C IO_Limit 1[15:12] Appropriate
14 W address+0x0101C). IO_Base_Up
PCIE_MAC IO_Base_Up PCIE_CONF_HDR12_TYP value
and IO_Limit_Up should also be
Base address IO_Limit_Up E1[15:0]
specified if IOWIN_32B (bit 1 of
+0x1030 PCIE_CONF_HDR12_TYP
PCIE_BAR_WIN (PCIE_MAC Base
E1[31:16]
address+0x00FC)) is set. It will be
filled up by native driver during
Host boot-up.
PCIE_CONF_HDR8_TYPE Mem_Limit and Mem_Base
1[15:4] should be specified according to
Mem_Base PCIE_CONF_HDR8_TYPE the downstream device Memory
PCIE_MAC Mem_Limit 1[31:20] Range to bit 31 to 20 and bit 15
Base address Pref_Mem_Base PCIE_CONF_HDR9_TYPE Appropriate to 4 of the
15 W
+0x1020~0x10 Pref_Mem_Limit 1[15:4] value PCIE_CONF_HDR8_TYPE1
2F Pref_Base_Up_32b PCIE_CONF_HDR9_TYPE register (PCIE_MAC Base
Pref_Limit_Up_32b 1[31:20] address+0x1020).
PCIE_CONF_HDR10_TYP Pref_Mem_Limit and
E1 Pref_Mem_Base should also be

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Step Address Register Name Local Address R/W Value Description

PCIE_CONF_HDR11_TYP specified according to the
E1 downstream device Memory
Range to bit 31 to 20 and bit 15
to 4 of the
PCIE_CONF_HDR9_TYPE1
register (PCIE_MAC Base
address+0x1024) if
PFWIN_IMPL(bit 2 of
PCIE_BAR_WIN (PCIE_MAC Base
address+0x00FC)) is set.
Pref_Base_Up_32 and
Pref_Limit_Up_32 should also be
specified according to the
downstream device Memory
Range to
PCIE_CONF_HDR10_TYPE1
register (PCIE_MAC Base
address+0x1028) and
PCIE_CONF_HDR11_TYPE1
register (PCIE_MAC Base
address+0x102C) if PFWIN_64B
(bit 3 of PCIE_BAR_WIN
(PCIE_MAC Base
address+0x00FC)) is set. It will be
filled up by native driver during
Host boot-up.

[Link] Register Definition

The PCIe module register consists of:

 The Internal Registers of PCIe Controller

 The PCIe Configuration Space and PCIe Extended Configuration Space, accessible through the PCIe Configuration
interface
 The Extended Internal Register of PCIe Controller

Table 3-162 PCIe Module Register Mapping

Offset Description
0x0000 - 0x0FFF The internal registers of PCIe controller
0x1000 - 0x1FFF The PCIe configuration space and PCIe extended configuration space, accessible through the PCIe
configuration interface
0x2000 - 0x2FFF Reserved
0x3000 - 0x3FFF The extended internal registers of PCIe controller

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Offset Description
0x4000 - 0x7FFF Reserved

[Link].1 Internal Register of PCIe Controller

The internal register of PCIe controller can control PCIe controller. It includes Control, Status, Interrupt, and Event registers.
It maps to PCIe module register offset 0x0000 (PCIE_MAC Base address+0x0000).

Table 3-163 PCIe Internal Register

Offset Description
0x0000 - 0x017F Control and status registers
0x0180 - 0x01FF Interrupt and event registers
0x0200 - 0x02FF Routing, arbitration and priority rules
0x0300 - 0x03FF Interface optional feature definitions
0x0400 - 0x05FF DMA engines registers
0x0600 - 0x0BFF Address translation registers
0x0C00 - 0x0E7F Optional features register
0x0E80 - 0x0EFF MSI-X control registers
0x0F00 - 0x0F7F MSI-X status
0x0F80 - 0x0FFF MSI-X pending bit array registers
0x1000 - 0x1FFF Configuration space registers
0x2000 - 0x2FFF Reserved
0x3000 - 0x3FFF Reserved
0x4000 - 0x7FFF MSI-X table registers

[Link].2 PCIe Configuration Space and PCIe Extended Configuration Space

The PCIe Configuration Space and PCIe Extended Configuration Space are accessible through PCIe Configuration Space
interface. The Configuration Space register maps to PCIe module register offset 0x1000 (PCIE_MAC Base address+0x1000).

Table 3-164 PCIe Configuration Space and PCIe Extended Configuration Space
Offset Description
0x0000 - 0x003F Type 0/1 standard PCI configuration header
0x0040 - 0x007F Reserved
0x0080 - 0x00BB PCIe capability
0x00BC - 0x00CF Reserved
0x00D0 - 0x00DB MSI-X capability
0x00DC - 0x00DF Reserved
0x00E0 - 0x00F7 MSI capability
0x00F8 - 0x00FF PCI power management capability
0x0100 - 0x0107 Vendor-Specific capability
0x0108 - 0x010F LTR capability

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Offset Description
0x0110 - 0x011F L1 PM substates capability
0x0120 - 0x01CF Reserved
0x01D0 - 0x01DB PTM capability
0x01DC - 0x01FF Reserved
0x0200 - 0x0247 AER capability
0x0248 - 0x02FF Reserved
0x0300 - 0x032B Secondary PCIe extended capability
0x032C - 0x0FFF Reserved

[Link] PCIe PHY

[Link].1 Overview

The PCIe PHY is responsible for managing the fundamental PCIe protocol and signaling aspects. This includes critical
functionalities such as data serialization and de-serialization, 8b/10b encoding/decoding, analog buffers, elastic buffers,
and receiver detection mechanisms. The primary objective of this block is to synchronize the data's clock domain from the
original PCIe rate to one that is compatible with the general logic.

[Link].2 Features

 Direct disparity control for use in transmitting compliance pattern(s)

 Clock and Data Recovery (CDR) from serial stream on the PCIe bus
 8b/10b encoding/decoding and error indication
 128b/130b encoding/decoding and error indication
 Port 0 supports RC mode
 Port 0 supports x2 link, link rate of 2.5 GT/s, 5.0 GT/s
 Compliant with PCIe Base Specification Revision 3.0
 Compliant with PHY interface for PCIe (PIPE) 4.0
 Supports legacy PCI power management.
 Supports Active State Power Management (ASPM) L0s and L1 states.
 Supports L1 Power Management Substates (L1PMSS) with CLKREQ#.
 Supports the APB interface for PCIe PHY configuration.

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[Link].3 Block Diagram

PCIE_LNx_RXN
PCIE_LNx_TXN

PCIE_LNx_RXP
PCIE_LNx_TXP
TX Driver RX FE

TX Serial
CDR

Parallel to Serial
De-Serial Serial to Parallel

8b/10b 8b/10b
128b/130b 128b/130b Elastic Buffer
Encoder Decoder

PIPE Interface
PIPE Interface

MAC

Figure 3-219 Block Diagram of PCIe PHY

Figure 3-219 depicts the block diagram of the PCIe PHY, which comprises two primary sub-modules.

 Analog PHY (PHYA): Contains the TX driver, serializer, RX front-end, CDR, and de-serializer.
 Digital PHY (PHYD): Includes essential features such as 8b/10b encoding/decoding, and elastic buffers. These elastic
buffers are utilized to account for any differences in frequencies between the bit rates at each end of a link, whereby
the PCIe Specification stipulates that the elastic buffer can cover a range of ± 300 ppm.

The interface between the PHY and PCIe controller follows the PIPE specification.

REFCLK+
PCIe RC >>
Reference PCIe Endpoint
Clock
REFCLK-
>>

Zc-DC Zc-DC

Figure 3-220 PCIe 100 MHz Reference Clock (REFCLK) Architecture on PCB

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[Link].4 Function Description

[Link].4.1 Far-End Loopback Mode

The request for loopback functionality can be conveyed by setting Symbol 5 bit 2 of the Training Sequence (TS1) ordered
set. Upon issuing the loopback request, both the MAC (LTSSM) and PHY must be in Loopback mode. Therefore, the PCIe
MAC is responsible for controlling the power-down, Loopback, and TXElecIdle features of the PHY through the PIPE
interface. Consequently, the PCIe PHY is set to Loopback mode.

Table 3-165 Loopback Mode Defined in PIPE Specification

powerdown[1:0] TXDectectRX/Loopback TXElecIdle Description

PHY transmits data. MAC provides data bytes to be sent every clock
0 0
cycle.

P0: 2’b00 0 1 PHY does not transmit data and is in electrical idle.
1 0 PHY goes into loopback mode (Far-end loopback).
1 1 Illegal. MAC should never do this.

[Link].4.2 Test Mode for Compliance Test

Upon entering Polling state, the compliance pattern will be transmitted. The Compliance state is designed to evaluate the
conformity of the transmitter and interconnect in the device under test setup with the voltage and timing specifications
outlined in the PCIe base or CEM standards. To enter polling compliance, one of the following conditions must be met:

 (a) the enter compliance bit in the Link Control 2 register is set to 1'b1 before entering polling active state; or
 (b) a passive test load is applied to all transmitter lanes.

[Link].5 PCIe Electrical Characteristics

The PCIe electrical characteristics conform to the standards specified in the PCIe Base Specification Revision 4.0 and PCIe
Card Electromechanical Specification Revision 4.0 for system board usages.

Table 3-166 PCIe 2.5 GT/s Electrical Characteristics

Description Min Typ Max Unit
Data rate 2.5 GT/s
(1)
Unit interval 399.88 - 400.12 ps
Transmitter parameters
TX differential peak-to-peak output voltage(2) 253 - 1200 mV
(2)
TX eye width 246 - - ps
TX DC differential impedance 80 - 120 Ω
Receiver parameters
RX eye width(3) 287 - - ps
RX DC differential impedance 80 - 120 Ω
(1) Do not account for SSC caused variations.
(2) Refer to PCI Express Card Electromechanical Specification Revision 4.0, Section 4.8.10, Table 24.

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(3) Refer to PCI Express Card Electromechanical Specification Revision 4.0, Section 4.8.1, Table 29.

Table 3-167 PCIe 5.0 GT/s Electrical Characteristics

Description Min Typ Max Unit
Data rate 5.0 GT/s
Unit interval(1) 199.94 - 200.06 ps
Transmitter parameters
TX differential peak-to-peak output voltage(2) 225 - 1200 mV
(2)
TX eye width 95 - - ps
TX DC differential impedance - - 120 Ω
Receiver parameters
1.5 to 100 MHz RMS jitter(3) 1.4 - - ps RMS
< 1.5 MHz RMS Jitter 3.0 ps RMS
1.5 – 100 MHz Dj 30 ps PP
> 100 MHz Dj 27 ps PP
(1) Do not account for SSC caused variations.
(2) Refer to PCIe Card Electromechanical Specification Revision 3.0, Section 4.8.2, Table 4-7.
(3) Refer to PCIe Card Electromechanical Specification Revision 3.0, Section 4.8.5, Table 4-13.

Table 3-168 PCIe 100 MHz REFCLK Electrical Characteristics

Description Min Typ Max Unit
(1)
Rising Edge Rate 0.6 4 V/ns
Falling Edge Rate 0.6 4 V/ns
Differential Input High Voltage +150 mV
Differential Input Low Voltage -150 mV
Absolute Crossing Point Voltage (VCROSS) +250 +550 mV
Variation of VCROSS over all rising clock edges +140 mV
Ring-back Voltage Margin (VRB) -100 +100 mV
Time before VRB is allowed 500 ps
Average Clock Period Accuracy -300 +2800 ppm
Absolute Period (including Jitter
9.847 10.203 ns
and Spread Spectrum Modulation)
Cycle to Cycle jitter 150 ps
Absolute Max Input Voltage 1.15 V
Absolute Min Input Voltage -0.3 V
Duty Cycle 40 60 %
Rising edge rate (REFCLK+) to
20 %
falling edge rate (REFCLK-) matching
Clock source DC impedance 40 60 Ω
(1) Before application of SSC.

[Link].6 Power Management

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Table 3-169 Power Requirement

Description Min Typ Max Unit
AVDD12(1) 1.2V-7% 1.2 1.2V+5% V
(1)
AVDD15 1.5V-7% 1.5 1.5V+5% V
(1) The power voltage is defined in package ball node and tolerance includes PCB IR and PMIC variation (DC 1% + AC 4%).

[Link] References

 PCIe Base Specification Revision 3.0

 PCIe Card Electromechanical Specification Revision 3.0
 PCI Power Management Specification Version 1.2
 PHY Interface For the PCIe Version 3.0
 AMBA AXI Specification Version 2.0
 AMBA 4 AXI4 Stream Protocol Specification, Version 1.0 - ARM, March 2010

[Link] Appendix

[Link].1 Clock Related Signal

Signal I/O Width Description Remark

pl_pclk I 1 PIPE clock from PHY. 250 MHz
PCIe Transaction Layer and Bridge Layer Clock from SYSTEM.
tl_clk/br_clk I 1
The two clocks should belong to the same clock group.
AXI clock from the AXI Bus.
axi_clk250 I 1
The clock can be the same as “tl_clk” if AXI runs in “tl_clk” domain.
PCIe timer clock from the system.
ref_clk I 1 >= 20 MHz
The clock can be the same as “tl_clk” if “tl_clk” is fixed frequency.
AHB/APB interface clock from AHB/APB.
ahb_apb_clk I 1 The clock can be the same as “tl_clk” if AHB/APB interface runs in
“tl_clk” domain.
MBIST (Memory Built-In Self-Test) diagnosis clock.
mbist_diag_clk I 1
If there is no diagnosis circuit in MAC, tie to 0.
Indicates the “ref_clk” frequency.
pcie_ref_clock_freq I 22 For example, if ref_clk is 26 MHz, tie to fixed value 26 or register with
default value 26.
Indicates the “tl_clk” frequency.
pcie_tl_clock_freq I 22 For example, if tl_clk is 200 MHz, tie to fixed value 200 or register
with default value 200.
DFT related signal
scan_clk I 1
If the DFT flow is not expected to initiate currently, tie to 0.

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[Link].2 AHB Slave Interface

Signal I/O Width Description

Each AHB slave has its own slave select signal and this signal indicates that the
ahb_pcie_hsel I 1
current transfer is intended for the selected slave.
Indicates the type of the current transfer, which can be NONSEQUENTIAL,
ahb_pcie_htrans I 2
SEQUENTIAL, IDLE or BUSY.
ahb_pcie_haddr I 32 The 32-bit system address bus.
ahb_pcie_hwrite I 1 When HIGH, this signal indicates a write transfer and when LOW, a read transfer.
Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit)
ahb_pcie_hsize I 2
or word (32-bit).
The write data bus is used to transfer data from the master to the bus slaves
ahb_pcie_hwdata I 32
during write operations.
Indicates which byte in HWDATA will be written in a write transfer.
ahb_pcie_hbstrb I 4
If AHB master does not support write strobe, just tie the signal to 4’hf.
When HIGH, the HREADY_IN signal informs all slaves that the previous transfer is
ahb_pcie_hready I 1
complete.
The read data bus is used to transfer data from bus slaves to the bus master
ahb_pcie_slv_hrdata O 32
during read operations.
ahb_pcie_slv_hready O 1 When HIGH, the HREADY signal indicates that a transfer has finished on the bus.

[Link].3 AXI Master Interface

The table below enumerates the signals present in the AXI4 master 0 interface. These signals are also utilized for the
following interface signals:

 AXI4 Master 1 (axi4_mst1_)

 AXI4 Master 2 (axi4_mst2_)
 AXI4 Master 3 (axi4_mst3_)

Signal Width I/O Description

axi4_mst0_awid 4 O Write address ID
axi4_mst0_awaddr 64 O Write address bus
axi4_mst0_awregion 4 O Write region
axi4_mst0_awlen 8 O Burst length
axi4_mst0_awsize 3 O Burst size
axi4_mst0_awburst 2 O Burst type
axi4_mst0_awlock 1 O Lock type
axi4_mst0_awcache 4 O Cache type
axi4_mst0_awprot 3 O Protection type
axi4_mst0_awqos 4 O QoS value
Function Number: When several physical and/or virtual functions are
axi4_mst0_awfunc 12 O implemented, this signal indicates which function has initiated the
request.

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Signal Width I/O Description

 Bit [8:0]: Virtual Function Number:
 0 indicates that the physical function has initiated the request,
 1 - 511 indicate that one of the virtual functions 1 to 511 has
initiated the request.
This signal must be tied to 0s if virtual functions are not implemented.
 Bit [11:9]: Physical Function Number
This signal must be tied to 0s if only one physical function is
implemented.
Write Address user side band signal:
 Bit [0]: Asserted to 1b when an ECRC error is detected in the AXI
Burst
 Bit [1]: Asserted to 1b when a PCIe Memory Error (Poisoned TLP
Reception or Receive Buffer Memory Error) is detected in the AXI
Burst
 Bit [2]: Asserted to 1b when a Bridge Buffer Memory Error is
detected in the AXI Burst
 Bit [3]: Asserted to 1b when an AXI Application Data Error is
detected in the AXI Burst (only relevant if the transaction's
requester is an AXI slave Interface).
 Bit [7:4]: Provides the transaction's requester module. Allowed
values for this field are:
– 4’d0: PCIe RX Interface, received on even BAR
– 4’d1: PCIe RX Interface, received on odd BAR
– 4’d2: AXI4-Lite Slave Interface
– 4’d4 + k: AXI4 Slave Number k=0 - 3 Interface
axi4_mst0_awuser 32 O – 4’d8 + k: DMA Engine Number k=0 - 7
 Bit [9:8]: Address Type (00b: Untranslated, 01b: Translation
Request, 10b: Translated)
 Bit [10]: Reserved
 Bit [12:11]: When the transaction's requester module is the PCIe RX
Interface, this field indicates from which BAR the request has come.
Allowed values for this field are:
– 2’d0: Request was received on BAR0 when
AXI4_MST0_AWUSER[4]=0, or on BAR1 when
AXI4_MST0_AWUSER[4]=1
– 2’d1: Request was received on BAR2 when
AXI4_MST0_AWUSER[4]=0, or on BAR3 when
AXI4_MST0_AWUSER[4]=1
– 2’d2: Request was received on BAR4 when
AXI4_MST0_AWUSER[4]=0, or on BAR5 when
AXI4_MST0_AWUSER[4]=1
– 2’d3: Request was received on expansion ROM
 Bit [13]: PCIe attribute value for No Snoop

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Signal Width I/O Description

 Bit [14]: PCIe attribute value for relaxed ordering
 Bit [15]: PCIe attribute value for ID-based ordering
 Bit [31:16]: PCIe requester ID
axi4_mst0_awvalid 1 I Write address valid
axi4_mst0_awready 1 O Write address ready
axi4_mst0_wid 4 O Write ID (for AXI3; unused in AXI4)
64, 128, or Write ID (for AXI3; unused in AXI4)
axi4_mst0_wdata O
256
Write Data Error:
 If G_DATA_PROT=0:
– Bit [0]: Bridge Buffer uncorrectable read error: this bit is asserted
when an uncorrectable error has been detected by the memory's
ECC logic when reading data from the PCIe2AXI buffer. The error
is reported on the same clock cycle as the affected data.
– Bit [31:1]: Reserved
 If G_DATA_PROT=1:
– Bit [0]: Parity for AXI4_MST0_WDATA[31:0]
– Bit [3:1]: Reserved
– Bit [4]: Parity for AXI4_MST0_WDATA[63:32]
– Bit [7:5]: Reserved
– …
– Bit [28]: Parity for AXI4_MST0_WDATA[255:224]
axi4_mst0_wderr 8, 16, or 32 O
– Bit [31:29]: Reserved
 If G_DATA_PROT=4:
– Bit [0]: Parity for AXI4_MST0_WDATA[7:0]
– Bit [0]: Parity for AXI4_MST0_WDATA[15:8]
– …
– Bit [31]: Parity for AXI4_MST0_WDATA[255:248]
When data protection is implemented (G_DATA_PROT =1 or =4), this
signal contains the data protection bits for the data transmitted on
AXI4_MST0_WDATA on the same clock cycle.
Note that parity is not checked for 8-bit bytes or 32-bit words that are
not valid, as indicated by AXI4_MST0_WSTRB on the same clock cycle.
Note also that bridge buffer uncorrectable read errors are reported by
corrupting all data protection bits on the same clock cycle as the
affected data.
axi4_mst0_wstrb 8, 16, or 32 O Write strobes
axi4_mst0_wlast 1 O Write last
axi4_mst0_wvalid 1 O Write valid
axi4_mst0_wready 1 I Write ready
axi4_mst0_bid 4 I Response ID
axi4_mst0_bresp 2 I Write response

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Signal Width I/O Description

axi4_mst0_bvalid 1 I Write response valid
axi4_mst0_bready 1 O Write response
axi4_mst0_arid 4 O Read address ID
axi4_mst0_araddr 64 O Read address bus
axi4_mst0_arregion 4 O Read region
axi4_mst0_arlen 8 O Burst length
axi4_mst0_arsize 3 O Burst size
axi4_mst0_arburst 2 O Burst type
axi4_mst0_arlock 1 O Lock type
axi4_mst0_arcache 4 O Cache type
axi4_mst0_arprot 3 O Protection type
axi4_mst0_arqos 4 O QoS value
Function Number: When several physical and/or virtual functions are
implemented, this signal indicates which function has initiated the
request.
 Bit [8:0]: Virtual Function Number:
 0 indicates that the physical function has initiated the request,
axi4_mst0_arfunc 12 O  1 - 511 indicate that one of the virtual functions 1 to 511 has
initiated the request. This signal must be tied to 0s if virtual
functions are not implemented.
 Bit [11:9]: Physical Function Number
This signal must be tied to 0s if only one physical function is
implemented.
Read Address user side band signal:
 Bit [0]: Asserted to 1b when an ECRC error is detected in the AXI
Burst
 Bit [1]: Asserted to 1b when a PCIe Memory Error (Poisoned TLP
Reception or Receive Buffer Memory Error) is detected in the AXI
Burst
 Bit [2]: Asserted to 1b when a Bridge Buffer Memory Error is
detected in the AXI Burst.
 Bit [3]: Asserted to 1b when an AXI Application Data Error is
axi4_mst0_aruser 32 O
detected in the AXI Burst (only relevant if the transaction's
requester is an AXI slave Interface).
 Bit [7:4]: Provides the transaction's requester module. Allowed
values for this field are:
 4’d0: PCIe RX Interface, received on even BAR
 4’d1: PCIe RX Interface, received on odd BAR
 4’d2: AXI4-Lite Slave Interface
 4’d4 + k: AXI4 Slave Number k=0 - 3 Interface
 4’d8 + k: DMA Engine Number k=0.7

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Signal Width I/O Description

 Bit [9:8]: Address Type (00b: Untranslated, 01b: Translation Request,
10b: Translated)
 Bit [10]: Translation Request No Write (NW) flag
 Bit [12:11]: When the transaction's requester module is PCIe RX
Interface, this field indicates from which BAR the request has come.
Allowed values for this field are:
 2’d0: Request was received on BAR0 when
AXI4_MST0_ARUSER[4]=0, or on BAR1 when
AXI4_MST0_ARUSER[4]=1
 2’d1: Request was received on BAR2 when
AXI4_MST0_ARUSER[4]=0, or on BAR3 when
AXI4_MST0_ARUSER[4]=1
 2’d2: Request was received on BAR4 when
AXI4_MST0_ARUSER[4], or on BAR5 when
AXI4_MST0_ARUSER[4]=1
 2’d3: Request was received on Expansion ROM
 Bit [13]: PCIe Attribute value for No Snoop
 Bit [14]: PCIe Attribute value for Relaxed Ordering
 Bit [15]: PCIe Attribute value for ID-Based Ordering
 Bit [31:16]: PCIe Requester ID
axi4_mst0_arvalid 1 O Read address valid
axi4_mst0_arready 1 I Read address ready
axi4_mst0_rid 4 I Response ID
64, 128, or Read data
axi4_mst0_rdata I
256
Read Data Error:
 If G_DATA_PROT=0:
 Bit [0]: Buffer uncorrectable read error: this bit allows the
application to report a data error in the data phase(s) in which
it is asserted.
 Bit [31:1]: Reserved.
 If G_DATA_PROT=1:
 Bit [0]: Parity for AXI4_MST0_RDATA[31:0]
 Bit [3:1]: Reserved
axi4_mst0_rderr 8, 16, or 32 I
 Bit [4]: Parity for AXI4_MST0_RDATA[63:32]
 Bit [7:5]: Reserved
 ...
 Bit [28]: Parity for AXI4_MST0_RDATA[255:224]
 Bit [31:29]: Reserved
 If G_DATA_PROT=4:
 Bit [0]: Parity for AXI4_MST0_RDATA[7:0]
 Bit [0]: Parity for AXI4_MST0_RDATA[15:8]
 ...

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Signal Width I/O Description

 Bit [31]: Parity for AXI4_MST0_RDATA[255:248]
When data protection is implemented (G_DATA_PROT =1 or =4), this
signal contains the data protection bits for the data transmitted on
AXI4_MST0_RDATA on the same clock cycle. Note that parity is not
checked for 8-bit bytes or 32-bit words that are not valid, as indicated by
AXI4_MST0_ARADDR/ARSIZE/ARLEN on the same clock cycle.
axi4_mst0_rresp 2 I Read response
axi4_mst0_rlast 1 I Read last
Read user side band signal:
 Bit [3:0]: Reserved
 Bit [4]: Asserted to 1b to indicate that this burst must be discarded.
axi4_mst0_ruser 32 I
If the device that initiated the read request is a PCIe device, then this
device will later detect a PCIe Completion timeout.
 Bit [31:5]: Reserved
axi4_mst0_rvalid 1 I Read valid
axi4_mst0_rready 1 O Read ready

[Link].4 AXI4 Slave Interfaces

The following table lists the signals in the AXI4 Slave 0 interface. The same signals are used for the AXI4 Slave 1
(axi4_slv1_), AXI4 Slave 2 (axi4_slv2_), and AXI4 Slave 3 (axi4_slv3_) interface signals.

Signal Width I/O Description

axi4_slv0_awid 4 I Write address ID
axi4_slv0_awaddr 64 I Write address bus
axi4_slv0_awregion 4 I Write region
axi4_slv0_awlen 8 I Burst length
axi4_slv0_awsize 3 I Burst size
axi4_slv0_awburst 2 I Burst type
axi4_slv0_awlock 1 I Lock type
axi4_slv0_awcache 4 I Cache type
axi4_slv0_awprot 3 I Protection type
axi4_slv0_awqos 4 I QoS value
Function Number: When several physical and/or virtual functions
are
implemented, this signal indicates which function has initiated the
request.
 Bit [8:0]: Virtual Function Number:
axi4_slv0_awfunc 12 I  0 indicates that the physical function has initiated the
request,
 1 - 511 indicate that one of the virtual functions 1 to 511
has initiated the request.
This signal must be tied to 0s if virtual functions are not

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Signal Width I/O Description

implemented.
 Bit [11:9]: Physical Function Number
This signal must be tied to 0s if only one physical function is
implemented.
axi4_slv0_awvalid 1 I Write address valid
axi4_slv0_awready 1 O Write address ready
axi4_slv0_wid 4 I Write ID (for AXI3; unused in AXI4)
axi4_slv0_wdata 64, 128, or 256 I Write data
Write Data Error:
 If G_DATA_PROT=0:
 Bit [0]: Buffer uncorrectable read error: this bit allows the
application to report a data error in the data phase(s) in
which it is asserted.
 Bit [31:1]: Reserved.
 If G_DATA_PROT=1:
 Bit [0]: Parity for AXI4_SLV0_WDATA[31:0]
 Bit [3:1]: Reserved
 Bit [4]: Parity for AXI4_SLV0_WDATA[63:32]
 Bit [7:5]: Reserved
 ...
axi4_slv0_wderr 8, 16, or 32 I
 Bit [28]: Parity for AXI4_SLV0_WDATA[255:224]
 Bit [31:29]: Reserved
 If G_DATA_PROT=4:
 Bit [0]: Parity for AXI4_SLV0_WDATA[7:0]
 Bit [0]: Parity for AXI4_SLV0_WDATA[15:8]
 ...
 Bit [31]: Parity for AXI4_SLV0_WDATA[255:248]
When data protection is implemented (G_DATA_PROT =1 or =4),
this signal contains the data protection bits for the data
transmitted on AXI4_SLV0_WDATA on the same clock cycle. Note
that parity is not checked for 8-bit bytes or 32-bit words that are
not valid, as indicated by AXI4_SLV0_WSTRB on the same clock
cycle.
axi4_slv0_wstrb 8, 16, or 32 I Write strobes
axi4_slv0_wlast 1 I Write last
axi4_slv0_wvalid 1 I Write valid
axi4_slv0_wready 1 O Write ready
axi4_slv0_bid 4 O Response ID
axi4_slv0_bresp 2 O Write response
axi4_slv0_bvalid 1 O Write response valid
axi4_slv0_bready 1 I Response ready
axi4_slv0_arid 4 I Read address ID
axi4_slv0_araddr 64 I Read address bus
axi4_slv0_arregion 4 I Read region

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Signal Width I/O Description

axi4_slv0_arlen 8 I Burst length
axi4_slv0_arsize 3 I Burst size
axi4_slv0_arburst 2 I Burst type
axi4_slv0_arlock 1 I Lock type
axi4_slv0_arcache 4 I Cache type
axi4_slv0_arprot 3 I Protection type
axi4_slv0_arqos 4 I QoS value
Function Number: When several physical and/or virtual functions
are
implemented, this signal indicates which function has initiated the
request.
 Bit [8:0]: Virtual Function Number:
 0 indicates that the physical function has initiated the
request
axi4_slv0_arfunc 12 I
 1 - 511 indicate that one of the virtual functions 1 to 511
has initiated the request.
This signal must be tied to 0s if virtual functions are not
implemented.
 Bit [11:9]: Physical Function Number
This signal must be tied to 0s if only one physical function is
implemented.
axi4_slv0_arvalid 1 I Read address valid
axi4_slv0_arready 1 O Read address ready
axi4_slv0_rid 4 O Response ID
axi4_slv0_rdata 64, 128, or 256 O Read data
Read Data Error:
 If G_DATA_PROT=0:
 Bit [0]: Bridge Buffer uncorrectable read error: this bit is
asserted when an uncorrectable error has been detected
by the memory's ECC logic when reading data from the
PCIe2AXI buffer. The error is reported on the same clock
cycle as the affected data.
 Bit [31:1]: Reserved.
 If G_DATA_PROT=1:
axi4_slv0_rderr 8, 16, or 32 O  Bit [0]: Parity for AXI4_SLV0_RDATA[31:0]
 Bit [3:1]: Reserved
 Bit [4]: Parity for AXI4_SLV0_RDATA[63:32]
 Bit [7:5]: Reserved
 ...
 Bit [28]: Parity for AXI4_SLV0_RDATA[255:224]
 Bit [31:29]: Reserved
 If G_DATA_PROT=4:
 Bit [0]: Parity for AXI4_SLV0_RDATA[7:0]
 Bit [0]: Parity for AXI4_SLV0_RDATA[15:8]

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Signal Width I/O Description

 ...
 Bit [31]: Parity for AXI4_SLV0_RDATA[255:248]
When data protection is implemented (G_DATA_PROT = 1 or = 4),
this signal contains the data protection bits for the data
transmitted on AXI4_SLV0_RDATA on the same clock cycle. Parity is
not checked for 8-bit bytes or 32-bit words that are not valid, as
indicated by AXI4_SLV0_ARADDR/ARSIZE/ARLEN. Bridge Buffer
uncorrectable read errors are reported by corrupting all data
protection bits on the same clock cycle as the affected data.
axi4_slv0_rresp 2 O Read response
axi4_slv0_rlast 1 O Read last
Read user side band signal:
 Bit [0]: Asserted to 1b when an ECRC error is detected in the
AXI Burst
 Bit [1]: Asserted to 1b when a PCIe Memory Error (Poisoned
TLP Reception or Receive Buffer Memory Error) is detected in
the AXI Burst
 Bit [2]: Asserted to 1b when a Bridge Buffer Memory Error is
detected in the AXI Burst
axi4_slv0_ruser 32 O  Bit [3]: Reserved
 Bit [4]: Asserted to 1b to indicate that this AXI Burst was
inferred by the Bridge due to a PCIe completion timeout or a
discarded AXI packet (with the read response = SLVERR)
 Bit [12:5]: Reserved
 Bit [13]: PCIe Attribute value for No Snoop
 Bit [14]: PCIe Attribute value for Relaxed Ordering
 Bit [15]: PCIe Attribute value for ID-Based Ordering
 Bit [31:16]: PCIe Completer ID
axi4_slv0_rvalid 1 O Read valid
axi4_slv0_rready 1 I Read ready

[Link].5 PIPE Interface

Signal I/O Width Description

pl_powerdown Power Down: determines the power state (P0, P0s, P1, or
O 2
(common to all lanes) P2).
Link Signaling Rate: controls the link signaling rate:
 00: Use 2.5 GT/s signaling rate
pl_rate
O 2  01: Use 5.0 GT/s signaling rate
(common to all lanes)
 10: Reserved
 11: Reserved
pl_width PIPE Interface Width: indicates current PIPE interface
O 2
(common to all lanes) width

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Signal I/O Width Description

 00: 8-bit
 01: 16-bit
 10: 32-bit
 11: 64-bit
This signal can be left unconnected if not present on the
PHY
PIPE Interface Clock Rate: indicates current PIPE interface
clock rate
 000: 62.5 MHz
 001: 125 MHz
pl_pclk_rate  010: 250 MHz
O 3
(common to all lanes)  011: 500 MHz
 100: 1 GHz
 111: 101: Reserved
This signal can be left unconnected if not present on the
PHY.
pl_txmargin
O 3 Transmit Margin: selects transmitter voltage levels.
(common to all lanes)
pl_txswing
O 1 Transmitter Voltage Swing Level
(common to all lanes)
pl_txdeemph Transmitter Deemphasis at 5.0 GT/s
O 2
(common to all lanes) Only for Gen2 PHY.
Transmit Detect Receive: Prompts the PHY to start a
pl_txdetectrx_common receiver detection operation or to begin loopback.
O 1
(common to all lanes) If the PHY has a single TX/RX Detect input, please use the
signal.
For L1SS Function.
Enable L1SS function in PHY.
pl_l1ss_l1ss_en
O 1 Proprietary signal for MediaTek PHY.
(common to all lanes)
This signal can be left unconnected if not present on the
PHY.
For L1SS Function.
Disable electrical idle detect logic in PHY.
pl_l1ss_rx_ei_dis
O 1 Proprietary signal for MediaTek PHY.
(common to all lanes)
This signal can be left unconnected if not present on the
PHY.
For L1SS Function.
Disable transmitter DC common mode logic in PHY.
pl_l1ss_tx_cm_dis
O 1 Proprietary signal for MediaTek PHY.
(common to all lanes)
This signal can be left unconnected if not present on the
PHY.
pl_l1ss_l1p2_prd
O 1 For L1SS Function.
(common to all lanes)

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Signal I/O Width Description

Indicate MAC is in L1.2 state including L1.2_ETNRY/
L1.2_IDLE/ L1.2_EXIT
Proprietary signal for MediaTek PHY.
This signal can be left unconnected if not present on the
PHY.
For SRIS Function.
pl_sris_enable Enable SRIS function in PHY.
O 1
(common to all lanes) This signal can be left unconnected if not present on the
PHY.
Transmit Detect Receive:
Prompts the PHY to start a receiver detection operation or
pl_txdetectrx
O N_L to begin loopback.
(per lane)
If the PHY has per-lane TX-Detect-RX input, please use the
signal.
pl_txdata G_PCIE_PIPE_IF
O Transmit Data
(per lane) _W*8*N_L
pl_txdatak G_PCIE_PIPE_IF Transmit Data Control
O
(per lane) _W_G2*N_L The DATAK width depends on Gen2 data width.
pl_txelecidle Transmit Electrical Idle:
O N_L
(per lane) Forces the transmit output to electrical idle.
Transmit Compliance:
pl_txcompliance Forces the running disparity to negative in Compliance
O N_L
(per lane) mode (negative COM character) and can also be used to
turn off Lanes that are not initialized
Receive Polarity:
pl_rxpolarity
O N_L Prompts the PHY layer to perform a polarity inversion on
(per lane)
the receiver decoding block.
PHY RX Control. This signal can be left unconnected if this
pl_rxstandby port does not exist on the PHY.
O N_L
(per lane) This signal can be left unconnected if not present on the
PHY.
PHY Status:
pl_phystatus
I N_L If PHY has a single PHY status output, the same value can
(per lane)
be replicated on all PL_PHYSTATUS bits.
pl_rxstatus Receive Status: encodes receive status and error codes for
I 3*N_L
(per lane) the receive data stream and receiver detection.
pl_rxdata G_PCIE_PIPE_IF
I Receive Data
(per lane) _W*8*N_L
pl_rxdatak G_PCIE_PIPE_IF Receive Data Control
I
(per lane) _W_G2*N_L The DATAK width depends on Gen2 data width.
pl_rxelecidle Receive Electrical Idle: indicates-that electrical idle is
I N_L
(per lane) detected on receiver lane.

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[Link].6 IO Related Signals

Signal Name Type Description Ball Location

PCIe Control Signals Port
PERSTN DO Fundamental reset AA3, AA8
CLKREQN DIO Clock request AA1, AC8
WAKEN DI Link reactivation AA4, AB3
PCIe Port
PCIE_CKN(1) AI AN3
Reference clock differential pair
(1)
PCIE_CKP AI AN4
PCIE_LN0_RXN AI AP1
Lane 0 receive data differential pair
PCIE_LN0_RXP AI AP2
PCIE_LN0_TXN AO AM2
Lane 0 transmit data differential pair
PCIE_LN0_TXP AO AM1
(1) Connect this pin through an external 49.9 Ω (1%) resistor to GND.

[Link].7 Interrupt Related Signals

Signal I/O Width Description Note

PCIe main interrupt output.
pcie_interrupt_out O 1 tl_clk domain
It is a level signal and is active high.

3.12.8 Keypad Scanner (Keypad)

[Link] Keypad Overview

The keypad module implements a scanning algorithm for hardware-based key press decoding and reduces CPU
overhead.

[Link] Keypad Features

The keypad module supports the following features:

 Two types of keyboards:

 2 × 2 single keys
 2 × 2 configurable double keys
 Configurable key debounce time
 The double keypad supports an 8-key matrix divided into 4 subgroups of 2 keys and a 20 Ω resistor
 Key detection block providing key press, key release, and de-bounce mechanisms
 Interrupt event detection for key presses and key releases
 Detection of one or two keys pressed simultaneously with any combination

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[Link] Keypad Block Diagram

The keypad module contains 2 submodules, KP0 and KP1. KP0 supports single keys, and KP1 supports double keys. Figure
3-221 and Figure 3-222 show the structural block diagrams of Keypad Top and KP1.

kp0_row_enable[1:0]
f32k_ck
keypad_krow_oe[1:0]
KP0
APB kp0_row_scan[1:0]
(single key)
keypad_kcol_i[1:0] keypad_krow_o[1:0]

kp0_irq_b
kp_irq_b
row_enable[1:0]
row_scan[1:0]
2'h3
col_enable[1:0] keypad_kcol_oe[1:0]
KP1 col_scan[1:0]
keypad_kcol_o[1:0]
keypad_krow_i[1:0] (double key) kp1_irq_b
2'h3

Figure 3-221 Block Diagram of Keypad Top

KP1
32kHz clk
Kp_counter

kp_fsm
irq_b
APB_BUS Kp_register

keypad_kcol_i[1:0] keypad_krow_o[1:0]
keypad_krow_oe[1:0]
keypad_krow_i[1:0] Kp_scanner keypad_kcol_o[1:0]
keypad_kcol_oe[1:0]

Figure 3-222 KP1 Block Diagram

KP1 comprises the following modules:

Table 3-170 KP1 Module Description

Module Description
The register control module, housing the registers the APB can read and write. It is also
Kp_register
responsible for sampling the present state of the keys.

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Module Description
Kp_scanner Scans the keypad state.
Kp_FSM Manages the working flow of the keypad and generates an IRQ signal.
Kp_counter Counts the de-bounce time.

[Link] Keypad Signal Descriptions

Table 3-171 presents keypad signal descriptions.

Table 3-171 Keypad Signal Descriptions

Signal Name Type Description Ball Location
KPCOL0 DIO KeyPad column 0 H31
KPCOL1 DIO KeyPad column 1 J31
KPROW0 DIO KeyPad row 0 J30
KPROW1 DIO KeyPad row 1 K30

[Link] Keypad Function Description

The keypad module supports two types of keypads: 2 × 2 single keys and 2 × 2 configurable double keys. The keypad
interface includes 2 columns and 2 rows (see Figure 3-221). The key detection block provides the key pressed, key released
and de-bounce mechanisms.

Each time the key is pressed or released, i.e. something different in the 2 × 2 matrix, the key detection block senses the
change and recognizes if a key has been pressed or released. Whenever the key status changes and becomes stable, a
keypad IRQ is issued. Then, the MCU can read the key(s) pressed directly in the KP_MEM1 and KP_MEM2 registers. The
status register can only be changed by the key press detection FSM.

[Link] Keypad Theory of Operations

Key press detection depends on the HIGH or LOW level of the external keypad interface. If the keys are pressed at the
same time, and a key shares the same column and the same row with other keys, the pressed key cannot be correctly
decoded. For example, if there are three keys pressed: key1 = (x1, y1), key2 = (x2, y2), and key3 = (x1, y2), both key3 and
key4 = (x2, y1) are detected, and therefore, they cannot be distinguished correctly. Hence, the keypad detects only one key
or two keys pressed simultaneously in any combination. Pressing more than two keys simultaneously in a specific pattern
may cause wrong information retrieval.

When the state of the key matrix changes, there is a de-bounce time. Set a suitable de-bounce time before enabling the
Keypad. If the time value is set too small, the Keypad becomes overly sensitive and detects multiple unexpected key
presses.

[Link] Keypad Programming Guide

Table 3-172 presents Keypad setting flow.

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Table 3-172 Keypad Setting Flow

Default
Step Address Register Name MSB LSB Local Address R/W Description
Value
Set up keypad
Select the single
keypad base
1 KP_SEL 0 0 KP_SEL RW 1’b0 keypad or the double
address + 0x020
keypad function
Set de-bounce time.
keypad base
2 KP_DEBOUNCE 13 0 DEBOUNCE RW 14'h400 De-bounce time =
address + 0x018
KP_DEBOUNCE/32 ms.
keypad base
3 KP_EN 0 0 KP_EN RW 1’d0 Enable keypad scanner
address + 0x024
Wait for keypad to issue an interrupt and read keypad MEM register.
Read keypad status
keypad base
4 KP_STA 0 0 STA RO 1'b0 0: No key pressed
address + 0x000
1: Key pressed

keypad base Read keypad MEM

5 KP_MEM1 15 0 KEY15~KEY0 RO 16’hffff
address + 0x004 register

keypad base Read keypad MEM

6 KP_MEM2 15 0 KEY31~KEY16 RO 16’hffff
address + 0x008 register

[Link] Keypad Applications

The 2 × 2 double Keypad supports a 2 × 2 × 2 = 8-key matrix. The 8 keys are divided into 4 subgroups, and each
group consists of 2 keys and a 20 Ω resistor.

Figure 3-223 represents a 2 × 2 double Keypad matrix (8 keys) example configuration.

Device

KCOL1

KCOL0

KROW0 0 2

1 3

KROW1 13 15

14 16

Figure 3-223 2 × 2 KeyPad Matrix (8 Keys)

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3.12.9 General-purpose Input/Output (GPIO)

[Link] Overview
The General-Purpose Input/Output (GPIO) peripheral provides dedicated pins that are configurable as either inputs or
outputs. Each GPIO pin has the following key functions:

 Configurable direction: Input or output

 Control of the state driven on the output pin when GPIO is configured as an output
 Detection of the state of the pin when GPIO is configured as an input
 Configurable interrupt event generation

[Link] Features

[Link].1 Pad Pin List

The MT8390 offers the following types of pin control for GPIO. The corresponding I/O cells are described in the tables
below.

I/O Cell Table

General 1.8V I/O cell Table 3-175
KP2K I/O cell Table 3-176
KP200K I/O cell Table 3-177
I3C I/O cell Table 3-178
RST I/O cell Table 3-179
MSDC3A18 I/O cell Table 3-180
MSDC3A18OD33 I/O cell Table 3-181
AGPIO General 1.8V I/O cell Table 3-182

Table 3-173 GPIO Pin Control

Pin Description
The pad can be used in either Transmit (TX) or Receive (RX) mode, which is configured by the E pin of
the pad.
E pin
 E = 1, TX mode, the TX path is from I to I/O.
 E = 0, RX mode, the RX path is from I/O to O.
E2/E4/E8 pin To configure the TX driving strength. See Table 3-174 for details.
To control the RX input buffer.
IES pin  IES = 1, the RX path is enabled
 IES = 0, the RX path is disrupted, and O pin is 0
SMT pin Schmitt trigger hysteresis control
PU/PD pin To pull up or pull down the resistor.

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Table 3-174 Driving Strength Control

{E8, E4, E2} Driving Strength (mA)
3’b000 2
3’b001 4
3’b010 6
3’b011 8
3’b100 10
3’b101 12
3’b110 14
3’b111 16

[Link].2 I/O Cell

Table 3-175 General 1.8V I/O Cell

Pin Description Type Level Description Note
I Input 0.75V Input signal of driver
Data input/output.
Input/
IO 1.8V Output pin of driver (TX mode)/input pin of receiver
Output
(RX mode)
To enable output. High asserted.
E Input 0.75V
E = 1, TX mode; E = 0, RX mode.
Register programmable 2G Type
(E8, E4, E2):
2mA: [000] 10mA: [100]
E2, E4, E8 Input 0.75V TX driving strength control
4mA: [001] 12mA: [101]
6mA: [010] 14mA: [110]
8mA: [011] 16mA: [111]
O Output 0.75V Output signal of RX receiver
To enable RX input buffer. High asserted data path:
from IO to O. IES = 0, O = 0
IES Input 0.75V
For VIO turn-off applications, IES = 0 prevents
leakage in VDDIO power domain.
To enable RX input buffer Schmitt trigger hysteresis
SMT Input 0.75V control. High asserted. Register programmable
SMT= 1, Schmitt trigger enabled
PU Input 0.75V 75K pull-up resistor control. High activation Register programmable
PD Input 0.75V 75K pull-down resistor control. High activation Register programmable
RX duty selection
 RDSEL[0]: Level shifter duty high when asserted Register programmable
RDSEL[1:0] Input 0.75V (high pulse width adjustment) Default setting:
 RDSEL[1]: Level shifter duty low when asserted 1.8V: RDSEL[1:0]=[00]
(low pulse width adjustment)
Register programmable
TDSEL[3:0] Input 0.75V TX duty selection
Default setting:

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Pin Description Type Level Description Note

 TDSEL[2][0]: Output level shifter duty high 1.8V: TDSEL[3:0]=[0000]
when asserted (high pulse width adjustment) 1.2V: TDSEL[3:0]=[0000]
 TDSEL[3][1]: Output level shifter duty low when
asserted (low pulse width adjustment) *Please set BIAS control pin,
1.8V: BSEL0=0, BDSEL[1:0]=[00]
1.2V: BSEL0=1, BDSEL[1:0]=[00]

*Please set TDSEL[3:0]=[1111]

@ if VCCK is lower than 0.4V.

Table 3-176 KP 2K I/O Cell

Pin Description Type Level Description Note
I Input 0.75V Input signal of driver
Data input/output.
Input/
IO 1.8V Output pin of driver (TX mode)/input pin of receiver
Output
(RX mode)
To enable output. High asserted.
E Input 0.75V
E = 1, TX mode; E = 0, RX mode.
Register programmable 2G Type
(E8, E4, E2):
2mA: [000] 10mA: [100]
E2, E4, E8 Input 0.75V TX driving strength control
4mA: [001] 12mA: [101]
6mA: [010] 14mA: [110]
8mA: [011] 16mA: [111]
O Output 0.75V Output signal of RX receiver
To enable RX input buffer. High asserted data path:
from IO to O. IES = 0, O = 0
IES Input 0.75V
For VIO turn-off applications, IES = 0 prevents
leakage in VDDIO power domain.
To enable RX input buffer Schmitt trigger hysteresis
SMT Input 0.75V control. High asserted. Register programmable
SMT= 1, Schmitt trigger enabled
PUPD Input 0.75V PUPD R1 R0 R value Register programmable
R0 Input 0.75V 0 0 0 High Z Register programmable
0 0 1 PU-75K
0 1 0 PU-2K
0 1 1 PU-75K/2K
R1 Input 0.75V 1 0 0 High Z Register programmable
1 0 1 PD-75K
1 1 0 PD-2K
1 1 1 PD-75K/2K

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Pin Description Type Level Description Note

75K/2K means parallel connection of resistance.
RX duty selection
 RDSEL[0]: Level shifter duty high when asserted Register programmable
RDSEL[1:0] Input 0.75V (high pulse width adjustment) Default setting: 1.8V:
 RDSEL[1]: Level shifter duty low when asserted RDSEL[1:0]=[00]
(low pulse width adjustment)
Register programmable
Default setting:
1.8V: TDSEL[3:0]=[0000]
TX duty selection 1.2V: TDSEL[3:0]=[0000]
 TDSEL[2][0]: Output level shifter duty high
TDSEL[3:0] Input 0.75V when asserted (high pulse width adjustment) *Please set BIAS control pin,
 TDSEL[3][1]: Output level shifter duty low when 1.8V: BSEL0=0, BDSEL[1:0]=[00]
asserted (low pulse width adjustment) 1.2V: BSEL0=1, BDSEL[1:0]=[00]

*Please set TDSEL[3:0]=[1111] @

if VCCK is lower than 0.4V.

Table 3-177 KP 200K I/O Cell

Pin Description Type Level Description Note
I Input 0.75V Input signal of driver
Data input/output.
Input/
IO 1.8V Output pin of driver (TX mode)/input pin of receiver
Output
(RX mode)
To enable output. High asserted.
E Input 0.75V
E = 1, TX mode; E = 0, RX mode.
Register programmable 2G Type
(E8, E4, E2):
2mA: [000] 10mA: [100]
E2, E4, E8 Input 0.75V TX driving strength control
4mA: [001] 12mA: [101]
6mA: [010] 14mA: [110]
8mA: [011] 16mA: [111]
O Output 0.75V Output signal of RX receiver
To enable RX input buffer. High asserted data path:
from IO to O. IES = 0, O = 0
IES Input 0.75V
For VIO turn-off applications, IES = 0 prevents
leakage in VDDIO power domain.
To enable RX input buffer Schmitt trigger hysteresis
SMT Input 0.75V control. High asserted. Register programmable
SMT= 1, Schmitt trigger enabled
PUPD Input 0.75V Register programmable
R0 Input 0.75V Register programmable

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Pin Description Type Level Description Note

PUPD R1 R0 R value
0 0 0 High Z
0 0 1 PU-75K
0 1 0 PU-200K
0 1 1 PU-75K/200K
R1 Input 0.75V Register programmable
1 0 0 High Z
1 0 1 PD-75K
1 1 0 PD-200K
1 1 1 PD-75K/200K
75K/200K means parallel connection of resistance.
RX duty selection
 RDSEL[0]: Level shifter duty high when asserted Register programmable
RDSEL[1:0] Input 0.75V (high pulse width adjustment) Default setting: 1.8V:
 RDSEL[1]: Level shifter duty low when asserted RDSEL[1:0]=[00]
(low pulse width adjustment)
Register programmable
Default setting:
1.8V: TDSEL[3:0]=[0000]
TX duty selection 1.2V: TDSEL[3:0]=[0000]
 TDSEL[2][0]: Output level shifter duty high
TDSEL[3:0] Input 0.75V when asserted (high pulse width adjustment) *Please set BIAS control pin,
 TDSEL[3][1]: Output level shifter duty low when 1.8V: BSEL0=0, BDSEL[1:0]=[00]
asserted (low pulse width adjustment) 1.2V: BSEL0=1, BDSEL[1:0]=[00]

*Please set TDSEL[3:0]=[1111] @

if VCCK is lower than 0.4V.

Table 3-178 I3C I/O Cell

Pin Description Type Level Description Note
I Input 0.75V Input signal of driver
Data input/output.
Input/
IO 1.8V Output pin of driver (TX mode)/input pin of
Output
receiver (RX mode)
To enable output. High asserted.
E Input 0.75V
E = 1, TX mode; E = 0, RX mode.
Register programmable 2G Type
(E8, E4, E2):
2mA: [000] 10mA: [100]
E2, E4, E8 Input 0.75V TX driving strength control
4mA: [001] 12mA: [101]
6mA: [010] 14mA: [110]
8mA: [011] 16mA: [111]

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Pin Description Type Level Description Note

EH Input 0.75V To enable the I2C mode. Register programmable
EH1, EH2 Input 0.75V TX driving strength control for the I2C mode Register programmable
O Output 0.75V Output signal of the RX
To enable RX input buffer. High asserted data
path: from IO to O. IES = 0, O = 0
IES Input 0.75V
For VIO turn-off applications, IES = 0 prevents
leakage in VDDIO power domain.
To enable RX input buffer Schmitt trigger
SMT Input 0.75V hysteresis control. High asserted. Register programmable
SMT= 1, Schmitt trigger enabled
PU Input 0.75V 75K pull-up resistor control. High activation Register programmable
PD Input 0.75V 75K pull-down resistor control. High activation Register programmable
Pull-up/down resistance selection.
 RSEL=0, R=75K (GPIO mode)
RSEL Input 0.75V
 RSEL=1, RSEL1=0, R=5K (SoundWire IO
mode)
Additional strong pull resistor control for the I2C
RSEL1 Input 0.75V
pull-up resistor
Additional strong pull resistor control for the I2C
RSEL2 Input 0.75V
pull-up resistor.
RX duty selection
 RDSEL[0]: Level shifter duty high when
RDSEL[1:0] = [00]
RDSEL[1:0] Input 0.75V asserted (high pulse width adjustment)
Other settings are not allowed.
 RDSEL[1]: Level shifter duty low when
asserted (low pulse width adjustment)
TX duty selection
 TDSEL[2][0]: Output level shifter duty high
when asserted (high pulse width
TDSEL[3:0] = [0000]
TDSEL[3:0] Input 0.75V adjustment)
Other settings are not allowed.
 TDSEL[3][1]: Output level shifter duty low
when asserted (low pulse width
adjustment)

Table 3-179 RST I/O Cell

Pin Description Type Level Description Note
I Input 0.75V Input signal of driver
O Output 0.75V Output signal of the RX
To enable RX input buffer. High asserted data
path: from IO to O. IES = 0, O = 0
IES Input 0.75V
For VIO turn-off applications, IES = 0 prevents
leakage in VDDIO power domain.

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Pin Description Type Level Description Note

O18_ANALOG_DOUNT_TOUCH control
IES18 Input 0.75V  IES18 = 1, O18_ANALOG_DOUNT_TOUCH = IO Register programmable
 IES18 = 0, O18_ANALOG_DOUNT_TOUCH = 0
To enable RX input buffer Schmitt trigger
SMT Input 0.75V hysteresis control. High asserted. Register programmable
SMT= 1, Schmitt trigger enabled
PU Input 0.75V 75K pull-up resistor control. High activation Register programmable
PD Input 0.75V 75K pull-down resistor control. High activation Register programmable
RX duty selection
 RDSEL[0]: Level shifter duty high when RDSEL[1:0] = [00]
RDSEL[1:0] Input 0.75V asserted (high pulse width adjustment) Other settings are not
 RDSEL[1]: Level shifter duty low when allowed.
asserted (low pulse width adjustment)
O18_ANALOG_ Analog IO. Will be connected to an analog circuit
Output 1.8V Register programmable
DOUNT_TOUCH (for system reset)
AIO_ANALOG_D Internal pin to core side. Connected to I by
Output 1.8V/1.2V
ONT_TOUCH resistor

Table 3-180 MSDC3A18 I/O Cell

Pin Description Type Level Description Note
I Input 0.75V Input signal of driver
Data input/output.
Input/
IO 1.8V Output pin of driver (TX mode)/input pin of
Output
receiver (RX mode)
To enable output. High asserted.
E Input 0.75V
E = 1, TX mode; E = 0, RX mode.
Register programmable 2G Type
(E8, E4, E2):
2mA: [000] 10mA: [100]
E2, E4, E8 Input 0.75V TX driving strength control
4mA: [001] 12mA: [101]
6mA: [010] 14mA: [110]
8mA: [011] 16mA: [111]
O Output 0.75V Output signal of RX receiver
To enable RX input buffer. High asserted
data path: from IO to O. IES = 0, O = 0
IES Input 0.75V
For VIO turn-off applications, IES = 0
prevents leakage in VDDIO power domain.
To enable RX input buffer Schmitt trigger
SMT Input 0.75V hysteresis control. High asserted. Register programmable
SMT= 1, Schmitt trigger enabled
R0 Input 0.75V Register programmable
R1 Input 0.75V Register programmable

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Pin Description Type Level Description Note

PU/PD R1 R0 R value Register programmable
0 0 0 High Z
0 0 1 PU-10K
0 1 0 PU-50K
0 1 1 PU-10K/50K
1 0 0 High Z
PUPD Input 0.75V Register programmable
1 0 1 PD-10K
1 1 0 PD-50K
1 1 1 PD-10K/50K
10K/50K means parallel connection of
resistance.
RX duty select
 RDSEL[1:0]: Input buffer duty high when
asserted (high pulse width adjustment) Register programmable
RDSEL[5:0] Input 0.75V  RDSEL[3:2]: Input buffer duty low when Default setting:
asserted(low pulse width adjustment) RDSEL[5:0]=000000
 RDSEL[5:4]: Level shifter duty high when
asserted (high pulse width adjustment)
TX duty select
 TDSEL[1:0]: Output level shifter duty Register programmable
high when asserted (high pulse width Default setting:
TDSEL[3:0] Input 0.75V adjustment) TDSEL[3:0]=0000
 TDSEL[3:2]: Output level shifter duty low TDSEL[3:0]=1111 if operating in low
when asserted(low pulse width speed mode( VCCK= 0.45v +-10%)
adjustment)

Table 3-181 MSDC3A18OD33 I/O Cell

Pin Description Type Level Description Note
VCC3IO Power 3V 3V Power Port. For IO output buffer
VCC18I Power 1.8V 1.8V Power Port. For IO pre-driver and RX path
VCCK Power 0.75V 0.75V Power Port. For IO control logic
GND3IO Ground 0V Ground Port
GNDK Ground 0V Ground Port
I Input 0.75V Input Signal of Driver
Input/ Data Input/Output. Output pin of Driver (TX mode)/Input
IO 1.8V/3.0V
Output Pin of Receiver (RX mode)
Output Enable. High asserted. E=1, TX mode. E=0, RX
E Input 0.75V
mode.
Output Slew Rate Control. High asserted. SR=1, slower
SR Input 0.75V
slew. SR=0, no slew rate controlled.
E2, E4, E8 Input 0.75V TX driving strength control Register programmable

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Pin Description Type Level Description Note

2G Type
(E8, E4, E2):
2mA: [000] 10mA: [100]
4mA: [001] 12mA: [101]
6mA: [010] 14mA: [110]
8mA: [011] 16mA: [111]

O Output 0.75V Output Signal of RX receiver

Power down mode:
RX input buffer enable. High asserted. Datapath: from IO IES=0 is a must
IES Input 0.75V
to O. IES=0, O=0 Quiescent mode: IES=0
is suggested
RX input buffer Schmitt trigger hysteresis control enable.
SMT Input 0.75V
High asserted. SMT=1, Schmitt trigger enable
PUPD/R0/R1 control pin of PU/PD. See the attached truth
table below

PUPD/R0/R1 Input 0.75V Register programmable

 TDSEL0, TDSEL2: Output level shifter duty high when

asserted (high pulse width adjustment)
TDSEL[3:0] Input 0.75V Register programmable
 TDSEL1, TDSEL3: Output level shifter duty low when
asserted (low pulse width adjustment)
 RDSEL0, RDSEL1, RDSEL4: input level shifter duty
high when asserted (high pulse width adjustment)
RDSEL[5:0] Input 0.75V Register programmable
 TDSEL2, TDSEL3, RDSEL5: input level shifter duty low
when asserted (low pulse width adjustment)

Table 3-182 AGPIO General 1.8V I/O Cell

Pin Description Type Level Description Notes
I Input 0.75V Input signal of driver
Data input/output.
Input/
IO 1.8V Output pin of driver (TX mode)/input pin of
Output
receiver (RX mode)
To enable output. High asserted.
E Input 0.75V
E = 1, TX mode; E = 0, RX mode.

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Pin Description Type Level Description Notes

Register programmable 2G Type
(E8, E4, E2):
2mA: [000] 10mA: [100]
E2, E4, E8 Input 0.75V TX driving strength control
4mA: [001] 12mA: [101]
6mA: [010] 14mA: [110]
8mA: [011] 16mA: [111]
O Output 0.75V Output signal of RX receiver
To enable RX input buffer. High asserted data
path: from IO to O. IES = 0, O = 0
IES Input 0.75V
For VIO turn-off applications, IES = 0 prevents
leakage in VDDIO power domain.
To enable RX input buffer Schmitt trigger
SMT Input 0.75V hysteresis control. High asserted. Register programmable
SMT= 1, Schmitt trigger enabled
PU Input 0.75V 75K pull-up resistor control. High activation Register programmable
PD Input 0.75V 75K pull-down resistor control. High activation Register programmable
RX duty selection
 RDSEL[0]: Level shifter duty high when Register programmable
RDSEL[1:0] Input 0.75V asserted (high pulse width adjustment) Default setting: 1.8V:
 RDSEL[1]: Level shifter duty low when RDSEL[1:0]=[00]
asserted (low pulse width adjustment)
Register programmable
Default setting:
TX duty selection 1.8V: TDSEL[3:0]=[0000]
 TDSEL[2][0]: Output level shifter duty high 1.2V: TDSEL[3:0]=[0000]
when asserted (high pulse width
TDSEL[3:0] Input 0.75V adjustment) *Please set BIAS control pin,
 TDSEL[3][1]: Output level shifter duty low 1.8V: BSEL0=0, BDSEL[1:0]=[00]
when asserted (low pulse width 1.2V: BSEL0=1, BDSEL[1:0]=[00]
adjustment)
*Please set TDSEL[3:0]=[1111]
@ if VCCK is lower than 0.4V.
AIO_ANALOG_
Input/Output 1.8V Analog IO. Will be connected to analog circuit
DONT_TOUCH
Analog/digital IO function selection port
When G=0, analog IO mode
G Input 0.75V  G=0 => analog IO mode
When G=1, digital IO mode
 G=1 => digital IO mode

[Link] Signal Multiplexing

Each GPIO pin of the MT8390 may have up to 8 auxiliary functions (Aux Func.0 to Aux Func.7) that can be either output or
input. The following sections explain the output and input signal multiplexing cases.

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 Setting the GPIO_DIR register to 1 configures the GPIO as the output mode.
 Setting the GPIO_DIR register to 0 configures the GPIO as the input mode.

[Link].1 Output Signal Multiplexing

 When the GPIO_MODE register is set to be 0, the GPIO function (i.e., Aux Func.0) is selected. Additional registers, such
as GPIO_DOUT, are also programmable to control the output state (e.g., output low or output high).
 When the GPIO_MODE register is set to any other values, the corresponding pin-mux function, for example, Aux
Func.1 or Aux Func.2, is selected.

[Link].2 Input Signal Multiplexing

 When the GPIO_MODE register is set to 0, the GPIO function (i.e., Aux Func.0) is selected. Additional registers such as
PU and PD are also programmable for other required usages, such as input high-Z, input pull down, or input pull high.
Note that the PU and PD settings for each pin are separated into different control register domains.
 When the GPIO_MODE register is set to other values, one of the other pin mux functions such as Aux Func.1 or Aux
Func.2, is selected.

[Link] Bitwise Command Register

To explain the bitwise command registers, take the following registers related to the same GPIO pads input/out direction as
an example.

Register Base Address Description

(GPIO Base Requires a “read-modify-write” operation to set the I/O direction for
GPIO_DIR0
address+0x0000)[31:0] the corresponding GPIO pads.
(GPIO Base Bitwise functions
GPIO_DIR0_SET
address+0x0004)[31:0]  Bits written with "1" in GPIO_DIR0_SET set the corresponding
GPIO pads as output pins.
 Bits written with "1" in GPIO_DIR0_CLR set the corresponding
(GPIO Base
GPIO_DIR0_CLR GPIO pads as input pins.
address+0x0008)[31:0]
 Bits written with “0” have no effect, i.e., no read-modify-write
operation is needed for the bitwise registers.
GPIO_DOUT
Set the output value of 0/1 if the corresponding pads are configured
GPIO_DOUT_SET -
as output pins.
GPIO_DOUT_CLR

See below for the example of writing the output value through the following registers.

Register Base Address Description

(GPIO Base Requires a “read-modify-write” operation to set the output value for
GPIO_DOUT0
address+0x0100)[31:0] the corresponding GPIO pads.
(GPIO Base Bitwise functions
GPIO_DOUT0_SET
address+0x0104)[31:0]

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Register Base Address Description

 Writing "1" to the bits in GPIO_DOUT0_SET sets the
corresponding GPIO pads output value to 1.
(GPIO Base  Writing “1” to bits in GPIO_DOUT0_CLR sets the corresponding
GPIO_DOUT0_CLR
address+0x0108)[31:0] GPIO pads output value to 0.
 Bits written with “0” have no effect, i.e., no read-modify-write
operation is needed for the bitwise registers.

[Link] Block Diagram

Latch @ SYSRST#
SYSRST#
INPUT/OUTPUT

GPIO_DIN
Control GPIO_DIR
GPIO Logic APB
GPIO_MODE
GPIO_DOUT
BUS
PU/PD I/F
DRV_STRENGTH

Figure 3-224 GPIO Block Diagram

[Link] GPIO Signal Descriptions

Table 3-183 presents GPIO signal descriptions.

Table 3-183 GPIO Signal Descriptions

Signal Name Type Description Ball Location
GPIO0 DIO General-purpose input and output Y10
GPIO1 DIO General-purpose input and output U10
GPIO2 DIO General-purpose input and output Y6
GPIO3 DIO General-purpose input and output Y7
GPIO4 DIO General-purpose input and output Y8
GPIO5 DIO General-purpose input and output W7
GPIO6 DIO General-purpose input and output W3
GPIO7 DIO General-purpose input and output W4
GPIO8 DIO General-purpose input and output W5
GPIO9 DIO General-purpose input and output V4
GPIO10 DIO General-purpose input and output V5
GPIO11 DIO General-purpose input and output W8
GPIO12 DIO General-purpose input and output R31
GPIO13 DIO General-purpose input and output T30

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Signal Name Type Description Ball Location

GPIO14 DIO General-purpose input and output T31
GPIO15 DIO General-purpose input and output U32
GPIO16 DIO General-purpose input and output AB32
GPIO17 DIO General-purpose input and output AA35
GPIO18 DIO General-purpose input and output G4
GPIO19 DIO General-purpose input and output G3
GPIO20 DIO General-purpose input and output E3
GPIO21 DIO General-purpose input and output G5
GPIO22 DIO General-purpose input and output E4
GPIO23 DIO General-purpose input and output E5
GPIO24 DIO General-purpose input and output F4
GPIO25 DIO General-purpose input and output Y9
GPIO26 DIO General-purpose input and output AA7
GPIO27 DIO General-purpose input and output AA11
GPIO28 DIO General-purpose input and output Y5
GPIO29 DIO General-purpose input and output AA9
GPIO30 DIO General-purpose input and output Y11
GPIO31 DIO General-purpose input and output U2
GPIO32 DIO General-purpose input and output U3
GPIO33 DIO General-purpose input and output V1
GPIO34 DIO General-purpose input and output V2
GPIO35 DIO General-purpose input and output U4
GPIO36 DIO General-purpose input and output U5
GPIO37 DIO General-purpose input and output T6
GPIO38 DIO General-purpose input and output T5
GPIO39 DIO General-purpose input and output T4
GPIO40 DIO General-purpose input and output T1
GPIO41 DIO General-purpose input and output T2
GPIO42 DIO General-purpose input and output H31
GPIO43 DIO General-purpose input and output J31
GPIO44 DIO General-purpose input and output J30
GPIO45 DIO General-purpose input and output K30
GPIO46 DIO General-purpose input and output AB33
GPIO47 DIO General-purpose input and output AA4
GPIO48 DIO General-purpose input and output AA3
GPIO49 DIO General-purpose input and output AA1
GPIO50 DIO General-purpose input and output AB34
GPIO51 DIO General-purpose input and output AC32
GPIO52 DIO General-purpose input and output AC33

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Signal Name Type Description Ball Location

GPIO53 DIO General-purpose input and output AD32
GPIO54 DIO General-purpose input and output AD33
GPIO55 DIO General-purpose input and output Y4
GPIO56 DIO General-purpose input and output W6
GPIO57 DIO General-purpose input and output M36
GPIO58 DIO General-purpose input and output L36
GPIO59 DIO General-purpose input and output Y2
GPIO60 DIO General-purpose input and output AA2
GPIO61 DIO General-purpose input and output W2
GPIO62 DIO General-purpose input and output W1
GPIO63 DIO General-purpose input and output K36
GPIO64 DIO General-purpose input and output K37
GPIO65 DIO General-purpose input and output F5
GPIO66 DIO General-purpose input and output F6
GPIO67 DIO General-purpose input and output H7
GPIO68 DIO General-purpose input and output G6
GPIO69 DIO General-purpose input and output V6
GPIO70 DIO General-purpose input and output T11
GPIO71 DIO General-purpose input and output V7
GPIO72 DIO General-purpose input and output V8
GPIO73 DIO General-purpose input and output U7
GPIO74 DIO General-purpose input and output U8
GPIO75 DIO General-purpose input and output T9
GPIO76 DIO General-purpose input and output T10
GPIO77 DIO General-purpose input and output T8
GPIO78 DIO General-purpose input and output T7
GPIO79 DIO General-purpose input and output G2
GPIO80 DIO General-purpose input and output G1
GPIO81 DIO General-purpose input and output F2
GPIO82 DIO General-purpose input and output E2
GPIO83 DIO General-purpose input and output R36
GPIO84 DIO General-purpose input and output P36
GPIO85 DIO General-purpose input and output P34
GPIO86 DIO General-purpose input and output R34
GPIO87 DIO General-purpose input and output R33
GPIO88 DIO General-purpose input and output T33
GPIO89 DIO General-purpose input and output P31
GPIO90 DIO General-purpose input and output P32
GPIO91 DIO General-purpose input and output R30

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Signal Name Type Description Ball Location

GPIO92 DIO General-purpose input and output K32
GPIO93 DIO General-purpose input and output K31
GPIO94 DIO General-purpose input and output L30
GPIO95 DIO General-purpose input and output L31
GPIO96 DIO General-purpose input and output L33
GPIO97 DIO General-purpose input and output L34
GPIO98 DIO General-purpose input and output M31
GPIO99 DIO General-purpose input and output N37
GPIO100 DIO General-purpose input and output K34
GPIO101 DIO General-purpose input and output M33
GPIO102 DIO General-purpose input and output M35
GPIO103 DIO General-purpose input and output M34
GPIO104 DIO General-purpose input and output N33
GPIO105 DIO General-purpose input and output M30
GPIO106 DIO General-purpose input and output M32
GPIO107 DIO General-purpose input and output G36
GPIO108 DIO General-purpose input and output H36
GPIO109 DIO General-purpose input and output J36
GPIO110 DIO General-purpose input and output J37
GPIO111 DIO General-purpose input and output G33
GPIO112 DIO General-purpose input and output G32
GPIO113 DIO General-purpose input and output H35
GPIO114 DIO General-purpose input and output H34
GPIO115 DIO General-purpose input and output H33
GPIO116 DIO General-purpose input and output J34
GPIO117 DIO General-purpose input and output J33
GPIO118 DIO General-purpose input and output G31
GPIO119 DIO General-purpose input and output G30
GPIO120 DIO General-purpose input and output H32
GPIO121 DIO General-purpose input and output AD30
GPIO122 DIO General-purpose input and output AC31
GPIO123 DIO General-purpose input and output AC30
GPIO124 DIO General-purpose input and output AB31
GPIO125 DIO General-purpose input and output N30
GPIO126 DIO General-purpose input and output N31
GPIO127 DIO General-purpose input and output P30
GPIO128 DIO General-purpose input and output N34
GPIO129 DIO General-purpose input and output P33
GPIO130 DIO General-purpose input and output P35

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Signal Name Type Description Ball Location

GPIO131 DIO General-purpose input and output AB9
GPIO132 DIO General-purpose input and output AC9
GPIO133 DIO General-purpose input and output AB8
GPIO134 DIO General-purpose input and output AC4
GPIO135 DIO General-purpose input and output AB3
GPIO136 DIO General-purpose input and output AA8
GPIO137 DIO General-purpose input and output AC8
GPIO138 DIO General-purpose input and output AB7
GPIO139 DIO General-purpose input and output AB6
GPIO140 DIO General-purpose input and output AB5
GPIO141 DIO General-purpose input and output AC5
GPIO142 DIO General-purpose input and output AA5
GPIO143 DIO General-purpose input and output AA6
GPIO144 DIO General-purpose input and output AC6
GPIO145 DIO General-purpose input and output AC7
GPIO146 DIO General-purpose input and output AB4
GPIO147 DIO General-purpose input and output AD11
GPIO148 DIO General-purpose input and output AD10
GPIO149 DIO General-purpose input and output AB2
GPIO150 DIO General-purpose input and output AB1
GPIO151 DIO General-purpose input and output D37
GPIO152 DIO General-purpose input and output E36
GPIO153 DIO General-purpose input and output F37
GPIO154 DIO General-purpose input and output D35
GPIO155 DIO General-purpose input and output E34
GPIO156 DIO General-purpose input and output F33
GPIO157 DIO General-purpose input and output F32
GPIO158 DIO General-purpose input and output E32
GPIO159 DIO General-purpose input and output D36
GPIO160 DIO General-purpose input and output F36
GPIO161 DIO General-purpose input and output D33
GPIO162 DIO General-purpose input and output E35
GPIO163 DIO General-purpose input and output D3
GPIO164 DIO General-purpose input and output D4
GPIO165 DIO General-purpose input and output D2
GPIO166 DIO General-purpose input and output D1
GPIO167 DIO General-purpose input and output C4
GPIO168 DIO General-purpose input and output C3
GPIO169 DIO General-purpose input and output AC35

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Signal Name Type Description Ball Location

GPIO170 DIO General-purpose input and output AD35
GPIO171 DIO General-purpose input and output AD37
GPIO172 DIO General-purpose input and output AD36
GPIO173 DIO General-purpose input and output AB37
GPIO174 DIO General-purpose input and output AB35
GPIO175 DIO General-purpose input and output K33
GPIO176 DIO General-purpose input and output K35

[Link] Function Description

The I/O pins of the MT8390 can be programmed for multiple purposes, such as GPIO, NAND and SPI, by setting the
GPIO_MODE register for different functions. Note that all functions must comply with the priority rule.

 When there are more than one I/O set as the same output function, all of the selected I/Os are able to output specific
signals.
 When there are more than one I/O set as the same input (or bi-directional) function, only the I/O with the largest
GPIO index works functionally.

[Link].1 Main Functions

Table 3-184 Main Functions of GPIOs

Main Function Description Notes
 000 as GPIO mode
GPIO_MODE GPIO mode selection.
 001 to 111 as Aux Func.
 0 as input
GPIO_DIR GPIO direction.
 1 as output
GPIO_DOUT GPIO output. -
GPIO_DIN GPIO input. -
 PU = 1, PD = 0 as pull-up
PU/PD Pull up/down resistor control. High activation.  PU = 0, PD = 1 as pull-down
 PU = 0, PD = 0 as no-pull
 2 mA: [000]
 4 mA: [001]
 6 mA: [010]
Driving strength of the GPIO, which can be  8 mA: [011]
DRV_STRENGTH
configured up to 16 mA.  10 mA: [100]
 12 mA: [101]
 14 mA: [110]
 16 mA: [111]
INPUT/OUTPUT I/O to the Aux Func IP. -
Latch To latch the GPIO signal during startup. -

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Main Function Description Notes

Used for strapping (for more details, refer to
Section [Link].2).

[Link].2 Strapping Functions

Table 3-185 lists the strapping pins. The strapping pin state is latched when the system “resetb” changes from low to high.
The strapping pin state decides which stage mode the system enters, or where the BROM boots from. When the strapping
stage is completed, the strapping pin state can be changed.

To exit the strapping mode, configure the register TPBANK in the GPIO. Refer to Table 3-186 for more details.

Table 3-185 Strapping Configurations

Pin Name Description TRAP_FORCE_EN TRAP_FORCE_VALUE
[0] PAD_AUD_DAT_MOSI0 Bit0 Bit7
trap_out_io
[1] PAD_PWRAP_SPI_CSN Bit1 Bit8
[0] PAD_AUD_CLK_MOSI Bit2 Bit9
Boot selection mode
[1] PAD_AUD_SYNC_MOSI Bit3 Bit10
PAD_AUD_DAT_MOSI1 emmc_bit_speed_mode Bit4 Bit11
PAD_CMMCLK0 spi_nor_address_mode Bit5 Bit12
PAD_SCP_VREQ_VAO boot_room_boot_partition_sequence Bit6 Bit13

Table 3-186 Strapping Configuration Register

Address and Bit Name Description
To enable the strapping configuration with
0x100056F0[6:0] TRAP_FORCE_EN(JTAG) TRAP_FORCE_VALUE(JTAG)
Active high
0x100056F0[13:7] TRAP_FORCE_VALUE(JTAG) To force the value to JTAG strapping.

[Link].3 Secure Function

All GPIO control registers have a secure function.

 Enable the secure function by the sec_en register.

 The secure function is disabled by default.
 If the sec_en register bit = 1, the GPIO register follows the register map security definition.

[Link] Theory of Operations

[Link].1 Select GPIO Mode

To enable certain function on certain pads, change the GPIO mode of the pad. When the GPIO_MODE register is set to 0,
the GPIO function (i.e., Aux Func.0) is selected. When the GPIO_MODE register is set to any other values, the
corresponding pin-mux function, for example, Aux Func.1 or Aux Func.2, is selected.

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[Link].2 Configure Pad Output Value and Observe Pad Input

When a certain pad’s GPIO mode is configured as 0, you can configure the pad output value and observe the input value.
When the pad GPIO mode is not 0, you cannot configure the pad output value by GPIO setting. You can observe the pad
input value when the pad holds on stable.

1. If you want to configure the pad output value, follow the steps below.
Step 1: Set GPIO_MODE as 0
Step 2: Set GPIO_DIR as 1
Step 3: Setting GPIO_DOUT as 1 means output high, while setting GPIO_DOUT as 0 means output low
2. If you want to observe the pad input value, follow the steps below.
Step 1: Set GPIO_MODE as 0
Step 2: Set GPIO_DIR as 0
Step 3: Setting GPIO_DIN as 1 means input high, while setting GPIO_DIN as 0 means input low

[Link].3 Configure Pins of Pads

The pins of pads can be configured when needed, but the default value should be sufficient for most scenarios.

[Link] Programming Guide

[Link].1 GPIO Mode as Input

Table 3-187 GPIO Mode Input Programming Outline

Step Sequence Register Name Register Value Address
1 Set the AUX function to GPIO Mode0. GPIO_MODE 0 GPIO Base + GPIO_MODE
Set the GPIO DIR register to be configured as
2 GPIO_DIR 0 GPIO Base + GPIO_DIR
the input.

[Link].2 GPIO Mode as Output

Table 3-188 GPIO Mode Output Programming Outline

Step Sequence Register Name Register Value Address
1 Set the AUX function to GPIO Mode0. GPIO_MODE 0 GPIO Base + GPIO_MODE
Set the GPIO DIR register to be
2 GPIO_DIR 1 GPIO Base + GPIO_DIR
configured as the output.
 Set 1 as output high
3 Set GPIO DOUT value GPIO_DOUT GPIO Base + GPIO_DOUT
 Set 0 as output low

[Link] Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

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[Link] Electrical Characteristics

Table 3-189 Electrical Characteristics and Operating Conditions of 1.8V Applications

Parameter Description Min Typ Max Unit
VCC18O Supply voltage of IO power 1.62 1.8 1.98 V
(1)
Freq Maximum operating frequency - - 55 MHz
VCCK Supply voltage of core power 0.495 0.75 0.825 V
Input
VIH High-level input voltage 0.65 * VCC18O - VCC18O + 0.3 V
VIL Low-level input voltage -0.3 - 0.35 * VCC18O V
Rpu Input pull-up resistance 40 75 190 KΩ
Rpd Input pull-down resistance 40 75 190 KΩ
Output
VOH (DC) High-level output voltage 0.75 * VCC18O - V
VOL (DC) Low-level output voltage - - 0.25*VCC18O V
Leakage
Input leakage current
IIN -10 - 10 µA
(Any input 0V < VIN < VCC18O)
IVCC18Oz VCC18O standby leakage @ I/O hi-z and RX off -10 - 10 µA
IVCCKz VCCK standby leakage @ I/O hi-z and RX off -10 - 10 µA
(1) I3C mode maximum operating frequency = 3.4 MHz
MSDC I/O maximum operating frequency = 208 MHz
SPMI I/O maximum operating frequency = 120 MHz

3.12.10 Pulse Width Modulation (PWM)

[Link] Overview
The Pulse Width Modulation (PWM) is a technique designed to generate pulse sequences with programmable frequency
and duration for various applications, including but not limited to Liquid-Crystal Display (LCD) backlight and charging.
Prior to enabling the PWM, the pulse sequences must be prepared in the registers. The PWM then reads the stored pulse
sequences to generate the expected waveform to meet specific requirements of the given applications.

[Link] Features
Different PWM modes as listed below are available.

Table 3-190 Pulse Width Modulation (PWM) Modes

Mode Description
Normal Mode Generates pulse sequences with programmable frequency and duration.
FIFO Mode Generates pulse sequences for the data that is programmable by the CPU.
Memory Mode and Random Mode Generate pulse sequence for the data sent from SRAM.

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[Link] Block Diagram

Pulse Width Modulation (PWM)

PWM UNIT

DATA_ACCESS
Control and Status
APB (PWM_SEND_DATA0,
Register
PWM_SEND_DATA1)

DMA control & Waveform output

AHB PWM_GENERATION
Arbiter

Figure 3-225 Block Diagram of PWM

Figure 3-225 illustrates the PWM block diagram, which consists of several functional components:

 Control and status registers: Receive commands from the system.

 DMA control and arbitrator: Facilitates communication between the system RAM and the PWM when the normal
PWM is set to the memory mode or random mode.
 DATA_ACCESS: Manages the data flow from the AHB/APB.
 PWM_GENERATION: Controls the transmission of the PWM waveform.

[Link] Function Description

[Link].1 Waveform Generation

The PWM outputs waveforms through the PAD pins. The theoretical methodology for generating PWM waveforms differs
across modes, as outlined in Section [Link]. The PWM generates waveforms by dividing frequencies and data
sequences in a specific manner as described in the following sections.

[Link].1.1Frequency Division Generation

The PWM generates a waveform by dividing the frequency in the normal mode.

Bclk To PAD
PWM
APB

Figure 3-226 Frequency Division Generation

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[Link].1.2Data Sequence Generation

The PWM module generates a waveform by data sequence generation in the PWM FIFO, memory and random modes.

AHB To PAD
PWM
APB

32-bit

Figure 3-227 Data Sequence Generation

[Link] Theory of Operations

For the programming guide of each mode, refer to Section [Link].

[Link].1 Normal Mode

ON OFF

guard_duration=0
pwm_thresh+1 pwm_thresh+1
idle_value

data_width+1 guard_duration+1 data_width+1

Figure 3-228 PWM Normal Mode

Figure 3-228 shows the PWM waveform in the normal mode.

The frequency is determined by PWM_DATA_WIDTH (PWM Base address+0x00AC) [12:0] and the duty cycle is determined
by PWM_THRESH (PWM Base address+0x00B0) [12:0].
𝐶𝐿𝐾𝑆𝑅𝐶
PWM Frequency =
𝐶𝐿𝐾𝐷𝐼𝑉 ∗ (𝐷𝐴𝑇𝐴_𝑊𝐼𝐷𝑇𝐻 + 1)

Without consideration of GUARD_DURATION (PWM Base address+0x8C) [15:0], the duty cycle is:
𝑃𝑊𝑀_𝑇𝐻𝑅𝐸𝑆𝐻 + 1
Duty cycle =
𝐷𝐴𝑇𝐴_𝑊𝐼𝐷𝑇𝐻 + 1

Guard_ duration (PWM Base address+0x08C) [15:0] is the time interval between two complete waveforms. When
PWM_WAVE_NUM (PWM Base address+0x00A8) [15:0] = 0, it means that hardware is continuously outputting the
waveform, and the waveform can only be terminated by disabling PWM.

Note that CLKSRC is the frequency of the source clock.

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[Link].2 FIFO Mode

SEND SEND
DATA1 DATA0

PWM

64-bit
Stop bit
position
PWM is not enabled
or is done
lduration hduration

guard_value idle_value
~ ~ ~ ~
0 1 1 0 1 0 1 1 0 1
guard_duration
send_data0 send_data1 send_data0 send_data1

Repeat waveform number

Figure 3-229 FIFO Mode

If the pulse sequence data is less than or equal to 64-bit, the data can be directly set in PWM_SEND_DATA0 (PWM Base
address+0x00A0) [31:0], PWM_SEND_DATA1 (PWM Base address+0x00A4) [31:0] and SRCSEL (PWM Base address+0x0000)
[5] =0 to reduce memory bandwidth, where SRCSEL is set to 0 to indicate that PWM is in FIFO mode. STOP_BITPOS (PWM
Base address+0x0000) [14:9] is used to indicate the stop bit position in the total 64-bit data.

For example, if STOP_BITPOS (PWM Base address+0x0000) [14:9] is 31, only PWM_SEND_DATA0 (PWM Base
address+0x00A0) [31:0] is generated. And if STOP_BITPOS (PWM Base address+0x0000) [14:9] is 63, PWM_SEND_DATA0
(PWM Base address+0x00A0) [31:0] and PWM_SEND_DATA1 (PWM Base address+0x00A4) are generated.

[Link].3 Memory Mode

lduration hduration

guard_value idle_value
~ ~ ~ ~
0 1 1 0 1 0 1 1 0 1
guard_duration
send_data0 send_data1 send_data0 send_data1

Figure 3-230 Memory Mode

In the periodical mode, all pulse sequences are repeatedly generated by the number of PWM_WAVE_NUM (PWM Base
address+0x00A8) [15:0]. If PWM_WAVE_NUM (PWM Base address+0x00A8) [15:0] =0, the hardware continuously outputs
waveforms, and the waveform generation can be stopped by PWM_ENABLE (PWM global Base address+0x0000) [31:0].

SRCSEL (PWM Base address+0x0000) [5] =1 means the memory mode. The pulse sequence data is put in memory with
address set by PWM_BUF0_BASE_ADDR (PWM Base address+0x0090) [31:0] and PWM_BUF0_BASE_ADDR2 (PWM Base
address+0x00BC) [3:0]. The length is PWM_BUF0_SIZE (PWM Base address+0x0094) [15:0]. STOP_BITPOS (PWM Base
address+0x0000) [14:9] indicates the stop bit position in the last 32-bit data.

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Memory

32-bit

Figure 3-231 Memory Mode and Stop-bit Position

Note:
It can be any kind of memory (usually SYSRAM) so long as the software can read or write the address. The software requests to locate an
unused memory and get the address, so it is necessary to write the address and length at PWM_BUF0_BASE_ADDR and
PWM_BUF0_SIZE.

[Link].4 Random Mode

On the other hand, the pulse sequence is stored in dual memory buffers in random mode. Figure 3-232 shows the format
of pulse sequences stored in the memory.
The valid bit indicates that the data is ready in the respective memory buffer. The PWM generation clears this bit after all
data in that buffer is fetched. The memory buffers are set by the address PWM_BUF0_BASE_ADDR (PWM Base
address+0x0090) [31:0] and PWM_BUF0_SIZE (PWM Base address+0x0094) [15:0] for memory 0, and
PWM_BUF1_BASE_ADDR (PWM Base address +0x0098) [31:0] and PWM_BUF1_SIZE (PWM Base address+0x009C) [15:0]
for memory 1.

The program should prepare for the pulse sequence and set the valid bit to 1 in time before all data in other memory
buffers is fetched. Otherwise, the hardware issues an UNDERFLOW interrupt to inform that the pulse generation stops
because there is no valid data. If an UNDERFLOW interrupt is received, the software needs to disable PWM, set the valid
bit again, and enable PWM to restart pulse generation.

Valid 0 Memory 0 Memory 1 Valid 1

32-bit 32-bit

Figure 3-232 PWM Random Mode

Note:
Any kind of memory can be used by PWM (usually SYSRAM) so long as the software can read or write the address. The software issues a
request, and PWM can locate an unused memory and get the address. So, you need to assign the address and length at
PWM_BUF0_BASE_ADDR, PWM_BUF0_SIZE, PWM_BUF1_BASE_ADDR, and PWM_BUF1_SIZE.

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[Link] PWM Signal Descriptions

Table 3-191 presents PWM signal descriptions.

Table 3-191 PWM Signal Descriptions

Signal Name Type Description Ball Location
PWM_0 DO PWM output 0 V4, AB33, AC8, C4
PWM_1 DO PWM output 1 V5, Y11, AA5, C3
PWM_2 DO PWM output 2 E5, AA11, R34, AB5
PWM_3 DO PWM output 3 F4, Y5, R33, AC5

[Link] Programming Guide

[Link].1 Normal Mode

Table 3-192 Normal Mode Setting Procedures

PWM Setting Sequence for Old Mode
Step Description R/W Address Bit MACRO Value Note
PWM_BASE +
1 Set PWM_ENABLE W [N] PWM_ENABLE 1'b0 Disable PWM[N]
0x0000
PWM_BASE +
2 Set PWM_CON W 0x080+ [15] OLD_PWM_MODE 1'b1
PWM_NUM*0x40
PWM_BASE +
3 Set PWM_CON W 0x080+ [8] GUARD_VALUE USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
4 Set PWM_CON W 0x080+ [7] IDLE_VALUE USER_DEFINED
PWM_NUM*0x40
If WAVE_NUM=0,
PWM_BASE + waveform
Set
5 W 0x0A8+ [15:0] PWM_WAVE_NUM USER_DEFINED generation does not
PWM_WAVE_NUM
PWM_NUM*0x40 stop until it is
disabled.
PWM_BASE +
6 Set PWM_GDURATION W 0x08C+ [15:0] PWM_GDURATION USER_DEFINED
PWM_NUM*0x40
Set PWM_BASE + 0xAC
7 W [12:0] PWM_DATA_WIDTH USER_DEFINED
PWM_DATA_WIDTH + PWM_NUM*0x40
PWM_BASE + 0xB0
8 Set PWM_THRESH W [12:0] PWM_THRESH USER_DEFINED
+ PWM_NUM*0x40
PWM_BASE +
9 Set PWM_ENABLE W [N] PWM_ENABLE 1'b1 Enable PWM[N]
0x0000

[Link].2 FIFO Mode

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Table 3-193 FIFO Mode Setting Procedures

PWM Setting Sequence for FIFO Mode
Step Description R/W Address Bit MACRO Value Note
PWM_BASE +
1 Set PWM_ENABLE W [N] PWM_ENABLE 1'b0 Disable PWM[N]
0x0000
PWM_BASE +
2 Set PWM_CON W 0x080+ [15] OLD_PWM_MODE 1'b0
PWM_NUM*0x40
PWM_BASE +
3 Set PWM_CON W 0x080+ [6] MODE 1'b0
PWM_NUM*0x40
PWM_BASE +
4 Set PWM_CON W 0x080+ [5] SRCSEL 1'b0
PWM_NUM*0x40
PWM_BASE +
5 Set PWM_CON W 0x080+ [8] GUARD_VALUE USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
6 Set IDLE_VALUE W 0x080+ [7] IDLE_VALUE USER_DEFINED
PWM_NUM*0x40
If
WAVE_NUM=0,
PWM_BASE +
waveform
7 Set PWM_WAVE_NUM W 0x0A8+ [15:0] PWM_WAVE_NUM USER_DEFINED
generation does
PWM_NUM*0x40
not stop until it is
disabled.
PWM_BASE +
8 Set PWM_GDURATION W 0x08C+ [15:0] PWM_GDURATION USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
9 Set PWM_HDURATION W 0x084+ [15:0] PWM_HDURATION USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
10 Set PWM_LDURATION W 0x088+ [15:0] PWM_LDURATION USER_DEFINED
PWM_NUM*0x40
This value should
be written only
in periodical FIFO
PWM_BASE +
mode. In other
11 Set PWM_SEND_DATA0 W 0x0A0+ [31:0] PWM_SEND_DATA0 USER_DEFINED
modes, this
PWM_NUM*0x40
buffer is for an
internal memory
access.
This value should
be written only
PWM_BASE +
in periodical FIFO
12 Set PWM_SEND_DATA1 W 0x0A4+ [31:0] PWM_SEND_DATA1 USER_DEFINED
mode. In other
PWM_NUM*0x40
modes, this
buffer is for

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PWM Setting Sequence for FIFO Mode

Step Description R/W Address Bit MACRO Value Note
internal memory
access.
Stop bit position
for source data
in periodical
mode.
In FIFO mode, it
is used to
PWM_BASE +
indicate the stop
13 Set PWM_CON W 0x080+ [14:9] STOP_BITPOS USER_DEFINED
bit position in a
PWM_NUM*0x40
total of 64 bits.
In memory
mode, it is for
the stop bit
position of the
last 32 bits.
PWM_BASE +
14 Set PWM_ENABLE W [N] PWM_ENABLE 1'b1 Enable PWM[N]
0x0000

[Link].3 Memory Mode

Table 3-194 Memory Mode Setting Procedures

PWM Setting Sequence for Memory Mode
Step Description R/W Address Bit MACRO Value Note
PWM_BASE +
1 Set PWM_ENABLE W [N] PWM_ENABLE 1'b0 Disable PWM[N]
0x0000
PWM_BASE +
2 Set PWM_CON W 0x080+ [15] OLD_PWM_MODE 1'b0
PWM_NUM*0x40
PWM_BASE +
3 Set PWM_CON W 0x080+ [6] MODE 1'b0
PWM_NUM*0x40
PWM_BASE +
4 Set PWM_CON W 0x080+ [5] SRCSEL 1'b1
PWM_NUM*0x40
PWM_BASE +
5 Set PWM_CON W 0x080+ [8] GUARD_VALUE USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
6 Set PWM_CON W 0x080+ [7] IDLE_VALUE USER_DEFINED
PWM_NUM*0x40
If WAVE_NUM=0,
PWM_BASE + waveform
7 Set PWM_WAVE_NUM W 0x0A8+ [15:0] PWM_WAVE_NUM USER_DEFINED generation does
PWM_NUM*0x40 not stop until it is
disabled.

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PWM Setting Sequence for Memory Mode

Step Description R/W Address Bit MACRO Value Note
PWM_BASE +
8 Set PWM_GDURATION W 0x08C+ [15:0] PWM_GDURATION USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
9 Set PWM_HDURATION W 0x084+ [15:0] PWM_HDURATION USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
10 Set PWM_LDURATION W 0x088+ [15:0] PWM_LDURATION USER_DEFINED
PWM_NUM*0x40
Base address of
Set PWM_BASE +
PWM_BUF0_BASE_A memory buffer0
11 PWM_BUF0_BASE_ADD W 0x090+ [31:0] USER_DEFINED
DDR for PWM's
R PWM_NUM*0x40
waveform data
Extend base
Set PWM_BASE + address of
PWM_BUF0_BASE_A
12 PWM_BUF0_BASE_ADD W 0x0BC+ [3:0] USER_DEFINED memory buffer0
DDR2
R2 PWM_NUM*0x40 for PWM's
waveform data
Length of
PWM_BASE + waveform data in
PWM_BUF0_BASE_A
13 Set PWM_BUF0_SIZE W 0x094+ [15:0] USER_DEFINED memory buffer0
DDR_EXTEND
PWM_NUM*0x40 PWM should
generate
Stop bit position
for source data in
periodical mode.
In FIFO mode, it is
used to indicate
PWM_BASE +
the stop bit
14 Set PWM_CON W 0x080+ [14:9] STOP_BITPOS USER_DEFINED
position in a total
PWM_NUM*0x40
of 64 bits. In
memory mode, it
is for the stop bit
position of the last
32 bits.
PWM_BASE +
15 Set PWM_ENABLE W [N] PWM_ENABLE 1'b1 Enable PWM[N]
0x0000

[Link].4 Random Mode

Table 3-195 Random Mode Setting Procedures

PWM Setting Sequence for Random Mode
Step Description R/W Address Bit MACRO Value Note
PWM_BASE + Disable
1 Set PWM_ENABLE W [N] PWM_ENABLE 1'b0
0x0000 PWM[N]

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PWM Setting Sequence for Random Mode

Step Description R/W Address Bit MACRO Value Note
PWM_BASE +
2 Set PWM_CON W 0x080+ [15] OLD_PWM_MODE 1'b0
PWM_NUM*0x40
PWM_BASE +
3 Set PWM_CON W 0x080+ [6] MODE 1'b1
PWM_NUM*0x40
PWM_BASE +
4 Set PWM_CON W 0x080+ [5] SRCSEL 1'b1
PWM_NUM*0x40
PWM_BASE +
5 Set PWM_CON W 0x080+ [8] GUARD_VALUE USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
6 Set PWM_CON W 0x080+ [7] IDLE_VALUE USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
7 Set PWM_GDURATION W 0x08C+ [15:0] PWM_GDURATION USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
8 Set PWM_HDURATION W 0x084+ [15:0] PWM_HDURATION USER_DEFINED
PWM_NUM*0x40
PWM_BASE +
9 Set PWM_LDURATION W 0x088+ [15:0] PWM_LDURATION USER_DEFINED
PWM_NUM*0x40
Base address of
Set PWM_BASE + memory
PWM_BUF0_BASE_ADD
10 PWM_BUF0_BASE_ADD W 0x090+ [31:0] USER_DEFINED buffer0 for
R
R PWM_NUM*0x40 PWM's
waveform data
Length of
PWM_BASE + waveform data
PWM_BUF0_BASE_ADD
11 Set PWM_BUF0_SIZE W 0x094+ [15:0] USER_DEFINED in memory
R_EXTEND
PWM_NUM*0x40 buffer0 PWM
should generate
Base address of
Set PWM_BASE + memory
PWM_BUF1_BASE_ADD
12 PWM_BUF1_BASE_ADD W 0x098+ [31:0] USER_DEFINED buffer1 for
R
R PWM_NUM*0x40 PWM's
waveform data
Length of
PWM_BASE + waveform data
PWM_BUF1_BASE_ADD
13 Set PWM_BUF1_SIZE W 0x09C+ [15:0] USER_DEFINED in memory
R_EXTEND
PWM_NUM*0x40 buffer1 PWM
should generate
Memory1/0 is
PWM_BASE +
BUF1_VALID/ not empty.
14 Set PWM_VALID W 0x0B8+ [1:0] 2’b11
BUF0_VALID When finishing
PWM_NUM*0x40
writing data to

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PWM Setting Sequence for Random Mode

Step Description R/W Address Bit MACRO Value Note
memory1, write
1 to inform
PWM the data
in memory1 is
ready.
Stop bit
position for
source data in
periodical
mode.
In FIFO mode, it
is used to
PWM_BASE +
indicate the
15 Set PWM_CON W 0x080+ [14:9] STOP_BITPOS USER_DEFINED
stop bit
PWM_NUM*0x40
position in a
total of 64 bits.
In memory
mode, it is for
the stop bit
position of the
last 32 bits.
PWM_BASE +
16 Set PWM_ENABLE W [N] PWM_ENABLE 1'b1 Enable PWM[N]
0x0000

[Link] Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

3.13 Miscellaneous

3.13.1 Timers and Counters

[Link] System Timer (SYSTMR)

[Link].1 Overview

The SYSTMR is a 64-bit and always-on up-counter used as a universal timer in the device. The counter value of
SYSTMR is passed to the application cores (A78 and A55), SCP, GPU, and other processors to provide uniform
system timestamps for operating systems such as Android™, Linux®, and RTOS (Real-Time Operating System).

[Link].2 Feature

The SYSTMR supports the following key features:

 Enabled by default to tick with a 13 MHz clock period

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 Hardware counter incremented compensation when switching to a 32 kHz clock source

 8 × 32-bit counter timeout value (read as 32-bit down counter)
 Security access permission control for each control register (with one-time lock bit)

[Link].3 Block Diagram

Figure 3-233 Block Diagram of SYSTMR

[Link].4 Function Description

 Low power mode

When the system enters low power mode, SYSTMR receives clk_26m_dis from SPM and switches to the 32 kHz clock.
SYSTMR can ensure the accuracy of the counter value in low power mode by using the 32 kHz clock counter.
 Halt on debug
If the CPU wants to stop system debugging, the CPU can send the cpu_dbgack signal. SYSTMR stops counting after
receiving cpu_dbgack to keep the current counter value.
 Timer IRQ
You can set the timer value by writing to the CNTTVAL register. Then, the timer starts counting down. The timer issues
an IRQ when it counts down to 0.

[Link].5 Theory of Operations

SYSTMR is a general counter with the function of counting up and counting down. However, in low power mode, we use a
compensation mechanism to ensure that the exact counter value can be maintained between 26m clock and 32k clock.
The relationship between 26 MHz and 32 kHz is not an integer, so there is a Quantization Error.

1. 26 MHz/32.768 kHz =793.4570313. One cycle of 32.768 kHz takes 793.4570313 cycles of 26 MHz.
2. After adding the integer 793, each cycle of 32 kHz causes 0.45703125 cycles of 26 MHz error (about 17.5781 ns).
3. One cycle of 32 kHz produces an error of 17.5781 ns; 56.8889M cycles of 32k produces an error of about 1 second ->
the time to accumulate a 1-second error is 1736.11 seconds.

It means every 1736.11 seconds pass, there is a 1-second error. In order to eliminate the Quantization Error, conduct the
following analysis:

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1. Use the moving average and find 793.45703125 => 793.45703125 = 793*X + 794*(1-X ) => X= 0.54296875.
2. To find the best P and Q by Numerical Analysis, use 793*(139/256) + 794*(117/256) = 793.45703125.

Bit Counter P/Q X(=P/Q) Eq. Increment Error Day Year

5 13/24 0.541666667 793.4583333 -5.00801E-11 -7.0529514 -0.02
6 19/35 0.542857143 793.4571429 -4.29258E-12 -82.284433 -0.23
7 19/35 0.542857143 793.4571429 -4.29258E-12 -82.284433 -0.23
8 120/211 0.542986425 793.4570136 -6.79821E-13 519.56742 1.42
9 139/256 0.54296875 793.4570313 0 N/A N/A

In every 256 32k cycles, add 139 times 793 and 117 times 794 to realize the compensation mechanism.

[Link].6 Programming Guide

[Link].6.1 Counter

Although SYSTMR uses a 26 MHz clock source, the counter value is updated at a frequency of 13M. The counter value of
SYSTMR is about 76.92 ns per unit. When running at 26 MHz, the counter value increases by 1; when running at 32 kHz,
the counter value increases by 396 or 397.

In the CNTCR register, the counter is mainly controlled by the following bits. For a more complete register introduction,
refer to “MT8390 Register Map.”

Register Name Address Bit Name Type Description

0 CNT_EN RW Enable SYSTMR counter. Default setting is 1.

2 RW Enable 32 kHz auto-switch function of SYSTMR counter.

CNT_32K_AS_EN
Default setting is 1.
10 COMP_15_EN RW v1.5 is based on 13 MHz and 32 kHz to tick SYSTMR.
CNTCR 0x00000 11 COMP_20_EN RW v2.0 is only based on 32 kHz to tick SYSTMR.
v2.5 solves discontinuity issue of v2.0.
12 COMP_25_EN RW v2.5 and v2.0 need to be enabled together. v2.0 can be
enabled alone.
13 KP_LSB9b_EN RW The 10 LSB remain 0 when the clock switches to 32 kHz if
this bit is set.

 CNT_32K_AS_EN
This bit decides when 26 MHz is turned off, whether SYSTMR is switched to update the counter at 32 kHz frequency. If
this bit is not enabled, the counter pauses when 26 MHz is turned off. In general, this bit should not be disabled.

 COMP_15_EN
In compensation v1.5, SYSTMR only uses one hardware counter to count the counter value. At the 26 MHz clock, the
counter adds 1 every cycle; when 26 MHz is turned off, SYSTMR uses the 32 kHz clock, as the discussion of 1.5 Low
Power, adding 396 or 397 every cycle.

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 COMP_20_EN/COMP_25_EN
In compensation v2.0, SYSTMR uses a 26 MHz counter and a 32 kHz counter to count the counter values, and the two
counters count at 26 MHz and 32 kHz clocks, respectively. SYSTMR is mainly based on the 32 kHz counter because the
32 kHz counter is always counting and will not be turned off.

Every time the 32 kHz clock rises, the 26 MHz counter is aligned with the 32 kHz counter, and then the 26 MHz counter
value continues to increment at 26 MHz frequency.

In normal mode, SYSTMR outputs a 26 MHz counter value. Turning off the 26 MHz clock means low power mode is
enabled. The 26 MHz counter pauses, and SYSTMR switches to output the 32 kHz counter value.

However, this architecture may result in discontinuous SYSTMR values. For systems that are sensitive to continuous count
values, the software must enable COMP_25_EN to solve the discontinuity issue.

The following describes the reading and writing of counter values.

Register Name Address Type Description

CNTCV_L 0x00008 RW 64-bit SYSTMR counter value[31:0].
CNTCV_H 0x0000C RW 64-bit SYSTMR counter value[63:32].

 Initial counter value

Write 0 to CNTCV_H and CNTCV_L. It takes about 3 32 kHz cycles to synchronize (~100 us).
*If CNT_EN = 0, CNTCV_H/CNTCV_L still changes. Wait for CNT_EN = 1, and then wait for 3 32 kHz cycles to update.
 Read counter value
Because the data is from the SYSTMR clock domain to the APB clock domain, it needs to be synchronized. Due to
hardware limitations, no matter where the counter value is read from, CNTCV_L needs to be read first to avoid
unexpected results.

[Link].6.2 Timer

The software can control timer and interrupt through the following register.

Register Name Address Bit Name Type Description

0 CNTTVAL[N]_EN RW Enable system timer N.
1 IRQ[N]_EN RW Enable system timer N interrupt.
CNTTVAL[N]_CON 0x00040+8*N
RW Read: system timer N interrupt status.
4 IRQ[N]_STA
Write: write 1’b1 to clear interrupt.

The software can set the timer value through the following register.

Register Name Address Type Description

System timer N down counter.
CNTTVAL[N] 0x00044+8*N RW Read: 32-bit down counter value.
Write: set timeout value.
Note: N = 0 to 7

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 Set timer value

a. Set CNTTVAL[N]*_CON to 0x1: Enable timer[N] to write.
b. Write counter down value to CNTTVAL[N].
c. Set CNTTVAL[N]_CON to 0x3: Enable IRQ_EN of timer[N] for timeout IRQ.
d. Read CNTTVAL[N]: Read current count down value (optional).
e. After IRQ is asserted, you need to write CNTTVAL[N]_CON bit 4 to clear IRQ. (CNTTVAL[N]_EN must be 1 to clear
the IRQ)

 Timer domain check

Domain check will limit the timer so that only specific domains can access it.

Register Name Address Bit Name Type Description

Disable domain check for read control registers of
timers. Bits 7 to 0 are for timers 7 to 0.
7:0 RD_DOMAIN_DIS RW
0: Enable domain check for reading (Default).
1: Disable domain check for reading.
DOMAIN_DIS 0x00080
Disable domain check for write control registers of
timers. Bits 15 to 8 are for timers 7 to 0.
15:8 WR_DOMAIN_DIS RW
0: Enable domain check for writing (Default).
1: Disable domain check for writing.
Domain value of timer N.
DOMAIN_VAL 0x0084 [3+4*N:4*N] DOMAIN_VAL_[N] RW
Domain value is 4 bits.

[Link] General-Purpose Timer (APXGPT)

[Link].1 Overview

The Application Processor General-Purpose Timer (APXGPT) module consists of five sets of GPTs that feature 32-bit up-
counters and one set of GPTs that contain 64-bit up-counters. Section [Link].3 shows the block diagram. Each GPT
supports four operation modes as follows. For further details, see Table 3-196 and Section [Link].6.

 ONE-SHOT mode
 REPEAT mode
 KEEP-GO mode
 FREERUN mode

Each GPT can operate on either of the two clock sources: 32.768 kHz Real-Time Clock (RTC) or the 13 MHz system clock,
with a 4-bit pre-scaler that provides a programmable clock frequency from these two clock sources.

By selecting the desired modes and working clocks, a specific time delay can be obtained. Upon reaching a programmable
timer value, an Interrupt Request (IRQ) will be sent to the CPU and System Power Management (SPM).

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[Link].2 Features

 Selection of two clock sources for the up-counter of each GPT

 Programmed to be active in the low power mode
 Interrupt generation when a programmable timer value is reached
 Three comparison modes available for the set timer boundary value

[Link].3 Block Diagram

cnt_64[63:0]
GPT[5]

GPT[1]
slow_ck
GPT[0]
f13m_ck
sw_cg_en[0]
clk_ctrl[0] APXGPT_
en[0]
CK_GEN
irq_ack[0]
mode[1:0] en_d2 apxgpt_ck

CONTROL mode[1:0] met

APB irq_ack[0] APXGPT_IRQ
APXGPT_REG all_irq_b0[5:0]
clr[0]
cmp_mode[3:0]
APXGPT_ENG
event event irq_sta[5:0]
_b0 _b1 write_comp[0]
pre_scale[3:0] ctr_read[63:0]
met_gptck

event_b0

Figure 3-234 Block Diagram of APXGPT

[Link].4 Function Description

The APXGPT is primarily built upon an up-counter that counts using the rising edge of a clock. The operating clock
frequency can be selected from two sources, usually 13 MHz and 32.768 kHz, which can be internally divided to provide
additional frequency options. As the clock period is known, the counter boundary should be set to obtain a specific time
delay. The time is then calculated by multiplying the count by the clock period. Upon reaching the counter boundary, an
interrupt request will be generated.

The table below presents detailed descriptions for the four operation modes of each GPT.

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Table 3-196 Operation Mode of GPT

When
Example: Compare is set to 2
Auto Interrupt GPTn_COUNT
Mode Count Behavior (Underlining means that an
Stop Supported Equals to
interrupt is asserted.)
GPTn_COMPARE
Count stops when GPTn_COUNT
ONE-SHOT Yes Yes EN is reset to 0 0,1,2,2,2,2,2,2,2,2,2,2,…
equals GPTn_COMPARE
Count is reset to 0 when
REPEAT No Yes GPTn_COUNT equals Count is reset to 0 0,1,2,0,1,2,0,1,2,0,1,2…
GPTn_COMPARE
Count is reset to 0 when the
KEEP-GO No Yes No action 0,1,2,3,4,5,6,7,8,9,10,…
count is overflowed.
Count is reset to 0 when the
FREERUN No No No action 0,1,2,3,4,5,6,7,8,9,10,…
count is overflowed.
Note:
 GPTn_COUNT (APXGPT Base address+(0x0008+0x20*(n-1))), GPTn_COMPARE (apxgpt Base address + (0x000C+0x20*(n-1)))
(n=0,1,2,3,4,5)
 Each timer operates independently and can be programmed to select between the 32.768 kHz RTC or the13 MHz system clock.
Once the clock source is set, the selected clock's division ratio can be programmed and fine-tuned within the range of 1 to 13, or
coarse-tuned with values of 16, 32, and 64.

[Link].4.1 Clocking

The APXGPT module employs four main input clocks, namely:

 slow_clock
 f13m_ck
 pclk_ck
 hclk_ck

The first two clocks serve as the operation clock of the up-counter. Select one of them through the register setting. The
APB clock (PCLK) and hopping clock (HCLK) are bus-related clocks.

Table 3-197 Clock Source of GPT

Name Frequency Description
slow_ck 32.768 kHz APXGPT counter clock
f13m_ck 13 MHz APXGPT counter clock
pclk_ck 26 MHz APB clock
hclk_ck 26 MHz To synchronize with the bus clock

[Link].4.2 Interrupts

When the GPT reaches the programmable compared value of the up-counter, “GPTn” (n = 0, 1, 2, 3, 4, 5) generates an
interrupt request (IRQ) to send to the GPU. These GPT interrupts are merged and connected to the SPM.

Upon GPT triggering an IRQ, it issues a wake-up signal to the "Sleep Control" to wake up the MCU if it is in the sleep mode.

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[Link].5 Theory of Operations

The read operation value of the GPT6 64-bit timer is split into two 32-bit APB reads. The lower word is read first, followed
by the higher word. The read operation of lower word freezes the “read value” of the higher word, but does not freeze the
timer counting. This ensures that the separated read operation acquires the correct timer value.

When programming and utilizing the GPT, note the following points:

 The counter value can be read at any time when the clock source is the system clock or the RTC.
 The comparative value can be programmed at any time. If it is rewritten during a count operation, the counter is reset
to 0 and restarts the count.

[Link].6 Programming Guide

The following sections describe the operating sequence of all the operation modes, using GPT0 as an example to
demonstrate the programming sequence.

[Link].6.1 ONE-SHOT Mode

Table 3-198 APXGPT ONE-SHOT Mode Setting Flow

Step Address Register Name Local Address R/W Value Description
Set the APXGPT control register.
Select GPT0 clock source,
APXGPT base Refer to the
1 GPT0_CON CLK RW 00: System clock (13 MHz)
address + 0x0000 description.
01: RTC (32.768 kHz)
Set the GPT0 clock divider,
0000: Clock source divided by 1
0001: Clock source divided by 2
0010: Clock source divided by 3
0011: Clock source divided by 4
0100: Clock source divided by 5
0101: Clock source divided by 6
0110: Clock source divided by 7
APXGPT base Refer to the
2 GPT0_CON CLKDIV RW 0111: Clock source divided by 8
address + 0x0000 description.
1000: Clock source divided by 9
1001: Clock source divided by 10
1010: Clock source divided by 11
1011: Clock source divided by 12
1100: Clock source divided by 13
1101: Clock source divided by 16
1110: Clock source divided by 32
1111: Clock source divided by 64
Set the GPT0 control register for
APXGPT base ONE-SHOT mode.
3 GPT0_CON MODE RW 2’b00
address + 0x0000 00: ONE-SHOT mode
01: REPEAT mode

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Step Address Register Name Local Address R/W Value Description

10: KEEP-GO mode
11: FREERUN mode
APXGPT base GPT0_COMPAR Refer to the
4 COMPARE RW Set the compare value of GPT0.
address + 0x000C E description.
APXGPT base Set IRQEN to “1” to enable GPT0
5 GPT0_CON IRQEN RW 1’b1
address + 0x0000 interrupt.
Enable GPT0 and wait for GPT0 interrupt.
APXGPT base
6 GPT0_CON EN RW 1’b1 Set EN to “1” to enable GPT0.
address + 0x0000
Wait for IRQSTA = “1”,
0: No associated interrupt is
APXGPT base Refer to the
7 GPT0_CON IRQSTA RO generated.
address + 0x0000 description.
1: Associated interrupt is pending
and waiting for service.
Clear GPT0 interrupt (Choose one of the two methods)
APXGPT base Set PREFIX= 4’h2 to clear GPT0
GPT0_CON PREFIX WO 4’h2
address + 0x0000 interrupt.
8
APXGPT base Interrupt of GPTn. Can be written
IRQ_STA IRQ_STA WO 1’b1
address + 0x0FC0 to 1 to clear.

[Link].6.2 REPEAT Mode

Table 3-199 APXGPT REPEAT Mode Setting Flow

Step Address Register name Local address R/W Value Description
Set the APXGPT control register.
Select GPT0 clock source,
APXGPT base Refer to the
1 GPT0_CON CLK RW 00: System clock (13 MHz)
address + 0x0000 description.
01: RTC (32.768 kHz)
Set the GPT0 clock divider,
0000: Clock source divided by 1
0001: Clock source divided by 2
0010: Clock source divided by 3
0011: Clock source divided by 4
0100: Clock source divided by 5
0101: Clock source divided by 6
APXGPT base Refer to the 0110: Clock source divided by 7
2 GPT0_CON CLKDIV RW
address + 0x0000 description. 0111: Clock source divided by 8
1000: Clock source divided by 9
1001: Clock source divided by 10
1010: Clock source divided by 11
1011: Clock source divided by 12
1100: Clock source divided by 13
1101: Clock source divided by 16
1110: Clock source divided by 32

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Step Address Register name Local address R/W Value Description

1111: Clock source divided by 64
Set the GPT0 control register for
REPEAT mode.
APXGPT base 00: ONE-SHOT mode
3 GPT0_CON MODE RW 2’b01
address + 0x0000 01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
APXGPT base GPT0_COMPAR Refer to the
4 COMPARE RW Set the compare value of GPT0.
address + 0x000C E description.
APXGPT base Set IRQEN= “1” to enable GPT0
5 GPT0_CON IRQEN RW 1’b1
address + 0x0000 interrupt.
Enable GPT0 and wait for GPT0 interrupt
APXGPT base
6 GPT_CON EN RW 1’b1 Set EN to “1” to enable GPT0.
address + 0x0000
Wait for IRQSTA = “1”,
0: No associated interrupt is
APXGPT base Refer to the
7 GPT0_CON IRQSTA RO generated.
address + 0x0000 description.
1: Associated interrupt is pending
and waiting for service.
Clear GPT0 interrupt (Choose one of the two methods)
APXGPT base Set PREFIX= 4’h2 to clear GPT0
GPT0_CON PREFIX WO 4’h2
address + 0x0000 interrupt.
8
APXGPT base Interrupt of GPTn. Can be written
IRQ_STA IRQ_STA WO 1’b1
address + 0x0FC0 to 1 to clear.

[Link].6.3 KEEP-GO Mode

Table 3-200 APXGPT KEEP-GO Mode Setting Flow

Step Address Register name Local address R/W Value Description
Set the APXGPT control register.
Select the GPT0 clock source,
APXGPT base Refer to the
1 GPT0_CON CLK RW 00: System clock (13 MHz)
address + 0x0000 description.
01: RTC (32.768 kHz)
Set the GPT0 clock divider,
0000: Clock source divided by 1
0001: Clock source divided by 2
0010: Clock source divided by 3
0011: Clock source divided by 4
APXGPT base Refer to the
2 GPT0_CON CLKDIV RW 0100: Clock source divided by 5
address + 0x0000 description.
0101: Clock source divided by 6
0110: Clock source divided by 7
0111: Clock source divided by 8
1000: Clock source divided by 9
1001: Clock source divided by 10

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Step Address Register name Local address R/W Value Description

1010: Clock source divided by 11
1011: Clock source divided by 12
1100: Clock source divided by 13
1101: Clock source divided by 16
1110: Clock source divided by 32
1111: Clock source divided by 64
Set the GPT0 control register for
KEEP-GO mode.
APXGPT base 00: ONE-SHOT mode
3 GPT0_CON MODE RW 2’b10
address + 0x0000 01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
APXGPT base GPT0_COMPAR Refer to the
4 COMPARE RW Set the compare value of GPT0
address + 0x000C E description.
APXGPT base Set IRQEN = “1” to enable GPT0
5 GPT_IRQEN IRQEN RW 1’b1
address + 0x0000 interrupt.
Enable GPT0.
APXGPT base
6 GPT0_CON EN RW 1’b1 Set EN to “1” to enable GPT0.
address + 0x0000
Wait for IRQSTA = “1”,
0: No associated interrupt is
APXGPT base Refer to the
7 GPT0_CON IRQSTA RO generated,
address + 0x0000 description.
1: Associated interrupt is pending
and waiting for service.
Read the GPT0 counter value
APXGPT base Refer to the
8 GPT0_COUNT COUNTER RO The timer counter of GPT0.
address + 0x0008 description.
Clear GPT0 interrupt. (Choose one of the two methods)
APXGPT base Set PREFIX = 4’h2 to clear GPT0
GPT0_CON PREFIX WO 4’h2
address + 0x0000 interrupt.
9
APXGPT base Interrupt of GPTn. Can be written
IRQ_STA IRQ_STA WO 1’b1
address + 0x0FC0 to 1 to clear.

[Link].6.4 FREERUN Mode

Table 3-201 APXGPT FREERUN Mode Setting Flow

Step Address Register name Local address R/W Value Description
Set the APXGPT control register.
Select GPT0 clock source,
APXGPT base Refer to the
1 GPT0_CON CLK RW 00: System clock (13 MHz)
address + 0x0000 description.
01: RTC (32.768 kHz)
Set the GPT0 clock divider,
APXGPT base Refer to the
2 GPT0_CON CLKDIV RW 0000: Clock source divided by 1
address + 0x0000 description.
0001: Clock source divided by 2

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Step Address Register name Local address R/W Value Description

0010: Clock source divided by 3
0011: Clock source divided by 4
0100: Clock source divided by 5
0101: Clock source divided by 6
0110: Clock source divided by 7
0111: Clock source divided by 8
1000: Clock source divided by 9
1001: Clock source divided by 10
1010: Clock source divided by 11
1011: Clock source divided by 12
1100: Clock source divided by 13
1101: Clock source divided by 16
1110: Clock source divided by 32
1111: Clock source divided by 64
Set the GPT0 control register for
KEEP-GO mode,
APXGPT base 00: ONE-SHOT mode
3 GPT0_CON MODE RW 2’b11
address + 0x0000 01: REPEAT mode
10: KEEP-GO mode
11: FREERUN mode
Enable GPT0.
APXGPT base
4 GPT0_CON EN RW 1’b1 Set EN to “1” to enable GPT0.
address + 0x0000
Read the GPT0 counter value.
APXGPT base Refer to the
5 GPT0_COUNT COUNTER RO The timer counter of GPT0.
address + 0x0008 description.

[Link].6.5 GPT5 64-Bit Counter Read

Table 3-202 GPT5 64-bit Counter Read Flow

Step Address Register name Local address R/W Value Description
Read the lower 32 bits of the GPT5 counter.

APXGPT base Refer to the The lower word of the timer count
1 GPT5_COUNT_L RO
address + 0x00A8 description. of GPT5.
Read the higher 32 bits of the GPT5 counter.
APXGPT base Refer to the The higher word of the timer count
2 GPT5_COUNT_H RO
address + 0x00B0 description. of GPT5.

[Link].7 Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

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[Link] Watchdog Timer (WDT)

The WDT module is a part of TOPRGU. For more information refer to Section 5.5 Reset.

3.13.2 Auxiliary Analog-to-Digital Converter (AUXADC)

[Link] Overview
The Auxiliary Analog/Digital Converter (AUXADC) module is designed to identify the plugged peripheral and
perform temperature and voltage measurement. There are 6 input channels that allow diverse applications, such
as temperature/voltage measurement and light sensing. The device features one AUXADC module.

[Link] Features

The module contains:

 Immediate analog-digital conversion

 Background detection and interrupt

[Link] Block Diagram

The software controls AUXADC through the APB. Once the hardware receives the command, it triggers AUXADC’s channel
sampling automatically. The software polls the status register or waits for interrupts from the CPU.

lowbattery_irq PDN_AUXADC

det_spl det_dac da_adc_pwdb

adc_sel
adsc_aux_pwdb da_adc_spl
da_adc_dac VIN0
monitor_busy adc_st
AUXADC_MONITOR AUXADC_SIF da_adc_chsel

ad_adc_comp
control ADC_SFS ADC_SDATA ADC VIN5

AUXADC_CORE
immidiate_str VIN7
autoset_str
APB puwait_en adc_rdy
AUXADC_REG
sel_latch
adc_state AUXADC_IF

latch_data

Figure 3-235 Block Diagram of AUXADC

[Link] Function Description

 Immediate analog-digital conversion

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In the immediate mode, AUXADC samples the value once only when the flag in the AUXADC_CON1 register is set. For
example, if the flag IMM0 in AUXADC_CON1 is set, the module samples the data for channel 0. The IMM flags have to
be cleared and set again to initialize another sampling. The value sampled for channel 0 is stored in the register
AUXADC_DAT0. If the AUTOSET(x) flag in the register AUXADC_CON0 is set, the auto-sampling function is enabled in
channel(x). The module samples the data for channel(x) whenever the corresponding data register is read.
If multiple channels are selected at the same time, the tasks are performed sequentially on every selected channel
from channel 5 to channel 0.
 Background detection and interrupt
If background detection is enabled, AUXADC automatically compares the selected channel data with the user-defined
value. If the results are continuously greater or less than the given value, AUXADC issues an interrupt to inform the
system user.

[Link] AUXADC Timing and Functional Characteristics

Table 3-203 presents timing and functional characteristics for AUXADC in the device.

Table 3-203 AUXADC Specifications

Parameter Min Typ Max Unit
fOP Operating frequency 3.25 MHz
N Resolution 12 Bit
3.25 /
fS Sampling rate at N-bit MSPS
(N+8)
INSW Input swing 0.05 1.45 V
Input capacitance unselected channel 50 pF
CIN
Input capacitance selected channel 4 pF
RIN Input resistance unselected channel 400 MΩ
Fcycle_latency Cycle latency N+8 1/fOP
DNL Differential non-linearity +1.0/-1.0 LSB
INL Integral non-linearity +2.0/-2.0 LSB
Signal to noise and distortion ratio (1 kHz full swing input;
SNR+D 60 67 dB
1.0833 MHz clock rate)

[Link] Theory of Operations

Successive-Approximation Register (SAR) ADC provides low power consumption, cost-effective and medium resolution. The
AUXADC module has the SAR ADC architecture.

The following shows an example of 12-bit conversion. VREF is the reference voltage of AUXADC.

AUXADC implements a binary search algorithm. An initial register VDA value, the mid-value between (212-1) and 0, is
compared with the input voltage VIN. The value represents VREF /2. If VIN is bigger than VDA, the output of comparison is 1,
and the MSB is 1. Otherwise, the MSB is 0. Subsequently, bit 11 is set to 1, and another comparison is done. Bit10 to bit 0
are executed as the previous action. Then, the 12-bit digital value is available.

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Comparator
VIN
-
VDA
+

VREF

Digital-analog
12-bit
SAR digital logic
converison

VDA

8/8 VREF

7/8 VREF

6/8 VREF

5/8 VREF

4/8 VREF

3/8 VREF

2/8 VREF
VIN
1/8 VREF
Comparison

bit11=0 bit10=0 bit9=1 bit8=0 bit7=1 bit6=0 bit5=1 bit4=1 bit3=0 bit2=0 bit1=1 bit0=1

Figure 3-236 Theory of AUXADC Operation

[Link] Programming Guide

[Link].1 Immediate Mode

Table 3-204 Immediate Mode Programming Sequence

Immediate Mode
Description R/W Address Bit MACRO Value Note

INFRACFG_AO_BASE + Set 0 to enable

Open AUXADC Clock W [10] AUXADC_CG_SET 1'b1
0x0088 AUXADC clock.
Set 1 to sample
Set Immediate Mode W AUXADC_BASE + 0x0004 [15:0] AUXADC_CON1 USER_DEFINED corresponding
channel once.
Sample data is
AUXADC_BASE + 0x0014 +
Polling Ready R [12] RDYn 1'b1 ready when this bit
n*4
changes to 1.
AUXADC_BASE + 0x0014 +
Read Result R [11:0] DATn - Sample result
n*4

[Link].2 Background Detection

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Table 3-205 Background Detection Programming Sequence

Background Detection
Description R/W Address Bit MACRO Value Note
Set Threshold AUXADC_BASE + Set Threshold Voltage
W [11:0] VOL USER_DEFINED
Voltage 0x0084
Set Compare AUXADC_BASE + 0: Lower
W [12] INV USER_DEFINED
direction 0x0084 1: Higher
Set Detection AUXADC_BASE + Set channel to be sampled in
W [3:0] CHSEL USER_DEFINED
Channel 0x0088 background.
Background sample period:
When this value is not 0, the
background detection is
activated automatically and
Set Detection AUXADC_BASE + other ADC sampling functions
W [13:0] BG_DET_PERIOD USER_DEFINED
Period 0x008C are stopped. The counter counts
by 32K clock. When counter
value is greater than
DET_PERIOD, the detection is
activated.
Background de-bounce time:
When the number of the
detected channel is higher or
Set Detection AUXADC_BASE +
W [13:0] BG_DET_TIME USER_DEFINED lower than the pre-defined
De-bounce 0x0090
voltage and exceeds
"debounce_time", the interrupt
is issued.

3.13.3 Thermal Control Subsystem (TCSYS)

[Link] Introduction

Thermal management is crucial on the SoC platform. Through thermal management, an SoC can operate within specific
temperature constraints whole fulfilling computing performance requirements. Operations under over-temperature
condition for a long period of time may cause reliability issues.

The thermal management system includes several thermal sensors embedded in possible hotspots on the die and a
thermal controller module for periodic measurement for each hotspot. The measurement results are read by the software.
However, in order to minimize software efforts for monitoring temperature, the thermal controller generates interrupts to
a system handler for abnormal conditions.

[Link] Features

The thermal management system includes the following features:

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 Support up to four thermal sensors per hardware module unit.

 Programmable periodic temperature measurement.
 Two independent Finite State Machines (FSMs) for temperature monitoring.
 Different types of low pass filters for thermal sensor readings.

[Link] Block Diagram

There are three major building blocks for the thermal control subsystem, as Figure 3-237 shows.

 Sensing device: Thermal Sensing Micro-Circuit Unit (TSMCU)

 Convertor: Low Voltage Thermal Sensor (LVTS) convertor
 Digital controller: LVTS_CTRL

Figure 3-237 Thermal Control Subsystem

[Link] TCSYS Signal Descriptions

Table 3-206 presents TCSYS signal descriptions.

Table 3-206 TCSYS Signal Descriptions

Signal Name Type Description Ball Location
LVTS_26M DI LVTS supported 26 MHz input frequency AD37, P30
LVTS_FOUT DO LVTS output clock frequency N30, AC35
LVTS_SCF DI LVTS serial clock frequency N34, AD36
LVTS_SCK DI LVTS serial clock P33, AB37
LVTS_SDI DI LVTS data input P35, AB35
LVTS_SDO DO LVTS data output AD35, N31

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[Link] Function Description

Thermal controller periodically polls all sensors for SoC operating within a pre-defined temperature range to avoid function
failure and reliability issues. According to the temperature measurement, the system performance can be adjusted for a
system design with power dissipation being monitored. Figure 3-238 shows the temperature measurement scheme. Note
that the hottest location in an SoC may vary in different applications.

When the thermal controller informs the software of an abnormal condition, the consecutive power reduction
methodology should be efficient and with low latency.

ADC value
Small
HOT

HOT threshold
HOT2NORMAL threshold

High offset
Low offset
NORMAL

COLD threshold

COLD

Large

Figure 3-238 Block Diagram of System Temperature Measurement Scheme

[Link] Theory of Operations

[Link].1 Interrupt Control

Figure 3-239 shows the interrupt conditions of high and low temperature monitors. Software can determine which
temperature sensors to be monitored. Once any of the following three interrupt conditions occur in any of the monitored
temperature sensors, an interrupt is generated.
 Cold interrupt: Asserted when the temperature crosses and falls below the cold threshold.
 Hot interrupt: Asserted when the temperature crosses and rises above the hot threshold.
 Hot-to-normal interrupt: Asserted when the temperature crosses and falls below the hot-to-normal threshold.

Figure 3-240 shows the Finite State Machine (FSM) diagram. The states are as listed below.
 COLD_ST: The temperature is lower than the cold threshold.
 NORMAL_ST: The temperature is within the hot-to-normal threshold and cold threshold.
 HOT1_ST: The temperature is within the hot-to-normal threshold and hot threshold, and the previous state is
NORMAL_ST.
 VERY_HOT_ST: The temperature is higher than the hot threshold.

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 HOT2_ST: The temperature is within the hot-to-normal threshold and hot threshold, and the previous state is
VERY_HOT_ST.

Hot threshold
Hot to normal
threshold

Cold threshold

Hot to
Cold Cold Hot
normal
interrupt interrupt interrupt
interrupt

Figure 3-239 Interrupt Conditions for High/Low Temperature Monitoring

HOT2

NORMAL

VERY_HOT

COLD

HOT1

Figure 3-240 Finite State Machine for High/Low Temperature Monitoring

The system also provides a feature to control the junction temperature within the pre-defined HIGH-OFFSET and LOW-
OFFSET. Figure 3-241 depicts the concept of the feature and Figure 3-242 shows the FSM. There are two interrupts and two
alarms:

 LOW-OFFSET alarm to RGU: Asserted when the temperature crosses and drops below the low offset.
 HIGH-OFFSET alarm to RGU: Asserted when the temperature crosses and rises above the high offset.
 LOW-OFFSET Interrupt: Asserted when the temperature crosses and drops below the low offset. The FSM transitions
from the NORMAL state into the LOW OFFSET state.
 HIGH-OFFSET Interrupt: Asserted when the temperature crosses and rises above the high offset. The FSM transitions
from the NORMAL state into the HIGH OFFSET state.

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Hot threshold
High offset
Monitor
temprature
Low offset

Cold threshold
Low offset Low offset
interrupt/ interrupt/
alarm High offsetalarm
interrupt/alarm

Figure 3-241 Interrupt Conditions of High/Low OFFSET Monitoring

Set new temperature monitoring

NORMAL

HIGH
OFFSET
LOW
OFFSET

Figure 3-242 Finite State Machine for High/Low OFFSET Monitoring

[Link].2 Thermal Sensor Locations

Thermal sensors are placed at different locations within a die for monitoring the junction temperatures of the different die
locations.

Table 3-208 lists the locations of all thermal sensors.

Table 3-207 Locations Monitored by Temperature Sensors

Core Module Sensor
#1 BIG-CPU (Bottom) TS-1 and TS-2
#2 BIG-CPU (Top) TS-3 and TS-4
#3 CPU TS-5 to TS-8
#4 APU TS-9 and TS-10
#5 GPU TS-11 and TS-12
#6 SOC/TOP TS-13 to TS-15
#7 CAM TS-16 and TS-17
Note:
 The difference between BIG-CPU and CPU is that CPU represents cores other than Big Cores

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[Link] Programming Guide

Table 3-208 lists the thermal controller programming sequence.

TMU_BASE (CPU View):

 THERM_CTRL_AP register base address: 0x1100B000

 THERM_CTRL_MCU register base address: 0x11278000

Table 3-208 Thermal Controller Programming Guide

Step Sequence REG_Name REG_Value Address offset
1 Enable controller clock LVTSCLKEN 0x00000001 TMU_BASE+0x00E4
Establish LVTS connection 0xC103FFFF
2 LVTS_CONFIG TMU_BASE+0x0050
(Set in order, 2 us delay for each command) 0xC502FF55
3 Check LVTS connection ID LVTS_ID Read Only TMU_BASE+0x004C
0xC1030E01
0xC1030CFC
0xC1030A8C
0xC103098D
Initialize LVTS device 0xC10308F1
4 LVTS_CONFIG TMU_BASE+0x0050
(Set in order, 2 us delay for each command) 0xC10307A6
0xC10306b8
0xC1030500
0xC1030420
0xC1030300
LVTSEDATA00 0x00xxxxxx TMU_BASE+0x0054
LVTSEDATA01 0x00xxxxxx TMU_BASE+0x0058
5 Prepare calibration data
LVTSEDATA02 0x00xxxxxx TMU_BASE+0x005c
LVTSEDATA03 0x00xxxxxx TMU_BASE+0x0060
6 Configure PNP data to select the monitored sensors LVTSTSSEL 0x13121110 TMU_BASE+0x0040
Configure sampling method for the thermal sensors
7 LVTSMSRCTL0 0x000006DB TMU_BASE+0x0038
(optional)
LVTSMONCTL1 0x0000000C TMU_BASE+0x0004
8 Configure measurement period and cycles (optional)
LVTSMONCTL2 0x000101AD TMU_BASE+0x0008
9 Trigger events setting (optional) LVTSMONINT User-defined TMU_BASE+0x000C
Enable periodical measurement for the thermal
10 LVTSMONCTL0 0x0000020F TMU_BASE+0x0000
sensors
LVTSMSR0 TMU_BASE+0x0090
LVTSMSR1 TMU_BASE+0x0094
11 Read thermal sensors measurement results Read only
LVTSMSR2 TMU_BASE+0x0098
LVTSMSR3 TMU_BASE+0x00B8

3.14 Boot Flash

The device supports the following boot flash:

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 eMMC
 SPI NOR

Table 3-209 presents the boot flash selection options.

Table 3-209 Boot Flash Selection

AUD_SYNC_MOSI Boot Flash
0 eMMC (default)
1 SPI NOR

3.15 ROM Power Down Mode

After system boot, ROM can be powered down and prevented from any probe of ROM content.

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4 Ball Map

Figure 4-1 presents simplified diagram of the location of the balls on the package.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
A 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
B 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
D 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
E 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
F 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
G 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
H 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
J 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
K 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
M 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
N 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
P 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
T 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
U 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
V 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
W 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Y 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AA 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AB 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AC 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AD 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AE 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AF 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AG 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AH 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AJ 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AK 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AL 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AM 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AN 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AP 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AR 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AT 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
AU 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

3 EMI 3 Storage 3 Display

3 Audio 3 Connectivity 3 Image
3 Ground 3 System 3 Power Supply
3 Reserved

Figure 4-1 Ball Map Diagram

For detailed information about package outlines, thermal characteristics, and markings, see Chapter 7 Package
Information.

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4.1 Quadrant Pinout

Figure 4-2 shows a top view mapping of the package quadrants.

Figure 4-2 Package Quadrants Mapping

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Table 4-1 shows pin mapping on the top left part of the package.

Table 4-1 Ball Map-Top Left

1 2 3 4 5 6 7 8 9 10 11 12 13

A DUMMY DUMMY EMI2_TP EMI2_DQ8 DVSS DVSS EMI2_DMI1 EMI2_DQ15 EMI2_DQ0 EMI2_DMI0

B DUMMY EMI2_EXTR DVSS DVSS DVSS EMI2_DQS1_T DVSS EMI2_DQ14 DVSS EMI2_DQ7 DVSS EMI2_DQ1 DVSS

C DVSS MSDC1_DAT3 MSDC1_DAT2 DVSS EMI2_DQS1_C DVSS DVSS EMI2_DQ12 DVSS DVSS DVSS DVSS

D MSDC1_DAT1 MSDC1_DAT0 MSDC1_CMD MSDC1_CLK DVSS DVSS EMI2_DQ13 EMI2_DQ10 DVSS DVSS DVSS DVSS EMI2_DQ3

E DVDD18_MSDC1 SPIM2_MISO CMMPDN1 CMMCLK0 CMMCLK1 DVSS EMI2_DQ9 DVSS EMI2_DQ11 DVSS EMI2_DQS0_C DVSS EMI2_DQ5

F SPIM2_MOSI CMMCLK2 SCL5 SDA5 DVSS DVSS DVSS DVSS EMI2_DQS0_T DVSS DVSS

G SPIM2_CLK SPIM2_CSB CMMRST0 CMMPDN0 CMMRST1 SDA6 DVDD28_MSDC1 DVSS DVSS DVSS DVSS DVSS EMI2_DQ2

H DVSS DVSS DVSS SCL6 DVSS DVSS DVSS DVSS DVSS DVSS

J DVSS CSI1A_L1P_T0C CSI1A_L1N_T1A CSI1A_L0N_T0B CSI1A_L0P_T0A DVSS DVSS DVSS DVSS DVSS DVDD18_IORT DVSS AVDD12_EMI2

K CSI1B_L0N_T0B DVSS CSI1B_L0P_T0A CSI1A_L2N_T1C CSI1A_L2P_T1B DVSS DVSS DVSS DVSS AVDD075_EMI2

L CSI1B_L1P_T0C CSI1B_L1N_T1A DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVDD_CORE

M DVSS DVSS CSI0A_L2P_T1B DVSS DVSS AVDD12_CSI1 DVSS DVSS DVSS

N DVSS CSI0A_L0P_T0A CSI0A_L0N_T0B CSI0A_L1P_T0C CSI0A_L1N_T1A CSI0A_L2N_T1C DVSS DVSS DVSS

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Table 4-2 shows pin mapping on the top center part of the package.

Table 4-2 Ball Map-Top Center

14 15 16 17 18 19 20 21 22 23 24 25

A EMI2_CS1 EMI2_CKE0 EMI3_CKE0 EMI3_CS1 EMI3_DMI0

B EMI2_DQ6 DVSS EMI2_CA0 EMI2_CKE1 EMI3_CKE1 EMI3_CA0 DVSS EMI3_DQ6 DVSS

C DVSS DVSS EMI2_CA1 DVSS EMI2_CS0 DVSS EMI3_CS0 DVSS EMI3_CA1 DVSS DVSS DVSS

D DVSS DVSS DVSS EMI2_CA5 DVSS NC DVSS DVSS EMI3_CA3 DVSS DVSS EMI3_DQ5

E DVSS DVSS DVSS EMI2_CA4 DVSS DVSS DVSS DVSS EMI3_CA4 DVSS DVSS EMI3_DQ3

F DVSS EMI2_CA2 EMI2_CA3 DVSS EMI2_CK_T DVSS EMI3_CK_T DVSS DVSS NC DVSS DVSS

G EMI2_DQ4 DVSS NC DVSS EMI2_CK_C DVSS EMI3_CK_C DVSS EMI3_CA5 EMI3_CA2 DVSS EMI3_DQ4

H DVSS DVSS DVSS DVSS DVSS NC DVSS DVSS DVSS DVSS DVSS DVSS

J DVSS AVDDQ_EMI2 DVSS AVDDQ_EMI2 DVSS AVDDQ_EMI2 DVSS AVDDQ_EMI2 DVSS AVDDQ_EMI2 AVDD18_EMI2 DVSS

K AVDDQ_EMI2 AVDD2_EMI2 AVDDQ_EMI2 AVDD2_EMI2 AVDDQ_EMI2 AVDD2_EMI2 AVDDQ_EMI2 AVDD2_EMI2 AVDDQ_EMI2 AVDD2_EMI2 AVDD075_EMI2 DVSS

L DVDD_PROC_B DVSS AVDD18_PROC DVSS

M DVDD_MM DVSS DVDD_SRAM_MM DVSS DVDD_MM DVDD_MM DVDD_CORE DVDD_PROC_B DVDD_SRAM_PROC_B DVSS DVSS DVDD_PROC_B

N DVDD_MM DVDD_MM DVSS DVDD_MM DVSS DVDD_MM DVDD_CORE DVDD_PROC_B DVDD_PROC_B DVSS DVDD_PROC_B DVDD_PROC_B

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Table 4-3 shows pin mapping on the top right part of the package.

Table 4-3 Ball Map-Top Right

26 27 28 29 30 31 32 33 34 35 36 37

EMI3_DQ0 EMI3_DQ15 EMI3_DMI1 DVSS EMI3_DQS1_T EMI3_DQ9 DVSS DUMMY DUMMY A

EMI3_DQ1 DVSS EMI3_DQ7 DVSS EMI3_DQ14 DVSS DVSS EMI3_DQS1_C DVSS DVSS EMI2_RESET_N DUMMY B

DVSS EMI3_DQ2 DVSS EMI3_DQ11 DVSS DVSS EMI3_DQ13 DVSS EMI3_DQ8 DVSS DVSS DVDD18_IOEMMC C

DVSS DVSS DVSS DVSS DVSS DVSS DVSS EMMC_DAT0 DVSS EMMC_DAT4 EMMC_DAT2 EMMC_DAT7 D

DVSS EMI3_DQS0_T DVSS EMI3_DQ12 EMI3_DQ10 DVSS EMMC_DAT3 DVSS EMMC_RSTB EMMC_DSL EMMC_DAT6 E

DVSS EMI3_DQS0_C DVSS DVSS DVSS DVSS EMMC_CLK EMMC_CMD DVSS DVSS EMMC_DAT1 EMMC_DAT5 F

DVSS DVSS DVSS DVSS I2SO2_D2 I2SO2_D1 I2SIN_D2 I2SIN_D1 DVSS DVSS I2SIN_MCK DVDD18_IOLT G

DVSS DVDD18_VQPS DVSS DVSS DVSS KPCOL0 I2SO2_D3 I2SO2_BCK I2SO2_MCK I2SIN_D3 I2SIN_BCK H

DVSS DVSS DVSS DVSS KPROW0 KPCOL1 I2SO2_D0 I2SO2_WS I2SIN_WS I2SIN_D0 J

SPMI_M_
DVDD_PROC_B DVDD_PROC_B DVDD_PROC_B DVSS KPROW1 PWRAP_SPI_CK PWRAP_SPI_CSN SPMI_M_SCL PMIC_WATCHDOG SCL4 SDA4 K
SDA
PWRAP_SPI_ PMIC_
DVDD_PROC_B DVDD_PROC_B DVDD_PROC_B DVSS PWRAP_SPI_MI PMIC_SRCLKENA1 SDA1 L
MO SRCLKENA0
AUD_DAT_ AUD_SYNC_
DVDD_PROC_B DVDD_PROC_B DVDD_PROC_B DVSS SCP_VREQ_VAO AUD_DAT_MISO1 AUD_CLK_MOSI AUD_DAT_MOSI0 SCL1 DVSS M
MISO0 MOSI
DVDD_SRAM_
DVSS DVSS DVSS DMIC1_CLK DMIC1_DAT AUD_DAT_MOSI1 DMIC2_CLK DVSS PMIC_RTC32K_CK N
PROC_B

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Table 4-4 shows pin mapping on the middle left part of the package.

Table 4-4 Ball Map-Middle Left

1 2 3 4 5 6 7 8 9 10 11 12 13

P CSI0B_L0N_T0B CSI0B_L0P_T0A CSI0B_L1P_T0C CSI0B_L1N_T1A CSI0B_L2P_T1B CSI0B_L2N_T1C DVSS AVDD12_CSI0 DVSS DVSS DVSS DVSS

DVDD_SRAM
R DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS
_MM

T JTDO JTRST DVSS JTDI JTCK JTMS SPIM1_MISO SPIM1_MOSI SPIM1_CSB SPIM1_CLK SPIM0_CLK DVSS

U UART0_TXD UART0_RXD UART2_TXD UART2_RXD SPIM0_MIO2 SPIM0_MIO3 DVDD28_IODPI GPIO01 DVDD_CORE DVDD_CORE

AVDD18_
V UART1_TXD UART1_RXD GPIO09 GPIO10 SPIM0_CSB SPIM0_MOSI SPIM0_MISO DVSS
PLLGP34
AVDD18_
W SDA3 SCL3 GPIO06 GPIO07 GPIO08 SDA0 GPIO05 GPIO11 DVSS
PLLGP34

Y SCL2 SCL0 DSI1_DSI_TE GPIO02 GPIO03 GPIO04 DSI0_LCM_RST GPIO00 DISP_PWM1 DVDD_APU

AA PCIE_CLKREQ_N SDA2 PCIE_PERESET_N PCIE_WAKE_N DPI_D11 DPI_D12 DSI0_DSI_TE DPI_D5 DISP_PWM0 DVDD18_IORM DSI1_LCM_RST DVDD_APU

DVDD_SRAM
AB DPI_CK DPI_DE DPI_D4 DPI_D15 DPI_D9 DPI_D8 DPI_D7 DPI_D2 DPI_D0 DVSS
_APU
DVDD_SRAM
AC DPI_D3 DPI_D10 DPI_D13 DPI_D14 DPI_D6 DPI_D1 DVSS
_GPU

AD DVDD18_IODPI DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DPI_VSYNC DPI_HSYNC DVSS DVDD_GPU

AVDD12_ AVDD075_DRV
AE AUXIN3 AUXIN2 AUXIN4 AUXIN5 AUXIN0 REFP DVSS DVSS AVDD18_DSI DVSS DVDD_GPU
AUXADC _DSI

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Table 4-5 shows pin mapping on the middle center part of the package.

Table 4-5 Ball Map-Middle Center

14 15 16 17 18 19 20 21 22 23 24 25

P DVDD_MM DVDD_CORE DVSS DVDD_MM DVSS DVDD_MM DVDD_MM DVSS DVSS DVSS DVDD_PROC_L DVSS

DVDD_SRAM_
R DVDD_MM DVDD_CORE DVSS DVDD_MM DVSS DVDD_MM DVDD_MM DVDD_PROC_L DVSS DVSS DVDD_PROC_L
PROC_L

T DVDD_MM DVDD_MM DVDD_MM DVDD_MM DVSS DVDD_CORE DVDD_PROC_L DVSS DVSS DVDD_PROC_L

TN_
U DVDD_CORE DVDD_CORE DVDD_CORE DVDD_CORE AVDD12_PLLGP1 DVDD_CORE DVSS DVDD_PROC_L DVSS DVDD_PROC_L DVDD_PROC_L
APPLLGP
AVDD12_ DVDD_SRAM_
V DVSS DVDD_APU DVDD_CORE DVDD_CORE TP_APPLLGP AVDD18_PLLGP1 DVSS DVDD_PROC_L DVSS DVSS
PLLGP34 PROC_L
AVDD12_
W DVSS DVDD_APU AVDD18_APU DVSS DVDD_CORE DVDD_CORE DVSS DVSS DVSS DVDD_PROC_L DVSS
PLLGP34

Y DVDD_APU DVSS DVDD_APU DVDD_APU DVSS DVDD_CORE DVDD_CORE DVSS DVDD_SRAM_CORE DVDD_CORE DVDD_CORE DVDD_CORE

AA DVDD_APU DVSS DVDD_APU DVDD_APU DVSS DVDD_CORE DVDD_CORE DVSS DVSS DVDD_CORE DVDD_CORE DVSS

AB DVDD_APU DVSS DVDD_APU DVSS DVSS DVDD_CORE DVDD_CORE DVSS DVSS DVDD_CORE DVDD_CORE DVSS

AC DVDD_GPU DVDD_GPU AVDD12_PLLGP2 AVDD18_PLLGP2 DVSS DVDD_CORE DVDD_CORE DVSS DVSS DVDD_CORE DVDD_CORE DVSS

AD DVDD_GPU DVDD_GPU DVDD_GPU DVSS DVSS DVDD_ADSP DVDD_ADSP DVSS DVDD_SRAM_CORE DVDD_CORE DVDD_CORE DVSS

AE DVDD_GPU DVDD_GPU DVDD_GPU DVSS DVSS DVDD_ADSP DVDD_ADSP DVSS DVSS DVDD_CORE DVDD_CORE

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Table 4-6 shows pin mapping on the Middle Right part of the package.

Table 4-6 Ball Map-Middle Right

26 27 28 29 30 31 32 33 34 35 36 37
DMIC1_DAT_ DMIC2_DAT_ USB0_DRV_
DVSS DVSS DVSS DVSS USB2_IDDIG USB2_DRV_VBUS DMIC2_DAT USB0_VBUS_VALID P
R R VBUS
USB2_VBUS_
DVDD_PROC_L DVDD_PROC_L DVSS DVSS GPIO12 USB1_DRV_VBUS USB1_IDDIG USB0_IDDIG DVDD18_IOLT R
VALID

DVDD_PROC_L DVDD_PROC_L DVDD_PROC_L DVSS GPIO13 GPIO14 SYSRSTB USB1_VBUS_VALID TESTMODE DVSS DVSS DVSS T

DVDD_PROC_L DVDD_PROC_L AVDD18_USB_P2 AVDD33_USB_P2 DVSS DVSS GPIO15 AVDD33_USB_P0 DVSS DVSS USB_DM_P1 USB_DP_P1 U

DVSS DVDD_PROC_L DVSS DVSS DVSS AVDD33_USB_P1 DVSS USB_DP_P2 USB_DM_P2 DVSS V

AVDD18_USB_P0 AVDD12_USB_P0 DVSS USB_DM_P0 USB_DP_P0 DVSS DVSS DVSS SSUSB_RXN SSUSB_RXP W

DVSS AVDD12_USB_P1 AVDD12_USB_P2 DVSS DVSS DVSS SSUSB_TXP SSUSB_TXN DVSS DVSS Y

DVDD28_
DVSS DVSS AVDD18_USB_P1 DVSS DVSS DVSS GPIO17 AA
MSDC2
DVDD18_
DVSS DVSS DVSS PCM_DI GPIO16 DPTX_HPD HDMITX_PWR5V MSDC2_DAT3 MSDC2_DAT2 AB
MSDC2

DVSS AVDD12_SSUSB AVDD18_SSUSB PCM_DO PCM_SYNC HDMITX_HTPLG HDMITX_CEC MSDC2_CMD AC

MSDC2_
DVSS AVDD12_CKSQ AVDD18_CKSQ PCM_CLK DVDD18_IOLM HDMITX_SCL HDMITX_SDA DVSS MSDC2_CLK MSDC2_DAT0 AD
DAT1

DVSS DVSS DVSS DVSS DVSS DVSS DVSS X26M_IN DVSS DVSS AE

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Table 4-7 shows pin mapping on the Bottom Left part of the package.

Table 4-7 Ball Map-Bottom Left

AF AVDD18_AUXADC AUXIN1 DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVDD_SRAM_GPU

AG DVSS DSI0_D0P_T0C DSI0_D2N_T0B DSI0_D2P_T0A DVSS DVSS DVSS

AH DVSS DSI0_D3N DSI0_D1N_T2B DSI0_D1P_T2A DSI0_D0N_T1A DSI0_CKP_T1B DSI0_CKN_T1C DVSS DVSS AVDD12_DSI AVDD18_PCIE DVSS

AJ DSI0_D3P_T2C DVSS DVSS DVSS DVSS DVSS DVSS AVDD12_PCIE DVSS DVSS

AK DSI1_D0N_T1A DSI1_CKN_T1C DSI1_CKP_T1B DSI1_D3N DVSS DVSS DVSS DVSS DVSS

AL DVSS DVSS DSI1_D2P_T0A DSI1_D2N_T0B DSI1_D0P_T0C DSI1_D1N_T2B DSI1_D1P_T2A DSI1_D3P_T2C DVSS DVSS DVSS DVSS EMI1_DQ4

AM PCIE_LN0_TXP PCIE_LN0_TXN DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS EMI1_DQS0_C DVSS DVSS

AN DVSS PCIE_CKN PCIE_CKP DVSS DVSS DVSS EMI1_DQ10 EMI1_DQ12 DVSS EMI1_DQS0_T DVSS EMI1_DQ3

AP PCIE_LN0_RXN PCIE_LN0_RXP DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS EMI1_DQ5

AR DVSS EMI0_TP EMI1_DQ8 DVSS EMI1_DQ13 DVSS DVSS EMI1_DQ11 DVSS EMI1_DQ2 DVSS DVSS

AT DUMMY EMI0_EXTR DVSS DVSS EMI1_DQS1_C DVSS DVSS EMI1_DQ14 DVSS EMI1_DQ7 DVSS EMI1_DQ1 DVSS

AU DUMMY DUMMY DVSS EMI1_DQ9 EMI1_DQS1_T DVSS EMI1_DMI1 EMI1_DQ15 EMI1_DQ0 EMI1_DMI0

1 2 3 4 5 6 7 8 9 10 11 12 13

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Table 4-8 shows pin mapping on the Bottom Center part of the package.

Table 4-8 Ball Map-Bottom Center

AF DVDD_GPU DVDD_GPU DVDD_GPU DVDD_GPU DVSS DVDD_ADSP DVDD_ADSP DVSS DVDD_SRAM_CORE DVDD_CORE DVDD_CORE

AG DVDD_CORE

AH AVDD075_EMI0 AVDD2_EMI0 AVDDQ_EMI0 AVDD2_EMI0 AVDDQ_EMI0 AVDD2_EMI0 AVDDQ_EMI0 AVDD2_EMI0 AVDDQ_EMI0 AVDD2_EMI0 AVDD075_EMI0 AVDD18_EMI0

AJ AVDD12_EMI0 AVDDQ_EMI0 DVSS AVDDQ_EMI0 DVSS AVDDQ_EMI0 DVSS AVDDQ_EMI0 DVSS AVDDQ_EMI0 AVDDQ_EMI0 DVSS

AK DVSS DVSS DVSS DVSS DVSS NC DVSS DVSS DVSS DVSS DVSS DVSS

AL DVSS EMI1_CA2 EMI1_CA5 DVSS EMI1_CK_C DVSS EMI0_CK_C DVSS NC DVSS EMI0_DQ4 EMI0_DQ2

AM DVSS NC DVSS DVSS EMI1_CK_T DVSS EMI0_CK_T DVSS EMI0_CA3 EMI0_CA2 DVSS DVSS

AN DVSS DVSS EMI1_CA4 DVSS DVSS DVSS DVSS EMI0_CA4 DVSS DVSS DVSS EMI0_DQ5

AP DVSS DVSS EMI1_CA3 DVSS DVSS NC DVSS EMI0_CA5 DVSS DVSS DVSS EMI0_DQ3

AR DVSS DVSS EMI1_CA1 DVSS EMI1_CS0 DVSS EMI0_CS0 DVSS EMI0_CA1 DVSS DVSS DVSS

AT EMI1_DQ6 DVSS EMI1_CA0 EMI1_CKE1 EMI0_CKE1 EMI0_CA0 DVSS EMI0_DQ6 DVSS

AU EMI1_CS1 EMI1_CKE0 EMI0_CKE0 EMI0_CS1 EMI0_DMI0

14 15 16 17 18 19 20 21 22 23 24 25

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Table 4-9 shows pin mapping on the Bottom Right part of the package.

Table 4-9 Ball Map-Bottom Right

DVSS DVSS DVSS DVSS DVSS EDP_LN1_TXN EDP_LN1_TXP DVSS DVSS DVSS EDPAUXP EDPAUXN AF

AVDD18_EDPTX AVDD12_EDPTX DVSS EDP_LN0_TXN EDP_LN0_TXP DVSS DVSS DVSS DVSS DP_LN0_TXP AG

AVDD18_DPTX DVSS DVSS DP_LN1_TXN DP_LN1_TXP DVSS DVSS DP_LN0_TXN AH

DVSS DVSS DVSS AVDD12_DPTX DVSS DVSS DVSS DP_LN2_TXN DP_LN2_TXP DVSS DPAUXP DPAUXN AJ

DVSS DVSS DVSS DVSS DVSS DP_LN3_TXN DP_LN3_TXP DVSS DVSS HDMITX21_CH2_P AK

AVDD12_ AVDD18_ HDMITX21_CH2_

DVSS DVSS DVSS DVSS DVSS DVSS AL
HDMITX21 HDMITX21 M
HDMITX21_CH1_ HDMITX21_CH1_
DVSS EMI0_DQS0_T DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS AM
P M
HDMITX21_CH0_
DVSS EMI0_DQS0_C DVSS EMI0_DQ11 DVSS EMI0_DQ9 DVSS DVSS HDMITX21_CH0_P AN
M

DVSS DVSS DVSS DVSS EMI0_DQ10 EMI0_DQ13 DVSS DVSS DVSS DVSS DVSS AP

HDMITX21_CLK_ HDMITX21_CLK_
DVSS DVSS DVSS EMI0_DQ12 DVSS DVSS EMI0_DQS1_C DVSS AR
P M

EMI0_DQ1 DVSS EMI0_DQ7 DVSS EMI0_DQ14 DVSS EMI0_DQS1_T DVSS DVSS DVSS DVSS DUMMY AT

EMI0_DQ0 EMI0_DQ15 EMI0_DMI1 DVSS DVSS EMI0_DQ8 EMI0_RESET_N DUMMY DUMMY AU

26 27 28 29 30 31 32 33 34 35 36 37

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4.2 Pin Characteristics

Table 4-10 describes the pin characteristics and the multiplexed signals on each ball.

Table 4-10 Pin Characteristics

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO0 DIO 0
TP_GPIO0_AO DIO 1
SPIM5_CSB DO 2
GPIO00 Y10 UTXD1 DO 3 0 DVDD18_IORM OFF I
DMIC3_CLK DO 4
I2SIN_MCK DIO 5
I2SO2_MCK DO 6
GPIO1 DIO 0
TP_GPIO1_AO DIO 1
SPIM5_CLK DO 2
GPIO01 U10 URXD1 DI 3 0 DVDD18_IORM OFF I
DMIC3_DAT DI 4
I2SIN_BCK DIO 5
I2SO2_BCK DIO 6
GPIO2 DIO 0
TP_GPIO2_AO DIO 1
SPIM5_MOSI DIO 2
GPIO02 Y6 URTS1 DO 3 0 DVDD18_IORM OFF I
DMIC3_DAT_R DI 4
I2SIN_WS DIO 5
I2SO2_WS DIO 6

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO3 DIO 0
TP_GPIO3_AO DIO 1
SPIM5_MISO DIO 2
GPIO03 Y7 UCTS1 DI 3 0 DVDD18_IORM OFF I
DMIC4_CLK DO 4
I2SIN_D0 DI 5
I2SO2_D0 DO 6
GPIO4 DIO 0
TP_GPIO4_AO DIO 1
SPDIF_IN2 DI 2
GPIO04 Y8 I2SO1_MCK DO 3 0 DVDD18_IORM OFF I
DMIC4_DAT DI 4
I2SIN_D1 DI 5
I2SO2_D1 DO 6
GPIO5 DIO 0
TP_GPIO5_AO DIO 1
SPDIF_IN1 DI 2
GPIO05 W7 I2SO1_BCK DO 3 0 DVDD18_IORM OFF I
DMIC4_DAT_R DI 4
I2SIN_D2 DI 5
I2SO2_D2 DO 6
GPIO6 DIO 0
TP_GPIO6_AO DIO 1
SPDIF_IN0 DI 2
GPIO06 W3 I2SO1_WS DO 3 0 DVDD18_IORM OFF I
DMIC1_CLK DO 4
I2SIN_D3 DI 5
I2SO2_D3 DO 6

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO7 DIO 0
TP_GPIO7_AO DIO 1
SPIM3_CSB DO 2
GPIO07 W4 TDMIN_MCK DIO 3 0 DVDD18_IORM OFF I
DMIC1_DAT DI 4
CMVREF0 DO 5
CLKM0 DO 6
GPIO8 DIO 0
TP_GPIO0_AO DIO 1
SPIM3_CLK DO 2
GPIO08 W5 TDMIN_BCK DIO 3 0 DVDD18_IORM OFF I
DMIC1_DAT_R DI 4
CMVREF1 DO 5
CLKM1 DO 6
GPIO9 DIO 0
TP_GPIO1_AO DIO 1
SPIM3_MOSI DIO 2
GPIO09 V4 TDMIN_LRCK DIO 3 0 DVDD18_IORM OFF I
DMIC2_CLK DO 4
CMFLASH0 DO 5
PWM_0 DO 6
GPIO10 DIO 0
TP_GPIO2_AO DIO 1
SPIM3_MISO DIO 2
GPIO10 V5 TDMIN_DI DI 3 0 DVDD18_IORM OFF I
DMIC2_DAT DI 4
CMFLASH1 DO 5
PWM_1 DO 6

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 MT8390
IoT APPLICATION PROCESSOR
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Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO11 DIO 0
TP_GPIO3_AO DIO 1
SPDIF_OUT DO 2
GPIO11 W8 0 DVDD18_IORM OFF I
I2SO1_D0 DO 3
DMIC2_DAT_R DI 4
CMVREF6 DO 6
GPIO12 DIO 0
TP_GPIO4_AO DIO 1
GPIO12 R31 0 DVDD18_IOLT OFF I
SPIM4_CSB DO 2
HDMITX20_HTPLG DI 7
GPIO13 DIO 0
TP_GPIO5_AO DIO 1
GPIO13 T30 0 DVDD18_IOLT OFF I
SPIM4_CLK DO 2
HDMITX20_CEC DIO 7
GPIO14 DIO 0
TP_GPIO6_AO DIO 1
GPIO14 T31 0 DVDD18_IOLT OFF I
SPIM4_MOSI DIO 2
HDMITX20_SCL DIO 7
GPIO15 DIO 0
TP_GPIO7_AO DIO 1
GPIO15 U32 0 DVDD18_IOLT OFF I
SPIM4_MISO DIO 2
HDMITX20_SDA DIO 7
GPIO16 DIO 0
TP_GPIO0_AO DIO 1
GPIO16 AB32 0 DVDD18_IOLM OFF I
UTXD3 DO 2
HDMITX20_PWR5V DO 7

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 MT8390
IoT APPLICATION PROCESSOR
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Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO17 DIO 0
TP_GPIO1_AO DIO 1
URXD3 DI 2
GPIO17 AA35 0 DVDD18_IOLM OFF I
CMFLASH2 DO 3
EDP_TX_HPD DI 4
CMVREF7 DO 6
GPIO18 DIO 0
TP_GPIO2_AO DIO 1
CMFLASH0 DO 2
CMMPDN0 G4 CMVREF4 DO 3 0 DVDD18_IORT OFF I
TDMIN_MCK DIO 4
UTXD1 DO 5
TP_UTXD1_AO DO 6
GPIO19 DIO 0
TP_GPIO3_AO DIO 1
CMFLASH1 DO 2
CMMRST0 G3 CMVREF5 DO 3 0 DVDD18_IORT OFF I
TDMIN_BCK DIO 4
URXD1 DI 5
TP_URXD1_AO DI 6
GPIO20 DIO 0
TP_GPIO4_AO DIO 1
CMFLASH2 DO 2
CMMPDN1 E3 CLKM2 DO 3 0 DVDD18_IORT OFF I
TDMIN_LRCK DIO 4
URTS1 DO 5
TP_URTS1_AO DO 6

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 MT8390
IoT APPLICATION PROCESSOR
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Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO21 DIO 0
TP_GPIO5_AO DIO 1
CMFLASH3 DO 2
CMMRST1 G5 CLKM3 DO 3 0 DVDD18_IORT OFF I
TDMIN_DI DI 4
UCTS1 DI 5
TP_UCTS1_AO DI 6
GPIO22 DIO 0
CMMCLK0 E4 CMMCLK0 DO 1 0 DVDD18_IORT OFF I
TP_GPIO6_AO DIO 5
GPIO23 DIO 0
CMMCLK1 DO 1
CMMCLK1 E5 PWM_2 DO 3 0 DVDD18_IORT OFF I
TP_GPIO7_AO DIO 5
DP_TX_HPD DI 6
GPIO24 DIO 0
CMMCLK2 DO 1
CMMCLK2 F4 0 DVDD18_IORT OFF I
PWM_3 DO 3
EDP_TX_HPD DI 6
GPIO25 DIO 0
LCM_RST DO 1
DSI0_LCM_RST Y9 0 DVDD18_IORM OFF I
LCM1_RST DO 2
DP_TX_HPD DI 3
GPIO26 DIO 0
DSI_TE DI 1
DSI0_DSI_TE AA7 0 DVDD18_IORM OFF I
DSI1_TE DI 2
EDP_TX_HPD DI 3

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 MT8390
IoT APPLICATION PROCESSOR
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Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO27 DIO 0
LCM1_RST DO 1
LCM_RST DO 2
DSI1_LCM_RST AA11 0 DVDD18_IORM OFF I
DP_TX_HPD DI 3
CMVREF2 DO 4
PWM_2 DO 6
GPIO28 DIO 0
DSI1_TE DI 1
DSI_TE DI 2
DSI1_DSI_TE Y5 0 DVDD18_IORM OFF I
EDP_TX_HPD DI 3
CMVREF3 DO 4
PWM_3 DO 6
GPIO29 DIO 0
DISP_PWM0 AA9 DISP_PWM0 DO 1 0 DVDD18_IORM OFF I
DISP_PWM1 DO 2
GPIO30 DIO 0
DISP_PWM1 DO 1
DISP_PWM1 Y11 DISP_PWM0 DO 2 0 DVDD18_IORM OFF I
CMFLASH3 DO 3
PWM_1 DO 4
GPIO31 DIO 0
UTXD0 DO 1
UART0_TXD U2 TP_UTXD1_AO DO 2 1 DVDD18_IORM PU OH
TP_UTXD2_AO DO 4
SSPM_UTXD_AO DO 7

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 MT8390
IoT APPLICATION PROCESSOR
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Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO32 DIO 0
URXD0 DI 1
UART0_RXD U3 TP_URXD1_AO DI 2 1 DVDD18_IORM PU I
TP_URXD2_AO DI 4
SSPM_URXD_AO DI 7
GPIO33 DIO 0
UTXD1 DO 1
UART1_TXD V1 0 DVDD18_IORM OFF I
URTS2 DO 2
TP_UTXD1_AO DO 4
GPIO34 DIO 0
URXD1 DI 1
UART1_RXD V2 0 DVDD18_IORM OFF I
UCTS2 DI 2
TP_URXD1_AO DI 4
GPIO35 DIO 0
UTXD2 DO 1
UART2_TXD U4 URTS1 DO 2 0 DVDD18_IORM OFF I
TP_URTS1_AO DO 4
TP_UTXD2_AO DO 5
GPIO36 DIO 0
URXD2 DI 1
UART2_RXD U5 UCTS1 DI 2 0 DVDD18_IORM OFF I
TP_UCTS1_AO DI 4
TP_URXD2_AO DI 5
JTMS T6 GPIO37 DIO 0 1 DVDD18_IORM PU I
JTCK T5 GPIO38 DIO 0 1 DVDD18_IORM OFF I
JTDI T4 GPIO39 DIO 0 1 DVDD18_IORM PU I
JTDO T1 GPIO40 DIO 0 1 DVDD18_IORM OFF OL
JTRST T2 GPIO41 DIO 0 1 DVDD18_IORM PU I

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 MT8390
IoT APPLICATION PROCESSOR
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Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO42 DIO 0
KPCOL0 H31 1 DVDD18_IOLT PU I
KPCOL0 DIO 1
GPIO43 DIO 0
KPCOL1 DIO 1
KPCOL1 J31 0 DVDD18_IOLT OFF I
DP_TX_HPD DI 2
CMFLASH2 DO 3
GPIO44 DIO 0
KPROW0 J30 1 DVDD18_IOLT OFF OL
KPROW0 DIO 1
GPIO45 DIO 0
KPROW1 DIO 1
KPROW1 K30 EDP_TX_HPD DI 2 0 DVDD18_IOLT OFF I
CMFLASH3 DO 3
I2SIN_MCK DIO 4
GPIO46 DIO 0
DP_TX_HPD DI 1
DPTX_HPD AB33 0 DVDD18_IOLM OFF I
PWM_0 DO 2
VBUSVALID_2P DI 3
GPIO47 DIO 0
PCIE_WAKE_N AA4 0 DVDD18_IORM OFF I
WAKEN DI 1
GPIO48 DIO 0
PCIE_PERESET_N AA3 0 DVDD18_IORM OFF I
PERSTN DO 1
GPIO49 DIO 0
PCIE_CLKREQ_N AA1 0 DVDD18_IORM OFF I
CLKREQN DIO 1
GPIO50 DIO 0
HDMITX_PWR5V AB34 HDMITX20_PWR5V DO 1 0 DVDD18_IOLM OFF I
IDDIG_1P DI 3

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO51 DIO 0
HDMITX20_HTPLG DI 1
HDMITX_HTPLG AC32 0 DVDD18_IOLM OFF I
EDP_TX_HPD DI 2
USB_DRVVBUS_1P DO 3
GPIO52 DIO 0
HDMITX_CEC AC33 HDMITX20_CEC DIO 1 0 DVDD18_IOLM OFF I
VBUSVALID_1P DI 3
GPIO53 DIO 0
HDMITX_SCL AD32 HDMITX20_SCL DIO 1 0 DVDD18_IOLM OFF I
IDDIG_2P DI 3
GPIO54 DIO 0
HDMITX_SDA AD33 HDMITX20_SDA DIO 1 0 DVDD18_IOLM OFF I
USB_DRVVBUS_2P DO 3
GPIO55 DIO 0
SCL0 DIO 1
SCL0 Y4 1 DVDD18_IORM PU I
SCP_SCL0 DIO 2
SCP_SCL1 DIO 3
GPIO56 DIO 0
SDA0 DIO 1
SDA0 W6 1 DVDD18_IORM PU I
SCP_SDA0 DIO 2
SCP_SDA1 DIO 3
GPIO57 DIO 0
SCL1 M36 1 DVDD18_IOLT PU I
SCL1 DIO 1
GPIO58 DIO 0
SDA1 L36 1 DVDD18_IOLT PU I
SDA1 DIO 1

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO59 DIO 0
SCL2 DIO 1
SCL2 Y2 1 DVDD18_IORM PU I
SCP_SCL0 DIO 2
SCP_SCL1 DIO 3
GPIO60 DIO 0
SDA2 DIO 1
SDA2 AA2 1 DVDD18_IORM PU I
SCP_SDA0 DIO 2
SCP_SDA1 DIO 3
GPIO61 DIO 0
SCL3 DIO 1
SCL3 W2 1 DVDD18_IORM PU I
SCP_SCL0 DIO 2
SCP_SCL1 DIO 3
GPIO62 DIO 0
SDA3 DIO 1
SDA3 W1 1 DVDD18_IORM PU I
SCP_SDA0 DIO 2
SCP_SDA1 DIO 3
GPIO63 DIO 0
SCL4 K36 1 DVDD18_IOLT PU I
SCL4 DIO 1
GPIO64 DIO 0
SDA4 K37 1 DVDD18_IOLT PU I
SDA4 DIO 1
GPIO65 DIO 0
SCL5 DIO 1
SCL5 F5 1 DVDD18_IORT PU I
SCP_SCL0 DIO 2
SCP_SCL1 DIO 3
GPIO66 DIO 0
SDA5 DIO 1
SDA5 F6 1 DVDD18_IORT PU I
SCP_SDA0 DIO 2
SCP_SDA1 DIO 3

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 MT8390
IoT APPLICATION PROCESSOR
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Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO67 DIO 0
SCL6 DIO 1
SCL6 H7 1 DVDD18_IORT PU I
SCP_SCL0 DIO 2
SCP_SCL1 DIO 3
GPIO68 DIO 0
SDA6 DIO 1
SDA6 G6 1 DVDD18_IORT PU I
SCP_SDA0 DIO 2
SCP_SDA1 DIO 3
GPIO69 DIO 0
SPIM0_CSB DO 1
SPIM0_CSB V6 SCP_SPI0_CS DO 2 0 DVDD18_IORM OFF I
DMIC3_CLK DO 3
CMVREF0 DO 5
GPIO70 DIO 0
SPIM0_CLK DO 1
SPIM0_CLK T11 SCP_SPI0_CK DO 2 0 DVDD18_IORM OFF I
DMIC3_DAT DI 3
CMVREF1 DO 5
GPIO71 DIO 0
SPIM0_MOSI DIO 1
SPIM0_MOSI V7 SCP_SPI0_MO DO 2 0 DVDD18_IORM OFF I
DMIC3_DAT_R DI 3
CMVREF2 DO 5
GPIO72 DIO 0
SPIM0_MISO DIO 1
SPIM0_MISO V8 SCP_SPI0_MI DI 2 0 DVDD18_IORM OFF I
DMIC4_CLK DO 3
CMVREF3 DO 5

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO73 DIO 0
SPIM0_MIO2 DIO 1
UTXD3 DO 2
SPIM0_MIO2 U7 0 DVDD18_IORM OFF I
DMIC4_DAT DI 3
CLKM0 DO 4
CMVREF4 DO 5
GPIO74 DIO 0
SPIM0_MIO3 DIO 1
URXD3 DI 2
SPIM0_MIO3 U8 0 DVDD18_IORM OFF I
DMIC4_DAT_R DI 3
CLKM1 DO 4
CMVREF5 DO 5
GPIO75 DIO 0
SPIM1_CSB DO 1
SCP_SPI1_A_CS DO 2
SPIM1_CSB T9 0 DVDD18_IORM OFF I
TDMIN_MCK DIO 3
SCP_SCL0 DIO 4
CMVREF6 DO 5
GPIO76 DIO 0
SPIM1_CLK DO 1
SCP_SPI1_A_CK DO 2
SPIM1_CLK T10 0 DVDD18_IORM OFF I
TDMIN_BCK DIO 3
SCP_SDA0 DIO 4
CMVREF7 DO 5

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO77 DIO 0
SPIM1_MOSI DIO 1
SPIM1_MOSI T8 SCP_SPI1_A_MO DO 2 0 DVDD18_IORM OFF I
TDMIN_LRCK DIO 3
SCP_SCL1 DIO 4
GPIO78 DIO 0
SPIM1_MISO DIO 1
SPIM1_MISO T7 SCP_SPI1_A_MI DI 2 0 DVDD18_IORM OFF I
TDMIN_DI DI 3
SCP_SDA1 DIO 4
GPIO79 DIO 0
SPIM2_CSB DO 1
SCP_SPI2_CS DO 2
SPIM2_CSB G2 I2SO1_MCK DO 3 0 DVDD18_IORT OFF I
UTXD2 DO 4
TP_UTXD2_AO DO 5
PCM_SYNC DIO 6
GPIO80 DIO 0
SPIM2_CLK DO 1
SCP_SPI2_CK DO 2
SPIM2_CLK G1 I2SO1_BCK DO 3 0 DVDD18_IORT OFF I
URXD2 DI 4
TP_URXD2_AO DI 5
PCM_CLK DIO 6

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO81 DIO 0
SPIM2_MOSI DIO 1
SCP_SPI2_MO DO 2
SPIM2_MOSI F2 I2SO1_WS DO 3 0 DVDD18_IORT OFF I
URTS2 DO 4
TP_URTS2_AO DO 5
PCM_DO DO 6
GPIO82 DIO 0
SPIM2_MISO DIO 1
SCP_SPI2_MI DI 2
SPIM2_MISO E2 I2SO1_D0 DO 3 0 DVDD18_IORT OFF I
UCTS2 DI 4
TP_UCTS2_AO DI 5
PCM_DI DI 6
GPIO83 DIO 0
USB0_IDDIG R36 0 DVDD18_IOLT OFF I
IDDIG DI 1
GPIO84 DIO 0
USB0_DRV_VBUS P36 0 DVDD18_IOLT OFF I
USB_DRVVBUS DO 1
GPIO85 DIO 0
USB0_VBUS_VALID P34 0 DVDD18_IOLT OFF I
VBUSVALID DI 1
GPIO86 DIO 0
IDDIG_1P DI 1
UTXD1 DO 2
USB1_IDDIG R34 URTS2 DO 3 0 DVDD18_IOLT OFF I
PWM_2 DO 4
TP_GPIO4_AO DIO 5
AUXIF_ST0 DO 6

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO87 DIO 0
USB_DRVVBUS_1P DO 1
URXD1 DI 2
USB1_DRV_VBUS R33 UCTS2 DI 3 0 DVDD18_IOLT OFF I
PWM_3 DO 4
TP_GPIO5_AO DIO 5
AUXIF_CLK0 DO 6
GPIO88 DIO 0
VBUSVALID_1P DI 1
UTXD2 DO 2
USB1_VBUS_VALID T33 URTS1 DO 3 0 DVDD18_IOLT OFF I
CLKM2 DO 4
TP_GPIO6_AO DIO 5
AUXIF_ST1 DO 6
GPIO89 DIO 0
IDDIG_2P DI 1
URXD2 DI 2
USB2_IDDIG P31 UCTS1 DI 3 0 DVDD18_IOLT OFF I
CLKM3 DO 4
TP_GPIO7_AO DIO 5
AUXIF_CLK1 DO 6
GPIO90 DIO 0
USB2_DRV_VBUS P32 USB_DRVVBUS_2P DO 1 0 DVDD18_IOLT OFF I
UTXD3 DO 2
GPIO91 DIO 0
USB2_VBUS_VALID R30 VBUSVALID_2P DI 1 0 DVDD18_IOLT OFF I
URXD3 DI 2

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO92 DIO 0
PWRAP_SPI_CSN K32 1 DVDD18_IOLT PU OH
PWRAP_SPI0_CSN DO 1
GPIO93 DIO 0
PWRAP_SPI_CK K31 1 DVDD18_IOLT OFF OL
PWRAP_SPI0_CK DO 1
GPIO94 DIO 0
PWRAP_SPI_MO L30 PWRAP_SPI0_MO DIO 1 1 DVDD18_IOLT OFF I
PWRAP_SPI0_MI DIO 2
GPIO95 DIO 0
PWRAP_SPI_MI L31 PWRAP_SPI0_MI DIO 1 1 DVDD18_IOLT OFF I
PWRAP_SPI0_MO DIO 2
GPIO96 DIO 0
PMIC_SRCLKENA0 L33 1 DVDD18_IOLT PU OH
SRCLKENA0 DO 1
GPIO97 DIO 0
PMIC_SRCLKENA1 L34 1 DVDD18_IOLT PU OH
SRCLKENA1 DO 1
GPIO98 DIO 0
SCP_VREQ_VAO M31 0 DVDD18_IOLT OFF I
SCP_VREQ_VAO DO 1
GPIO99 DIO 0
PMIC_RTC32K_CK N37 1 DVDD18_IOLT OFF I
RTC32K_CK DI 1
GPIO100 DIO 0
PMIC_WATCHDOG K34 1 DVDD18_IOLT OFF OL
WATCHDOG DO 1
GPIO101 DIO 0
AUD_CLK_MOSI DO 1
AUD_CLK_MOSI M33 0 DVDD18_IOLT OFF I
I2SO1_MCK DO 2
I2SIN_BCK DIO 3
GPIO102 DIO 0
AUD_SYNC_MOSI DO 1
AUD_SYNC_MOSI M35 0 DVDD18_IOLT OFF I
I2SO1_BCK DO 2
I2SIN_WS DIO 3

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO103 DIO 0
AUD_DAT_MOSI0 DO 1
AUD_DAT_MOSI0 M34 0 DVDD18_IOLT OFF I
I2SO1_WS DO 2
I2SIN_D0 DI 3
GPIO104 DIO 0
AUD_DAT_MOSI1 DO 1
AUD_DAT_MOSI1 N33 0 DVDD18_IOLT OFF I
I2SO1_D0 DO 2
I2SIN_D1 DI 3
GPIO105 DIO 0
AUD_DAT_MISO0 DI 1
AUD_DAT_MISO0 M30 0 DVDD18_IOLT OFF I
VOW_DAT_MISO DI 2
I2SIN_D2 DI 3
GPIO106 DIO 0
AUD_DAT_MISO1 DI 1
AUD_DAT_MISO1 M32 0 DVDD18_IOLT OFF I
VOW_CLK_MISO DI 2
I2SIN_D3 DI 3
GPIO107 DIO 0
I2SIN_MCK DIO 1
SPLIN_MCK DI 2
I2SIN_MCK G36 0 DVDD18_IOLT OFF I
SPDIF_IN0 DI 3
CMVREF4 DO 4
AUXIF_ST0 DO 5
GPIO108 DIO 0
I2SIN_BCK DIO 1
SPLIN_LRCK DI 2
I2SIN_BCK H36 0 DVDD18_IOLT OFF I
DMIC4_CLK DO 3
CMVREF5 DO 4
AUXIF_CLK0 DO 5

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO109 DIO 0
I2SIN_WS DIO 1
SPLIN_BCK DI 2
I2SIN_WS J36 0 DVDD18_IOLT OFF I
DMIC4_DAT DI 3
CMVREF6 DO 4
AUXIF_ST1 DO 5
GPIO110 DIO 0
I2SIN_D0 DI 1
SPLIN_D0 DI 2
I2SIN_D0 J37 0 DVDD18_IOLT OFF I
DMIC4_DAT_R DI 3
CMVREF7 DO 4
AUXIF_CLK1 DO 5
GPIO111 DIO 0
I2SIN_D1 DI 1
I2SIN_D1 G33 SPLIN_D1 DI 2 0 DVDD18_IOLT OFF I
DMIC3_CLK DO 3
SPDIF_OUT DO 4
GPIO112 DIO 0
I2SIN_D2 DI 1
SPLIN_D2 DI 2
I2SIN_D2 G32 0 DVDD18_IOLT OFF I
DMIC3_DAT DI 3
TDMIN_MCK DIO 4
I2SO1_WS DO 5

© 2022-2024 MediaTek Inc. All rights reserved. Page 420 of 469

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO113 DIO 0
I2SIN_D3 DI 1
SPLIN_D3 DI 2
I2SIN_D3 H35 0 DVDD18_IOLT OFF I
DMIC3_DAT_R DI 3
TDMIN_BCK DIO 4
I2SO1_D0 DO 5
GPIO114 DIO 0
I2SO2_MCK H34 I2SO2_MCK DO 1 0 DVDD18_IOLT OFF I
I2SIN_MCK DIO 2
GPIO115 DIO 0
I2SO2_BCK H33 I2SO2_BCK DIO 1 0 DVDD18_IOLT OFF I
I2SIN_BCK DIO 2
GPIO116 DIO 0
I2SO2_WS J34 I2SO2_WS DIO 1 0 DVDD18_IOLT OFF I
I2SIN_WS DIO 2
GPIO117 DIO 0
I2SO2_D0 J33 I2SO2_D0 DO 1 0 DVDD18_IOLT OFF I
I2SIN_D0 DI 2
GPIO118 DIO 0
I2SO2_D1 G31 I2SO2_D1 DO 1 0 DVDD18_IOLT OFF I
I2SIN_D1 DI 2
GPIO119 DIO 0
I2SO2_D2 DO 1
I2SIN_D2 DI 2
I2SO2_D2 G30 0 DVDD18_IOLT OFF I
UTXD3 DO 3
TDMIN_LRCK DIO 4
I2SO1_MCK DO 5

© 2022-2024 MediaTek Inc. All rights reserved. Page 421 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO120 DIO 0
I2SO2_D3 DO 1
I2SIN_D3 DI 2
I2SO2_D3 H32 0 DVDD18_IOLT OFF I
URXD3 DI 3
TDMIN_DI DI 4
I2SO1_BCK DO 5
GPIO121 DIO 0
PCM_CLK DIO 1
SPIM4_CSB DO 2
PCM_CLK AD30 0 DVDD18_IOLM OFF I
SCP_SPI1_B_CS DO 3
TP_UTXD2_AO DO 4
AUXIF_ST0 DO 5
GPIO122 DIO 0
PCM_SYNC DIO 1
SPIM4_CLK DO 2
PCM_SYNC AC31 0 DVDD18_IOLM OFF I
SCP_SPI1_B_CK DO 3
TP_URXD2_AO DI 4
AUXIF_CLK0 DO 5
GPIO123 DIO 0
PCM_DO DO 1
SPIM4_MOSI DIO 2
PCM_DO AC30 0 DVDD18_IOLM OFF I
SCP_SPI1_B_MO DO 3
TP_URTS2_AO DO 4
AUXIF_ST1 DO 5

© 2022-2024 MediaTek Inc. All rights reserved. Page 422 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO124 DIO 0
PCM_DI DI 1
SPIM4_MISO DIO 2
PCM_DI AB31 0 DVDD18_IOLM OFF I
SCP_SPI1_B_MI DI 3
TP_UCTS2_AO DI 4
AUXIF_CLK1 DO 5
GPIO125 DIO 0
DMIC1_CLK DO 1
DMIC1_CLK N30 SPINOR_CK DO 2 0 DVDD18_IOLT OFF I
TDMIN_MCK DIO 3
LVTS_FOUT DO 6
GPIO126 DIO 0
DMIC1_DAT DI 1
DMIC1_DAT N31 SPINOR_CS DO 2 0 DVDD18_IOLT OFF I
TDMIN_BCK DIO 3
LVTS_SDO DO 6
GPIO127 DIO 0
DMIC1_DAT_R DI 1
DMIC1_DAT_R P30 SPINOR_IO0 DIO 2 0 DVDD18_IOLT OFF I
TDMIN_LRCK DIO 3
LVTS_26M DI 6
GPIO128 DIO 0
DMIC2_CLK DO 1
DMIC2_CLK N34 SPINOR_IO1 DIO 2 0 DVDD18_IOLT OFF I
TDMIN_DI DI 3
LVTS_SCF DI 6

© 2022-2024 MediaTek Inc. All rights reserved. Page 423 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO129 DIO 0
DMIC2_DAT DI 1
DMIC2_DAT P33 SPINOR_IO2 DIO 2 0 DVDD18_IOLT OFF I
SPDIF_IN1 DI 3
LVTS_SCK DI 6
GPIO130 DIO 0
DMIC2_DAT_R DI 1
DMIC2_DAT_R P35 SPINOR_IO3 DIO 2 0 DVDD18_IOLT OFF I
SPDIF_IN2 DI 3
LVTS_SDI DI 6
GPIO131 DIO 0
DPI_D0 DO 1
GBE_TXD3 DO 2
DPI_D0 AB9 DMIC1_CLK DO 3 0 DVDD28_IODPI OFF I
I2SO2_MCK DO 4
TP_GPIO0_AO DIO 5
SPIM5_CSB DO 6
GPIO132 DIO 0
DPI_D1 DO 1
GBE_TXD2 DO 2
DPI_D1 AC9 DMIC1_DAT DI 3 0 DVDD28_IODPI OFF I
I2SO2_BCK DIO 4
TP_GPIO1_AO DIO 5
SPIM5_CLK DO 6

© 2022-2024 MediaTek Inc. All rights reserved. Page 424 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO133 DIO 0
DPI_D2 DO 1
GBE_TXD1 DO 2
DPI_D2 AB8 DMIC1_DAT_R DI 3 0 DVDD28_IODPI OFF I
I2SO2_WS DIO 4
TP_GPIO2_AO DIO 5
SPIM5_MOSI DIO 6
GPIO134 DIO 0
DPI_D3 DO 1
GBE_TXD0 DO 2
DPI_D3 AC4 DMIC2_CLK DO 3 0 DVDD28_IODPI OFF I
I2SO2_D0 DO 4
TP_GPIO3_AO DIO 5
SPIM5_MISO DIO 6
GPIO135 DIO 0
DPI_D4 DO 1
GBE_RXD3 DI 2
DPI_D4 AB3 DMIC2_DAT DI 3 0 DVDD28_IODPI OFF I
I2SO2_D1 DO 4
TP_GPIO4_AO DIO 5
WAKEN DI 6
GPIO136 DIO 0
DPI_D5 DO 1
GBE_RXD2 DI 2
DPI_D5 AA8 DMIC2_DAT_R DI 3 0 DVDD28_IODPI OFF I
I2SO2_D2 DO 4
TP_GPIO5_AO DIO 5
PERSTN DO 6

© 2022-2024 MediaTek Inc. All rights reserved. Page 425 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO137 DIO 0
DPI_D6 DO 1
GBE_RXD1 DI 2
DMIC3_CLK DO 3
DPI_D6 AC8 0 DVDD28_IODPI OFF I
I2SO2_D3 DO 4
TP_GPIO6_AO DIO 5
CLKREQN DIO 6
PWM_0 DO 7
GPIO138 DIO 0
DPI_D7 DO 1
GBE_RXD0 DI 2
DPI_D7 AB7 0 DVDD28_IODPI OFF I
DMIC3_DAT DI 3
CLKM2 DO 4
TP_GPIO7_AO DIO 5
GPIO139 DIO 0
DPI_D8 DO 1
GBE_TXC DIO 2
DPI_D8 AB6 DMIC3_DAT_R DI 3 0 DVDD28_IODPI OFF I
CLKM3 DO 4
TP_UTXD2_AO DO 5
UTXD2 DO 6
GPIO140 DIO 0
DPI_D9 DO 1
GBE_RXC DI 2
DPI_D9 AB5 DMIC4_CLK DO 3 0 DVDD28_IODPI OFF I
PWM_2 DO 4
TP_URXD2_AO DI 5
URXD2 DI 6

© 2022-2024 MediaTek Inc. All rights reserved. Page 426 of 469

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO141 DIO 0
DPI_D10 DO 1
GBE_RXDV DI 2
DPI_D10 AC5 DMIC4_DAT DI 3 0 DVDD28_IODPI OFF I
PWM_3 DO 4
TP_URTS2_AO DO 5
URTS2 DO 6
GPIO142 DIO 0
DPI_D11 DO 1
GBE_TXEN DO 2
DPI_D11 AA5 DMIC4_DAT_R DI 3 0 DVDD28_IODPI OFF I
PWM_1 DO 4
TP_UCTS2_AO DI 5
UCTS2 DI 6
GPIO143 DIO 0
DPI_D12 DO 1
GBE_MDC DO 2
DPI_D12 AA6 0 DVDD28_IODPI OFF I
CLKM0 DO 4
SPIM3_CSB DO 5
UTXD1 DO 6
GPIO144 DIO 0
DPI_D13 DO 1
GBE_MDIO DIO 2
DPI_D13 AC6 0 DVDD28_IODPI OFF I
CLKM1 DO 4
SPIM3_CLK DO 5
URXD1 DI 6

© 2022-2024 MediaTek Inc. All rights reserved. Page 427 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO145 DIO 0
DPI_D14 DO 1
GBE_TXER DO 2
DPI_D14 AC7 0 DVDD28_IODPI OFF I
CMFLASH0 DO 4
SPIM3_MOSI DIO 5
GBE_AUX_PPS2 DIO 6
GPIO146 DIO 0
DPI_D15 DO 1
GBE_RXER DI 2
DPI_D15 AB4 0 DVDD28_IODPI OFF I
CMFLASH1 DO 4
SPIM3_MISO DIO 5
GBE_AUX_PPS3 DIO 6
GPIO147 DIO 0
DPI_HSYNC DO 1
GBE_COL DI 2
DPI_HSYNC AD11 I2SO1_MCK DO 3 0 DVDD28_IODPI OFF I
CMVREF0 DO 4
SPDIF_OUT DO 5
URTS1 DO 6
GPIO148 DIO 0
DPI_VSYNC DO 1
GBE_INTR DI 2
DPI_VSYNC AD10 I2SO1_BCK DO 3 0 DVDD28_IODPI OFF I
CMVREF1 DO 4
SPDIF_IN0 DI 5
UCTS1 DI 6

© 2022-2024 MediaTek Inc. All rights reserved. Page 428 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO149 DIO 0
DPI_DE DO 1
GBE_AUX_PPS0 DIO 2
DPI_DE AB2 I2SO1_WS DO 3 0 DVDD28_IODPI OFF I
CMVREF2 DO 4
SPDIF_IN1 DI 5
UTXD3 DO 6
GPIO150 DIO 0
DPI_CK DO 1
GBE_AUX_PPS1 DIO 2
DPI_CK AB1 I2SO1_D0 DO 3 0 DVDD28_IODPI OFF I
CMVREF3 DO 4
SPDIF_IN2 DI 5
URXD3 DI 6
GPIO151 DIO 0
EMMC_DAT7 D37 1 DVDD18_IOEMMC PU I
MSDC0_DAT7 DIO 1
GPIO152 DIO 0
EMMC_DAT6 E36 1 DVDD18_IOEMMC PU I
MSDC0_DAT6 DIO 1
GPIO153 DIO 0
EMMC_DAT5 F37 1 DVDD18_IOEMMC PU I
MSDC0_DAT5 DIO 1
GPIO154 DIO 0
EMMC_DAT4 D35 1 DVDD18_IOEMMC PU I
MSDC0_DAT4 DIO 1
GPIO155 DIO 0
EMMC_RSTB E34 1 DVDD18_IOEMMC PU OH
MSDC0_RSTB DO 1
GPIO156 DIO 0
EMMC_CMD F33 1 DVDD18_IOEMMC PU I
MSDC0_CMD DIO 1

© 2022-2024 MediaTek Inc. All rights reserved. Page 429 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO157 DIO 0
EMMC_CLK F32 1 DVDD18_IOEMMC OFF OL
MSDC0_CLK DO 1
GPIO158 DIO 0
EMMC_DAT3 E32 1 DVDD18_IOEMMC PU I
MSDC0_DAT3 DIO 1
GPIO159 DIO 0
EMMC_DAT2 D36 1 DVDD18_IOEMMC PU I
MSDC0_DAT2 DIO 1
GPIO160 DIO 0
EMMC_DAT1 F36 1 DVDD18_IOEMMC PU I
MSDC0_DAT1 DIO 1
GPIO161 DIO 0
EMMC_DAT0 D33 1 DVDD18_IOEMMC PU I
MSDC0_DAT0 DIO 1
GPIO162 DIO 0
EMMC_DSL E35 1 DVDD18_IOEMMC OFF I
MSDC0_DSL DI 1
GPIO163 DIO 0
MSDC1_CMD D3 MSDC1_CMD DIO 1 0 DVDD28_MSDC1 OFF I
SPDIF_OUT DO 2
GPIO164 DIO 0
MSDC1_CLK D4 MSDC1_CLK DO 1 0 DVDD28_MSDC1 OFF I
SPDIF_IN0 DI 2
GPIO165 DIO 0
MSDC1_DAT0 D2 MSDC1_DAT0 DIO 1 0 DVDD28_MSDC1 OFF I
SPDIF_IN1 DI 2
GPIO166 DIO 0
MSDC1_DAT1 D1 MSDC1_DAT1 DIO 1 0 DVDD28_MSDC1 OFF I
SPDIF_IN2 DI 2
GPIO167 DIO 0
MSDC1_DAT2 C4 MSDC1_DAT2 DIO 1 0 DVDD28_MSDC1 OFF I
PWM_0 DO 2

© 2022-2024 MediaTek Inc. All rights reserved. Page 430 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO168 DIO 0
MSDC1_DAT3 DIO 1
MSDC1_DAT3 C3 0 DVDD28_MSDC1 OFF I
PWM_1 DO 2
CLKM0 DO 3
GPIO169 DIO 0
MSDC2_CMD DIO 1
MSDC2_CMD AC35 0 DVDD28_MSDC2 OFF I
LVTS_FOUT DO 2
TDMIN_MCK DIO 6
GPIO170 DIO 0
MSDC2_CLK DO 1
MSDC2_CLK AD35 0 DVDD28_MSDC2 OFF I
LVTS_SDO DO 2
TDMIN_BCK DIO 6
GPIO171 DIO 0
MSDC2_DAT0 DIO 1
MSDC2_DAT0 AD37 0 DVDD28_MSDC2 OFF I
LVTS_26M DI 2
TDMIN_LRCK DIO 6
GPIO172 DIO 0
MSDC2_DAT1 DIO 1
MSDC2_DAT1 AD36 0 DVDD28_MSDC2 OFF I
LVTS_SCF DI 2
TDMIN_DI DI 6
GPIO173 DIO 0
MSDC2_DAT2 AB37 MSDC2_DAT2 DIO 1 0 DVDD28_MSDC2 OFF I
LVTS_SCK DI 2
GPIO174 DIO 0
MSDC2_DAT3 AB35 MSDC2_DAT3 DIO 1 0 DVDD28_MSDC2 OFF I
LVTS_SDI DI 2
GPIO175 DIO 0
SPMI_M_SCL K33 1 DVDD18_IOLT OFF OL
SPMI_M_SCL DIO 1

© 2022-2024 MediaTek Inc. All rights reserved. Page 431 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
GPIO176 DIO 0
SPMI_M_SDA K35 1 DVDD18_IOLT OFF I
SPMI_M_SDA DIO 1
SYSRSTB T32 SYSRSTB DI DVDD18_IOLT
TESTMODE T34 TESTMODE DI DVDD18_IOLT
X26M_IN AE34 X26M_IN AI AVDD12_CKSQ
EMI0_CA0 AT22 EMI0_CA0 DO DDRIO AVDDQ_EMI
EMI0_CA1 AR22 EMI0_CA1 DO DDRIO AVDDQ_EMI
EMI0_CA2 AM23 EMI0_CA2 DO DDRIO AVDDQ_EMI
EMI0_CA3 AM22 EMI0_CA3 DO DDRIO AVDDQ_EMI
EMI0_CA4 AN21 EMI0_CA4 DO DDRIO AVDDQ_EMI
EMI0_CA5 AP21 EMI0_CA5 DO DDRIO AVDDQ_EMI
EMI0_CK_C AL20 EMI0_CK_C DO DDRIO AVDDQ_EMI
EMI0_CK_T AM20 EMI0_CK_T DO DDRIO AVDDQ_EMI
EMI0_CKE0 AU20 EMI0_CKE0 DO DDRIO AVDDQ_EMI
EMI0_CKE1 AT20 EMI0_CKE1 DO DDRIO AVDDQ_EMI
EMI0_CS0 AR20 EMI0_CS0 DO DDRIO AVDDQ_EMI
EMI0_CS1 AU22 EMI0_CS1 DO DDRIO AVDDQ_EMI
EMI0_DMI0 AU25 EMI0_DMI0 DIO DDRIO AVDDQ_EMI
EMI0_DMI1 AU31 EMI0_DMI1 DIO DDRIO AVDDQ_EMI
EMI0_DQ0 AU27 EMI0_DQ0 DIO DDRIO AVDDQ_EMI
EMI0_DQ1 AT26 EMI0_DQ1 DIO DDRIO AVDDQ_EMI
EMI0_DQ10 AP30 EMI0_DQ10 DIO DDRIO AVDDQ_EMI
EMI0_DQ11 AN29 EMI0_DQ11 DIO DDRIO AVDDQ_EMI
EMI0_DQ12 AR29 EMI0_DQ12 DIO DDRIO AVDDQ_EMI
EMI0_DQ13 AP31 EMI0_DQ13 DIO DDRIO AVDDQ_EMI
EMI0_DQ14 AT30 EMI0_DQ14 DIO DDRIO AVDDQ_EMI
EMI0_DQ15 AU29 EMI0_DQ15 DIO DDRIO AVDDQ_EMI
EMI0_DQ2 AL25 EMI0_DQ2 DIO DDRIO AVDDQ_EMI

© 2022-2024 MediaTek Inc. All rights reserved. Page 432 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
EMI0_DQ3 AP25 EMI0_DQ3 DIO DDRIO AVDDQ_EMI
EMI0_DQ4 AL24 EMI0_DQ4 DIO DDRIO AVDDQ_EMI
EMI0_DQ5 AN25 EMI0_DQ5 DIO DDRIO AVDDQ_EMI
EMI0_DQ6 AT24 EMI0_DQ6 DIO DDRIO AVDDQ_EMI
EMI0_DQ7 AT28 EMI0_DQ7 DIO DDRIO AVDDQ_EMI
EMI0_DQ8 AU34 EMI0_DQ8 DIO DDRIO AVDDQ_EMI
EMI0_DQ9 AN31 EMI0_DQ9 DIO DDRIO AVDDQ_EMI
EMI0_DQS0_C AN27 EMI0_DQS0_C DIO DDRIO AVDDQ_EMI
EMI0_DQS0_T AM27 EMI0_DQS0_T DIO DDRIO AVDDQ_EMI
EMI0_DQS1_C AR32 EMI0_DQS1_C DIO DDRIO AVDDQ_EMI
EMI0_DQS1_T AT32 EMI0_DQS1_T DIO DDRIO AVDDQ_EMI
EMI0_EXTR AT2 EMI0_EXTR AIO DDRIO AVDDQ_EMI
EMI0_RESET_N AU35 EMI0_RESET_N DO DDRIO AVDDQ_EMI
EMI0_TP AR3 EMI0_TP AIO DDRIO AVDDQ_EMI
EMI1_CA0 AT16 EMI1_CA0 DO DDRIO AVDDQ_EMI
EMI1_CA1 AR16 EMI1_CA1 DO DDRIO AVDDQ_EMI
EMI1_CA2 AL15 EMI1_CA2 DO DDRIO AVDDQ_EMI
EMI1_CA3 AP16 EMI1_CA3 DO DDRIO AVDDQ_EMI
EMI1_CA4 AN16 EMI1_CA4 DO DDRIO AVDDQ_EMI
EMI1_CA5 AL16 EMI1_CA5 DO DDRIO AVDDQ_EMI
EMI1_CK_C AL18 EMI1_CK_C DO DDRIO AVDDQ_EMI
EMI1_CK_T AM18 EMI1_CK_T DO DDRIO AVDDQ_EMI
EMI1_CKE0 AU18 EMI1_CKE0 DO DDRIO AVDDQ_EMI
EMI1_CKE1 AT18 EMI1_CKE1 DO DDRIO AVDDQ_EMI
EMI1_CS0 AR18 EMI1_CS0 DO DDRIO AVDDQ_EMI
EMI1_CS1 AU16 EMI1_CS1 DO DDRIO AVDDQ_EMI
EMI1_DMI0 AU13 EMI1_DMI0 DIO DDRIO AVDDQ_EMI
EMI1_DMI1 AU7 EMI1_DMI1 DIO DDRIO AVDDQ_EMI

© 2022-2024 MediaTek Inc. All rights reserved. Page 433 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
EMI1_DQ0 AU11 EMI1_DQ0 DIO DDRIO AVDDQ_EMI
EMI1_DQ1 AT12 EMI1_DQ1 DIO DDRIO AVDDQ_EMI
EMI1_DQ10 AN8 EMI1_DQ10 DIO DDRIO AVDDQ_EMI
EMI1_DQ11 AR9 EMI1_DQ11 DIO DDRIO AVDDQ_EMI
EMI1_DQ12 AN9 EMI1_DQ12 DIO DDRIO AVDDQ_EMI
EMI1_DQ13 AR6 EMI1_DQ13 DIO DDRIO AVDDQ_EMI
EMI1_DQ14 AT8 EMI1_DQ14 DIO DDRIO AVDDQ_EMI
EMI1_DQ15 AU9 EMI1_DQ15 DIO DDRIO AVDDQ_EMI
EMI1_DQ2 AR11 EMI1_DQ2 DIO DDRIO AVDDQ_EMI
EMI1_DQ3 AN13 EMI1_DQ3 DIO DDRIO AVDDQ_EMI
EMI1_DQ4 AL13 EMI1_DQ4 DIO DDRIO AVDDQ_EMI
EMI1_DQ5 AP13 EMI1_DQ5 DIO DDRIO AVDDQ_EMI
EMI1_DQ6 AT14 EMI1_DQ6 DIO DDRIO AVDDQ_EMI
EMI1_DQ7 AT10 EMI1_DQ7 DIO DDRIO AVDDQ_EMI
EMI1_DQ8 AR4 EMI1_DQ8 DIO DDRIO AVDDQ_EMI
EMI1_DQ9 AU4 EMI1_DQ9 DIO DDRIO AVDDQ_EMI
EMI1_DQS0_C AM11 EMI1_DQS0_C DIO DDRIO AVDDQ_EMI
EMI1_DQS0_T AN11 EMI1_DQS0_T DIO DDRIO AVDDQ_EMI
EMI1_DQS1_C AT5 EMI1_DQS1_C DIO DDRIO AVDDQ_EMI
EMI1_DQS1_T AU5 EMI1_DQS1_T DIO DDRIO AVDDQ_EMI
EMI2_CA0 B16 EMI2_CA0 DO DDRIO AVDDQ_EMI
EMI2_CA1 C16 EMI2_CA1 DO DDRIO AVDDQ_EMI
EMI2_CA2 F15 EMI2_CA2 DO DDRIO AVDDQ_EMI
EMI2_CA3 F16 EMI2_CA3 DO DDRIO AVDDQ_EMI
EMI2_CA4 E17 EMI2_CA4 DO DDRIO AVDDQ_EMI
EMI2_CA5 D17 EMI2_CA5 DO DDRIO AVDDQ_EMI
EMI2_CK_C G18 EMI2_CK_C DO DDRIO AVDDQ_EMI
EMI2_CK_T F18 EMI2_CK_T DO DDRIO AVDDQ_EMI

© 2022-2024 MediaTek Inc. All rights reserved. Page 434 of 469

Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
EMI2_CKE0 A18 EMI2_CKE0 DO DDRIO AVDDQ_EMI
EMI2_CKE1 B18 EMI2_CKE1 DO DDRIO AVDDQ_EMI
EMI2_CS0 C18 EMI2_CS0 DO DDRIO AVDDQ_EMI
EMI2_CS1 A16 EMI2_CS1 DO DDRIO AVDDQ_EMI
EMI2_DMI0 A13 EMI2_DMI0 DIO DDRIO AVDDQ_EMI
EMI2_DMI1 A7 EMI2_DMI1 DIO DDRIO AVDDQ_EMI
EMI2_DQ0 A11 EMI2_DQ0 DIO DDRIO AVDDQ_EMI
EMI2_DQ1 B12 EMI2_DQ1 DIO DDRIO AVDDQ_EMI
EMI2_DQ10 D8 EMI2_DQ10 DIO DDRIO AVDDQ_EMI
EMI2_DQ11 E9 EMI2_DQ11 DIO DDRIO AVDDQ_EMI
EMI2_DQ12 C9 EMI2_DQ12 DIO DDRIO AVDDQ_EMI
EMI2_DQ13 D7 EMI2_DQ13 DIO DDRIO AVDDQ_EMI
EMI2_DQ14 B8 EMI2_DQ14 DIO DDRIO AVDDQ_EMI
EMI2_DQ15 A9 EMI2_DQ15 DIO DDRIO AVDDQ_EMI
EMI2_DQ2 G13 EMI2_DQ2 DIO DDRIO AVDDQ_EMI
EMI2_DQ3 D13 EMI2_DQ3 DIO DDRIO AVDDQ_EMI
EMI2_DQ4 G14 EMI2_DQ4 DIO DDRIO AVDDQ_EMI
EMI2_DQ5 E13 EMI2_DQ5 DIO DDRIO AVDDQ_EMI
EMI2_DQ6 B14 EMI2_DQ6 DIO DDRIO AVDDQ_EMI
EMI2_DQ7 B10 EMI2_DQ7 DIO DDRIO AVDDQ_EMI
EMI2_DQ8 A4 EMI2_DQ8 DIO DDRIO AVDDQ_EMI
EMI2_DQ9 E7 EMI2_DQ9 DIO DDRIO AVDDQ_EMI
EMI2_DQS0_C E11 EMI2_DQS0_C DIO DDRIO AVDDQ_EMI
EMI2_DQS0_T F11 EMI2_DQS0_T DIO DDRIO AVDDQ_EMI
EMI2_DQS1_C C6 EMI2_DQS1_C DIO DDRIO AVDDQ_EMI
EMI2_DQS1_T B6 EMI2_DQS1_T DIO DDRIO AVDDQ_EMI
EMI2_EXTR B2 EMI2_EXTR AIO DDRIO AVDDQ_EMI
EMI2_RESET_N B36 EMI2_RESET_N DO DDRIO AVDDQ_EMI

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
EMI2_TP A3 EMI2_TP AIO DDRIO AVDDQ_EMI
EMI3_CA0 B22 EMI3_CA0 DO DDRIO AVDDQ_EMI
EMI3_CA1 C22 EMI3_CA1 DO DDRIO AVDDQ_EMI
EMI3_CA2 G23 EMI3_CA2 DO DDRIO AVDDQ_EMI
EMI3_CA3 D22 EMI3_CA3 DO DDRIO AVDDQ_EMI
EMI3_CA4 E22 EMI3_CA4 DO DDRIO AVDDQ_EMI
EMI3_CA5 G22 EMI3_CA5 DO DDRIO AVDDQ_EMI
EMI3_CK_C G20 EMI3_CK_C DO DDRIO AVDDQ_EMI
EMI3_CK_T F20 EMI3_CK_T DO DDRIO AVDDQ_EMI
EMI3_CKE0 A20 EMI3_CKE0 DO DDRIO AVDDQ_EMI
EMI3_CKE1 B20 EMI3_CKE1 DO DDRIO AVDDQ_EMI
EMI3_CS0 C20 EMI3_CS0 DO DDRIO AVDDQ_EMI
EMI3_CS1 A22 EMI3_CS1 DO DDRIO AVDDQ_EMI
EMI3_DMI0 A25 EMI3_DMI0 DIO DDRIO AVDDQ_EMI
EMI3_DMI1 A31 EMI3_DMI1 DIO DDRIO AVDDQ_EMI
EMI3_DQ0 A27 EMI3_DQ0 DIO DDRIO AVDDQ_EMI
EMI3_DQ1 B26 EMI3_DQ1 DIO DDRIO AVDDQ_EMI
EMI3_DQ10 E30 EMI3_DQ10 DIO DDRIO AVDDQ_EMI
EMI3_DQ11 C29 EMI3_DQ11 DIO DDRIO AVDDQ_EMI
EMI3_DQ12 E29 EMI3_DQ12 DIO DDRIO AVDDQ_EMI
EMI3_DQ13 C32 EMI3_DQ13 DIO DDRIO AVDDQ_EMI
EMI3_DQ14 B30 EMI3_DQ14 DIO DDRIO AVDDQ_EMI
EMI3_DQ15 A29 EMI3_DQ15 DIO DDRIO AVDDQ_EMI
EMI3_DQ2 C27 EMI3_DQ2 DIO DDRIO AVDDQ_EMI
EMI3_DQ3 E25 EMI3_DQ3 DIO DDRIO AVDDQ_EMI
EMI3_DQ4 G25 EMI3_DQ4 DIO DDRIO AVDDQ_EMI
EMI3_DQ5 D25 EMI3_DQ5 DIO DDRIO AVDDQ_EMI
EMI3_DQ6 B24 EMI3_DQ6 DIO DDRIO AVDDQ_EMI

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
EMI3_DQ7 B28 EMI3_DQ7 DIO DDRIO AVDDQ_EMI
EMI3_DQ8 C34 EMI3_DQ8 DIO DDRIO AVDDQ_EMI
EMI3_DQ9 A34 EMI3_DQ9 DIO DDRIO AVDDQ_EMI
EMI3_DQS0_C F27 EMI3_DQS0_C DIO DDRIO AVDDQ_EMI
EMI3_DQS0_T E27 EMI3_DQS0_T DIO DDRIO AVDDQ_EMI
EMI3_DQS1_C B33 EMI3_DQS1_C DIO DDRIO AVDDQ_EMI
EMI3_DQS1_T A33 EMI3_DQS1_T DIO DDRIO AVDDQ_EMI
DSI0_CKN_T1C AH7 DSI0_CKN_T1C AIO AVDD12_DSI
DSI0_CKP_T1B AH6 DSI0_CKP_T1B AIO AVDD12_DSI
DSI0_D0N_T1A AH5 DSI0_D0N_T1A AIO AVDD12_DSI
DSI0_D0P_T0C AG5 DSI0_D0P_T0C AIO AVDD12_DSI
DSI0_D1N_T2B AH3 DSI0_D1N_T2B AIO AVDD12_DSI
DSI0_D1P_T2A AH4 DSI0_D1P_T2A AIO AVDD12_DSI
DSI0_D2N_T0B AG6 DSI0_D2N_T0B AIO AVDD12_DSI
DSI0_D2P_T0A AG7 DSI0_D2P_T0A AIO AVDD12_DSI
DSI0_D3N AH2 DSI0_D3N AIO AVDD12_DSI
DSI0_D3P_T2C AJ3 DSI0_D3P_T2C AIO AVDD12_DSI
DSI1_CKN_T1C AK6 DSI1_CKN_T1C AIO AVDD12_DSI
DSI1_CKP_T1B AK7 DSI1_CKP_T1B AIO AVDD12_DSI
DSI1_D0N_T1A AK5 DSI1_D0N_T1A AIO AVDD12_DSI
DSI1_D0P_T0C AL5 DSI1_D0P_T0C AIO AVDD12_DSI
DSI1_D1N_T2B AL6 DSI1_D1N_T2B AIO AVDD12_DSI
DSI1_D1P_T2A AL7 DSI1_D1P_T2A AIO AVDD12_DSI
DSI1_D2N_T0B AL4 DSI1_D2N_T0B AIO AVDD12_DSI
DSI1_D2P_T0A AL3 DSI1_D2P_T0A AIO AVDD12_DSI
DSI1_D3N AK8 DSI1_D3N AIO AVDD12_DSI
DSI1_D3P_T2C AL8 DSI1_D3P_T2C AIO AVDD12_DSI
CSI0A_L0N_T0B N3 CSI0A_L0N_T0B AIO AVDD12_CSI

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
CSI0A_L0P_T0A N2 CSI0A_L0P_T0A AIO AVDD12_CSI
CSI0A_L1N_T1A N5 CSI0A_L1N_T1A AIO AVDD12_CSI
CSI0A_L1P_T0C N4 CSI0A_L1P_T0C AIO AVDD12_CSI
CSI0A_L2N_T1C N6 CSI0A_L2N_T1C AIO AVDD12_CSI
CSI0A_L2P_T1B M6 CSI0A_L2P_T1B AIO AVDD12_CSI
CSI0B_L0N_T0B P1 CSI0B_L0N_T0B AIO AVDD12_CSI
CSI0B_L0P_T0A P2 CSI0B_L0P_T0A AIO AVDD12_CSI
CSI0B_L1N_T1A P4 CSI0B_L1N_T1A AIO AVDD12_CSI
CSI0B_L1P_T0C P3 CSI0B_L1P_T0C AIO AVDD12_CSI
CSI0B_L2N_T1C P6 CSI0B_L2N_T1C AIO AVDD12_CSI
CSI0B_L2P_T1B P5 CSI0B_L2P_T1B AIO AVDD12_CSI
CSI1A_L0N_T0B J4 CSI1A_L0N_T0B AIO AVDD12_CSI
CSI1A_L0P_T0A J5 CSI1A_L0P_T0A AIO AVDD12_CSI
CSI1A_L1N_T1A J3 CSI1A_L1N_T1A AIO AVDD12_CSI
CSI1A_L1P_T0C J2 CSI1A_L1P_T0C AIO AVDD12_CSI
CSI1A_L2N_T1C K6 CSI1A_L2N_T1C AIO AVDD12_CSI
CSI1A_L2P_T1B K7 CSI1A_L2P_T1B AIO AVDD12_CSI
CSI1B_L0N_T0B K3 CSI1B_L0N_T0B AIO AVDD12_CSI
CSI1B_L0P_T0A K5 CSI1B_L0P_T0A AIO AVDD12_CSI
CSI1B_L1N_T1A L4 CSI1B_L1N_T1A AIO AVDD12_CSI
CSI1B_L1P_T0C L3 CSI1B_L1P_T0C AIO AVDD12_CSI
SSUSB_RXN W36 SSUSB_RXN AI AVDD12_SSUSB
SSUSB_RXP W37 SSUSB_RXP AI AVDD12_SSUSB
SSUSB_TXN Y34 SSUSB_TXN AO AVDD12_SSUSB
SSUSB_TXP Y33 SSUSB_TXP AO AVDD12_SSUSB
PCIE_CKN AN3 PCIE_CKN AIO AVDD12_PCIE
PCIE_CKP AN4 PCIE_CKP AIO AVDD12_PCIE
PCIE_LN0_RXN AP1 PCIE_LN0_RXN AIO AVDD12_PCIE

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
PCIE_LN0_RXP AP2 PCIE_LN0_RXP AIO AVDD12_PCIE
PCIE_LN0_TXN AM2 PCIE_LN0_TXN AIO AVDD12_PCIE
PCIE_LN0_TXP AM1 PCIE_LN0_TXP AIO AVDD12_PCIE
DP_LN0_TXN AH35 DP_LN0_TXN AIO AVDD12_DPTX
DP_LN0_TXP AG35 DP_LN0_TXP AIO AVDD12_DPTX
DP_LN1_TXN AH31 DP_LN1_TXN AIO AVDD12_DPTX
DP_LN1_TXP AH32 DP_LN1_TXP AIO AVDD12_DPTX
DP_LN2_TXN AJ33 DP_LN2_TXN AIO AVDD12_DPTX
DP_LN2_TXP AJ34 DP_LN2_TXP AIO AVDD12_DPTX
DP_LN3_TXN AK31 DP_LN3_TXN AIO AVDD12_DPTX
DP_LN3_TXP AK32 DP_LN3_TXP AIO AVDD12_DPTX
DPAUXN AJ37 DPAUXN AIO AVDD12_DPTX
DPAUXP AJ36 DPAUXP AIO AVDD12_DPTX
EDP_LN0_TXN AG29 EDP_LN0_TXN AIO AVDD12_EDPTX
EDP_LN0_TXP AG30 EDP_LN0_TXP AIO AVDD12_EDPTX
EDP_LN1_TXN AF31 EDP_LN1_TXN AIO AVDD12_EDPTX
EDP_LN1_TXP AF32 EDP_LN1_TXP AIO AVDD12_EDPTX
EDPAUXN AF37 EDPAUXN AIO AVDD12_EDPTX
EDPAUXP AF36 EDPAUXP AIO AVDD12_EDPTX
USB_DM_P0 W31 USB_DM_P0 AIO AVDD33_USB_P0
USB_DM_P1 U36 USB_DM_P1 AIO AVDD33_USB_P1
USB_DM_P2 V35 USB_DM_P2 AIO AVDD33_USB_P2
USB_DP_P0 W32 USB_DP_P0 AIO AVDD33_USB_P0
USB_DP_P1 U37 USB_DP_P1 AIO AVDD33_USB_P1
USB_DP_P2 V34 USB_DP_P2 AIO AVDD33_USB_P2
AUXIN0 AE6 AUXIN0 AIO AVDD18_AUXADC
AUXIN1 AF2 AUXIN1 AIO AVDD18_AUXADC
AUXIN2 AE3 AUXIN2 AIO AVDD18_AUXADC

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 MT8390
IoT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Signal Name Signal Type Aux. Function Reset Function Buffer Type Power Domain PU/PD Reset IO Reset
AUXIN3 AE2 AUXIN3 AIO AVDD18_AUXADC
AUXIN4 AE4 AUXIN4 AIO AVDD18_AUXADC
AUXIN5 AE5 AUXIN5 AIO AVDD18_AUXADC
REFP AE7 REFP AIO AVDD18_AUXADC
HDMITX21_CH0_M AN34 HDMITX21_CH0_M AIO AVDD18_HDMITX21
HDMITX21_CH0_P AN35 HDMITX21_CH0_P AIO AVDD18_HDMITX21
HDMITX21_CH1_M AM37 HDMITX21_CH1_M AIO AVDD18_HDMITX21
HDMITX21_CH1_P AM36 HDMITX21_CH1_P AIO AVDD18_HDMITX21
HDMITX21_CH2_M AL35 HDMITX21_CH2_M AIO AVDD18_HDMITX21
HDMITX21_CH2_P AK35 HDMITX21_CH2_P AIO AVDD18_HDMITX21
HDMITX21_CLK_M AR35 HDMITX21_CLK_M AIO AVDD18_HDMITX21
HDMITX21_CLK_P AR34 HDMITX21_CLK_P AIO AVDD18_HDMITX21

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 MT8390
IOT APPLICATION PROCESSOR
UNCLASSIFIED

4.3 Power Rails

Table 4-11 Power Rails
Ball Name Ball Location Type Description
AVDD2_EMI0 AH15, AH17, AH19, AH21, AH23 P DRAM power
AVDD2_EMI2 K15, K17, K19, K21, K23 P DRAM power
AVDD12_AUXADC AE1 P Analog power for AUXADC
AVDD12_CKSQ AD28 P Analog power for CKSQ
AVDD12_CSI0 P8 P Analog power for CSI0
AVDD12_CSI1 M9 P Analog power for CSI1
AVDD12_DPTX AJ29 P Analog power for DPTX
AVDD12_DSI AH10 P Analog power for DSI
AVDD12_EDPTX AG27 P Analog power for EDPTX
AVDD12_EMI0 AJ14 P DRAM power
AVDD12_EMI2 J13 P DRAM power
AVDD12_HDMITX21 AL28 P Analog power for HDMITX
AVDD12_PCIE AJ11 P Analog power for PCIE
AVDD12_PLLGP1 U19 P Analog power for APPLL
AVDD12_PLLGP2 AC16 P Analog power for APPLL
AVDD12_PLLGP34 V14, W14 P Analog power for APPLL
AVDD12_SSUSB AC28 P Analog power for SSUSB
AVDD12_USB_P0 W29 P Analog power for USB_P0
AVDD12_USB_P1 Y28 P Analog power for USB_P1
AVDD12_USB_P2 Y29 P Analog power for USB_P2
AVDD18_APU W17 P Analog power 1.8V for APU
AVDD18_AUXADC AF1 P Analog power 1.8V for AUXADC
AVDD18_CKSQ AD29 P Analog power 1.8V for CKSQ
AVDD18_DPTX AH28 P Analog power 1.8V for DPTX
AVDD18_DSI AE10 P Analog power 1.8V for DSI
AVDD18_EDPTX AG26 P Analog power 1.8V for EDPTX
AVDD18_EMI0 AH25 P DRAM power
AVDD18_EMI2 J24 P DRAM power
AVDD18_HDMITX21 AL29 P Analog power 1.8V for HDMITX
AVDD18_PCIE AH11 P Analog power 1.8V for PCIE
AVDD18_PLLGP1 V20 P Analog power 1.8V for APPLL
AVDD18_PLLGP2 AC17 P Analog power 1.8V for APPLL
AVDD18_PLLGP34 V13, W13 P Analog power 1.8V for APPLL
AVDD18_PROC L24 P Analog power 1.8V for CPU
AVDD18_SSUSB AC29 P Analog power 1.8V for SSUSB
AVDD18_USB_P0 W28 P Analog power 1.8V for USB_P0
AVDD18_USB_P1 AA29 P Analog power 1.8V for USB_P1
AVDD18_USB_P2 U28 P Analog power 1.8V for USB_P2
AVDD33_USB_P0 U33 P Analog power 3.3V for USB_P0
AVDD33_USB_P1 V32 P Analog power 3.3V for USB_P1

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 MT8390
IOT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Type Description

AVDD33_USB_P2 U29 P Analog power 3.3V for USB_P2
AVDD075_DRV_DSI AE11 P Analog power for DSI
AVDD075_EMI0 AH14, AH24 P DRAM power
AVDD075_EMI2 K13, K24 P DRAM power
AVDDQ_EMI0 AH16, AH18, AH20, AH22, AJ15, AJ17, AJ19,
P DRAM power
AJ21, AJ23, AJ24
AVDDQ_EMI2 J15, J17, J19, J21, J23, K14, K16, K18, K20, K22 P DRAM power
DVDD_ADSP AD19, AD20, AE19, AE20, AF19, AF20 P Digital power input for ADSP
DVDD_APU V16, W16, Y13, Y14, Y16, Y17, AA13, AA14,
P Digital power input for APU
AA16, AA17, AB14, AB16
L13, M20, N20, P15, R15, T19, U12, U13, U14,
U15, U16, U17, U20, V17, V18, W19, W20, Y19,
DVDD_CORE Y20, Y23, Y24, Y25, AA19, AA20, AA23, AA24,
P Digital power input for Vcore
AB19, AB20, AB23, AB24, AC19, AC20, AC23,
AC24, AD23, AD24, AE23, AE24, AF23, AF24,
AG14
DVDD_GPU AC14, AC15, AD13, AD14, AD15, AD16, AE13,
P Digital power input for GPU
AE14, AE15, AE16, AF14, AF15, AF16, AF17
M14, M18, M19, N14, N15, N17, N19, P14,
DVDD_MM P17, P19, P20, R14, R17, R19, R20, T14, T15, P Digital power input for ISP
T16, T17
DVDD_PROC_B K26, K27, K28, L21, L26, L27, L28, M21, M25,
P Digital power input for Big Core
M26, M27, M28, N21, N22, N24, N25
DVDD_PROC_L P24, R22, R25, R26, R27, T22, T25, T26, T27,
P Digital power input for Little Core
T28, U22, U24, U25, U26, U27, V22, V27, W24
DVDD_SRAM_APU AB13 P Digital power input for APU SRAM
DVDD_SRAM_CORE Y22, AD22, AF22 P Digital power input for Core SRAM
DVDD_SRAM_GPU AC13, AF13 P Digital power input for GPU SRAM
DVDD_SRAM_MM M16, R13 P Digital power input for ISP SRAM
DVDD_SRAM_PROC_B Digital power input for Big Core
M22, N26 P
SRAM
DVDD_SRAM_PROC_L Digital power input for Little Core
R21, V24 P
SRAM
DVDD18_IODPI AD1 P Digital power input for I/O
DVDD18_IOEMMC C37 P Digital power input for I/O
DVDD18_IOLM AD31 P Digital power input for I/O
DVDD18_IOLT G37, R37 P Digital power input for I/O
DVDD18_IORM AA10 P Digital power input for I/O
DVDD18_IORT J11 P Digital power input for I/O
DVDD18_MSDC1 E1 P Digital power input for I/O
DVDD18_MSDC2 AB36 P Digital power input for I/O
DVDD18_VQPS H27 DIO eFuse blowing power input
DVDD28_IODPI U9 P Digital power input for DPI
DVDD28_MSDC1 G7 P Digital power input for MSDC1
DVDD28_MSDC2 AA36 P Digital power input for MSDC2
A5, A6, A32, A35, B3, B4, B5, B7, B9, B11, B13,
DVSS B15, B23, B25, B27, B29, B31, B32, B34, B35,
G GND
C2, C5, C7, C8, C10, C11, C12, C13, C14, C15,
C17, C19, C21, C23, C24, C25, C26, C28, C30,

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 MT8390
IOT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Type Description

C31, C33, C35, C36, D5, D6, D9, D10, D11, D12,
D14, D15, D16, D18, D20, D21, D23, D24, D26,
D27, D28, D29, D30, D31, D32, D34, E6, E8,
E10, E12, E14, E15, E16, E18, E19, E20, E21,
E23, E24, E26, E28, E31, E33, F7, F8, F9, F10,
F12, F13, F14, F17, F19, F21, F22, F24, F25,
F26, F28, F29, F30, F31, F34, F35, G8, G9, G10,
G11, G12, G15, G17, G19, G21, G24, G26, G27,
G28, G29, G34, G35, H4, H5, H6, H8, H9, H10,
H11, H12, H13, H14, H15, H16, H17, H18, H20,
H21, H22, H23, H24, H25, H26, H28, H29, H30,
J1, J6, J7, J8, J9, J10, J12, J14, J16, J18, J20, J22,
J25, J26, J27, J28, J29, K4, K8, K9, K10, K11,
K25, K29, L5, L6, L7, L8, L9, L10, L11, L23, L25,
L29, M4, M5, M7, M8, M10, M11, M13, M15,
M17, M23, M24, M29, M37, N1, N7, N10, N13,
N16, N18, N23, N27, N28, N29, N36, P7, P9,
P10, P11, P13, P16, P18, P21, P22, P23, P25,
P26, P27, P28, P29, R3, R4, R5, R6, R7, R8, R9,
R10, R11, R16, R18, R23, R24, R28, R29, T3,
T13, T18, T23, T24, T29, T35, T36, T37, U21,
U23, U30, U31, U34, U35, V12, V15, V21, V23,
V25, V26, V29, V30, V31, V33, V36, W12, W15,
W18, W21, W22, W23, W25, W30, W33, W34,
W35, Y15, Y18, Y21, Y27, Y30, Y31, Y32, Y35,
Y36, AA15, AA18, AA21, AA22, AA25, AA26,
AA27, AA32, AA33, AA34, AB12, AB15, AB17,
AB18, AB21, AB22, AB25, AB27, AB29, AB30,
AC12, AC18, AC21, AC22, AC25, AC27, AD2,
AD3, AD4, AD5, AD6, AD7, AD8, AD9, AD12,
AD17, AD18, AD21, AD25, AD26, AD34, AE8,
AE9, AE12, AE17, AE18, AE21, AE22, AE27,
AE28, AE29, AE30, AE31, AE32, AE33, AE35,
AE36, AF3, AF4, AF5, AF6, AF7, AF8, AF9, AF10,
AF12, AF18, AF21, AF26, AF27, AF28, AF29,
AF30, AF33, AF34, AF35, AG4, AG8, AG9, AG11,
AG28, AG31, AG32, AG33, AG34, AH1, AH8,
AH9, AH12, AH29, AH30, AH33, AH34, AJ4, AJ5,
AJ6, AJ7, AJ8, AJ9, AJ12, AJ13, AJ16, AJ18,
AJ20, AJ22, AJ25, AJ26, AJ27, AJ28, AJ30, AJ31,
AJ32, AJ35, AK9, AK10, AK11, AK12, AK13,
AK14, AK15, AK16, AK17, AK18, AK20, AK21,
AK22, AK23, AK24, AK25, AK26, AK27, AK28,
AK29, AK30, AK33, AK34, AL1, AL2, AL9, AL10,
AL11, AL12, AL14, AL17, AL19, AL21, AL23,
AL26, AL27, AL31, AL32, AL33, AL34, AM3,
AM4, AM5, AM6, AM7, AM8, AM9, AM10,
AM12, AM13, AM14, AM16, AM17, AM19,
AM21, AM24, AM25, AM26, AM28, AM29,
AM30, AM31, AM32, AM33, AM34, AM35,
AN2, AN5, AN6, AN7, AN10, AN12, AN14,
AN15, AN17, AN18, AN19, AN20, AN22, AN23,
AN24, AN26, AN28, AN30, AN32, AN33, AP3,
AP4, AP5, AP6, AP7, AP8, AP9, AP10, AP11,
AP12, AP14, AP15, AP17, AP18, AP20, AP22,
AP23, AP24, AP26, AP27, AP28, AP29, AP32,

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Unauthorized reproduction or disclosure of this document, in whole or in part, is strictly prohibited.
 MT8390
IOT APPLICATION PROCESSOR
UNCLASSIFIED

Ball Name Ball Location Type Description

AP33, AP34, AP36, AP37, AR2, AR5, AR7, AR8,
AR10, AR12, AR13, AR14, AR15, AR17, AR19,
AR21, AR23, AR24, AR25, AR26, AR27, AR28,
AR30, AR31, AR33, AT3, AT4, AT6, AT7, AT9,
AT11, AT13, AT15, AT23, AT25, AT27, AT29,
AT31, AT33, AT34, AT35, AT36, AU3, AU6,
AU32, AU33

4.4 Reserved and Unused Pin Handling Recommendations

MT8390 Baseband Design Notice provides specific pin handling recommendations for the case that the pins are not used.

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5 Electrical Characteristics

Stresses above the values listed in Table 5-1 may cause permanent damage to the device. The recommended minimum
and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage, and frequencies
based on characterization results. Exposure to absolute maximum rating conditions may affect device reliability. The
operating conditions in Table 5-2 must not be exceeded in order to ensure correct operation and reliability of the device.
All parameters specified in this document refer to these operating conditions, unless noted otherwise.

5.1 Absolute Maximum Ratings

Table 5-1 Absolute Maximum Ratings
Parameter Conditions Max. Unit
Digital power input for A78 core DVDD_PROC_B, DVDD_SRAM_PROC_B 1.21 V
Digital power input for A55 core DVDD_PROC_L 0.99 V
Digital power input for A55 core DVDD_SRAM_PROC_L 1.08 V
Digital power input for Vcore DVDD_CORE 0.83 V
Digital power input for GPU DVDD_GPU 0.88 V
AVDD12_AUXADC, AVDD12_CKSQ,
AVDD12_CSI0, AVDD12_CSI1,
AVDD12_DPTX, AVDD12_DSI,
AVDD12_EDPTX, AVDD12_HDMITX21,
AVDD12_PCIE, AVDD12_PLLGP1,
AVDD12_PLLGP2, AVDD12_PLLGP34, 1.32 V
AVDD12_SSUSB, AVDD12_USB_P0,
AVDD12_USB_P1, AVDD12_USB_P2,
AVDD12_EMI0, AVDD12_EMI2,
AVDD2_EMI0, AVDD2_EMI2,
AVDDQ_EMI0, AVDDQ_EMI2
Analog power input AVDD18_APU, AVDD18_AUXADC,
AVDD18_CKSQ, AVDD18_DPTX,
AVDD18_DSI, AVDD18_EDPTX,
AVDD18_HDMITX21, AVDD18_PCIE,
AVDD18_PLLGP1, AVDD18_PLLGP2, 1.98 V
AVDD18_PLLGP34, AVDD18_PROC,
AVDD18_SSUSB, AVDD18_USB_P0,
AVDD18_USB_P1, AVDD18_USB_P2,
AVDD18_EMI0, AVDD18_EMI2
AVDD33_USB_P0, AVDD33_USB_P1,
3.22 V
AVDD33_USB_P2
AVDD075_EMI0, AVDD075_EMI2 0.825 V
DVDD_ADSP, DVDD_MM,
0.83 V
DVDD_SRAM_CORE, DVDD_SRAM_MM
Digital power input
DVDD_APU 0.85 V
DVDD_SRAM_APU 0.88 V

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Parameter Conditions Max. Unit

DVDD_SRAM_GPU 0.94 V
DVDD18_IODPI, DVDD18_IOEMMC,
DVDD18_IOLM, DVDD18_IOLT,
1.95 V
DVDD18_IORM, DVDD18_IORT,
DVDD18_MSDC1, DVDD18_MSDC2
DVDD28_IODPI, DVDD28_MSDC1
3.15 V
DVDD28_MSDC2
Junction temperature - 125 °C
Warning: Stressing the device beyond the absolute maximum ratings may cause permanent damage. These are stress
ratings only.

5.1.1 Storage Condition

Table 5-2 defines storage conditions specifics.

Table 5-2 Storage Condition

Parameter Min. Max. Unit
Shelf life in sealed bag 40°C/90% RH 24 Months
After bag opened(1)
Mounted 30°C/60% RH 168 h
Stored 20 % RH
Baking
Low temperature device containers 40°C +5°C/-0°C and < 5% RH 192 h
High temperature device containers 125°C +5°C/-0°C 24 h
1. For devices subjected to infrared reflow, vapor-phase reflow, or equivalent processing.

5.2 Recommended Operating Conditions

Table 5-3 presents the recommended operating conditions of the device power pins.

Table 5-3 Recommended Operating Conditions for Power Supply

Pin Name Description Min. Typ. Max. Unit
AVDD075_DRV_DSI Analog power for DRV_DSI 0.7125 0.75 0.7875 V
AVDD12_AUXADC Analog power for AUXADC 1.14 1.2 1.26 V
AVDD12_CKSQ Analog power for CKSQ 1.14 1.2 1.26 V
AVDD12_CSI0 Analog power for CSI0 1.14 1.2 1.26 V
AVDD12_CSI1 Analog power for CSI1 1.14 1.2 1.26 V
AVDD12_DPTX Analog power for DPTX 1.14 1.2 1.26 V
AVDD12_DSI Analog power for DSI 1.14 1.2 1.26 V
AVDD12_EDPTX Analog power for EDPTX 1.14 1.2 1.26 V
AVDD12_HDMITX21 Analog power for HDMITX21 1.14 1.2 1.26 V
AVDD12_PCIE Analog power for PCIe 1.14 1.2 1.26 V
AVDD12_PLLGP1 Analog power for PLLGP1 1.14 1.2 1.26 V
AVDD12_PLLGP2 Analog power for PLLGP2 1.14 1.2 1.26 V

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Pin Name Description Min. Typ. Max. Unit

AVDD12_PLLGP34 Analog power for PLLGP34 1.14 1.2 1.26 V
AVDD12_SSUSB Analog power for SSUSB 1.14 1.2 1.26 V
AVDD12_USB_P0 Analog power for USB_P0 1.14 1.2 1.26 V
AVDD12_USB_P1 Analog power for USB_P1 1.14 1.2 1.26 V
AVDD12_USB_P2 Analog power for USB_P2 1.14 1.2 1.26 V
AVDD18_APU Analog power for APU 1.71 1.8 1.89 V
AVDD18_AUXADC Analog power for AUXADC 1.71 1.8 1.89 V
AVDD18_CKSQ Analog power for CKSQ 1.71 1.8 1.89 V
AVDD18_DPTX Analog power for DPTX 1.71 1.8 1.89 V
AVDD18_DSI Analog power for DSI 1.71 1.8 1.89 V
AVDD18_EDPTX Analog power for EDPTX 1.71 1.8 1.89 V
AVDD18_HDMITX21 Analog power for HDMITX21 1.71 1.8 1.89 V
AVDD18_PCIE Analog power for PCIe 1.71 1.8 1.89 V
AVDD18_PLLGP1 Analog power for PLLGP1 1.71 1.8 1.89 V
AVDD18_PLLGP2 Analog power for PLLGP2 1.71 1.8 1.89 V
AVDD18_PLLGP34 Analog power for PLLGP34 1.71 1.8 1.89 V
AVDD18_PROC Analog power for PROC 1.71 1.8 1.89 V
AVDD18_SSUSB Analog power for SSUSB 1.71 1.8 1.89 V
AVDD18_USB_P0 Analog power for USB Port0 1.71 1.8 1.89 V
AVDD18_USB_P1 Analog power for USB Port1 1.71 1.8 1.89 V
AVDD18_USB_P2 Analog power for USB Port2 1.71 1.8 1.89 V
AVDD33_USB_P0 Analog power for USB Port0 2.92 3.07 3.22 V
AVDD33_USB_P1 Analog power for USB Port1 2.92 3.07 3.22 V
AVDD33_USB_P2 Analog power for USB Port2 2.92 3.07 3.22 V
AVDD075_EMI0 Analog power for EMI0 0.675 0.75 0.825 V
AVDD075_EMI2 Analog power for EMI2 0.675 0.75 0.825 V
AVDD12_EMI0 Analog power for EMI0 1.08 1.2 1.32 V
AVDD12_EMI2 Analog power for EMI2 1.08 1.2 1.32 V
AVDD18_EMI0 Analog power for EMI0 1.62 1.8 1.98 V
AVDD18_EMI2 Analog power for EMI2 1.62 1.8 1.98 V
AVDD2_EMI0 (LPDDR4X) Analog power for EMI0 (LPDDR4X) 1.06 1.1 1.17 V
AVDD2_EMI0 (LPDDR4) Analog power for EMI0 (LPDDR4) 1.06 1.1 1.17 V
AVDD2_EMI2 (LPDDR4X) Analog power for EMI2 (LPDDR4X) 1.06 1.1 1.17 V
AVDD2_EMI2 (LPDDR4) Analog power for EMI2 (LPDDR4) 1.06 1.1 1.17 V
AVDDQ_EMI0 (LPDDR4X) Analog power for EMI0 (LPDDR4X) 0.57 0.6 0.65 V
AVDDQ_EMI0 (LPDDR4) Analog power for EMI0 (LPDDR4) 1.06 1.1 1.17 V
AVDDQ_EMI2 (LPDDR4X) Analog power for EMI2 (LPDDR4X) 0.57 0.6 0.65 V
AVDDQ_EMI2 (LPDDR4) Analog power for EMI2 (LPDDR4X) 1.06 1.1 1.17 V
DVDD_ADSP Digital power input for ADSP 0.71 0.75 0.81 V
DVDD_APU Digital power input for APU 0.53 0.75 0.84 V
DVDD_CORE Digital power input for Vcore 0.52 0.75 0.81 V
DVDD_GPU Digital power input for GPU 0.55 0.75 0.86 V
DVDD_MM Digital power input for ISP 0.52 0.75 0.81 V
DVDD_PROC_B Digital power input for Big Core 0.52 0.75 1.19 V
DVDD_PROC_L Digital power input for Little Core 0.52 0.75 0.97 V
DVDD_SRAM_APU Digital power input for APU SRAM 0.71 0.75 0.86 V

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Pin Name Description Min. Typ. Max. Unit

0.57+
0.71
DVDD_SRAM_CORE Digital power input for Core SRAM 0.75 0.81 V
0.57+
0.71
DVDD_SRAM_GPU Digital power input for GPU SRAM 0.85 0.92 V
0.57+
0.71
DVDD_SRAM_MM Digital power input for ISP SRAM 0.75 0.81 V
0.57+
0.71
DVDD_SRAM_PROC_B Digital power input for Big Core SRAM 0.85 1.19 V
0.57+
0.71
DVDD_SRAM_PROC_L Digital power input for Little Core SRAM 0.85 1.08 V
0.57+
DVDD18_IODPI Digital power input for I/O 1.71 1.8 1.89 V
DVDD18_IOEMMC Digital power input for I/O 1.71 1.8 1.89 V
DVDD18_IOLM Digital power input for I/O 1.71 1.8 1.89 V
DVDD18_IOLT Digital power input for I/O 1.71 1.8 1.89 V
DVDD18_IORM Digital power input for I/O 1.71 1.8 1.89 V
DVDD18_IORT Digital power input for I/O 1.71 1.8 1.89 V
DVDD18_MSDC1 Digital power input for I/O 1.71 1.8 1.89 V
DVDD18_MSDC2 Digital power input for I/O 1.71 1.8 1.89 V
DVDD28_IODPI Digital power input for DPI 1.71 3 3.15 V
DVDD28_MSDC1 Digital power input for MSDC1 1.71 3 3.15 V
DVDD28_MSDC2 Digital power input for MSDC2 1.71 3 3.15 V
Note: The values with “+” sign are for SRAM retention only, not for operation.

5.3 DC Electrical Specifications

This section provides DC electrical characteristics per buffer type.

5.3.1 PMIC_RTC32K_CK DC Specifications

Table 5-4 PMIC_RTC32K_CK DC Specifications
Parameter Min. Typ. Max. Unit
Operating voltage = 1.8 V
INPUT
VIH Input logic high voltage 0.65 × VDDIO(1) VDDIO(1) + 0.3 V
(1)
VIL Input logic low voltage -0.3 0.35 × VDDIO V
FRTC Input clock frequency 32 kHz
DCRTC Input signal duty cycle 45 50 55 %
OUTPUT
VOH DC output logic high voltage 0.75 × VDDIO(1) V
(1)
VOL DC output logic low voltage 0.25 × VDDIO V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD18_IOLT). For more information on the power supply name on
the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

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5.3.2 SPII2CUARTIO DC Electrical Specifications

Table 5-5 SPII2CUARTIO DC Specifications
Parameter Min. Typ. Max. Unit
Operating voltage = 1.8 V
INPUT
VIH Input logic high voltage 0.65 × VDDIO(1) VDDIO + 0.3 V
(1)
VIL Input logic low voltage -0.3 0.35 × VDDIO V
OUTPUT
VOH DC output logic high voltage 0.75 × VDDIO(1) V
VOL DC output logic low voltage 0.25 × VDDIO(1) V
(1) VDDIO in this table stands for corresponding power supply (i.e. VDD18_IORM). For more information on the power supply name on
the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

5.3.3 I2C/I2SIO DC Specifications

Table 5-6 I2C/I2S DC Specifications
Parameter Min. Typ. Max. Unit
Operating voltage = 1.8 V
INPUT
VIH Input logic high voltage 0.65 × VDDIO(1) VDDIO(1) + 0.3 V
(1)
VIL Input logic low voltage -0.3 0.35 × VDDIO V
OUTPUT
VOH DC output logic high voltage 0.75 × VDDIO(1) V
(1)
VOL DC output logic low voltage 0.25 × VDDIO V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD18_IOLT). For more information on the power supply name on
the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

5.3.4 I3CIO DC Specifications

Table 5-7 I3CIO DC Specifications
Parameter Min. Typ. Max. Unit
Operating voltage = 1.8 V
INPUT
VIH Input logic high voltage 0.65 × VDDIO(1) VDDIO(1) + 0.3 V
VIL Input logic low voltage -0.3 0.35 × VDDIO(1) V
OUTPUT
VOL DC output logic low voltage 0.2 × VDDIO(1) V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD18_IORT). For more information on the power supply name
on the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

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5.3.5 eMMCIO DC Specifications

Table 5-8 eMMCIO DC Specifications
Parameter Min. Typ. Max. Unit
Operating voltage = 1.8 V
INPUT
VIH Input logic high voltage 0.65 × VDDIO(1) VDDIO(1) + 0.3 V
(1)
VIL Input logic low voltage -0.3 0.35 × VDDIO V
OUTPUT
VOH DC output logic high voltage 1.4 V
VOL DC output logic low voltage 0.45 V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD18_IOEMMC). For more information on the power supply
name on the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

5.3.6 MSDC1IO DC Specifications

Table 5-9 MSDC1IO DC Specifications (2.8V/3.0V)
Parameter Min. Typ. Max. Unit
Operating voltage = 2.8V/3.0V
INPUT
VIH Input logic high voltage 0.75 × VDDIO(1) VDDIO(1) + 0.15 V
(1)
VIL Input logic low voltage -0.3 0.25 × VDDIO V
OUTPUT
VOH DC output logic high voltage 0.625 × VDDIO(1) VDDIO(1) + 0.15 V
(1)
VOL DC output logic low voltage -0.3 0.125 × VDDIO V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD28_MSDC1). For more information on the power supply name
on the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

Table 5-10 MSDC1IO DC Specifications

Parameter Min. Typ. Max. Unit
Operating voltage = 1.8 V
INPUT
VIH Input logic low voltage 0.7 × VDDIO(1) VDDIO(1) + 0.15 V
(1)
VIL Input logic high voltage -0.3 0.3 × VDDIO V
OUTPUT
VOH DC output logic high voltage 1.4 VDDIO(1) + 0.15 V
VOL DC output logic low voltage -0.3 0.45 V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD28_MSDC1). For more information on the power supply name
on the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

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5.3.7 MSDC2IO DC Specifications

Table 5-11 MSDC2IO DC Specifications (2.8V/3.0V)
Parameter Min. Typ. Max. Unit
Operating voltage = 2.8V/3.0V
INPUT
VIH Input logic high voltage 0.75 × VDDIO(1) VDDIO(1) + 0.15 V
(1)
VIL Input logic low voltage -0.3 0.25 × VDDIO V
OUTPUT
VOH DC output logic high voltage 0.625 × VDDIO(1) VDDIO(1) + 0.15 V
VOL DC output logic low voltage -0.3 0.125 × VDDIO(1) V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD28_MSDC2). For more information on the power supply name
on the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

Table 5-12 MSDC2IO DC

Parameter Min. Typ. Max. Unit
Operating voltage = 1.8 V
INPUT
VIH Input logic high voltage 0.7 × VDDIO(1) VDDIO(1) + 0.15 V
(1)
VIL Input logic low voltage -0.3 0.3 × VDDIO V
OUTPUT
VOH DC output logic high voltage 1.4 VDDIO(1) + 0.15 V
VOL DC output logic low voltage -0.3 0.45 V
(1) VDDIO in this table stands for corresponding power supply (i.e. DVDD28_MSDC2). For more information on the power supply name
on the corresponding ball, see Table 4-10 Pin Characteristics, Power Domain column.

5.4 Power Management

5.4.1 Power Sequence

Refer to PMIC datasheet for detailed timing sequence.

5.5 Reset

5.5.1 Overview
The Top Reset Generation Unit (TOPRGU) is responsible for generating and distributing reset signals to various subsystems
to ensure that the system operates in a stable and reliable manner. It consists of a Watchdog Timer (WDT), which helps
protect against potential system crashes by monitoring system operation and resetting it if an unexpected event occurs.

5.5.2 Features
 Hardware reset signals for the whole chip

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 Software controllable reset for subsystems

 Watchdog timer timeout reset
 Reset output signals for companion chips

5.5.3 Block Diagram

CHIP
Top Reset Generation Unit (TOPRGU)
PAD_SYSRSTB

PAD_EINT
IRQ irq

external_reset_request

SCPSYS FSM reset

Thermal
PAD_WATCHDOG
WDT

RESET_B wdt_event
PMIC

Figure 5-1 Block Diagram of TOPRGU

5.5.4 Function Description

TOPRGU is responsible for generating and distributing reset signals to various subsystems to ensure that the system
operates in a stable and reliable manner.

In addition, enhanced features such as a watchdog timer, configurable handling mode to reset requests, and dual-mode
reset event handling are provided for advanced usage.

 Watchdog timer
 TOPRGU provides a watchdog timer that generates a timeout event when it counts down to 0.
 Watchdog timer can be used to reset the system or raise an interrupt to the system when a timeout occurs. For
detailed usage, see Section [Link] and [Link].

 Configurable handling mode to reset requests

 A configurable IRQ/reset mode selection is provided for each reset request to allow advanced event handling. This
allows reset requests to be handled as interrupts to fit application needs. See Section [Link].

 Dual-mode reset event handling

 Dual-mode allows the watchdog timer to trigger an IRQ first upon a reset event, followed by a watchdog reset if
the watchdog timer times out again. Detailed usage can be found in Section [Link].

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5.5.5 Reset IO Signal Descriptions

Table 5-13 presents Reset signal description.

Table 5-13 Reset Signal Descriptions

Signal Name Type Description Ball Location
SYSRSTB DI System reset input T32
WATCHDOG DO Watchdog reset output K34

5.5.6 Theory of Operation

The TOPRGU includes three distinct stages of operation.

1. The IDLE state: No reset event has occurred and the watchdog counter is kicked periodically.
2. The IRQ state: When a reset event occurs for the first time in the dual-mode, the TOPRGU triggers an interrupt
instead of a reset. The watchdog counter automatically restarts and waits for a timeout again. For more details about
the dual-mode, refer to Section [Link].
3. The Reset state: When the watchdog counter times out again, the TOPRGU triggers a watchdog reset to reset the
entire chip.

5.5.7 Programming Guide

[Link] TOPRGU Initialization

The TOPRGU is set to the dual-mode by default; however, there are two ways to change its behavior. Note that the bold
text in this section indicates the corresponding register name.

1. Trigger PAD_ SYSRSTB to reset the WDT_MODE to the default value. Note that this register cannot be reset by the
watchdog reset.
2. Program WDT_MODE.

[Link] Program Watchdog Timer Length

The watchdog counter is kicked periodically, with the period referred to as the "Watchdog Timer length". The configuration
steps are as follows.

1. Set wdt_en(WDT_MODE[0]) to 1’b1.

2. Update WDT_LENGTH and trigger WDT_RESTART.

[Link] IRQ Mode

The TOPRGU is set to the dual-mode by default while all reset requests are in the IRQ mode by default. This means that the
interrupt is triggered (instead of the watchdog reset) immediately. To trigger the watchdog reset but not the interrupt, the
corresponding configuration of each reset request can be changed so that it is configured either as a reset or as an IRQ.

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[Link] Dual-Mode Reset

The dual-mode in the TOPRGU means that an IRQ is triggered first when a reset event occurs, followed by a watchdog
reset if the watchdog timer times out again.

The watchdog timer auto-restarts after an interrupt is triggered. The AP should clear the WDT_STA after receiving the
interrupt from the TOPRGU. When the interrupt is issued, the watchdog timer is restarted to {WDT_LENGTH, {9{1’b1}}}
and the watchdog reset is triggered when the timer expires. {WDT_LENGTH, {9{1’b1}}} means that the WDT timeout
period is a multiple of 512*T32k = 15.6 ms.

To configure the dual-mode, perform the following steps:

1. Set wdt_en (WDT_MODE[0]) = 1’b1.

2. Set dual_mode (WDT_MODE[6]) = 1’b1.

5.5.8 Register Definition

Refer to “MT8390 Register Map” for detailed register descriptions.

5.6 DSI Specifications

Table 5-14 presents MIPI D-PHY TX electrical characteristics.

Table 5-14 DSI D-PHY TX Electrical Characteristics

Description Min. Typ. Max. Unit Note
High-Speed data rate 125 - 1200 Mbps
High-Speed common mode voltage 150 200 250 mV
High-Speed differential output voltage 140 200 270 mV
High-Speed single ended output high voltage - - 360 mV
High-Speed single ended output impedance 40 50 62.5 Ω
- - 0.3 UI 1
High-Speed 20%-80% rise time and fall time - - 0.35 UI 2
100 - - ps 3
Low-Power output high level 0.95 1.2 1.3 V
Low-Power output low level -50 - 50 mV
Low-Power output impedance 110 - - Ω
Low-Power 15%-85% rise time and fall time - - 25 ns
1. Applicable when supporting maximum HS bit rates ≤ 1 Gbps (UI ≥ 1 ns)
2. Applicable when supporting maximum HS bit rates > 1 Gbps (UI ≤ 1 ns) but less than ≤ 1.5 Gbps
3. Applicable when supporting maximum HS bit rates ≤ 1.5 Gbps

Table 5-15 presents MIPI C-PHY TX electrical characteristics.

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Table 5-15 DSI C-PHY TX Electrical Characteristics

Description Min. Typ. Max. Unit Note
High-Speed symbol rate 125 - 1100 Msps
High-Speed common mode voltage 175 225 to 250 310 mV
High-Speed differential output voltage of strong one - - 300 mV
High-Speed differential output voltage of weak one 97 - - mV
High-Speed single ended output high voltage - - 425 mV
High-Speed single ended output impedance 40 50 60 Ω
High-Speed rise time and fall time from -58mV to 58mV - - 0.4 UI
Low-Power output high level 0.95 1.2 1.3 V
Low-Power output low level -50 - 50 mV
Low-Power output impedance 110 - - Ω
Low-Power 15%-85% rise time and fall time - - 25 ns

5.7 CSI-2 Specifications

Electrical characteristics are compatible with MIPI D-PHY Specification Revision 1.2.

Table 5-16 CSI D-PHY RX Electrical Characteristics

Description Min. Typ. Max. Unit Note
High-Speed data rate 80 - 2500 Mbps
High-Speed common point voltage 70 - 330 mV
High-Speed differential input high voltage - - 40 mV
High-Speed differential input low voltage -40 - - mV
High-Speed single ended input high voltage - - 460 mV
High-Speed single ended input low voltage -40 - - mV
High-Speed differential input impedance 80 100 125 Ω
Low-Power logic 1 input voltage 740 - - mV
Low-Power logic 0 input voltage - - 550 mV
Low-Power input hysteresis 25 - - mV
Minimum pulse width response 20 - - ns

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6 Clock Characteristics

The device has two external input clocks—low frequency (RTC32K_CK) and high frequency (X26M_IN).
Figure 6-1 shows the external clock sources and clock outputs.

Figure 6-1 Device Clock Diagram

6.1 Maximum Performance Ratings

Table 6-1 presents the maximum core and peripheral performance limitations and correlations.

Table 6-1 Maximum Performance Ratings

Module Max. Unit
Dual-core Arm Cortex-A78 A78 2200 MHz
Hexa-core Arm Cortex-A55 A55 2000 MHz
Graphics Accelerator GPU 950 MHz
HiFi 5 DSP DSP 800 MHz
VP6 832 MHz
AI Processor Unit
MDLA 900 MHz
System Companion Processor SCP 832 MHz
External Memory Interface LPDDR4(X) 3733 Mbps
SD Card 100 MBps
Memory Card Controller
eMMC 400 MBps

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Module Max. Unit

SDIO 100 MBps
Serial NOR Flash Interface SNOR 52 MHz
Digital Display Parallel Interface DPI 148 MHz
High-Definition Multimedia Interface Transmitter HDMITX 594 MHz
DisplayPort DPTX 5.4 Gbps/lane
Embedded DisplayPort Interface EDPTX 5.4 Gbps/lane
DSI D-PHY 1.5 Gbps/lane
Display Serial Interface
DSI C-PHY 1.1 Gsps/trio
Image Signal Processor ISP 32 MPix@30fps
CSI D-PHY 2.5 Gbps/lane
Camera Serial Interface 2
CSI C-PHY 4.5 Gsps/trio
Video Encoder VENC 624 MHz
Video Decoder VDEC 594 MHz
I2S master mode
192 kHz
(sampling frequency)
Inter-IC Sound
I2S slave mode
192 kHz
(sampling frequency)
Programmable Command Master Interface PCM (sampling frequency) 48 kHz
Pulse Density Modulation PDM 3.25 MHz
TDM
Time Division Multiplexed Interface 48 kHz
(sampling frequency)
Digital Interface SPDIF 192 kHz
I2C mode 3.4 Mbps
Inter-Integrated Circuit
I3C mode 12.5 Mbps
Universal Asynchronous Receiver/Transmitter UART 961,200 bps
Serial Peripheral Interface SPI master 52 MHz
USB SuperSpeed 5 Gbps
USB High-Speed 480 Mbps
Universal Serial Bus
USB Full-Speed 12 Mbps
USB Low-Speed 1.5 Mbps
MII 25 MHz
Ethernet Network Interface Controller RMII 50 MHz
RGMII 125 MHz
Peripheral Component Interconnect Express PCIe 8.0 GT/s
Pulse Width Modulation PWM 39 MHz
Auxiliary ADC AUXADC (clock rate) 3.25 MHz

6.2 PLL Spec

Table 6-2 shows ARMPLL_LL specifications.

Table 6-2 ARMPLL_LL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz

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Parameter Min. Typ. Max. Unit

FOUT Output clock frequency 2000 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-3 shows ARMPLL_BL specifications.

Table 6-3 ARMPLL_BL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 2252.25 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-4 shows CCIPLL specifications.

Table 6-4 CCIPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 1600 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-5 shows ETHPLL specifications.

Table 6-5 ETHPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 500 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
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Parameter Min. Typ. Max. Unit

AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-6 shows MSDCPLL specifications.

Table 6-6 MSDCPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 416.14648 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-7 shows TVDPLL1 specifications.

Table 6-7 TVDPLL1 Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 594.177 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-8 shows TVDPLL2 specifications.

Table 6-8 TVDPLL2 Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 594.177 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-9 shows MPLL specifications.

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Table 6-9 MPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 208.03 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-10 shows MMPLL specifications.

Table 6-10 MMPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 2750.048 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-11 shows MAINPLL specifications.

Table 6-11 MAINPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 2184.359 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-12 shows IMGPLL specifications.

Table 6-12 IMGPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 660 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %

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Parameter Min. Typ. Max. Unit

tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-13 shows UNIVPLL specifications.

Table 6-13 UNIVPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 2496.006 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-14 shows ADSPPLL specifications.

Table 6-14 ADSPPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 800 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-15 shows APLL1 specifications.

Table 6-15 APLL1 Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 196.001 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

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Table 6-16 shows APLL2 specifications.

Table 6-16 APLL2 Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 196.001 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-17 shows APLL3 specifications.

Table 6-17 APLL3 Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 196.001 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-18 shows APLL4 specifications.

Table 6-18 APLL4 Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 196.001 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-19 shows APLL5 specifications.

Table 6-19 APLL5 Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 196.001 MHz

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Parameter Min. Typ. Max. Unit

tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

Table 6-20 shows MFGPLL specifications.

Table 6-20 MFGPLL Specifications

Parameter Min. Typ. Max. Unit
FIN Input clock frequency 26 MHz
FOUT Output clock frequency 390 MHz
tSET Settling time 20 μs
FOUT(D) Output clock duty cycle 45 50 55 %
tJ(CLK) Output clock jitter (period jitter) 100 ps
DVDD Digital power supply 0.54 0.8 0.88 V
AVDD18 Analog power supply 1.71 1.8 1.89 V
AVDD12 Analog power supply 1.14 1.2 1.26 V

6.3 Clock Squarer

The Clock Squarer (CKSQ) is designed to receive clock signal from pin “X26M_IN” and distribute it to the chip internally.

Table 6-21 shows the CKSQ specifications.

Table 6-21 CKSQ Specifications

Symbol Parameter Min. Typ. Max. Unit
VIN Input signal amplitude 1,000 1,200 1,250 mVpp
DcycIN Input signal duty cycle 50 %
DcycOUT Output signal duty cycle DcycIN - 5 DcycIN + 5 %
Maximum positive overshoot 1.3 V
Minimum negative overshoot -0.1 V

6.4 Clock Signal Descriptions

Table 6-22 Clock Signal Descriptions
Signal Name Type Description Ball Location
RTC32K_CK DI RTC 32kHz clock input N37
X26M_IN AI 26 MHz clock input AE34
Output signal; control of PMIC 26 MHz / Buck / LDO normal mode or sleep
SRCLKENA0 DO High: Normal mode L33
Low: Sleep mode or low power mode

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Signal Name Type Description Ball Location

SRCLKENA1 DO Output signal; control of PMIC 26 MHz / Buck / LDO on or off L34

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7 Package Information

7.1 Thermal Specifications

7.1.1 Thermal Operating Specifications

Table 7-1 and Table 7-2 present the thermal resistance characteristics and maximum operating temperatures of the device.

Table 7-1 MT8390 AV/AZA Thermal Operating Specifications

Symbol Description Value Unit
θJA Package thermal resistances in natural convection 22.1 °C/Watt
θJB Package thermal resistances of junction-to-board 4.5 °C/Watt
θJC Package thermal resistances of junction-to-case 2.89 °C/Watt
TJ Max. operating junction temperature 95 °C

Table 7-2 MT8390 IV/KZA Thermal Operating Specifications

Symbol Description Value Unit
θJA Package thermal resistances in natural convection 21.9 °C/Watt
θJB Package thermal resistances of junction-to-board 4.5 °C/Watt
θJC Package thermal resistances of junction-to-case 0.82 °C/Watt
TJ Max. operating junction temperature 105 °C

7.2 Top Marking

Figure 7-1 shows the device top marking definition.

MEDIATEK
ARM
NNNNNN#N
YYWW-&&&&&
XXXXXX-%

Figure 7-1 Top Marking

Table 7-3 presents the printed device reference and decoding.

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Table 7-3 Printed Device Reference and Decoding

Parameter Value Description
NNNNNN#N Part number MT8390#V Product family
A for consumer-grade
#: Function code 1 -
I for industrial-grade
YYWW Date code - 2-digits year and week code
&&&&& Lot number - For internal use only
- A: PKG θJC=2.89°C/W
% Function code 2
K: PKG θJC=0.82°C/W
O Pin one designator - Pin one location

7.3 Mechanical Drawing

The following figure shows printed device reference diagram (MFC VFBGA 15.0 mm × 15.0 mm, 1204-ball, 0.4 mm pitch
package).

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8 Legal and Support Information

8.1 Related Documents and Products

Documents:
 MMD (MediaTek Module Design)—Power Delivery Network (PDN) and DRAM design implementation solutions
 MT8390 Baseband Design Notice—Application note including schematic examples for peripheral interfaces such as
GPIO, MSDC, SPI NOR, LPDDR4X, I2C/I3C, SPI, Display, Camera, USB, DPI, Ethernet, HDMI, PCIe, Audio, and power
design implementation recommendations.
 MT6319 Application Note for MT8390—MediaTek MT6319 PMIC application note covering functional description and
PCB layout guidelines.
 MT6365 Application Note for MT8390—MediaTek MT6365 PMIC application note covering functional description and
PCB layout guidelines.
 MT6680 Application Note for MT8390—MediaTek MT6680 PMIC application note covering functional description and
PCB layout guidelines.
 MA5721F Application Note for MT8390—MediaTek MA5721F PMIC application note covering functional description
and PCB layout guidelines.

Companion chips:
 MT6319—Integrated Power Management IC (PMIC)
 MT6365—Integrated Power Management IC
 MT6680—Integrated Power Management IC
 MA5721F—Integrated Power Management IC

8.2 Trademarks
Arm, Jazelle, Cortex, TrustZone, AMBA, and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US
and/or elsewhere.

Mali, CoreSight, Neon, and DynamIQ are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

Vulkan is a registered trademark of the Khronos Group, Inc.

PCIe is a registered trademark of PCI-SIG.

Cadence and Tensilica are registered trademarks of Cadence Design Systems, Inc.

HDMI is a trademark of HDMI Licensing, LLC.

I2C and I2S are trademarks of NXP Semiconductors.

OpenCL is a trademark of Apple, Inc.

SD is a registered trademark of SD Card Association.

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MMC and eMMC are trademarks of MultiMediaCard Association.

MIPI and MIPI I3C are registered trademarks of MIPI Alliance, Inc.

DisplayPort is a trademark of VESA.

Linux is a registered trademark of Linus Torvalds.

Android is a trademark of Google LLC.

Intel is a registered trademark of Intel Corporation or its subsidiaries.

All other product or service names are the property of their respective owners.

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