Unit1
1. State De-Morgan’s theorem.
2. Express the function Y = A + BC in canonical SOP.
3. Convert the given decimal numbers to their binary equivalent 108.364.
4. Outline the concept of duality in Boolean algebra.
5. Simplify the following Boolean expression into one literal.
W’X (Z’+YZ) + X (W+Y’Z).
6. Convert (115)10 and (235)10 into hexadecimal numbers.
7. Define ‘Minterm’ and ‘Maxterm’.
8. Draw the active high tri-state Gate & write its truth table.
9. Show how to connect NAND gates to get an AND gate and OR gate
10. Write the principle of Distributive law.
11. Interpret the truth table of EX- OR gate.
12. Reduce the expression a AB'C + A'B'C using Boolean theorems.
13. Apply De-Morgan’s theorem to simplify (A+BC')'
14. Implement Y= ∑m(1,4,5,6,7) in SOP form using AOI logic.
15. Implement the given function using NAND gates only. F(X, Y, Z) =
∑m(0,6)
16. Find the equivalent Gray code for [10110]2
17. What is meant by Prime Implicants and Essential prime implicants?
18. How can we minimize Boolean expression of the below function?
F=XY+X(Y+Z) +Y(Y+Z).
19. If A & B are Boolean variables and if A=1 & (A+B)'=0, determine B?
20. Convert (743)8 and (241)8 into binary.
Part B&C
1. Using K-map method, Reduce the following Boolean function
F=∑m(0,2,3,6,7) + d(8,10,11,15) and obtain minimal SOP.
2. Write the minimized Boolean expression for the function using K-map and
draw the logic diagram. F (w,x,y,z)= ∑m(0,1,2,4,5,6,8,9,12,13,14) .
3. Find the Minimized logic function using K-Maps. F (A, B, C, D) =
∑m(1,3,5,8,9,11,15) + d(2,13) . Implement the minimal SOP using NAND
and NOR gates.
4. Elaborate the minimization of the given Boolean function using Quine-Mc-
Cluskey method F= ∑m(0,1,2,5,7,8,9,10,13,15) . Realize the simplified
function using logic gates.
5. Develop the following Function using Tabulation method
F= ∑m(1,2,3,7,8,9,10,11,14,15) and realize the circuit using only NAND
Gates.
6. (i) Implement Y= (A + C)(A + D')(A + B + C')
(ii) Solve by perfect induction
(a) A+AB = A
(b) A(A+B) = A
(c) A+A’B = A+B and
(d) A(A’+B) =AB
7. Prepare Karnaugh Map for the following functions and draw the logic
diagram using basic gates.
(i) Y(A,B,C,D)=П M (0,1,3,5,6,7,10,14,15)
(ii) Y (A, B, C) =П M (0,2,4,5,6)
8. (i) Convert (725.25)8 to its decimal, binary and Hexadecimal equivalent.
(ii) Find 1’s and 2’s Complement of 8 digit binary number 10101101.
1. Design the given function using Prime implicant method and Verify your
result using K map F= ∑m(0,1,2,4,5,6,8,9,12,13,14) .
2. Determine the minimal Sum of Products for the following function
F(w,x,y,z)=∑m(1,3,4,5,9,10,11)+∑d(3,4,11) using Quine McCluskey method
and apply DeMorgan’s theorem for NAND -NOR implementation.
3. Construct a Karnaugh Map for the following function
F(A,B,C,D,E)=∑(0,5,6,8,9,10,11,16,20,24,25,26,27,29,31) and draw the logic
diagram.
4. A staircase light is controlled by two switches , one is at the top of the stairs
and the other is at the bottom of the stairs :
(i) Make a truth table for this system.
(ii) Write the logic function in SOP form.
(iii) Realize the circuit using AOI logic.
(iv) Realize the circuit using minimum number of NAND and NOR gates.
Unit 2
Part A
[Link] is meant by combinational circuits?
2. Determine the Boolean expression for a half adder.
3. Summarize the design procedure of combinational circuits.
4. How do you draw a full adder circuit?
5. Sketch the logic circuit of Half subtractor.
6. Implement full adder using half adders.
7. Distinguish between half subtractor and full subtractor.
8. State the concept of parallel binary adder.
9. Why carry look ahead adder is faster than ripple carry adder and full adder?
10. Compare the function of decoder and encoder.
11. Design a 2:1 Multiplexer.
12. Convert a two-to-four line decoder with enable input to 1:4 demultiplexer.
13. Identify the function of select inputs of a MUX.
14. How does a 1-bit comparator work?
15. Obtain the design of the given function using suitable multiplexer
F= Σm(0,2,5,7).
16. Interpret the characteristics of demultiplexer.
17. Asses the purpose of encoder.
18. Outline the characteristics of a priority encoder and how it differs from a
regular encoder?
19. Sketch the logic diagram of 2 to 4 decoder.
20. Outline the applications of Multiplexer.
Part-B & C
1. Describe about multiplexer and Simplify the following function using 8x1
Mux F= Σ(0,1,3,4,8,9,15) .
2. Write a brief note on the following combinational circuits: (i) Full adder (ii)
Full subtractor
3. Demonstrate on a 2-bit magnitude comparator with three outputs: A>B,
A=B and A<B.
4. Derive the circuit that implements an 8-to-3 binary encoder with neat
diagram.
5. Realize the function F(w, x, y, z)= Σ m(1,4,6,7,8,9,10,11,15) using 8 to 1
Multiplexer.
6. Discuss about the purpose of decoder and Implement a full adder and full
subtractor using decoder.
7. (i) Realize a circuit to carryout both addition and subtraction.,
(ii) How would you design a 1:8 demultiplexer circuit?
8. Explain the concept of priority encoder with truth table, Boolean expression
and logic diagram.
9. Find the Boolean expression of 2 to 4 decoder & 3 to 8 decoder and draw
the logic diagram from the truth table.
10. (i) Analyze the design of 8 x 1 multiplexer using only 2 x 1 multiplexer.
(ii) Formulate the following Boolean function using 4 x 1 multiplexers.
F( A, B,C, D)= Σ m(1,2,3,6,7,8,11,12,14) .
1. Implement the following Boolean function using an 8:1 multiplexer
considering D as the input and A,B,C as selection lines : F( A, B, C, D) =
AB’+BD+B’CD’
2. Design a certain logic circuit using 4x1 Multiplexer which has four inputs
A, B, C, and D. The output X of the circuit is logic 1 if two or more inputs are
logic 1.
3. Develop the circuit that compares two 4-bit numbers and Explain the design
procedure with truth table, Boolean expression and logic diagram.
4. With necessary diagrams, explain in detail about the working of a 4-bit look
ahead carry adder. Also mention its advantages over conventional adder
UNIT-3
1. List the classification of Sequential circuits.
2. Write the differences between Mealy and Moore circuits.
3. Define the term "state table"
4. Prepare the truth table for JK Flip flop.
5. Construct the state diagram of Mod-10 ring counter.
6. Draw the circuit diagram of ring Counter.
7. How many flip-flops are required to build a binary counter that counts from
0 to 7?
8. Summarize the excitation table of JK FF.
9. Analyze the differences between Latch and Flip-Flop.
10. Examine how does a ripple counter differ from a synchronous counter?
11. Distinguish between synchronous sequential circuits and asynchronous
sequential circuits.
12. Model a NAND based logic diagram of JK FF.
13. Compute the minimum number of flip-flops needed to design a counter of
Modulus 10.
14. Tabulate the differences between edge triggering and level triggering in
sequential circuits.
15. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. calculate
the Q output .
16. Outline the primary disadvantage of asynchronous counter.
17. Enumerate the D-Latch FF with truth table.
18. Illustrate the logic diagram of a clocked SR Flip-flop.
19. Draw the state diagram and characteristics equation of a T FF
20. For the D Flip Flop sketch the state diagram and denote the characteristics
equation.
Part B&C
1. (i) What is Flip flops? Write about the operations of different flip flops.
(ii) List the application of Flip flop.
2. How does a BCD ripple counter works. Explain with a timing diagram.
3. (i) Write the different type of clock pulse methods.
(ii)Enumerate about Triggering method for Flip-Flop.
4. Explain in detail about the pulse- triggered S-R Flip Flop with necessary
diagrams.
5. Using D flip-flop, Design a synchronous counter which counts in the sequence
000,001,010,011,100,101,110,111,000.
6. Determine the state table, characteristic table and an excitation table for D Flip
Flop.
7. (i) Examine a synchronous MOD-6 counter and explain the operation.
(ii) Analyze the MOD-6 counter with an appropriate waveform
8. Evaluate the design procedure of the Sequential circuit that has three flip flops
A, B, and C; one input X_in ; and one output Y_out. The state diagram is shown
in below figure. The circuit is to be designed by treating the unused states as don’t
care conditions. Analyze the circuit obtain from the design to determine the effect
of the unused [Link] T flip flops in the design.
9. Using SR flip flops, design a parallel counter which counts in the sequence
000,111,101,110,001,010,000,…
10. Summarize 4-bit SISO SIPO, PIPO and PISO shift register and draw its
waveforms.
11. (i) Reduce the following state table and tabulate the reduced state table.
ii) Examine the design of Synchronous counter with states
0, 1, 2, 3, 0, 1,.... using JK flip flop.
1. Design a J-K counter for the states 3, 4, 6 , 7 and 3.
2. Design a Synchronous BCD Counter using Flip-Flops and explain its
operation.
3. Devise a model of a D FF counter for the states 1, 5, 8,9,10, 11.
4. Develop a state table, characteristic table and an excitation table for SR Flip
Flop.
