EECS 3201: Midterm Review
Lecture 1: Digital Systems & Binary Numbers
1. Number Base Conversion:
○ Decimal to Binary (Integer Part):
■ Divide the number by 2.
■ Record the remainder.
■ Repeat the division process until the quotient is 0.
■ The binary number is the remainders read in reverse order.
○ Decimal to Binary (Fractional Part):
■ Multiply the decimal fraction by 2.
■ Record the integer part.
■ Repeat until you reach the desired precision.
○ Concatenating Integer and Fractional Parts:
■ Example: Decimal 41.6875 -> Integer part = 41 -> 101001, Fractional
part = 0.6875 -> 1011.
■ Final binary = 101001.1011.
2. Diminished Radix Complement & Radix Complement:
○ Diminished Radix Complement:
■ Found by subtracting each digit from the number from the largest digit
in that number system, but specifically from r-1 where r is the largest
number
■ For example in base 10 we would subtract from r-1 or 10-1 so from 9.
Diminished radix of 5236 is 9999-5236=4763
○ Radix Complement:
■ Obtained by adding 1 to the diminished radix complement answer
○ Subtraction with Complements:
■ Convert the subtrahend into its complement
■ Add it to the minuend
■ If using diminished, add 1 after summing
■ Discard any carry
■ If no carry take the complement of the result and add a negative sign
3. Binary Codes (BCD):
○ BCD represents each decimal digit by a 4-bit binary number.
■ Example: Decimal 184 -> BCD = 0001 1000 0100.
4. Register Transfer:
○ Transfer of binary data between registers.
○ Example: Moving data from memory to processor register or input register in
a processor.
5. Binary Logic (Logic Gates):
○ AND, OR, NOT gates.
■ Example:
■ AND: 1 & 1 = 1, 1 & 0 = 0.
■ OR: 1 | 0 = 1, 0 | 0 = 0.
■ NOT: ¬1 = 0, ¬0 = 1.
Lecture 2: Boolean Logic
1. Basic Definitions:
○ Closure: Operations on elements of a set result in an element of the same
set.
○ Associative Law: A+(B+C)=(A+B)+CA + (B + C) = (A + B) + C,
A⋅(B⋅C)=(A⋅B)⋅CA
○ Commutative Law: A+B=B+A, A⋅B=B⋅A
○ Identity Element: A+0=A, A⋅1=A
○ Inverse: A+¬A=1, A⋅¬A=0
○ Distributive Law: A⋅(B+C)=(A⋅B)+(A⋅C)
2. Two-Valued Boolean Algebra:
○ Boolean algebra is based on two values: 0 (false) and 1 (true).
3. Duality Principle:
○ Every algebraic expression deductible from the postulates of Boolean algebra
remain valid is the operators and identity elements are interchanged
○ The dual of a Boolean expression is obtained by interchanging AND and OR,
and 1s and 0s.
○ Do not complement the literals
4. Basic Theorems and Postulates of Boolean Algebra
*Operation Precedence for Boolean Algebra: Parantheses, NOT, AND, and OR*
5. Boolean Functions:
○ Functions defined using AND, OR, and NOT operations on Boolean variables.
○ Can be represented in a truth table
○ Can also be represented in algebraic form, in a variety of ways
- Expression used will dictate the interconnection of gates
- Interconnection of gates will dictate the logic expression
- Can manipulate a boolean expression according to the rules of
Boolean algebra to get a simpler expression
Example:
○ Complement of a function is obtained by interchanging AND and OR
operators and complementing each literal. Taking the dual refers to swapping
AND and OR operations. FIrst take dual, then complement the literals
A summary of Boolean Functions
6. Minterms and Maxterms:
○ Minterms: AND of all variables (can be 1
or 0).
○ Maxterms: OR of all variables (can be 1 or
0).
How to get sum of minterms to get the function
● The minterm whose sum defines the boolean functions are the ones which give 1 in
the function senction of the truth table
● If the function is not in this form, it can be ANDed with an expression such as
(x+x’)
How to get product of maxterms to get the function from truth table
● To get function to a certain form, you can use distributive law
● Can OR with xx’
7. Conversion between Canonical Forms (from sum of minterms to product of
maxterms
8. Sum of Products (SOP):
○ Expression in the form of AND operations followed by OR operations.
9. Product of Sums (POS):
○ Expression in the form of OR operations followed by AND operations.
10.Positive and Negative Logic:
○ Positive logic: Higher voltage is 1, lower voltage is 0.
○ Negative logic: Lower voltage is 1, higher voltage is 0.
11.Digital Logic Gates:
○ Inverted - requires 2 transistors
○ Buffer - equivalent to two inverters connected in cascade
○ OR - requires 6 transistors
○ NOR - complement of OR - requires 4 transistors (desirable)
○ AND - requires 6 transistors
○ NAND - complement of AND - requires 4 transistors (faster than NOR, more
desirable)
○ XOR - requires 12 transistors
○ XNOR requires 12 transistors (desirable)
Lecture 3: Logic Gate Minimization & K-Map
1. Gate Level Minimization:
1. Simplifying Boolean expressions to reduce the number of gates.
2. K-Map:
1. A graphical method for minimizing Boolean functions.
2. Three-Variable K-Map:
■ 2x4 grid for three variables (A, B, C).
3. Four-Variable K-Map:
■ 4x4 grid for four variables (A, B, C, D).
4. Grouping Procedure:
■ Group 1s in powers of 2 (1, 2, 4, 8) to minimize terms.
3. Product-of-Sums (POS) vs Sum-of-Products (SOP):
1. SOP (Sum of Products): A Boolean expression where 1s in the K-map are
grouped into the largest possible AND terms, then ORed together.
2. POS (Product of Sums): A Boolean expression where 0s in the K-map are
grouped into the largest possible OR terms, then ANDed together.
4. Don’t Care Conditions:
- Irrelevant combinations from the truth
table(usually specified) which can be
written as X in the k-map and used as
either 1 or 0, depending on what helps
the simplificaition the most. Can be
used as 1 to make bigger combinations.
5. Seven-Segment Display Logic:
6. NAND, NOR, XOR Implementation:
1. NAND: Can be used to create all other gates.
2. NOR: Also universal.
3. XOR: Useful for parity checks.
7. Step-by-Step for K-map Questions:
1. Write the Boolean expression.
2. Create the K-map with corresponding cells.
3. Group adjacent 1s or 0s.
4. Write the minimized Boolean expression based on the grouping.
Lecture 4: HDL (Verilog and VHDL)
1. HDL (Verilog and VHDL):
○ Verilog: Used for describing hardware circuits in digital logic design.
○ VHDL: Another HDL, more verbose but also widely used.
2. Verilog Data Types:
○ reg: Used for variables that hold values.
○ wire: Used for connecting components.
3. Verilog Module Structure:
4. Verilog Numbers:
5. Ports in Verilog:
6. Verilog Operators:
7. Verilog Three-state Gates:
Allow a signal to be in one of three states: 1, 0, or high-impedance (z).
8. Boolean Expressions in Verilog:
Use logic gates and operators to define digital behavior. And use “assign” to apply a
boolean expression.
9. Gate Delays:
Use #delay to simulate time delays in gates.
10.Test Bench:
A block used to simulate and test Verilog designs.
11.User Defined Primitives (UDP):
Allows the creation of custom logic functions.
12.Multi-bit Signals:
Use vectors (e.g., reg [7:0] data).
13.Continuous Assign Statement:
Used to assign values to wires continuously.
14.Conditional Terms:
15.Always Statement:
