Optimum Charge Pump Frequency Design for

SMART Power Technologies

Francesco Morandotti

22 November 2017
Contents

1 Introduction 3

2 Charge Pump History 5

2.1 Cockcroft-Walton . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Buck and Boost converters . . . . . . . . . . . . . . . . . . . . 7
2.3 Dickson Charge Pump . . . . . . . . . . . . . . . . . . . . . . 8

3 Charge Pump design Metrics 12

3.1 IV characteristic . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Circuit Topologies 16
4.1 Switched Mode Power Supply . . . . . . . . . . . . . . . . . . 16
4.2 Voltage Doubler . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Dickson Charge Pump . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Presented Charge Pump . . . . . . . . . . . . . . . . . . . . . 27
4.5 Charge Pump Core . . . . . . . . . . . . . . . . . . . . . . . . 28

5 Frequency Optimization 32
5.1 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 Clock Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 Charge Pump Characterization . . . . . . . . . . . . . . . . . 38
5.4 Bucket Capacitor Sizing and Frequency . . . . . . . . . . . . . 40
5.5 Blocking the Backwards path . . . . . . . . . . . . . . . . . . 44
5.6 Capacitors Current Leakage . . . . . . . . . . . . . . . . . . . 45
5.7 Area Consumption and Efficiency . . . . . . . . . . . . . . . . 47

1
6 Electromagnetic Interference Simulations 50
6.1 Line Impedance Stabilization Network . . . . . . . . . . . . . 50
6.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 52

7 Conclusions 58

Bibliography 58

2
 Abstract

Charge Pumps are integrated circuits able to step up the voltage over
chip supply without the need for external components. The first charge
pump was designed in 1976, and their development followed without impres-
sive advancements the development of flash memories, its main application,
up to recent years. In the last decade charge pumps have become an ever
trending topic in electronic literature, and we have witnessed the emergence
new applications.
The automotive industry aspires to innovation and more automation,
therefore electronics are becoming increasingly more important and a sizable
constituent of car the production cost. In this context high side switches
are among the most requested devices which require a charge pump in their
operation.
The aim of this thesis is to investigate different DC-DC converters topolo-
gies and to develop a high frequency cross coupled charge pump to reliably
turn on and assure low ohmic operation of the power double-diffuse MOS
transistor of a high side switch, while keeping a low electromagnetic noise
emission profile. Both the clock generator and the charge pump high fre-
quency behavior will be discussed.
The simulation has been conducted using Cadence Spectre Circuit Simu-
lator and the Infineon technology process libraries for SMART power appli-
cations. The electromagnetic compatibility analysis has also been performed
within the Spectre environment using a custom Ocean script developed by
Infineon EMC group.
List of Figures

2.1 Cockcroft and Walton generator equivalent circuit . . . . . . . 6

2.2 Split-π Converter Schematic . . . . . . . . . . . . . . . . . . . 7
2.3 Dickson Charge Pump Schematic . . . . . . . . . . . . . . . . 8
2.4 A floating gate transistor for memory applications . . . . . . . 10

3.1 IV characteristic design metric . . . . . . . . . . . . . . . . . . 13

4.1 Schematic of a Buck converter . . . . . . . . . . . . . . . . . . 17

4.2 Schematic of a Boost converter . . . . . . . . . . . . . . . . . 19
4.3 Schematic of a Marx generator . . . . . . . . . . . . . . . . . . 22
4.4 Schematic of a Voltage Doubler Charge Pump . . . . . . . . . 23
4.5 Two stages Dickson Charge Pump and non-overlapping clock
scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.6 Auxiliary switches improvement on the Dickson charge pump . 26
4.7 Presented Cross Coupled Charge Pump schematic . . . . . . . 28
4.8 Presented Charge Pump start up and stabilization . . . . . . . 30
4.9 Simulated detail of a single charge packet transfer to output . 31

5.1 Schmitt Trigger circuit schematic . . . . . . . . . . . . . . . . 33

5.2 Generating the second and third clock signal line . . . . . . . 36
5.3 Clock Signal Combination Chart . . . . . . . . . . . . . . . . . 37
5.4 Low load condition charge pump characterization . . . . . . . 38
5.5 Medium load condition charge pump characterization . . . . . 39
5.6 High load condition charge pump characterization . . . . . . . 39
5.7 Exponential output transient current . . . . . . . . . . . . . . 41
5.8 Fit of the output current . . . . . . . . . . . . . . . . . . . . . 42
5.9 Percentage of charge packet transferred to the output in re-
spect to the transfer time . . . . . . . . . . . . . . . . . . . . . 43
5.10 Capacitance Value in relationship to gate voltage in a general
MIS capacitor implemented with a PMOS transistor . . . . . . 46
5.11 Efficiency in respect to operating frequency sweep in low load
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1
5.12 Efficiency in respect to operating frequency sweep in medium
load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.1 CISPR-25 Automotive Standard Line Impedance Stabilization

Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 Electromagnetic noise emission profile at 50 µA current load . 53
6.3 Electromagnetic noise emission profile at 250 µA current load 55
6.4 Comparison between different charge pump designs output
current profiles . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2
Chapter 1

Introduction

In recent years we have witnessed an increasing demand for electronics in the

automotive industry. Among the various devices required by car manufac-
turers high side switches are of peculiar interest: these switches, in addition
to optimally driving currents to the various car subsystems, offer a wide
range of functionality including over-voltage and under-voltage protection,
temperature sensors, open-circuit or short-circuit detection as well as cur-
rent limitation. High Side Switches offer an innate advantage in respect to
low side switches; they require less wiring in the car, as the low supply is
readily available anywhere in the car being usually just the chassis, and they
also offer higher reliability by keeping the high potential line shorter, only
connecting the battery to the central unit [21]. The switch itself is realized
with a double-diffused metal-oxide-semiconductor (DMOS) N-type vertical
transistor: this means that the drain of the DMOS is the n-doped silicon
terminal connected to the high voltage of the external supply. If a P-type
DMOS was to be used there would be a highly non linear contact resistance
due to the pn junction formed between the p-doped substrate and the n-
doped epitaxy. Using a n-doped substrate the contact can be realized on
the back of the die saving precious area on the front side for more circuitry,
and allowing for a bigger contact to be implemented lowering the contact
resistance.
A charge pump is a DC-DC converter switched-capacitor circuit which takes
advantage of capacitive coupling in order to generate a voltage at a different
value from what is available from the chip supply, and it is therefore re-
quired to deliver a higher potential than the battery voltage to properly turn
on and control the gate of the discussed DMOS. Ideally the charge pump
performance increases with increasing size, but area is at a premium and
some other way of increasing the performance is sought-after: this work will
explore the possibility of increasing charge pump performance by increas-

3
ing the operation frequency. Whenever a high frequency switching circuit is
considered there is the additional challenge of electromagnetic interference
(EMI) which could lead to malfunction of the chip or of other nearby elec-
tronic devices [23]. The peaking currents and sharp transients required in
the operation of the charge pump introduce unwanted electromagnetic noise
which can couple with PCB traces, pins or, even worse, disturb the frequen-
cies reserved for signal transmission as radio or door key lock.

4
Chapter 2

Charge Pump History

A transformer is a device which allows to convert AC power at given voltage

and current levels to AC power at a different current and voltage level. The
power delivered cannot be increased by the conversion but, in an ideal lossless
scenario, the current-voltage product remains constant and either current or
voltage can be increased at the expense of the other quantity. A simple
transformer is built by winding insulated wires around a ferromagnetic core
in such way to produce two coils with a different amount of turns for each
coil. The input is connected to the primary coil and the output is connected
to the secondary coil. Due to Ampere’s circuital law when an alternating
current flows in the primary coil a variable magnetic field is generated and
amplified by the ferromagnetic material. The varying magnetic field induces
an alternating current in the secondary coil according to Faraday’s law of
induction. It’s worth noticing that both Ampere’s law and Faraday’s law,
together with Gauss’s laws, form the Maxwell equations. In an ideal trans-
former the voltage at the output is proportional to the voltage at the input
and the proportionality constant is equal to the number of turns of the sec-
ondary coil divided by the turns of the primary coil. The required voltage
can be obtained by choosing carefully the number of turns of the secondary
and primary coil. This process can only be sustained with alternating volt-
ages and currents as the laws of induction require time dependent quantities
and do not apply for constant DC currents and voltages: if a DC voltage or
current is required, as it often is, a rectifier is needed after the transformer,
but the rectifying process can be complicated and adds more inefficiencies to
the conversion losses.
Therefore it is interesting to study alternatives ways of generating a DC
voltage. A historical driving reason for the development of this kind systems
comes from the necessity in atomic and sub atomic physics experiments of
intense electric fields to accelerate particles. A possibility was explored by

5
physicist Van de Graaff in 1929. The Van de Graaff generator is able to
produce very high costant voltage potentials at low currents. It works by
running a rubber belt on an electrode which is charged by the triboelectric
effect. The charged electrode is connected to a large body, usually a hollow
metal sphere containing the electrode and the top roller, whose potential can
reach millions of volts. The other electrode can be either charged negatively
or left at ground potential. The Van de Graaff generator is bulky, requires
moving parts and is not generally able to generate currents of more than a
few hundred milliampere.

2.1 Cockcroft-Walton
In 1919 Greinacher first proposed a voltage multiplication technique consist-
ing on a series of diode capacitor stages and in 1939 this technique was used
by Walton and Cockcroft to generate voltages up to 800,000 volts in their
particle accelerator: their study on “Trasmutation of atomic nuclei by ar-
tificially accelerated atomic particles” won the Nobel Prize in 1951. They
used an elaborate stack of diodes and capacitors which when switched in the
right order could boost the relatively low voltage obtained from a regular
transformer to the high levels required by their experiments. It is important
to notice that the Cockcroft-Walton generator requires an AC input supply,
although a similar design could use a pulsated clock signal instead of the
sinusoidal AC wave. Consider figure 2.1:

Figure 2.1: Cockcroft and Walton generator equivalent circuit

While Vi is at a negative potential diode D1 conducts a current which

charges capacitor C1 . As Vi sweeps from the negative to the positive supply

6
voltages D1 is turned off while D2 starts conducting, and the same happens
in the second stage with D3 and D4 . Due to capacitive coupling the right had
plate of C1 is therefore raised to twice the positive supply potential, without
accounting for any losses. As the cycles continue all the capacitors in the
stack are subsequently charged. In general this converter is able to output
a potential proportional to the input swing times the number of stages. By
using discrete components for this charge pump the capacitors could be made
sufficiently large to grand an adequate efficiency while being cheaper and less
bulky than the other alternatives for generating high voltages. This type of
multiplier is not readily integrated on silicon because of the limited available
values for capacitance, usually just in the few picofarad range, much less
than what is available in discrete components. Other limitations of this
design include low current drivability, especially with many stages, and high
output resistance.

2.2 Buck and Boost converters

Other important switched DC-DC converter topologies are given by the buck
and boost converters: consisting of the same elements arranged differently,
the buck converter is used to step-down the voltage whereas the boost con-
verter is a voltage step-up converter. The analysis of the circuit behavior, the
operating modes and a few possible modifications of the standard topologies
are presented in chapter 4. Sometimes they are used together in a split-π
cascaded configuration by connecting the input of the buck converter at the
output of the boost converter [2], as pictured in figure 2.2.

Figure 2.2: Split-π Converter Schematic

The boost converter at the first stage generates an output voltage higher
than the input supply. The buck converter at the second stage steps down
the boosted voltage allowing for any ratio of the initial voltage supply to be

7
available. By controlling the switching scheme of S1 and S2 different voltages
above and below the input supply can be obtained from the same structure.
Lboost is the inductor for the boost step-up stage and Lbuck is the inductor
for the buck step-down stage. Switches S2d and S4d are often substituted for
diodes or diode connected transistors, as suggested in the brackets. With
this connection Cboost acts both as the filter capacitance for the first stage
and as the decoupling capacitance between both stages: it will absorb re-
turn the excess charge as needed, therefore mitigating the switching noise.
Although theoretically even the opposite combination of the buck-boost con-
verters could be implemented, it is not as common as the split-π converter
in literature [2]. The main limitation of the boost and buck topologies is
the inherent necessity of an inductor, which is not available as integrated
component. The value of the inductance and the size of the coil doesn’t have
to be as large as would be required for a transformer but the need for a
magnetic element, external from the chip and to be separately soldered on
the board, implicates more costs. DC-DC converters which do not require
for any magnetic element are categorized as charge pumps.

2.3 Dickson Charge Pump

In 1976 Dickson proposes a charge pump design that aims to overcome the
limitations introduced with the inductor [16]. A detailed explanation of the
Dickson charge pump topology is presented in chapter 4. In figure 2.3 a
generic Dickson charge pump is presented:

Figure 2.3: Dickson Charge Pump Schematic

It operates in a similar manner than the Cockcroft and Walton voltage

multiplier but with the difference the capacitors are connected in parallel and
not in series. In this configuration the capacitors must bear the whole clock

8
voltage swing but, if the technology process limits are respected, this allows
for a higher charge transfer between the stages which leads to improved per-
formance when a high current is in demand. A key parameter to choose when
adopting this technique is the value of the coupling capacitors in relation to
the value of the stray capacitance, which act as a capacitive divider at the
coupling nodes and decreases efficiency.
The equation describing the voltage of the output of the Dickson Charge
Pump is:

C IOut
VOutput = VSupply + n( VCLK − VD − ) − VD
C + Cp f (C + Cp )

Where VSupply and VCLK are the supply voltage and the clock swing re-
spectively, Cp is the parasite capacitance at every coupling node, n is the
number of stages employed and VD is the diode voltage drop between every
stage, assuming that the same diode device is used throughout the whole
design. The Dickson charge pump has been very successful topology, it is
reported in the all charge pump design specific textbooks [1] [2], and still
often presented in recent literature as the prime reference design [9]. The
study and design of charge pumps followed closely the development of semi-
conductor memory, of which is an essential component necessary to change
the logical state of the device. It is indeed remarked in the original Dickson
publication that the intended use for the presented charge pump design is
the application in a transistor-transistor logic (TTL) non-volatile quad latch
memory. At the time of Dickson’s publication the cutting edge memories
were floating gate MOSFET EPROM which would require up to 40 Volt
in order to change the state of the device. To understand the relationship
between the development of charge pumps and semiconductor memories it
is necessary to briefly overview the operation of a floating-gate MOSFET.
In this field effect transistor the gate terminal is left not connected and is
surrounded by non conductive layers, in particular it is isolated from the
channel by a insulator oxide layer. A schematic cross section is presented in
figure 2.4 the next page.

9
 Figure 2.4: A floating gate transistor for memory applications

Charge carriers trapped at this floating gate cannot escape the energy well
by means of classical physics; a small amount is continuously due to quantum
tunneling but most is conserved for very long periods of time. Possibly the
most used technique to access the charge stored on the floating terminal is
based on the hot-electron injection phenomena, and consists in accelerating
charge carriers to a high kinetic energy state in which they have the necessary
energy to overcome potential barrier due to the oxide layer. Two different
physical states, distinguished by having a different amount of charge stored
in the gate, can be used as logical states. Depositing and removing a fixed
charge packet on the floating gate will be crudely equivalent to store infor-
mation as a zero or a one. The voltages required to access the floating gate
are high but the current which required is very low; it deeply depends on the
technology available but the charge packet is ideally just what is needed to
distinguish effectively the states.
As technology advanced the E 2 PROM were developed and later during the
eighties the flash memories were invented; all shared the necessity of a high
voltage source to change the logical state. This focused research on charge
pumps designed to step up the voltage considerably while supplying low
amounts of current (often below 10µA), and most literature targets this op-
erating conditions and current load requirements [13]. The charge pump de-
veloped in thesis project has different specifications to meet as it is designed
to step up the voltage by 3.6V and to supply load currents of a few hundred
microampere: not much has been found in literature regarding charge pumps
which must supply high currents at low step up voltages.

10
 Starting from the nineties, as interest for integrated DC-DC converters
grew, many different topologies have been proposed and investigated. Some
are adaptations of the Dickson topology which improve some aspects of the
conversion process, others are new and original design which operate in rad-
ically different ways. Chapter 4 is dedicated to giving an overview of some
of the latest and most used topologies.

11
Chapter 3

Charge Pump design Metrics

A design metric is a simulated measurement of a particular characteristic

of the charge pump and is used to compare different designs or different
working condition for the same design [2]. it is important to find meaningful
and quantifiable ways to evaluate the performance of a charge pump in order
to compare between the various circuit topologies and the different device
sizing possibilities.

3.1 IV characteristic
The most straightforward design metric is the IV characteristics. The IV
characteristic gives precise information on the amount of current (I) that can
be sourced from the charge pump at a given output voltage (V). Sometimes it
is studied as the output voltage at which the charge pump settles for a given
load current [1]; these are two different ways of indicating the same metric as
the two characteristics differ for a switch of the current and voltage axis, and
any conclusion we might make on a certain VI curve is evidently broadened
for the equivalent axis-switched IV curve. In figure 3.1 two IV characteristics
for a generic ideal and non regulated charge pump are presented for two
different assumptions.
In the left output characteristic it is assumed a constant power output
for every load. Many nonlinearities effect the characteristic and information
regarding the charge pump performance can be extracted from the charac-
teristic’s shape [12]. For example the slope of the IV curve is the equiva-
lent output resistance of the converter for the particular value at which the
∂V
derivate is taken, as can be seen with R out = . The converter will func-
∂I
tion optimally only in conditions given by the specification and real charge
pump never exhibit the characteristic presented in the left side of figure 3.1

12
 Figure 3.1: IV characteristic for constant power (left) or Routput (right)

far from the designed operating point as efficiency degrades. Sometimes the
IV characteristic is given linearly, as in the right side of figure 3.1, implying
constant output resistance behavior.
The ideal IV characteristic of a regulated charge pump is different from
any shown in figure 3.1 as a perfect regulated power converter would have
precisely zero output resistance for every load current, which means that it
could provide any amount of current without ever degrading the boosted
voltage. Real regulated charge pumps usually exhibit a very low output
resistance up to a certain maximum load after which the output resistance
increases drastically. The IV characteristic can be useful to visualize the
improvements on a design as movements of the IV curves for both the fully
regulated system and for the open loop charge pump.

3.2 Efficiency
A second important design metric is the efficiency of the converter. It is
defined as the ration between power provided to the output and the sum of
power consumption of the charge pump and the quiescent power that is ad-
ditionally required for the device [2]. Efficiency often intended in literature
considering only the conversion of the charge pump core, therefore ignoring
all the power consumption of the surrounding circuits, which are indeed nec-
essary for the charge pump operation, most importantly the clock generator.
This is done because it can be interesting to compare different charge pumps
architectures which might require different regulation loops, clock schemes
and frequency, level shifters and so on.

13
It is important to also analyze the system level efficiency as some modifi-
cation which improve the charge pump efficiency might require additional
blocks which in turn could be detrimental to the overall design efficiency.
Every charge pump will have an optimum efficiency load current value and
will exhibit an increasing degraded performance as the load current value
drifts from the ideal conditions. The maximum efficiency load current can
be chosen by the designer and is normally targeted to the expected load
current specifications, although this might not always be the case when sit-
uationally other priorities become important. For example a charge pump
which is seldom required to output current might be designed to be most
efficient in its quiescent state and not at the expected load.

3.3 Noise
Noise is a critical aspect to many designs. The main kind of noise associated
with charge pumps is the unavoidable ripple output noise, which is inextrica-
bly tied to the switching nature of the converter itself. After the switching of
the pump clock an amount of charge will be delivered to the output and the
device will be unable to correct any noise related deviation from the target
level until the next clock pulse. The expected capacitative load will provide
some filtering, smoothing the output characteristic ripple: occasionally an
additional filter capacitor is placed in parallel to the load capacitance to fur-
ther suppress this noise at the expense of speed and efficiency. In general we
can write the charge packet transfered between the stages of a Dickson or
Dickson-like charge pump as ∆Q = C(∆Vclk − Vth ). The deviation from the
target regulation level due to the discrete nature of this charge packet can
∆Q
be written as ∆Vtarget = where Coutput is the total capacitance seen
Coutput
from the output. By substituting the first equation in the second:
C(∆Vclk − Vth )
∆Vtarget =
Coutput
The main contributions to the output noise are therefore the magnitude of
the clock voltage swing and the bucket capacitor size in respect to the total
output capacitance. Intuitively higher clock swings and capacitor values will
lead to higher levels of noise as the charge packet is increased, whereas a
higher frequency mitigates output ripple. Usually the pump clock is powered
directly from the chip supply, excluding those charge pump designs which
employ a secondary, smaller, charge pump to boost the pump clock levels.
Therefore the supply variations will also indirectly worsen the output ripple
noise by altering the clock swing.

14
3.4 Line Regulation
The effect of a varying supply on the output is further studied introducing
another design metric: Line regulation is defined as the ratio between the
change in output voltage with respect to the variation of the input supply
∆Vout
voltage
∆Vin
Line regulation is mainly affected by two different contributions. The
first is the Power Supply Rejection Ratio (sometimes named Power Supply
Rejection when expressed in decibels) of the comparator in the regulation
loop. A variation in the supply voltage not rejected by the comparator
would be amplified by the pump regulation and propagated to the output
resulting in a drift from the desired working conditions. The second is due
to the output switching noise. As was noticed discussing the ripple noise a
variation in the input level will produce a variation in the clock swing which
in turn will produce a unwanted deviation from the output target level. To
optimize line regulation it will be necessary to enhance the robustness of the
clock swing in respect to the input supply:
∂Voutput ∂Voutput ∂Vclk
= ≈0
∂Vinput ∂Vclk ∂Vinput

3.5 Start Up
Start Up is defined as the time elapsed from when the charge pump is turned
on to when its output has reached the operating voltage. Even assuming
open circuit conditions at the charge pump output during the start up phase
some time will elapse from when the circuit is switched on and when it can
supply a load current, as all internal nodes must be charged to their operating
condition. The start up is mainly affected by the number of stages, the
dimensioning of the devices, and by the required output voltage [8]. In the
automotive industry start up is seldom a critical aspect of the design as the
typical start up time is rated in a few microseconds, however in fast memory
applications it can be more challenging to meet specifications.

15
Chapter 4

Circuit Topologies

4.1 Switched Mode Power Supply

Switched mode power supplies are a category of devices which use and in-
ductor and a capacitor to store energy alternately as a magnetic or electric
field according to a clock timing schedule. This kind of converters offer high
efficiency, often over 90%, in a wide range of possible output current. The
high efficiency, in respect to other voltage references as for example a resis-
tive divider or a linear regulator, is due to the minimum quiescent power
needed: by operating in a switched mode during one phase all the power is
delivered to the load and during the opposite phase energy is stored in the
magnetic field [18]. All the power is used by the load and none is wasted
while the system is inactive as there is no resistor which always dissipates
heat. The main disadvantage of switched circuits is the ripple noise which
often requires a large decoupling capacitance.
A Buck converter generates a voltage below the supply and can output
currents ranging from a few hundreds micro amperes [1] and a few amperes.
It is formed by a switch, a capacitor, a diode and an inductor connected
as in figure 4.1.

16
 Figure 4.1: Schematic of a Buck converter

The load is modeled as a resistor R, the DC voltage of the circuit will be

refereed as the input supply voltage and the voltage drop across the resistor,
the voltage at node N2 , will be called output or regulated voltage. When the
switch is closed a current flows in the inductor and a magnetic field of energy
LI 2
Em = is created in the coil. The current across an inductor cannot
2
change instantly, it exponentially grows as the magnetic field builds up. At
the same time the voltage difference between node N1 and N2 decreases ex-
ponentially and monotonously goes to zero. During this time the diode D is
blocking any current from going directly to ground. When the switch opens
for the complementary phase the inductor requires a current which can now
flow trough the diode and to the load. The current in the inductor decreases
exponentially as the magnetic field is gradually drained. A decoupling capac-
itance is connected in parallel to the output in order to absorb excess charge
as power is delivered to the load and to return it while the magnetic field
is building up: the capacitance acts as a filter for the switching noise and
smooths the energy transfer to the output. There are two mode of operation
for a Buck converter, a continuous mode if the current in the inductor never
reaches zero while providing power or a discontinuous mode if the magnetic
field remains completely depleted for any amount of time. The two differ-
ent mode of operation have advantages and disadvantages, and in this study
[11] the authors mix the two operating modes in real time using a control
scheme in order to follow the instantaneous load requirements for maximum
efficiency.

17
 A Buck converter operating in continuous conduction mode has always
a current greater than zero flowing in the inductor: this current varies from
Imax to Imin periodically according to a clock with given duty cycle D. Consid-
ering the buck converter shown in figure 4.1 and assuming infinite Cdecoupling
and zero voltage drop for the diode we write the equation for conservation
of energy:
2 2
L∆Ion L∆Iof f
=
2 2
Where the difference between the current flowing in the inductor at the
beginning of the on phase and the current flowing at the end of the same
phase can be written as:
R Ton
(VN 1 − VN 2 )dt Ton (VN 1 − VN 2 )
∆Ion = 0 =
L L
By applying the same at ∆Iof f , which is the same as Imin − Imax and using
the definition of duty cycle:
Ton
D=
Ton + Tof f
We arrive to the final equation that states that the regulated voltage is
proportional to the supply voltage with a proportionality constant equal to
Vout
the duty cycle = D. In other words the duty cycle of the pulse width
Vin
modulated signal applied the input is itself the proportion of the supply
achieved by a buck converter operating in continuous conduction mode. The
system could be regulated adjusting D in order to keep a certain target
voltage at the output, and a filtering capacitance can be chosen to keep the
switching ripple noise below a defined threshold.
For the discontinuous conduction mode, which is ideal under low load
conditions, the analysis is similar. Again, it holds that the energy stored in
the inductor during the on phase is the same as the energy recouped in the
off stage. Let h be the fraction of the total period time needed for the current
in the inductor to decrease from the maximum value to zero. For clarity it is
noted that the limit between continuous conduction mode and discontinuous
mode is reached for h approaching zero. We now have:

∆Ion + ∆Iof f = 0

R Ton R Tof f
0
(VN 1 − VN 2 )dt Ton
(0 − VN 2 )dt Ton (VN 1 − VN 2 ) −DT VN 2
+ = + =0
L L L L
18
 The conversion process and the output voltage can be controlled, as for
the continuous conduction mode, by choosing an appropriate duty cycle value
D.
Vin
Vout =
2LIload
T +1
D2 Vin
The expression is less robust to variations in the operating conditions as
input voltage or load current, it is therefore advisable to design a feedback
loop to regulate the output voltage to the desired value.
A Boost converter generates a voltage above the supply. It uses the same
basic components of the Buck converter rearranged according to figure 4.2.
As in the previous case we model the load as a resistor located between the
ground and boosted voltage node N4. The diode, inductor and switch have
been connected so that during the on phase a large current is gradually build
up in the trough the inductor. When finally the switch is turned off the
inductor current flows in the diode and to the load. As the magnetic field
dissipates inside the inductor it provides current required for the load. The
concept is to convert energy in the coil and then to deliver it to the load as
the switch is opened. A filter capacitance of value C is placed at the output
in order to stabilize the voltage by storing on its plates the excess charge of
off phase which is then supplied back to the load in the on phase (on and off
stages are refereed to the state of the switch, which is complementary to the
output of current from the converter).

Figure 4.2: Schematic of a Boost converter

Like for the Buck converter there are two modes of operation: the continu-

19
ous and discontinuous conduction modes. Once again the distinction is made
when the inductor current reaches zero. In continuous conduction the induc-
tor current periodically varies between Imax and Imin where Imax > Imin > 0.
2 2
∆ILon ∆ILof f
For the conservation of energy we have =
2 2
For the conservation of charge we have ∆ILon = ∆ILof f because the total
change of current in the inductor over a complete cycle is zero. As the
switch is turned on a current starts flowing in the inductor while the voltage
drop across it steadily decreases. The magnetic field is being build up. No
current can flow to the output in this stage as the diode is reverse biased. If
there is any current load requirement at the output in this stage it has to be
supplied by the charge stored in the output filter capacitance in the previous
phase as no direct path can be established from the inductor to the output.
When the switch is turned off the voltage drop across the inductor should
be minimum and the current in the inductor should be maximum. This can
be achieved if the switch, which is often made with a single transistor, is
well dimensioned in relationship to the inductance value and the operating
clock frequency. Ideally the operation frequency is chosen so that for each
switching cycle there is enough time for the inductor to charge or discharge
completely. With the same assumptions made for the Buck converter, which
are zero voltage drop Vd for the diode, infinite Cf capacitance for the filter
(which means that any amount of extra charge can be stored during the off
phase and given back to the output at the subsequent on phase), and no
parasitic losses, we can derive the the equation which give the total change
of inductor current in the two different phases:
R Ton
(VN 3 − 0)dt Ton
∆ILon = 0 = VN 3
L L
R Tof f
(VN 3 − VN 4 )dt Tof f
∆ILof f = Ton = (VN 3 − VN 4 )
L L
We can now derive the transfer function for the boost converter in con-
tinuous mode as

Ton VN 3 + Tof f (VN 3 − VN 4 ) = 0

Vout 1
=
Vin 1−D
Where D is the clock duty cycle driving the switch. It is shown that
the regulation voltage can be kept as any value between the supply level

20
and, ideally, infinity for D approaching 1. A pulse wide modulation could be
applied in order to adjust the duty cycle and to maintain a target regulation
at the output.
If the inductor current goes to zero at the middle or end of the off state
then the converter is operating in discontinuous mode. With the same as-
sumption made before it can be shown that
VN 4 D+h
=
VN 3 h
where h is the fraction of clock period T elapsing since when the inductor
current starts to fall until it has reached zero, which can be calculated as
VN 3
h=
(VN 4 − VN 3 )D
VN 3
We can write the maximum inductor current as ILmax = DT and
L
using the fact that the average inductor current in the off phase must equal
the load current we get:
VN 3 DT VN 3 D
IL = = Iload
2L VN 4 − VN 3
Vout VN 3 D2 T
=1+
Vin 2LIlaod
As for the buck converter we notice that operating in the discontinuous
mode the ration of the output voltage to the input supply is a much more
complicated function of the voltage itself and of the other parameters in-
volved. A feedback regulation system should be employed using some pulse
with or frequency modulation to keep the regulation at the target level.
The buck and boost converters can be used in series to form a split-π
converter which is able to provide any voltage above or below the available
supply. The circuit analysis for the split-π is not reported as both its oper-
ating sub-circuits have been discussed individually.

4.2 Voltage Doubler

A charge pump is a particular kind of switching DC-DC converter which
doesn’t use any magnetic element in its operation. Energy is stored in the
form of charge on the plates of a capacitor, kept at different voltages, as
CV 2
E= instead of being stored, as it would happen in a transformer, in the
2
21
 LI 2
form of current flowing in a inductor according to E = . Charge pumps
2
are converters much more indicated for a monolithic integration because do
not require an external coil [14]. The first circuit topology presented is a
simple voltage multiplier. It conceptually works by charging the capacitors
in parallel and discharging them in series in order to obtain a high voltage
source at the expense of current. A similar circuit was first developed in
discrete components using spark gaps by Erwin Marx in 1924, and is refereed
to as a Marx generator [26]. Figure 4.3 shows this design.

Figure 4.3: Schematic of a Marx generator

The idea is to have two separate phases: In the charging phase the ca-
pacitors have a terminal connected to the positive supply and the other at
ground level. An exponentially decreasing current charges the capacitors
and if the switch is left open for enough time compared to the τ of the ex-
ponential current the top plate of the capacitor reaches equilibrium at the
positive voltage supply level. The amount of charge stored in this way is
calculable with the capacitor law Q = C · ∆V . In the second phase, after
the switches have contemporaneously switched connections, the capacitors
result connected in series, where the bottom plate of the first capacitor is
at analog ground and the output high voltage is the top plate of the last
capacitor. The output voltage under open circuit conditions for a N stages
multiplier becomes N times the supply voltage, assuming ideal components
and capacitors of the same size. Two stages, which means two capacitors
would be required achieve a multiplication of a factor of two; the same result
can be obtained with a voltage doubler using only one capacitor, and saving
approximately half of the silicon area. A simple voltage doubler schematic
which uses the described technique is presented in figure 4.4.

22
 Figure 4.4: Schematic of a Voltage Doubler Charge Pump

This topology is a simple and cheap way to double, and if required to

also invert, a given fixed potential with the limitation of being allowed to
step up the voltage up to a maximum factor of two. It works by charging
the flying capacitor Cf with the maximum available charge, connecting it
between ground and supply, and then the capacitor connections are switch
so that the bottom plate goes to supply and the top plate goes to the output.
It is noted that a perfect twofold multiplication is possible only in open load
or very low load current conditions, and if the load capacitance is negligible or
at least very small compared to Cf . Consider what happens when the output
is connected under no current load condition: charge is shared between Cf
and Cload and the new expression for the multiplying ratio, considering the
load capacitance losses expressed with CLoad > 0
?
Voutput 2Cf
= <2
Vinput Cf + CLoad
If the load capacitance was to match the value of Cf the converter would cease
to function as the charge delivered to the output is just enough to charge
the load up to the supply level. The dimensioning of Cf in respect to the
expected Cload is not only important for the operation but it is also critical for
determining the stability of the supplied line. A reasonable load capacitance
is actually beneficial to the stability of the line. During the charging phase
all load current is supplied to the output by the charge left on the load

23
capacitance. Cload must be large enough in respect to the operating frequency
and load requirements to supply this load current while maintaining the
voltage steady, and Cf should be greater than Cload in order to step up the
voltage as described by the given equation.

4.3 Dickson Charge Pump

The Dickson charge pump was proposed by Dickson in 1976 and gained scien-
tific interest [16]: it is to this day amongst the most quoted articles regarding
voltage multiplications techniques. Originally developed with memory ori-
ented specifications requirements it is a charge pump topology indicated for
high capacitive loads. A schematic of the circuit with two stages, as well as
the operating clock scheme is presented in figure 4.5.

Figure 4.5: Dickson Charge Pump Schematic and non-overlapping clock

scheme

24
 Any additional stage can be added with its own bucket capacitor, isolating
diode or diode-connected transistor and a clock connection to be placed at the
capacitor plate with the lower potential. Clock signals on adjacent capacitors
should be opposite and non overlapping to assure that charge can’t escape
backwards to the previous stages. To derive the equation which model the
behavior of the charge pump consider the first stage. While the clock signal is
low capacitor C1 is, excluding the effect of parasitics, charged up to Vin − Vth .
When the voltage in node N1 reaches Vin −Vth the diode-connected transistor
M1 is turned off. As the clock switches to the high value the bottom plate of
capacitor C1 goes to the supply level. The voltage of node N1 becomes Vin −
Vth + Vclk , where Vclk is also usually given by the supply. Some charge pumps
use a secondary, smaller charge pump, to further boost the output voltage by
raising the voltage swing of the pumping clocks. If we want to account also
for the parasitic losses we can consider that any stray capacitance present at
node N1 will form a capacitive divider with the bucket capacitor C1 resulting
in a lowered maximum achievable voltage during the pumping state given
by:
C
VN1 = VSupply + VClk − Vth
C + Cpar
As the voltage at node N1 is raising transistor M2 turns on. The clock
connected at the second node is opposite to the clock of the first so as M2
turns on a current can flow and charge C2 . Charge previously loaded on C1
is transferred to C2 . Every subsequent stage will work in the same manner
described for the first two stages. For n different stages we have:
C
VN1 = VSupply + n( VClk − Vth ) − Vth
C + Cpar
This equation has been derived under the assumption that no resistive load
is connected, so that Iout is zero. If a current is supplied by the output
the boosted voltage will inevitably be lowered by the loading effect, as de-
scribed in the section regarding the IV characteristic design metric. This
effect subtracts from the zero load condition a contribution for every stage
that depends on operation frequency, parasitic and bucket capacitance value
Iout
and current load required according to . The maximum peak
(Ci + Cpar )f
voltage seen at the output is therefore:
C Iout
Voutput = Vinput + n[ VClk − Vth − ]
C + Cpar (Ci + Cpar )f
Note that for most application the input of any DC-DC converter is the
positive supply level.

25
 Numerous improvements on the Dickson topology have been proposed in
literature; a selection of the most interesting designs developed in the last ten
years will be presented. This selection cannot exhaustively describe all the
modifications that have been published but aims at reviewing which are the
most common design techniques used to improve the Dickson charge pump.
In ideal condition the voltage step up granted by each stage is mainly related
to the difference between the clock swing and the diode drop. The voltage
swing is maximized by allowing the swing to be between the positive and
negative rail, where the Vth drop is usually between 0.5V and 0.8V. As tech-
nologies are developed we have seen a trend of deceasing input power supply
level, not matched by a decrease in the threshold voltage to the point where
in a very scaled technology every additional stage might increase the voltage
by just a fraction of the input value, if the Dickson topology is feasible at all.
As input power level is scaled down the stage gain attenuates at increasing
higher rate as the supply approaches Vth . More stages would become neces-
sary to reach the same output voltage, which in turn is area consuming and
provides additional challenge for stability. For these reasons much effort is
dedicated to reducing the diode voltage drop with Vth canceling techniques.
An interesting solution to nullify the diode voltage drop is explores using
auxiliary charge transfer switches [3]. The circuit schematic is provided in
figure 4.6.

Figure 4.6: Auxiliary switches improvement on the Dickson charge pump

The usual Dickson topology is modified by adding the transistors chain

MS1 to MS5 to the ordinary MOS diode connected chain M1 to M5 . The

26
gate of this secondary switches is driven by the fed-back voltage from the
successive node and allows current to flow even when the nodes it connects
are at a very similar voltage, therefore canceling the usual voltage threshold
drop. With this modification as the voltage difference between two adjacent
nodes approaches the threshold value current is not exponentially decaying
as it would be in the regular Dickson charge pump but it can still flow in
the auxiliary switch allowing the nodes to reach the same level. The main
problem with this topology is a reverse charge sharing effect for which current
can flow in the switch which can be solved with a non-overlapping switching
scheme to control the gate voltages in the off phase as discussed in [15].
Other proposed designs aim at improving various aspect of the Dickson
charge pump. In [7] a method to improve the reliability of the Dickson charge
pump is presented to overcome possible over voltage in the diode chain and
in publication [5] a low voltage implementation with high current capability
is discussed.

4.4 Presented Charge Pump

The Cross Coupled Charge Pump presented in this thesis steps the potential
up from 12V to 15.6V and is responsible for charging the gate of a DMOS
transistor used in a high side switch: this ensures a reliable turn on of the
device and assures that the DMOS is kept in the low ohmic operation region.
It is possible to place a switch either on the high or low voltage of a load
in oder to effectively connect or disconnect it from supply. When switch-
ing from high side the circuit is interrupted at the positive rail level and
the load cannot source current from the supply. When switching from the
low side the circuit is interrupted at the lower supply level and current is
prevented from being sinked to the ground. Both approaches can effectively
disconnect a device but in the automotive industry high side switches are
far more common both for safety and efficiency [21]. Switching on the low
side requires to constantly keep at high voltage all the wire from the battery
to the device requiring power, even when the device is not in use or turned
off. In the automotive industry this problem is of peculiar importance as
the battery is usually mounted under the hood and the peripheral devices
and sensors are connected with extensive wiring. It is much preferable not
to have lengthy high potential wires which might generate sparks in case of
emergency. Switches are made with a power transistor which requires a volt-
age fixed at a higher potential than the 12V battery to be turned on and keep
in the linear region. The presented charge pump is a frequency optimized

27
improvement over an already developed charge pump. The Charge Pump is
composed by many different blocks, some of which will be discussed. The
main focus is on the charge pump cores, which form the DC-DC converter,
and the clock generator, which is used to control the switching timing of the
charge pump cores.

4.5 Charge Pump Core

The presented design is implemented with two identical cores which work
with a 90 degrees clock phase difference. This means that a clock signal of a
core is never switching simultaneously with a clock signal of the other core.
A circuit diagram is presented in figure 4.7.

Figure 4.7: Presented Cross Coupled Charge Pump schematic

Each core is composed of two symmetrical branches, each driven by its

own clock signal: these clock signals have an opposite phase and a 50% duty

28
cycle and are non-overlapping. Therefore in any given moment, while one
branch clock is high the other branch clock is low.
Transistors M7 and M8 form an inverter; while the left branch clock
signal switches from 12V to 8.2V M7 starts conducting while M8 is shut off.
A current can than flow from the power supply rail, trough M7 , and charges
C2 raising node N1 to 12V. During the first pumping cycles, while the charge
pump is still turning on, capacitor C2 is charged and discharged with each
subsequent clock pulse with different quantities of charge, resulting in a net
charge bring stored in C2 . According to equation Q=CV a voltage difference
of around 3.6V is build up between node N1 and node N2 : when the charge
pump settles in normal operation capacitor C2 will be charged and discharged
with the same amount of charge and node N2 follows node N1 roughly keeping
the 3.6V difference due to the initial charge build up, which is left for the
most part unaltered. The difference between the voltages of node 1 and
2 actually floats between 3.5V and 3.8V throughout the operation of the
charge pump, according to the charging and discharging cycles of the flying
capacitors. The main parameters responsible for the charge and discharge of
the capacitors are the W/L ratios of M7 and M8 , which are also responsible
for the switching point of the inverter, the clock frequency, the actual value
of C2 as well as the load current required at the output stage. It is important
that the voltage drop between any two nodes of the charge pump is never
greater than 3.8V in order not to exceed the inherent breakdown voltage of
the technology with which the MOSFETs are implemented. Figure 4.8 shows
how the charge pump is turned on by plotting the charge pump output in
respect to time. The first 5 clock pulses (more are needed if capacitor values
are increased) are used for the initial charge build up on C2 and during the
following pulses the initial charge is mostly conserved. From a circuital point
of view we see that while node N2 is pumped at the higher voltage of 15.6V,
node N3 is complementary resting at the lower voltage of 12V: we deduce
that M5 and M3 are shut off while M4 and M6 are conducting. A current can
then flow through M4 into the output, ramping the pump output to 15.6V.

29
 Figure 4.8: Transient plot showing start up and settling

The output voltage, under open load conditions, is plotted in green in

figure 4.8: the effect of a single clock pulse on the first branch of the first
core is voltage spike 1, while the effect of the complementary clock pulse on
the second branch of the same core is the voltage spike 3. Peaks 2 and 4 are
due to the other core, and are therefore 90 degrees out of phase.
The current that flows to the output is coming in four different and dis-
crete steps: In the first step the current is provided by the first branch of the
first core as it has been discussed, then, a fourth of the clock period later we
have the second step, and the first branch of the second core is pumping cur-
rent to the output. The third and fourth steps are due to the negated clocks
of the second branches of the first and second core respectively. For example

30
consider the proposed design driven by a 5MHz clock and with a load current
required of 200µA. It is interesting to study how charge is transferred by the
charge pump. With every clock pulse a charge packet is transfered to the out-
put. Figure 4.9 shows how this charge packet is delivered: during the 100ns
that M4 is conducting a net amount of 10pC of charge transfer to the output.

Figure 4.9: Simulated detail of a single charge packet transfer to output

About 75% of this charge is provided in the first 50ns of the conduction
time, and only about 25% is transferred in the second half of the conduction
time. We can therefore give a quantitative justification to the qualitative
analysis of the output voltage spikes: 75% of the current provided at the
output in any given phase is coming from the last branch that has entered
conduction and the remaining 25% is supplied by the other core. Each branch
is therefore granting 10pC of charge to the output with every clock cycle,
and since there are four branches and the clock period is 200ns long we can
conclude that the average current provided to the output is, in fact, 200µA as
required. With different load currents and different parameters it is noticed
that the percentages of charge provided in the first half and second of the
conduction period deviate from the presented 75% and 25% values but the
fact that the most charge is transferred in the first half still holds.

31
Chapter 5

Frequency Optimization

5.1 Clock Generator

The clock generator is one of the main blocks of a charge pump. The most
important aspect of a clock generator for charge pump application is to main-
tain precisely the designed timing even with process, supply or temperature
variations. There are two main ways in which the timing is degraded. The
first is if the clock generator runs too slow or fast but still maintaining the
desired duty cycle. In this case the charging and discharging phases of the
pumping capacitors will deviate from the ideally designed condition in the
same way. If both phases are shortened the charge pump will work at an over-
all higher frequency and potentially this degrades efficiency as the pumping
capacitors will be switched before they are completely charged or discharged.
If instead both phases are lengthen the charge pump will operate at an over-
all lower frequency, the pumping capacitors will waste time after they have
been charged or discharged and this will lower performances as the current
sourced from a charge pump is dependent on the frequency approximately
according to ISourced ∝ (fCLK ∗C ∗∆VCapacitor ). A more problematic situation
arises when the clock high and low phases are asymmetrically variated. In
this case not only efficiency quickly decreases as the phase time difference
grows but also a higher ripple noise is seen at the output. This asymmetry
changes the output behavior discussed in the Charge Pump Core subsection
of chapter 4 by superimposing to the high frequency ripple noise a lower
frequency periodic oscillation of the average output voltage level. As the
asymmetrically long phase provides current to the load the output voltage
will be higher than expected and during the shorter phase the output will
drop considerably: these fluctuations are potentially more problematic that
the usual ripple noise as a fluctuation of the average value might bring the

32
output out of the specification levels.
The clock signal for the charge pump is generated with the Schmitt Trig-
ger circuit presented in figure 5.1.

Figure 5.1: Schmitt Trigger circuit schematic

The Schmitt Trigger is essentially a comparator with hysteresis which

senses the slow and constant charging and discharging of a capacitor and
switches the output when a certain level is reached: when the capacitor is
completely charged a first trigger level brings the output to the logical high
value and when the capacitor is discharged the trigger switches the output
to the logical low value. A precisely mirrored constant current flows trough
transistor M1 during the charging phase and the voltage in node N1 grows
Imirror
lineally with time according to VN 1 (t) = t
Coscillator

33
 When the voltage on the top plate of capacitor Coscillator reaches the
upper trigger level the output is switched high: the output is fed back to
the common gate of M1 and M2 shutting off M1 and turning on M2 . A
current designed to be matched with the charging current will discharge the
capacitor through transistor M2 . By matching the charging and discharging
current we can assure that the charging and discharging times are the same
providing a clock signal with 50% duty cycle appropriate for a charge pump
application.
To further explain the Schmitt trigger operation consider node N2 : when
node N1 reaches the higher threshold it will switch to a low value and when
node N1 reaches the lower threshold it will switch high. While node N1
voltage rises a current will flow in M6 and M8 while M5 is off. This current
grows in time as the gate-source voltage of M6 is increased. This current
must flow in M8 and as node N1 reaches the upper threshold the system is
triggered: M5 turns on quickly bringing node N2 to its lower value. The
square wave signal in node N2 is then buffered to the output and fed back
to the gates of M1 and M2 as previously discussed. On the feedback path
a switch is placed to enable or disable the clock generator. By choosing the
W/L ratios it is possible to determinate the threshold at which transistors
M5 and, symmetrically, M4 turn on, and therefore setting the working levels
of the hysteresis.
The clock frequency is controlled by choosing the capacitor value Coscillator
in relationship with the constant current flowing alternatively in M1 and M2 .
For example assume a voltage difference of 2V for the two trigger levels: if
both current sources provide 20uA of current and the value of the capac-
itor is taken to be 1pF it will take 100ns for the capacitor to charge and
the same time to discharge therefore the resulting square wave will have a
200ns period. Intuitively if the implemented capacitor is made smaller it will
require less time for the same current to complete a charge and discharge
cycle. The capacitor should not be made smaller than a minimum value
as smaller devices (in this case the capacitor value is related to its area by
C = Coxide W L) present a higher spread of the actually realized value in re-
lationship to the absolute designed value, and this would alter the delicate
timing. To raise the frequency of a clock generator implemented with the
minimum acceptable capacitor value the only alternative becomes to raise
the constant mirrored current, therefore raising current consumption of the
block. It should be noted however that the clock generator and logic current
consumption is in any case much lower than the current consumption of the
charge pump core.
With this design it is necessary to buffer the signal in order to avoid that
the parasitic elements of the large charge pump input transistors to alter the

34
delicate operation of the Schmitt Trigger. In other designs where the clock
generator directly drives the bucket capacitors it becomes important that the
circuit is able to provide enough current to properly charge and discharge the
capacitors.

5.2 Clock Lines

The proposed charge pump requires 4 clock lines in total as each of the
two cores has two different branches. Each core requires a clock and its
non overlapping negated signal, which can be easily obtained from the main
clock with an inverter. This assures two non overlapping clocks as the delay
introduced by the inverter is negligible in respect to the clock period. The
second core requires a clock 90 degrees out of phase in respect to the main
core, as explained in the charge pump core section, and its own negated
signal. In order to generate this out of phase signal different approaches
have been explored, including a logic combination of the signals and a delay
line method. The chosen solution was realized by designing an inverter to
sense the same capacitor top plate voltage of the main line and the switching
threshold is placed at the middle of the voltage ramp. This approach is simple
and able to assure that clock deviation from ideal conditions are below 5%
for process and temperature variations, which is acceptable in the thesis
context. As with the main line this signal is also buffered to provide cleaner
rising and falling edges. It can be proven that in general the switching point
of an inverter is
p
kn VthN + (kp VthP − 1) + ( kn kp (VthN + VthP − 1)2 )
VG =
kn − kp
where k is a constant that takes in account the different mobility, W/L
and the oxide capacitance in PMOS and NMOS transistors [19]. This tech-
nique is much simpler than the Schmitt-Trigger but it is more sensible to
process variations. We can see that a small variation in Vth will produce a
big variation on the switching point value:

kn kp (VthN + VthP − 1)
kn + p p
∂VG kn kp (VthN + VthP − 1)2 kn + kn kp
= =
∂VthN kn − kp kn − kp
kn kp (VthN + VthP − 1)
kp + p p
∂VG kn kp (VthN + VthP − 1)2 kp + kn kp
=− =−
∂VthP kn − kp kn − kp

35
 This problem is further amplified by the fact that in order to have a
switching point in the middle we want the k constants similar in value and as
can be seen from the equation above the switching point is less robust in this
situation as the denominator goes to zero. This susceptibility is suppressed in
the multi core design: by adding a third charge pump core the clock schedule
is change to a 3 clock system with a phase difference of 60 degrees between
the different lines.

Figure 5.2: Generating the second and third clock signal line

As before we base the clock generator off a Schmitt Trigger and want to
generate out of phase clock signals, the modified clock generator is presented
in figure 5.2 where the Schmitt Trigger main elements have been omitted for
simplicity.

Consider the clock signals in figure 5.3. CLK1 (green) is the master clock,
generated with the Schmitt-Trigger. The signals S1 and S2 are generated with
two inverters (M9 , M10 and M11 , M12 ) by sensing the voltage in node N1
and choosing two different switching points for the inverters: one will switch
at higher and one at a lower threshold. In other words the signal S1 , taken
from inverter M9 M10 which has the higher threshold, will have a duty cycle
of 66%, while signal S2 will have a duty cycle of 33%. To generate a shifted
clock this two signals have to be combined choosing alternatively S1 and S2

36
with transistors M13 -M16 . In figure 5.3 it is superimposed in red how the
clock signals must be selected in any given time in order to generate CLK2 :
S1 is selected when CLK1 is high and S2 is selected when CLK1 is low.
Using the same clock signal which already went in the feedback loop we can
control the gates of M13 M16 and we obtain the required clock signals with
a last buffer (CLK3 signal requires an additional inverter to be the correct
logic combination of S1 and S2 ).

Figure 5.3: Clock Signal Combination Chart

Adding a third core could be feasible without the necessity of additional

area consumption: three cores working at a frequency 33% higher would

37
require approximately 33% less area each, as the main contributor to area is
the bucket capacitor size.

5.3 Charge Pump Characterization

Recall that the circuit is composed by connecting the outputs of four equal
charge pump cores and driving each core with a clock signal and its non-
overlapping opposite signal. This means that the first clock signal will pilot
the first branch of the first core as well as the second branch of the third core
and so on. With this clocking scheme there are always two cores pumping
charge to the output at the same time [20].
The four core charge pump has been characterized with a frequency sweep
under different load condition
In Figures 5.(4-6) the average output voltage, clipped to consider only
the already settled region of the transient simulation, is plotted in respect to
different operating frequency in order to compare the behavior of the charge
pump with different bucket capacitance values.

Figure 5.4: Simulated output Voltage in respect to a frequency sweep at

100µA

38
Figure 5.5: Simulated output Voltage in respect to a frequency sweep at
200µA

Figure 5.6: Simulated output Voltage in respect to a frequency sweep at

300µA

It is interesting to study the temporal average of the output in order to

compare design which will have a different frequency and ripple noise and
wouldn’t be directly comparable in a meaningful way. The data has been
clipped to only consider the output after it has settled in order to avoid

39
including the turning on phase which will be different for different designs.
The simulation was run for a 100µA, 200µA and 300µA load current.
We see that for each capacitor value and load current condition there
is a small optimum range of frequencies at which the charge pump should
operate. We also notice the tendency of low capacitance design to have a
broader range of frequencies at which to operate. If the frequency is lower
than the optimum value some performance is lost as the capacitors have
more time available to transfer charge than what is strictly needed. On the
contrary if the frequency is too high there isn’t enough time to discharge the
capacitor.

5.4 Bucket Capacitor Sizing and Frequency

During every cycle a fixed amount of charge is transferred to the output. The
size of this charge packet depends load current, frequency, bucket capacitor
value, clock voltage levels and sizing of the pass devices.
The transient current at the output of a pass transistor (as M4 or M5 ) of
different sizing is always similar to figure 5.7, where it it only shown for the
particular condition of 10MHz frequency, 5pF bucket capacitance value and
200µA load current.

40
Figure 5.7: Exponential transient current delivered to the output. The small
bulge that repeatedly happens at halfway throughout the conduction time is
due to the other core out of phase which is alternatively either on or off (it
if much more evident when the other core switches on rather than off)

Different sizing and frequencies will alter the details but in any case there
is no current flowing to the output while the pass transistor is off and a
exponentially decreasing current when the branch is outputting current [4].
It is analogous to a CR circuit where the capacitance is given by the bucket
capacitor values and the resistance is given by the Rds resistance of the
pass transistors M4 and M5 . It is possible to find the time constant of
the equivalent RC circuit by fitting the exponential transient current and
studying how it varies between different designs. To do this first the data
relative to the current trough a pass device is taken from the simulation
environment and linearized by taking the natural logarithm of the current
values and applying a linear regression: the angular coefficient will be equal
−1
to .
τ
−t
I(t) = I0 e τ

41
 −t −t
ln(I(t)) = ln(I0 ) − = ln(I0 ) −
τ RC

The peak value I0 is crucial to the electromagnetic emission profile of the

charge pump as high transient currents quickly varying in time will emit high
frequency noise. This will be discussed in the electromagnetic interference
paragraph.
The natural logarithm of the transient current during a single output
charge transfer is plotted in figure 5.8. For clarity the data is shown partially
including the switching (noticeable at the beginning and end of the otherwise
straight line), but in order to fit the data only the actual discharge has been
considered, excluding the switching region. While fitting this data only a
single core has been considered as simulating with a multi core set up will
unavoidably lead to noise from different cores coupling back to the studied
core, causing a larger degree of uncertainty in the fitted τ constant.

Figure 5.8: Fit of the output current

This fit provides a clear relationship between frequency and the time
constant: τ should be tuned to be at least 2-3 times smaller than half of
the clock period to allow for most of the charge to be transferred. If a
period greater than necessary is chosen the performance will degrade because
the charge transferred with each cycle will not be increased by much as
it is a exponential tail but the number of packet transfer will be reduced

42
significantly being linearly dependent on the clock period. For example if
choosing the operating clock period we allow for five time constants instead
of three we see an increase in charge packet size of less than 5% but a decrease
of 40% in the number of charge packets delivered for the same amount of
time. Figure 5.9 shows the relative size of the charge packet transfered to
the output in respect to the time it remains on expresses as multiples of the
time constant.

Figure 5.9: Percentage of charge packet transferred to the output in respect

to the transfer time, expressed in RC time constants.

The RC constant is given by the Rds resistance and flying capacitor C

[18]. In order to keep the same amount of time constant in a higher frequency
design either the resistance or the capacitance must be reduced accordingly.
Ideally we would want the minimum resistance possible but this is in trade
off with introducing parasitics which decrease the pumping efficiency. More
1
precisely the resistance can be modeled as Rds = where L cannot
µCox W
Vov
L
be lower than a given amount [17]. On the other hand the coupling ratio
decreases as
C C
CR = =
C + Cpar C + (≈ W L ∗ Cox )
And therefore W cannot be made too large as the coupling ratio will
be decreased. Therefore whereas C is a parameter chosen by the designer

43
the on resistance of M4 and M5 is not so straight forwardly chosen: note
that as the charge pump becomes faster the charge packet size is greatly
reduced. Current required at the output is supplied with more but smaller
packets. This means that Ids during the on phase is actually slightly lower for
higher frequencies designs. On the other hand the voltage drop Vds remains
about the same as it is related to the topology and the target regulation
Vds
level. We conclude that Rds ∝ either remains constant or increases
Ids
slightly as the frequency increases. Rds is bounded by the transistor operating
region. The only way left to reduce the time constant is to scale down the
bucket capacitor. Looking at the characterizations of the previous section we
factually notice that designs with a lower bucket capacitor have the optimum
working conditions at a higher frequency.

5.5 Blocking the Backwards path

It can be argued that with this clock scheme it is important that the switching
time of the pass devices (M4 and M5 ) is as short as possible to avoid a
backwards path from the output, thought either M4 or M5 of the opposing
core, and back to the positive supply. Current lost in this way will degrade
efficiency. If the charge pump is switching two cores at the same time this
path could be problematic, but during normal operation it will always be a
much more resistive path than the load directly. In practice it never happens
that two core switch together and this path is blocked by two reasons: first
note that either M5 and M3 or M6 and M4 can be active contemporaneously,
which means that even when such path exists it cannot be sustained for
more than a fraction of nanosecond as the total time required to switch
the output transistors is in worst cases 1.5 nanoseconds long. In second
place we notice that due to the designed phase difference in the charge pump
driving clocks the delay between different cores outputting charge is inversely
proportional to the frequency multiplied by the number of cores. It would
require a charge pump working over the gigahertz range for the delay to be
comparable with the fraction of nanosecond that the backwards path can be
sustained. Therefore, even accounting for a 5ns statistical spread in the clock
signal delay, it is impossible for such backwards path to exist while a core is
turning on.

44
5.6 Capacitors Current Leakage
When studying the behavior of a circuit it is useful to utilize ideal device
models to describe the main effects and to better validate theoretical pre-
dictions. When simulating the actual device some losses appear due to the
physical construction of the device on silicon. Different techniques exist to
implement a capacitor in the technology used in this thesis. The different
possibilities have been investigated and compared. Because the technology
allows for only one metal layer all the capacitors are implemented with a
metal insulator semiconductor (MIS) implementation. This means that one
of the capacitor plate is made with a metal layer, the other is made of doped
poly-silicon and a isolator is deposited between them. the insulator of choice
is borophosphosilicate glass, or BPSG, and is the main cause for the spread
in the capacitance value of the capacitor. This spread from the nominal val-
ues is a consequence of the chemical-mechanical planarization needed before
the metal layer can be deposited. A MIS capacitor is implemented as a MOS
transistor where the gate is one terminal and the channel is the other termi-
nal. Unfortunately for this kind of capacitors the capacitance value depends
on the operating condition and might drastically change if the voltage at the
transistor terminal changes. In figure 5.10 the capacitance is plotted against
surface potential for a generic PMOS MIS capacitor. The characterization of
the devices is confidential but the losses in a MIS capacitor are well known for
many different technologies. The real characteristic will also be different for
a NMOS or PMOS although the difference between the two different behav-
iors can be somewhat averaged out by taking the parallel of two capacitors
of half the value and made with opposite devices.

45
Figure 5.10: Capacitance Value in relationship to gate voltage in a general
MIS capacitor implemented with a PMOS transistor

As it can be see the capacitor behaves best if in deep accumulation or

if in depletion region. The accumulation region is to be preferred for supe-
rior robustness of the capacitance value in respect to surface potential and
it is necessary to operate the device in this condition if there are any high
frequency signals. The reason for witch at high frequency the capacitance
value doesn’t recover the ideal value is that as surface potential is raised the
concentration of charge carriers in the bulk is too low to supply quickly and
effectively charge to the channel/BPSG interface. The metal layer, being
a conductor, doesn’t have this problem as a great number of loosely bond
electrons is available throughout the whole lattice. The low charge carriers
concentration in the bulk can be mitigated by depositing a second source
nplus/nldd which, for a NMOS based capacitor, is given by the usual source
and drain contacts. For a PMOS would be specifically placed with a dedi-
cated well. To avoid the need for such extra implants the MIS capacitor is
operated in the accumulation region, where it is also more robust to varia-
tion of its operating potential and exhibits a more ideal characteristic. By
operating the MOS in the accumulation region a great number of holes can
be stored in the channel, and act as the effective charge carrier with which
the capacitor is charged and discharged.
It will be crucial to assure that the capacitor is working always in the
accumulation region.

46
 Different capacitor implementation techniques have been taken in consid-
eration in addition to the ideal circuit model. A high voltage implementation,
a standard MOS implementation and a mixed technology. A further distinc-
tion has to be made as for each implementation there are the two variants of
NMOS based or PMOS based MIS capacitor. The orientation of the device
also plays a role as the bulk can better supply holes than electrons, whereas
the metal layer, being a conductor, can easily supply both charge carriers
indiscriminately. Choosing the device orientation is equivalent to choosing
the region in which to operate the capacitor and, as stated before, in order
to exploit the advantages given in the accumulation region the capacitor is
connected so that the gate is always at the higher potential.
The non idealities of the capacitors are responsible for the main loss of
efficiency of the circuit, in the form of lost charge deviated to ground instead
of to the output. This loss is a fixed amount of charge that escapes the revers
PN bulk/source junction every time the capacitor is charged. The fixed
amount depends on the device orientation and implementation technique,
and is linearly dependent both on the nominal capacitance value and on the
voltage swing that the capacitor is subject to. Being a net amount lost for
each charge/discharge cycle it is independent of the total amount of charge
on the capacitor and therefore the problem is much more prominent in low
load conditions, where the amount of charge lost can be up to about 50% of
the total charge transferred. At higher loads a much greater charge packet
is stored in the capacitor with each cycle and the amount of charge lost is
proportionally less significant. This leakage is slightly more prominent on
smaller capacitors, relative to a larger capacitor of the same kind.

5.7 Area Consumption and Efficiency

Area is a precious resource in chip design as a designed which requires less
area allows for more circuitry to be implemented on a single die, adding
functionality, control and sensing capability to the finished product. The
area used by a charge pump is most primarily determinate by the size of
its pumping capacitors as the switches and logic usually take up for a neg-
ligible fraction of the area necessary to fabricate the required capacitors.
Therefore when comparing designs which differ in bucket capacitor size it
is important to keep in mind that the design with a higher total capacitor
value will proportionally be also the most bulky design. As this capacitors
are implemented with MIS transistor there is a direct relationship between
the area used and the capacitor value CM IS = (W L) ∗ Coxide = Area ∗ Coxide .
It has been shown previously that higher frequency design require a smaller

47
flying capacitor in order to keep the time constant τ adequate for the charge
transfer process. It was noticed in the previous section that the leakage is
slightly more important in smaller capacitors than in larger ones. Therefore
we conclude that the efficiency of a charge pump designed to operate at a
higher frequency with smaller bucket capacitors will be a less efficient design:
further sustaining this claim it has been simulated a loss of efficiency of up to
3% in charge pumps which present smaller capacitors and a higher frequency
optimum operating value.

Figure 5.11: Efficiency in respect to operating frequency sweep. Note that

the overall efficiency are just above 20% for the low load condition

In figure 5.11 the efficiency is plotted against the cores working frequency
for different total area consumption, rated in the total pico-Farad required
by the design. For a two core charge pump four capacitors are required (one
per each of the two branches of a single core). The efficiency is also strongly
related to the required load for this charge pump topology, as the main
parasitic loss is related to the size and number of times that the capacitors
are charged and discharged and not dependent on the amount of charge
actually stored with each cycle. For this reason the efficiency plotted in
figure 5.12 at 200 µA load current show the same behavior with an overall

48
better efficiency for every frequency value. The efficiency at 300 µA is overall
even better at about 62%-65%.

Figure 5.12: Efficiency in respect to operating frequency sweep. Note that

the optimum efficiency is around 42%-44% for a medium load condition

The trade off between losing up to an extra 3% efficiency while saving up

to 80% of the space required is a design decision which strongly depends on
the application and the available silicon real estate. Heating of the device
becomes more problematic in smaller area designs as not only there is less
space to dissipate heat, but being less efficient there is also more thermal en-
ergy released by the conversion process. Thermal simulation become crucial
to the design of the most scaled down-high frequency designs.
A similar conclusion has been drawn in [6]: ”There is a trade off while
increasing boost capacitance of each stage i. e. the area of the die will be
increased which will increase production cost while increasing frequency the
switching losses will be increased.”

49
Chapter 6

Electromagnetic Interference
Simulations

Every time a capacitor is switched a sharp transient current occurs to either

charge or discharge it. This current will propagate electromagnetic noise: the
interference may couple up with pins, traces or wires and alter the operation
various sensitive devices refereed to as victims [22]. The charge pump, being
a power device able to supply high amounts of current is definitely a device
which can cause electromagnetic interference. In general any high power
switch capacitor circuit is prone to being a electromagnetic noise source [23].

6.1 Line Impedance Stabilization Network

Part of this thesis involves studying the electromagnetic emission profile of
the charge pump and assure that it is in compliance with the automotive
industry standards CISP R − 25. A Line Impedance Stabilization Network
(LISN) simulation is conducted to estimate the electromagnetic emission pro-
file of the charge pump. The LISN verification is well established method-
ology: in the automotive context the CISPR-25 standard is used to emulate
the impedance of the car cables, setting the passive device values in the
network. Every Electronic circuit has natural resonances that occur in the
conducted emission profile. This resonances are primarily caused by intense
currents, impedances mismatches and poor grounding practices. Using a
LISN network the difficult task of simulating the radiative profile of a circuit
is overcome by studying instead the conducted emission, which is easier and
provides consistent and reliable results [24]. The function of the LISN is to
present to the supply line of the equipment under test (EUT / DUT) with a
precise impedance over a designated frequency range. When the resonances

50
are reduced in the conducted emission profile, the corresponding frequency
in the radiated profile will also be reduced. These resonances are like the
fingerprints of an electronic system; they occur at the same frequency and
look the same for a particular design.

Figure 6.1: CISPR-25 Automotive Standard Line Impedance Stabilization

Network

In order to simulate electromagnetic emission a Infineon tool developed

by the electromagnetic compatibility (EMC) group has been used. This tool,
based on a Ocean script, is integrated in the spectre simulation environment,
where the available technology devices have been characterized. With this
tool it is possible to place the network and the electromagnetic receiver at
the top level schematic to simulate the network response and the laboratory
environment. The LISN is placed between the power supply line, coming
from the car battery, and the charge pump: the measurement port node is
connected to the electromagnetic receiver device. The simulation is then run
and the charge pump is allowed some time to reach steady state operation
before the measurement takes place. The script works in three steps: First
a windowing function is applied to the data in order to filter out non steady
state operation. Then the measurement signal is Fourier transformed over
some clock cycles (at least five clock cycles are required, allowing for more
clock cycles will include higher order harmonics at the cost of computation
time). Finally the emission spectrum is calculated and plotted and the de-
sign can be classified in one of five emission classes, ranging from the most
noisy class I to the least noisy class V. It will be required for the charge
pump to satisfy class V limitations during operation. A DC masking is used
to smooth the quick transient current emissions from the charge pump: the
DC masking requires current consumption and therefore it is useful to in-

51
clude EMC simulation during the design process in order to avoid needing to
enhance the DC consumption due to electromagnetic interference problems
once the design is completed.
The simulation parameters include a conservative step option which in-
crease the work load for the simulation but assure more precise results. The
detector has been operated in peaking mode, with Gaussian filter and spline
interpolation settings, according to the Infineon guidelines for using the tool
[25].

6.2 Simulation Results

The comparison between two different charge pumps is presented for a 50µA
load current conditions in figure 6.2.

52
Figure 6.2: Electromagnetic noise emission profile for a lower 10.5MHz fre-
quency (bottom) and a higher 21MHz (top) charge pump under 50 µA current
load. H1 is the first and main harmonic of the spectrum placed at the clock
frequency. Note that the faster design has half area consumption respect to
the slower model as described in the last section of chapter 5

The two different models, operating at 21MHz and 10MHz, show similar
emissions amplitudes in low load conditions, peaked at the respective operat-
ing frequency. The spectrum is characterized by a main emission tone placed
at the charge pump operating frequency. Successive harmonics are repeated

53
at integer multiple of the main clock frequency. The noise has been simulated
in the range 100kHz to 200MHz for completeness; the most important range
for this application is between 1 and 100 MHz.
The simulation is repeated for a high load condition. As noticed in the
previous section smaller charge pump have a slightly lower efficiency and
therefore consume more current to supply the same load when compared
with a lower frequency charge pump which employs larger capacitors. This
consideration may suggest that a higher frequency charge pump will be more
problematic in its electromagnetic noise emission. Figure 6.2 and 6.3 show
that this is not the case:

54
Figure 6.3: Electromagnetic noise emission profile for a lower 10.5MHz fre-
quency (bottom) and a higher 21MHz (top) charge pump under 250 µA
current load. H1 is the first and main harmonic of the spectrum placed at
the clock frequency. The target emission class level V maximum noise that
can be emitted at a given frequency is showed as a blue line: the emission
profile must be lower than this threshold for every frequency

To understand why the electromagnetic noise emitted by the higher fre-

quency charge pump is around 2dBµV lower than its slower alternative con-
sider figure 6.4, where the output current of three different charge pump is

55
superimposed and confronted. The green signal is relative to a 5MHz charge
pump which uses proportionally bigger capacitor in respect to the faster blue
(10MHz) and red (20MHz) alternatives. For this reason while the green only
switches once in the proposed time interval the blue will switch twice and
the red charge pump will switch four times. The total current consumption
is higher for the faster, less efficient, models, and in fact the sum of the areas
under the four red spikes will be higher than the sum of the area of the two
blue ones, which in turn will be higher that the area underlying only the
green signal. On the other hand note that the peak transient current inten-
sity will be lower for the faster models, which explains why the green peak
is the highest. By switching more often the average peak current intensity is
actually diminished in the faster design even if the total current consumption
is greater.

Figure 6.4: Comparison between differently dimensioned charge pump de-

signs output current profiles. The charge pump corresponding to the blue
signal a 5MHz frequency, the green one 10MHz and red is the fastest at
20MHz

In other words the presented charge pump working at a higher frequency

will not emit more electromagnetic noise because although the transient is
indeed sharper the current also lower in absolute value for every switched
capacitor, the resulting effect being that the main noise will be emitted at

56
a higher frequency but not with more amplitude. Both under high and low
load conditions the class V limitation are respected.

57
Chapter 7

Conclusions

The development of DC-DC converters was summarized and charge pump

design metrics which allow for performance comparison between different
designs have been discussed. An overview of DC-DC converters topologies
was presented and a cross coupled charge pump was proposed in order to
turn on the power DMOS in a high side switch application and assure that is
operated in the low ohmic region. The advanced functionality of a high side
switch make it an essential item in electronics for the automotive industry.
Frequency optimization has shown the possible benefits and challenges of a
faster charge pump: In particular it has been shown that a higher frequency
charge pump will use smaller capacitors for a reduced total area occupation
while still performing on par with much larger and slower designs. The
electromagnetic emissions of the charge pump has been studied and it was
shown that faster switching with lower currents will shift the first harmonic to
higher frequency, not increasing overall noise emissions: therefore the higher
frequency charge pump has been simulated in compliance with the modern
automotive standards. The charge pump has been partially layout but it was
only simulated and it has not been tested yet on silicon. As a continuation of
this work it would be interesting to test the device and verify that it behaves
as predicted by the analog SPICE-level and electromagnetic simulations. A
further study could investigate how much the charge pump could be made
smaller and faster before the aforementioned heating due to higher current
consumption and less dissipation area becomes problematic.

58
Bibliography

[1] Feng Pan, Tapan Samaddar: Charge Pump Circuit Design, 2006.

[2] Feng Pan: Charge Pump Design, 2015.

[3] Zong Han Hsieh, Nan Xiong Huang, Shui-Yuan Yang et alt: A novel
Mixed-Structure Design for High-Efficiency Charge Pump, 2009.

[4] Muhammad Ansari Qiang Chen, et alt: Diode Based Charge Pump De-
sign using 0.35um Technology, 2010.

[5] Oi-Ying Wong, et alt: A Low-Voltage Charge Pump with Wide Current
Driving Capability, 2010.

[6] Waquar Ahmad, Svante et alt: Single Clock Charge Pump Designed in
a 0.35um Technology, 2011.

[7] Ming-Dou Ker, Shih-Lun Chen et alt: Design of a Charge Pump Cir-
cuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS
Process, 2006.

[8] Jae-Youl Lee, Sung-Eun Kim, Seong-Jun Song et alt: A Regulated

Charge Pump With Small Ripple Voltage and Fast Start-Up, 2005.

[9] Davide Baderna, Alessandro Cabrini, Marco Pasotti, Guido Torelli:

Power efficiency evaluation in Dickson and voltage doubler charge pump
topologies, 2006.

[10] Jingjing Che, Chun Zhang et alt: Ultra-Low-Voltage Low-Power Charge

Pump for Solar Energy Harvesting Systems, 2009.

[11] Sébastien Cliquennois, Achille Donida, Piero Malcovati, Andrea Baschi-

rotto, and Angelo Nagari: A 65-nm, 1-A Buck Converter With Multi-
Function SAR-ADC-Based CCM/PSK Digital Control Loop, 2012.

59
[12] Feng Pan, Tapan Samaddar: Basic operation of a Charge Pump, in
Charge Pump Circuit Design 2006.

[13] Gaetano Palumbo and Domenico Pappalardo Charge Pump Circuit With
Only Capacitative Loads: Optimized Design 2006.

[14] Gaetano Palumbo and Domenico Pappalardo Charge pump circuits: an

overview on design strategies and topologies 2010.

[15] Jun Wu, Kana Chang : MOS Charge Pumps for low voltage applications,
1998.

[16] James Dickson: On-chip high-voltage generation in MNOS integrated

circuits using an improved voltage multiplier technique, 1976.

[17] Tony Chan Carusone, David Johns and Kenneth Martin: Analog Inte-
grated Circuit Design, 2015.

[18] Jacob Baker: CMOS: Circuit Design, Layout, and Simulation, 3rd Edi-
tion, 2012.

[19] Andrew Mason: Lecture notes on CMOS inverters, 2013.

[20] Bernhard Sorger: High Efficient Charge Pump Design in SMART Power
Technologies, 2012.

[21] Andreas Kucher: Protection and Diagnosis of Smart Power High-Side

Switches in Automotive Applications, in Analog Circuit Design, Herman
Casier Michiel Steyaert and Arthur Roermund, 2008.

[22] Tim Williams, et alt: EMC for product designers, 2010.

[23] Alexandre Boyer: Electromagnetic Compatibility of Integrated Circuits,

2009.

[24] David Staggs: Using a LISN as an Electronic System EMC Diagnostic

Tool, 2003.

[25] Bernd Deutschmann Infineon course material: Example of conducted

emission simulations, 2015.

[26] Wilson Carey: Marx Generator Design and Performance, 2002.

60