ECT 202 Analog Circuits

Module 3

Joseph George K N
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 Module 3

MOSFET amplifiers: MOSFET circuits at DC, MOSFET as an

amplifier, Biasing of discrete MOSFET amplifier,

Small signal equivalent circuit. Small signal voltage and current

gain, input and output impedance of CS configuration.

CS stage with current source load, CS stage with diode-connected

load.

Multistage amplifiers - effect of cascading on gain and bandwidth.

Cascode amplifier

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Objectives

• To understand the relevance of CMOS Technology

• To become familiar with the physical structure, working and the characteristics of
MOSFET.

• To analyze and design MOSFET amplifier circuits.

• To study the small signal analysis of MOSFET.

• To find the small signal voltage and current gain, input and output impedance of CS
configuration

• To realize Current Sources and diode connected load using MOSFET.

• To be able to analyze cascaded and cascoded amplifier configurations with BJT and
MOSFETs.

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 Relevance of MOSFET

The idea of MOFET was patented by J E Linienfeld in 1930s before the invention of
BJT.

Became popular only in 1960s - Owing to the fabrication limitations

CMOS devices were introduced in mid 60s initiating the revolution in semiconductor
industry

CMOS Technology advantages

Input current – Very low

Input Resistance – Very High
Power dissipation – Low
Packing density – High
Temperature stability – Superior
Noise immunity
Scalability

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 Table: Comparison of BJT and MOSFET

PARAMETER BJT MOSFET

Symbol

Metal Oxide Semiconductor Field Effect

Name Bipolar Junction Transistor
Transistor

Operating region Active, saturation and cut off Triode, saturation and cut off

Terminals Emitter, Base and Collector Gate (insulated), Drain and Source

Type Current controlled Voltage controlled

NPN and PNP n channel, p channel

Enhancement mode and Depletion mode

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 Cont.

PARAMETER BJT MOSFET

Input current Milli or micro amps Pico amps

Input Resistance Low (KΩ) Very High (MΩ)
Power dissipation High Low
Packing density Low High
Temperature poor Superior
stability
Scaling Not effective Improves performance
Application Low current applications High current, high power applications

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Field Effect Transistor

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 Field Effect Transistor
The name FET - an electric field is established by the charges present which controls the
conduction

Fig: (a) JFET (b) Water analogy for JFET

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 MOSFET
A slab of p-type material is
formed from a silicon base
(substrate).

To allow current flow through the

channel, two contacts (Source and There is no direct electrical connection
Drain terminals) are made through between the gate terminal and the
heavily doped n+ regions. channel of a MOSFET.

The gate, the dielectric and channel form

The Gate is connected to a metal contact a capacitor
surface but remains insulated from the n-
channel by a very thin silicon dioxide
(SiO2) layer (dielectric).
Many discrete devices provide an
additional terminal labeled B, resulting in
a four-terminal device.

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 Symbol

Or Or

Fig:

Structure

Or

The n+ regions (source

and drain) form diodes
with the p-type substrate.

Fig: Structure of NMOS

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Materials used in the device
The gate plate is realized by metal
(later replaced by non crystalline
The dielectric layer sandwiched between the
silicon with heavy doping -poly
gate and the substrate is created by growing
silicon)
silicon dioxide (or simply “oxide”) on top

The source and drain are heavily  The insulating SiO2 layer accounts for the
doped n+ regions. For proper very desirable high input impedance of the
operation these junctions must be device.
reverse biased.

The reason for the label metal–oxide–

semiconductor FET:
 metal for the drain, source, and gate
connections. The insulating layer between the
 oxide for the silicon dioxide insulating gate and the channel has resulted in
layer. another name for the device
insulated-gate FET (IGFET)
 semiconductor for the basic structure on
which the n- and p-type regions are
diffused.

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Operation
MOSFET may conduct current (ID)between the source and drain if a channel of electrons is
created by making the gate voltage sufficiently positive –Enhancement mode

Consider S and D are grounded and the gate voltage is varied.

As Vg increases from zero, positive charge on the

gate repels the holes in the substrate thereby
exposing negative ions and creating a depletion
region.
But no current flows and the MOSFET is off.

As VG increases, the width of the depletion region and

the potential at the oxide silicon interface increase.
The structure resembles two capacitors in series.

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 If VG is sufficiently high, electrons are attracted to the
interface ultimately leading to the formation of the
channel.

Now the interface is inverted.

The gate voltage at which the channel begins to appear
is called Threshold voltage VTH.(range: 300mV –500mV)

The channel between S and D can be viewed as a variable

resistor – value changes with gate voltage voltage dependent resistor

No current flows between S and D because the two terminals are at the same potential.

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 With applied VG and VD
Voltage VD is applied to the drain
terminal to start the current flow

Two views of operation

1. VG is varied while VD remains constant
2. VD is varied while VG remains constant

Transfer Characteristics
VD is kept constant and VG is varied.

If VG < VTH no channel exists, the device is

off, and ID = 0 regardless of the value of
VD.

If VG > VTH, then ID > 0, the source-drain

path may act as a simple resistor, yielding
the ID-VG characteristic as shown.

Current is carried by free electrons

traveling from source to drain

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Drain Characteristics
VD is varied while VG remains constant

The slope of the characteristic is equal to 1/Ron, where

Ron denotes the “on-resistance” of the transistor.

The graph can be plotted for different values of VG

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 As VGS increases, the concentration of electrons near the SiO2 surface increases.
The level of VGS that results in the significant increase in drain current is called
the threshold voltage VT.

 Since the channel is nonexistent with VGS 0 V and “enhanced” by the application
of a positive gate-to-source voltage, this type of MOSFET is called an
enhancement-type MOSFET.

 As VGS > VTH , the density of free carriers in the induced channel will increase,
resulting in an increased ID and the device acts as a voltage-dependent resistor.

 The drain current ID can be controlled by the Gate voltage.

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 Channel Pinch off

The potential difference between the gate and the

oxide-silicon interface decreases along the x-axis

If the drain voltage is high enough to produce VD – VG > VTH (at length L), then
the channel ceases to exist near the drain.

The gate-substrate potential

difference is not sufficient at
x = L to attract electrons and
the channel is “pinched off”

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If VD is increased, the voltage difference between
the gate and the substrate falls to VTH at some
point L1 < L.

So, the channel is pinched off between L1 and L.

Once the electrons reach the end of the channel,

they experience the high electric field in the
depletion region surrounding the drain junction
and are rapidly swept to the drain terminal.

VD no longer affects the current

ID will eventually reach a saturation significantly, and the MOSFET
level. acts as a constant current source.

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 Drain Current

The desired charge density Q = CV,

where, C is the gate capacitance per unit length
and V the voltage difference between the gate and the channel.
C = W Cox
where, Cox is the gate capacitance per unit area(F/m2)
and W is the width of the Transistor.

Also, V = VGS - VTH

coulomb/meter …... (1)

Since the charge density decreases along the length of the transistor, Eq. (1) is
modified as
…... (2)
where, V(x) is the channel potential at

Any further increase in VDS at the fixed value of VGS will not affect the
saturation level of ID until breakdown conditions are encountered.
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 …... (3)

Integrating,

Thus,

…... (4)

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Different Observations

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Triode and Saturation Regions

The device operates in the “triode region” if VDS < (VGS – VTH) It will be in the “deep triode
region” for VDS < 2(VGS – VTH),
where the transistor operates as
ID depends on VDS (obeys ohm’s law due to uninterrupted channel) a resistor.

The channel experiences pinch-off if VDS = (VGS – VTH).

And the drain current becomes, …... (5)

ID reaches saturation region, becomes

constant for VDS > (VGS – VTH)

MOSFET can operate as a

constant current source in the
saturation region

The square-law dependence of ID upon VGS – VTH suggests that the

device can act as a voltage-controlled current source

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 …... (6)

The k term is a constant that is a function of the construction of the device.

The value of k can be determined from

Exercise

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Comparison of BJT and MOSFET characteristics
BJT MOSFET

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 Channel Length Modulation
The point at which the channel vanishes moves toward the source
as the drain voltage increases, i.e.,

This phenomenon called “channel-length modulation” , yields

a larger drain current as VDS increases because ID α 1/L1.

Channel-length modulation results in a

finite output impedance given by the
inverse of the ID-VDS slope

To account for channel-length modulation, multiply ID by Other second order effects

a corrective term:  Velocity Saturation
 Body Effect
…... (7)  Subthreshold Conduction
where λ is called the “channel-length modulation coefficient.

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 MOS Transconductance
MOS transistor can be characterized by its transconductance:

gm is a measure of the “strength” of the device: a

higher value corresponds to a greater change in the
drain current for a given change in VGS.

Using Eq. for Id,

…... (8)

Also,

Or,

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 MOSFET : p-channel enhancement type (PMOS)
 The turn on process of PMOS is similar to
that of NMOS but all polarities reversed.

 When the VGS is sufficiently negative, an

inversion layer consisting of holes is formed
thus forming a channel.

With applied -VG and –VD

Voltage -VD is applied to the drain
terminal to start the current flow

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PMOS
Transfer Characteristics
VD is kept constant and VG is
varied.

If VG < VTH no channel exists, the

device is off, and ID = 0 regardless
of the value of VD.

If VG > VTH, then ID flows, the

source-drain path may act as a
simple resistor, yielding the ID-VG
characteristic as shown.
Transfer Characteristics Drain Characteristics

Drain Characteristics
Gate voltage is kept constant at -VG and VD is varied.

The slope of the characteristic is equal to 1/Ron,

where Ron denotes the “on-resistance” of the
transistor.
The graph can be plotted for different values of -VG

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Depletion mode MOSFET - n channel

With VG =0 and VD
A channel is diffused between the source
and drain with n type dopant.
Drain current IDSS flows for VGS = 0

With -VG and VD

The redistribution of carriers in the channel
causes an effective depletion of majority
carriers – depletion MOSFET.

ID is reduced with increasing negative gate

voltage (-VGS)

The channel region near the drain is more

depleted than that near the source
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With +VG and VD
The D MOSFET may also be operated in
enhancement mode, by applying
positive VG.

ID is increased with increasing positive

gate voltage (+VGS )

Conductivity of the channel

increases and the current
rises above IDSS .

As VGS increases positively,

then ID will increase at a rapid
rate

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Transfer Characteristics
VD is kept constant and VG is varied,
yielding the ID-VG characteristic as
shown.

The transfer curve can also be

obtained using Shockley’s equation

Drain Characteristics
Transfer Characteristics
• The region between cutoff and saturation level of ID is referred to as the
depletion region.

• The application of a positive gate-to-source voltage has “enhanced” the level

of free carriers in the channel – so the name enhancement region/mode

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 MOSFET as an Amplifier
 Functions as a voltage-controlled current source
when operated in the Saturation region.
Trans conductance amplifier
 Is a transconductance amplifier

The input is applied to the gate and the output is

sensed at the drain

If the bias currents and voltages of a MOSFET are

only slightly disturbed by input signal, it can be
represented by a linear, small-signal model.

CS Amplifier
For small signals, M1 converts the input voltage
variations to proportional drain current changes, and RD
transforms the drain currents to the output voltage.

Small signal Model

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 Biasing of MOFET Amplifier  To establish the desired DC voltages and
currents for the operation of the amplifier.

The biasing technics are quite different from those described for BJT amplifiers

The relationship between input and output quantities is nonlinear due to the squared term
in Shockley’s equation.

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Fixed Bias Configuration – Depletion mode MOSFET
Since VGG is a fixed dc supply, the voltage VGS is fixed in
magnitude, resulting in the designation “fixed-bias
configuration.

The coupling capacitors are open circuited

for the dc analysis.

The resistor RG is present to ensure that Vi

appears at the input to the FET amplifier.

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The zero-volt drop across RG permits replacing
RG by a short-circuit equivalent as shown.

Applying Kirchhoff’s voltage law,

This value of VGS is now applied in Shockley’s

equation to find the drain current ID.

Thus, the drain current ID is controlled

by Shockley’s equation.

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Also,

Drawback:
Since the configuration requires
two dc supplies, its use is limited

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Characteristics of fixed bias configuration

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Self Bias Configuration –
Depletion mode MOSFET

The self-bias configuration eliminates the

need for two dc supplies. The controlling
gate to-source voltage is now determined by
the voltage across a resistor RS

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Self Bias -DC Analysis
The zero-volt drop across RG permits replacing RG
by a short-circuit equivalent as shown.

Applying Kirchhoff’s voltage law, for the closed

loop

Thus VGS is not fixed, but a function of ID

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A mathematical solution could be obtained simply by substituting for
VGS in Shockley’s equation

By performing the squaring process and rearranging

terms,

The quadratic equation can then be solved for the

appropriate solution for ID.
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 Characteristics of self bias configuration

Draw a straight line connecting the two points

i.e.,

i.e.,

Fig: Finding the Q point for self bias configuration

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 Voltage Divider Biasing –
Depletion mode MOSFET
Eliminates the need for two dc supplies.

The controlling gate to source voltage is now

determined by the voltage VG

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 Voltage Divider Biasing - DC analysis
The capacitors are open circuited

Also,

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Voltage Divider Biasing - DC analysis

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 Characteristics of voltage divider biasing configuration
The characteristics and the load line are plotted on the same graph
and a solution determined at their intersection.

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Once the quiescent values are fixed, the other network values are determined by

Also,

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Voltage Divider Biasing (n-channel enhancement mode MOSFET )

Solve these equations to obtain ID and VGS.

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Small Signal Model of JFET
Represent the device using a model, so that it can be used in further analysis and design

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Small Signal Model of D-MOSFET

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Small Signal Model of E-MOSFET
Note:

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Common Source Amplifier

The basic CS stage is similar to the common

emitter topology, with the input applied to
the gate and the output sensed at the drain.

For small signals, M1

converts the input voltage variations to
proportional drain current changes

and

RD transforms the drain currents to the output

voltage.

Figure. (a) Common-source stage

(b) small-signal mode.

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 Design Goals

Now, the transconductance is given by

Also, =>
Therefore, Or,

Thus,

Avoid signal distortion that occurs when the device enters cutoff or triode

(a) Avoid the MOSFET cut off Mode,

If drain voltage VD (DC component) is too close to VDD,
when the signal is applied, VD(t) may cross VDD i.e.,

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The MOFET enters cutoff and the signal will be distorted

Minimize the drain voltage (DC) by designing ID as

large as possible

(b) Avoid the MOSFET Triode Mode,

Thus, the design goals are

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Small signal voltage and current gain, input and output
impedance of CS configuration

, since the gate terminal draws zero current.

, since the gate current is zero.

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 Realization of current sources MOS transistors operating in saturation can act
as current sources.

 An NMOS device serves as a current source

with one terminal tied to ground, i.e., it draws
current from node X to ground (sinks current).

 On the other hand, a PMOS transistor

draws current from VDD to node Y
(sources current).

If λ=0, these currents remain independent of VX

or VY so long as the transistors are in
saturation). λ - channel-length modulation coefficient.

 Note: The drain terminal of a MOSFET can draw a dc current and still
present a high impedance.

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Note:
PMOS or NMOS devices configured as shown in Fig. (c) and (d) do not operate as
current sources because variation of VX or Vy directly changes the gate-source voltage of
each transistor, thus changing the drain current considerably

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 Current mirror
The typical biasing schemes fail to So, special circuit is designed to create supply
establish a constant collector or and temperature independent current –
drain current if the supply voltage “golden current”
or the ambient temperature are
subject to change.

A method of “copying” this constant current without duplicating the entire circuitry is
used in the IC design
Current mirror
A circuit designed to copy a current through one
active device by controlling the current in the
circuit, keeping the output current constant
regardless of loading.

Replicates the input current of a current sink or

current source as an output current. The output
current may be identical to the input current or can
be a scaled version of it
Current mirror

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BJT circuit as current mirror

Current mirror (a)single stage

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BJT current mirror with more transistors

If there are a number of amplifier stages, a

constant dc current( IREF ) is generated at one
location and is then replicated at various other
locations for biasing the various amplifier
stages.

Current mirror with more

transistors

Advantage
The effort for generating a stable reference current, need not be repeated for every
amplifier stage.

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 MOFET circuit as current mirror

The drain current of the two transistors are

Taking the ratio of currents,

MOFET Current mirror

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MOFET circuit with more Transistors

A current mirror may consists of many current

sources.

This circuit is particularly useful in integrated

circuit design.

The multiple current sources can have different current values (different K values)
by modifying the MOSFET channel width-to length ratio (W/L) for each transistor

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CS stage With Current-Source Load

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CS stage With Diode Connected Load

Exhibits only a moderate gain due to the relatively low impedance of the
diode-connected device

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Voltage gain

i.e., the gain is given by the

dimensions of M1and M2and
remains independent of process
parameters μn and C ox and ID.

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Multistage Amplifiers

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 Multistage Amplifiers
Used to meet given amplifier specifications (gain, bandwidth, impedance level etc.), two or
more stages are cascaded.

 The stages are usually not identical - each is designed to serve a specific purpose.

For example,
To design an amplifier with large input impedance and small output impedance,

• The first stage is designed to have a large input resistance

to avoid signal loss when the amplifier
is fed from a high resistance source.

• The middle stages provide the required gain.

Also provide other functions such as conversion of
signal to single ended mode , DC level shifting etc.

• The final stage in the cascade is designed to have a low output resistance.
to avoid signal loss when a low value
load is connected to the amplifier.

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Note:

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Cascaded systems

Fig: 2 stage System

For 2 stage System,

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Total Gain of Cascaded systems

For n stage System,

Fig: n stage system

Overall gain increases.

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Bandwidth of Multistage Amplifier

Fig: Frequency response of single stage and multi

stage amplifiers

Overall bandwidth decreases.

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Multistage RC coupled Amplifier

Fig: Circuit of cascaded, two stage RC coupled Amplifier

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Multistage FET Amplifier

Fig: Circuit of cascaded, two stage FET amplifier

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 Cascoded systems
A combination of CE and CB stages (for BJT)

or CS and CG stages (for MOSFET)

The input is applied to the CE stage or CS stage – Amplifying stage

The output is taken from CB stage or CG stage – Impedance boosting stage

The load could be a passive load (resistive) or active load.

Note:

The voltage gain can be increased by raising the output impedance.

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 Bipolar Cascode Amplifier
To maximize the voltage gain of a common-
emitter stage, the collector load impedance
must be maximized.

In the case of an ideal current source serving as the

load, the voltage gain is

If a transistor is stacked on top of Q1, the circuit

achieves a high output impedance and a voltage
gain higher than that of a CE stage is achieved.

Fig: (a) Ideal current source serving as load (b) Cascode

connection to increase the output impedance

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Has one of the two configurations as shown.

Fig: BJT Cascode Amplifier (a) Configuration 1 (b) Configuration 2

In each case the collector of the leading transistor is connected

to the emitter of the following transistor.

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Note:
• A cascode amplifier comprises of a CE amplifier and a CB amplifier
stages in cascade. Q1 is in CE configuration and Q2 in CB configuration.

• Principal advantage of this circuit is its low internal capacitance which is

a limiting factor of gain at high frequencies.

• Cascode amplifier can amplify wide range of frequencies. This is because

no high frequency feedback occurs from the output back to input through
the miller capacitance as it occurs in transistor CE configuration.

 provides same voltage gain of CE amplifier but in wide range of

frequencies.

The advantages of CE and CB stages

are put together in cascode connection.

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Thus, cascode configuration provides

o a relatively high-input impedance and voltage gain for the first

stage
 to ensure the input Miller capacitance is at a minimum

o an excellent high-frequency response for the CB stage

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MOS Cascode Amplifier
The cascade of CS stage and CG stage is called a cascode topology
Overdrive voltage
M1 – input device and M2 – cascade device VOV = VGS − VTH

M1 generates a small signal drain current proportional

to Vin and M2 routes the current to RD

Now,

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The minimum output voltage for which both transistors
operate in saturation is equal to the overdrive voltage of
M1 plus that of M2.

Addition of M2 to the circuit reduces the output voltage

swing by at least the overdrive voltage of M2

M2 is stacked on top of M1

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The cascode configuration using MOSFET

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Summary

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Summary

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