Birla Institute of Technology & Science, Pilani
Work Integrated Learning Programmes Division
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Digital Learning Handout
Part A: Content Design
Course Title Processor Architectures and Design
Course No(s) ESZG611
Credit Units 5
Credit Model 3-2-0
Instructors Prof. Anupama Karuppiah
Version No: 1.0
Date: 27/01/2025
Course Description: Scalar Architectures – RISC Architectures, Instruction level Parallelism –
Scalar Pipelines, Superscalar architecture, Multicore processors, Data level Parallelism- GPU,
Thread level Parallelism, Vector architecture, Memory Systems- Virtual Memory, Paged
Memory, Cache, Hardware virtualization, Processor design for AI. Domain-specific processors”,
VLIW, Performance modelling of advanced processors.
Course Objectives
No Course Objective
CO1 To understand different Processor Architecture – RISC & CISC and Pipelines
CO2 To understand design of ILP Architectures
CO3 To understand design of DLP Architectures
CO4 To understand design of TLP Architectures
Text Book(s):
T1 Computer Architecture: A Quantitative Approach, by J.L. Hennessy & D.A. Patterson, Morgan
Kaufmann., 3rd Ed, 2006.
T2 Modern Processor Design: Fundamentals of Superscalar Processors, John Paul Shen &
Mikko.H.Lipasti , Tata McGraw Hill,2011.
T3 Advanced Computer Architecture: A Design Space Approach, Sima, Fountain,Kacsuk, Pearson,
2012.
Reference Book(s) & other resources:
R1 Parallel Computer Architecture: A Hardware / Software Approach, David E Culler &
Jaswinder Pal Singh., Morgan Kauffmann / Harcourt India, 2002.
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R2 Computer Architecture Pipelined& Parallel Processor Design, M.J.Flynn, Narosa Publishing
House, 2006
R3 DSP Processor Fundamentals, Phil Lapesly , Jeff Bier, Amit Shoham, Edward.A.Lee, Wiley India
Edition,2011.
R4 Journal & Conference Proceedings.
Learning Outcomes:
LO1 Students should gain an understanding of Basic Scalar Architecture
LO2 Students should gain a detailed understanding of designing scalar and super scalar
pipeline processors
LO3 Students should gain a detailed understanding of designing Vector and GPU
Architecture.
LO4 Students should gain a detailed understanding of Thread Level Parallelism –
Including memory and cache in TLP
LO4 With the acquired knowledge, students should be able to come up with their own
Micro-architectures given an ISA as a specification
Part B: Learning Plan
Contact List of Topic Title Sub-Topics Reference
Session
Introduction to Parallel Class Notes
1
Processing
Introduction to ILP Pipeline Dependencies, Arithmetic & T1- Ch-3,
2
Architectural Pipelines, Pipeline Idealism T2 – Ch1
Pipeline architectures – Typical RISC Pipeline Design T2-Ch2
3 Design of RISC Pipeline CISC Pipeline
Pipeline Examples
Superscalar Architectures - Widening of Pipeline T2 – Ch4
4 Pipeline Design – Data Path – Parallel Fetch & Decode &5
Part 1 Instruction Dispatch & Issue
Superscalar Architectures - Register Renaming & Tomasulo T2 – Ch4
5 Pipeline Design – Data Path- ROB &5
Part 2
Superscalar Architectures - Superscalar Pipeline Operation - Examples T2 – Ch 4 &
6 Pipeline Design – Data Path- Ch 5
Part 2
Superscalar Architectures – Basic Branch Prediction Schemes T2- Ch 9,
Branch Prediction -Part 1 BTA & Misprediction Penalty & Recovery Ch 10
7 Advanced Branch Prediction – Correlated Branch
Prediction
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Superscalar Architectures – Advanced Branch Prediction – Hybrid T2- Ch 9,
8 Branch Prediction – Part 2 Advanced Branch Prediction – Tournament Ch 10
Predictors
Fine Grained Parallel SIMD T1-Ch 4 &
SIMD Architectures
9 Coarse Grained SIMD Class Notes
Examples of SIMD operation
VMIPS Architecture T1-Ch4
10 Vector Processors Multi-Lane Systems
Performance Analysis of vector Systems
11 GPU -1 SIMD Extensions T1-Ch4
12 GPU -2 NVIDIA GPU Architectures - SIMT T1- Ch4
CUDA Class
13 GPU -3
Notes
Thread & Process Level Shared Memory & Distributed Memory T1-Ch5, T2
14 Parallel Architectures- Architecture Ch-11
Introduction Cache in TLP
Snoopy Cache Protocols T1-Ch5
MSI, MESI
15 Cache Architectures
MESIF, MOSIF
4C of Cache
Explicit Multi-Threading T2 – Ch11 +
Multi-Threaded Implicit Multi-Threading Class Notes
16
Architectures Hyper-Threads
Multiple-cores
Experiential Learning Components:
1. Project work: Design of Superscalar Pipelines.
2. Case Study:
3. Simulation: Yes
4. Work Integrated Learning Assignment Students can apply the learning to the work they are
doing in the embedded hardware/software field and present it briefly in the class.
5. Design work/ Field work: None
Objective of Experiential Learning Component:
• To develop skills which will help students to design micro-architectures of pipelined processors
• To develop the skills to handle data level parallelism – especially for Big Data
Scope of Experiential Learning Component:
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• This will help participants to understand Micro-Architecture design and design processors for
common RISC ISAs
• This will also help participants to design – Register access, Branch Predictors and Ccahe
Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
Evaluation Name Type Weight Duration Day, Date, Session, Time
Component
Assignment – I Online 15% 21 days
EC-1
Assignment -II Online 15% 21 days
EC - 2 Mid-Semester Test Closed Book 30% 2 hours
Comprehensive
EC - 3 Open Book 40% 2 ½ hours
Exam
EC1* (20% - 30%): Quiz (optional): 5-10 %, Lab Assignment/Assignment: 20% - 30%
Syllabus for Mid-Semester Test (Closed Book): Topics in Contact session: 1 to 8
Syllabus for Comprehensive Exam (Open Book): All topics
Important Links and Information:
eLearn Portal: https://elearn.bits-pilani.ac.in
Students must visit the eLearn portal regularly and stay updated with the latest announcements and
deadlines.
Contact Sessions: Students should attend the online lectures as per the schedule provided on the eLearn
portal.
Evaluation Guidelines:
1. EC-1 consists of either two Assignments or three Quizzes. Students will attempt them through the
course pages on the eLearn portal. Announcements will be made on the portal in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
3. For Open Book exams: “open book” means text/ reference books (publisher copy only) and does
not include any other learning material. No other learning material will be permitted during the
open book examinations. For Detailed Guidelines refer to the attached document.
EC3 Guidelines
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the student
should follow the procedure to apply for the Make-Up Test/Exam, which will be made available
on the eLearn portal. The Make-Up Test/Exam will be conducted only at selected exam centres
on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self-study schedule
as given in the course handout, attend the online lectures, and take all the prescribed evaluation
components such as Assignments/Quizzes, Mid-Semester Tests and Comprehensive Exams according to
the evaluation scheme provided in the handout.
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