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Asynchronous Counter Design Guide

The document discusses asynchronous and synchronous counters, detailing their characteristics, applications, and design procedures. It outlines the steps for designing an asynchronous counter, including determining the number of flip-flops, writing the counting sequence, and creating logic and timing diagrams. Additionally, it provides examples of various counter types and their configurations, such as Mod-6 and Mod-10 counters.

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allenmts2023
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68 views14 pages

Asynchronous Counter Design Guide

The document discusses asynchronous and synchronous counters, detailing their characteristics, applications, and design procedures. It outlines the steps for designing an asynchronous counter, including determining the number of flip-flops, writing the counting sequence, and creating logic and timing diagrams. Additionally, it provides examples of various counter types and their configurations, such as Mod-6 and Mod-10 counters.

Uploaded by

allenmts2023
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Asynchronous counters

Counter
• A circuit to count (binary) clock pulses.
• Types of counters :
oAsynchronous (Ripple) counters.(Triggered serially, Simple, Easy design, Slow)
oSynchronous (parallel) counters. (Triggered Together, Tedious, Complex, Fast)

• Applications:
• Frequency Dividers
• Digital Clocks
• Multimeters
• Data Converters
Design of Asynchronous counter general Procedure
• Step 1: Decide No. of F/F as N ≤ 2n , and the Flip-flop itself (D/T/JK)
n= no. of f/f
N no. to be counted (Mod-N counter)
• Step 2: Write the desired counting sequence. (TT/State Table/State
diagram)
• Step 3: if all the states are used, make the logic diagram and timing
diagram as desired (up/down/bidirectional)
• Step 4: Ignore this step, if no unused state (i.e no don’t care). If unused
states are there then in the counting sequence table add a column for
reset signal (R or R’) and obtain its minimal expression using either K-
map or by observation (usually implemented by NAND gate). Connect
the output of reset signal to clr or clr’ to get the desired count.
3
2-Bit negative edge triggered up Counter
2-Bit negative edge triggered down Counter
2-Bit negative edge triggered up-down Counter
Divide by 2 counter :

7
Divide by 2 counter :
•

8
Example :
• If an input frequency of 200 KHz is applied to
a binary ripple counter that has 6 FFs , what
is the out put frequency of the last FF in KHz
?
•

9
2-Bit positive edge-triggered up-Counter
2-Bit positive edge-triggered down-Counter
2-Bit positive edge-triggered up-down-Counter
Asynch Mod-6
Step 1: No. of F/F = 3 (2N>=6)
Step2: Nature: Asynchronous (o/p of f/f goes
to CLK of next F/F
Step 3: State Diagram
Step4-5: Circuit design for Reset Signal
Async Mod-10 (Decade Counter)

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