Computer Organization

Why to study?

• Acquire knowledge of computer system’s

functional components
• Their characteristics
• Their performance and their interactions
Knowing the Architecture and Organization
helps to write a program, that run more
efficiently on real machine.
Selection of a system for particular application.
 Computer Architecture
• It is science of integrating various components
used in the computer to achieve the level of
functionality and performance.
• It is concerned with structure and behaviour of
the computer as seen by user.
• Architecture refers to those attributes of system
visible to the programmer.
– Instruction set, number of bits used for data
representation, I/O mechanisms, addressing
techniques.
– e.g. Is there a multiply instruction?
 Computer Organization
• The way the hardware components operate and
the way they are connected together to form the
computer system.
• Organization is how features are implemented.
• It describes operational units and their
interconnections that realize the architectural
specification.

– Control signals, interfaces, memory technology.

– e.g. Is there a hardware multiply unit or is it done by
repeated addition?
A particular architecture of
computer may span for many
years but the organization
changes with changing
technology.
Basic Computer Organization
 Basic Computer Organization
Digital Computer
consists of
• Processor (CPU)
• Memory (Read only
and R/W )
• External memory
(HDD)
• Input /Output
Devices
• System Bus
 Function of Digital computer
1. Input :- the process of
entering the data and
instructions into the
computer system.
• Input device used for
this, also converts these
data and instructions in
computer acceptable
format.
 Function of Digital computer
2. Storage/ Memory: Saving
data and instructions so
that they are available for
processing.
3. Processing: Performing
Arithmetic or logical
operation on data in order
to convert them into useful
information.
 Function of Digital computer
4. Output: After processing
the data, some useful
information or results are
produced for the user.
5. Control : Directing the
manner and the sequence
for the above operations.
Concept of Bus: Address Bus, Data bus
and Control Bus.
• Buses are physical devices. They are realized in
the form of conducting paths on electronic PCB.
• They are used to interconnect different parts of a
computer.
• A CPU’s internal bus is within the IC.
• External Bus is on PCB, used for interconnecting
different subsystems.
• Various components forming computer system
are linked through buses that transfer
instructions, data, address and control
information among these components.
Concept of Address Bus, Data bus and
Control Bus.
 3 Types of buses: Address Bus, Data
bus and Control Bus
• Address bus: The microprocessor or CPU uses this bus to
select one of the devices at any given time for data transfer.
• CPU sends the address of the memory location or I/O
device on the address bus.
• The number of memory locations/ I-O that the CPU can
address is determined by number of address lines.
• If N address lines then 2N memory locations can be
addressed.
• It’s direction is from CPU to device. (Unidirectional)
• N=8 implies 28=256 locations.
• 32 address lines can access 4GB capacity.
 3 Types of buses: Address Bus, Data bus and Control Bus
• Data bus: It is used to transfer the data to and from the
selected memory/ I-O and microprocessor.
• It is indicated by double ended arrow. Data flow in both
directions or it is bidirectional.
• i.e. CPU can read or write data to or from device.
• All the devices share the same data bus but the device
selected by particular address will have the data
transfer executed.
• Increasing the data bus size increases the data transfer
rate of the CPU.
• Any device output connected on the data bus must be
tri-stated, so that they can float when device is not in
use.
 3 Types of buses: Address Bus, Data bus and Control Bus
• Control Bus: Control information is generally
transferred through individual lines.
• Each line specify particular control function.
• Also carries various Status information in the form
of acknowledgements from various devices.
• It is bidirectional bus.
• The CPU sends out control signals on control bus
to enable the output of addressed memory location
or I/O device.
• Typical control bus signals are
MEMORY READ, MEMORY WRITE, I/O READ,
I/O WRITE
 Multiplexing of Buses
• When the information flows through buses
• All information (A,D,C) is not simultaneously
generated.
• It is generated at specific instant of time and
independently.
• Also all information is not always available.
• The same bus is time multiplexed. This concept is used
in many real time processors.
• Hence the bus remains busy and its efficiency
increases.
• Separate buses leads to wastage of band width
 CPU Organization
• The CPU is brain of the computer.
• Function / Job of CPU : To execute programs
stored in the main memory by
Fetching Instruction.
Decoding the instruction
Executing them one after another.
 CPU Organization
Functions (jobs) of CPU
• Address generation
• Generation of control signals
• Providing appropriate timings
• Carrying out various Arithmetic and Logical
operations
CPU Organization
 CPU Organization: Control Unit
• The CPU contains several distinct parts.
• The control unit is responsible for coordinating and
synchronizing operations of various hardware blocks in the CPU
and the blocks connected to the CPU.
• Hence needs to generate different control signals.
• Control signals needs to be generated in specific sequences.
• Every instruction has a different sequence of control signals.
• So sequencing of control signals have to be carried out by CPU.
• Each signal is active for specific time duration.
• It controls overall operations and its sequence to carryout job
assigned.
• All instructions are stored in binary values.
 CPU Organization: ALU
Arithmetic and Logic Unit
• Performs different arithmetic and logical
operations on the operands sent to ALU.
• Provides the output with desired precision
especially during floating point operations.
CPU Organization: Instruction Decoder
• The instruction decoder receives the instruction from
the memory, interprets/ decodes the function to be
performed.
• When it is to be executed, instructions are fetched one
by one from memory into instruction decoder.
• Understanding position (Location) of operands and
operation to be performed is done by instruction
decoder.
• Then the control unit takes the charge to generate
various control signals required to complete
instruction.
CPU Organization: Register section
• Few registers or temporary storage for
operands are provided before processing.
• They also hold the results from the ALU
temporarily.
• They are high speed memories for fast
information transfer.
• Internal bus connects all these blocks inside
the CPU.
 Registers in CPU
• Registers are at the top position in the
memory hierarchy.

Register based CPU organization

Register based CPU organization
 Register based CPU organization
• Every CPU has set of registers to hold
information.
• The registers are of two types:
– Program Visible-
– Program Invisible - ( Not accessible to the user in
any case)
 Register based CPU organization
• Program Visible Registers can be accessed by user
through appropriate software instructions.
• Program Visible Registers can be further Classified as :
General Purpose Registers (GPRs)
Special Function Registers. (SFRs)
GPRs are used to store any type of information
address or data.
 Register based CPU organization
• A Special Function Register is used by CPU to
store information which help the way CPU
should function.
• The information in these registers control the
operation of various hardware blocks inside
the CPU.
• Ex. Program Counter, Stack Pointer, Instruction
Register
 Some common SFR
• Program Counter- It is a pointer register. It
holds the address of instruction that is to be
executed next.
• Stack Pointer- The contents of this register
point to the top of the stack. Whenever the
program execution flow is to be changed
during function calls then before changing the
flow the SP tells the CPU where the next
instruction to be pushed or popped out from
the stack.
 Some common SFR
• Instruction pointer register : It points to the
instruction to be brought for the execution.
• Memory Address Register (MAR) : The processor
provides the address from which the data or
instruction is to be fetched through MAR. It is
also used to forward the address of memory
location where data is to be stored.
• Memory Buffer Register ( MBR ) : This register
holds the data that has to be fetched from the
selected memory location or that has to be
stored in the selected location.
 Some common SFR
• Data Register (DR): This register holds data
that is to be pushed onto stack or that has
been popped out of stack.
• Flags: this register is a collection of one bit flip
flops. Each flip flop indicates certain
conditions that come into existence upon
execution of an instruction. Example sign,
zero, carry, parity etc.
 Register based CPU organization
Usually memory stores data, return address
during a subroutine call, pointer and counters,
operands and result.
However access to memory is time consuming
as memory accesses are slow. This leads to
wastage of time affecting the overall execution
time of instructions and hence the program
itself.
 Register based CPU organization
• The waiting time for fetching operands can be reduced
if the information is stored in temporary high speed
units called the registers, whose access is very fast.
• Every CPU is therefore having a set of general purpose
registers (GPR) for this purpose.
• These registers are connected through a common bus.
They communicate with one another for data transfer
and are involved during performing of various micro
operations.
• There should be provision for selecting source registers
for reading operands stored as well as destination
register to store results.
 Introduction to stack
• The stack is reserved storage where temporary
information maybe stored.
• A n-bit stack pointer is used to hold the address
of most recent stack entry.
• The location which has the most recent entry is
called as top of the stack.
• The stack operates on Last In First Out (LIFO)
principle.
• It is equivalent to stack of plates which are piled
on one another. While piling a new plate is put on
the last one. While removing that last plate is
removed first.
 Introduction to stack
• The contents of this register (SP) points to the top of
the stack. It is at this address that a new data can be
put on and the data that can be removed from stack.
• The operations which are possible on a stack are
insertion of data element (called PUSH) and removal of
data element (called POP)
• Every PUSH or POP operation dynamically changes the
contents of the stack. Apart from this there is a data
register (DR) which temporarily holds the data that is
to be Pushed onto the stack or data that is Popped out
from the stack.
 Stack implementation
• Register stack- a set of GPRs can
work as stack by implementing LIFO
principle.
• Memory stack- a part of the user
memory can be used to create a
stack.
Register stack
Register stack
• A set general purpose
register can be
organized to function as
LIFO which is essentially
the way the stack
works.
• A stack of 32 GPRs will
require 5 bit address to
access. Hence Stack
Pointer is 5 bit.
 Register stack

• A set of GPRs organized to function as LIFO.

• Stack of 32 GPRs. Address from 0 to 31
• Each register can be selected using 5 bit address as
25 = 32.
• Hence size of SP is 5 bit. If SP = 00000H register 0
• If SP = 00001H register 1 and so on
• If SP = 11111H register 31
• After every PUSH the stack pointer points to the next
register which is available for storing information.
 Register stack

• After every POP the stack pointer points to the register

from which the information has to be read out.
• Initially Assume stack is empty, stack pointer (SP)
points to 0.
• When stack is empty, EMPTY Flag is set to 1.
• During PUSH, first the full flag is checked, if stack is not
full then PUSH operation is possible.
• Then the SP is incremented by 1 and onto this address
the new data is stored. So first data goes to register 1.
• In the PUSH, first address is incremented and then the
data is stored at the address pointed SP register.
 Register stack

• When SP = 31, and next PUSH is to be carried, SP

becomes 0. The data is stored in register 0. This is
top of stack.
• After every PUSH operation SP is checked, if it is
not 0 next PUSH is possible.
• When SP becomes 0, further PUSH is not possible
hence stack is full. So Full flag will be set to 1
 Register stack

• The process is as follows:

• While (FULL != 1 ) /* PUSH is possible */
• SP ← SP+1 /* SP is first incremented */
• M[SP] ← DR /* data is pushed to stack at M[SP] */
• If(SP==0) FULL ← 1, EMPTY ← 0
else
Go for next PUSH
 Register stack

• The POP process is as follows:

• While (EMPTY != 1 ) /* POP is possible, data is present on stack */
• DR ← M[SP] /* data is POPed from memory pointed by SP M[SP] */

• SP ← SP-1 /* SP is then decremented */

• If(SP==0) FULL ← 0, EMPTY ← 1
else
Go for next POP
Memory stack
Memory stack
• Can be created in user memory, a part of
memory can functions as stack
• SP points to the top of the stack.
• Care has to be taken while initializing the stack.
• Stack is totally separate from rest of the
memory.
• To avoid overlap of memory and stack data,
stack should be initialized in the opposite
direction.
• Stack should be initialized at the highest
possible address.
• Filling should start from the highest address to
the lower addresses.
• The limits of the Stack are set up by two
registers. RL stores lower address and RH stores
higher/upper address limit.
 Memory stack
• If RL ≤ SP < RH PUSH or POP is possible.
• If SP < RL, stack FULL , PUSH not possible.
• If SP > RH, POP is not allowed as stack is empty.
• EMPTY or FULL flags are not required. (required
in Register stack)
• For PUSH
SP ← SP-1
M[SP] ← DR
• For POP
DR ← M[SP]
SP ← SP+1