Scribd
Upload
17 views1 page

Legacy Clock Generator

Uploaded by

Zeeshan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
17 views1 page

Legacy Clock Generator

Uploaded by

Zeeshan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

`timescale 1ns / 1ps

module LEGACY_CLOCK_GEN(

input CLOCK,
input RESET,
input CLK_sel,
input CLK_EN,
output I2C_CLOCK

);

parameter [4:0] DIVIDE_VALUE = 5'd24;

reg [4:0] I2C_COUNTER;


reg SCL_reg;

always@(posedge CLOCK or negedge RESET)


begin
if(RESET)
begin
I2C_COUNTER <= 5'd0;
SCL_reg <= 1'b1;
end

else
begin
if(CLK_sel == 1'b1)
begin
SCL_reg <= 1'b1;
end

else if(CLK_sel == 1'b0)


begin
if(I2C_COUNTER == DIVIDE_VALUE)
begin
I2C_COUNTER <= 5'd0;

case(CLK_EN)
1'b0 : SCL_reg <= 1'b1;
1'b1 : SCL_reg <= ~SCL_reg;
endcase
end

else
begin
I2C_COUNTER <= I2C_COUNTER + 1;
end
end
end
end

assign I2C_CLOCK = SCL_reg;

endmodule

You might also like