PCI Express: The Evolution to 8.

0 GT/s

Navraj Nandra, Director of Marketing

Mixed-Signal and Analog IP, Synopsys
 PCIe Enterprise Computing Market
Transition From Gen2 to Gen3 Gen3 transition will depend
on the spec release
release, but
The majority of Gen2
major processor providers
Gen 2 shipped with customers will move to Gen3
are expected to launch in
Total PCIe instances. systems deployed in for more bandwidth in 2009
2010 with PDKs in 2009
2009 and beyond are 2007 and 2008
estimates

Growth will continue for

the Gen 1 connectivity
market

2003
2003 2004 2005 2006 2007 2008 2009 2010 2011
2011
 PCI Express 3
3.0
0 Key Dates (CY)
Key
y Industry
y Q3 Q
Q4 Q
Q1 Q
Q2 Q3 Q
Q4 Q
Q1 Q
Q2 Q3 Q
Q4 Q1 Q
Q2
Milestones 2007 2007 2008 2008 2008 2008 2009 2009 2009 2009 2010 2010

PCI Express 3.0 Speed Announced

G 3
Gen
PCI Express 3.0 Specification (0.5)

PCI Express 3.0 Specification (0.7)

PCI Express 3.0 Specification (0.9)

PIPE 3.0 Specification (0.5) PCI Express

p 3.0 Specification
p f ()

PIPE 3.0 Specification (0.7)

ote: All future dates are estimates

PCI Express 3
3.0
0 (preliminary v0
v0.5)
5)
PCIe Architecture Raw Interconnect Bandwidth Lane Total Bandwidth for x16
Bit Rate Bandwidth Direction link
PCIe 1.1 2.5 GT/s 2 Gb/s ~250 MB/s ~8 GB/s

PCIe 2.0 5.0 GT/s 4 Gb/s ~500 MB/s ~16 GB/s

PCIe 3.0 8.0 GT/s 8 Gb/s ~1 GB/s ~32 GB/s

• PCIe 3.0
3 0 (Gen3) is 2x the bandwidth of Gen2
• @8 GT/s, the data Rate only provides 60% boost in Bandwidth
• Uses a combination of Protocol and Encoding Changes for the additional 40%
• Use 128b/130b encoding on individual lanes
• Use PHY la
layer
er packetization
packeti ation to identify
identif packet boundaries
bo ndaries
• Removes the “K” codes
• Scrambling
S bli only
l ((no 8b/10b) tto provide
id edge
d d density
it
• Backwards compatible with previous PCIe generations
PCI Express 3.0
3 0 Areas of Change

Application

A li ti
Application Transaction
Transaction Digital Controller
Link
Link Physical
Physical
Physical Interface
Logical (PIPE)
PIPE

Physical Coding
Electrical PCS Layer
y
S bl
Sub-layer New Electrical Requirements
-Jitter
-Sensitivity
Mechanical -Power
Electrical Sub-
bl k
block

Rx Tx
Lane
PCI Express 3.0
High Speed Transceiver
Key Features PCIe 3.0
Data Rate 8.0 ± 300 ppm Gbps
Unit Interval 124.9625 ps (min)
125.0375 ps (max)
Encoding Scrambling only with 128/130 bit encoding

Transmit Signaling:
• Differential
Diff ti l p-p output
t t voltage
lt 1200 mV V ((max))
• DC common-mode voltage limits 0 – 3.6 V
• Transition times (20% - 80%) 18 ps
• Max total output jitter (p-p) 0.24 UI (TBD)
PCI Express 3
3.0
0
High Speed Transceiver
Key Features PCIe
C 3.0
Receive Signaling:
• Receiver coupling AC (220 nF max)
• Differential p-p input voltage (max) 1200 mV (max)
• Input transition times (20% - 80%) 18 ps
• Min jitter tolerance (p
(p-p)
p) TBD
• Target BER 10-12
Equalization:
TX 3-tap programmable equalization (pre, main and post)

Continuous Time Linear Equalizer (CTLE)

RX recommended
PCI Express 3.0
3 0 Areas of Change

Application

A li ti
Application Transaction
Transaction Digital Controller
Link
Link Physical
Physical New Requirements
Physical Interface - 32-bit
32 bit support
Logical (PIPE)
PIPE - Equalization

Physical Coding
Electrical PCS Layer
y
S bl
Sub-layer

Mechanical
Electrical
S b bl k
Sub-block

Rx Tx
Lane
New PIPE 3
3.0
0 (v0
(v0.5)
5) Interface
PCI Express Mode PCLK Data Width
2.5 GT/s 250 MHz 8 bits
2.5 GT/s 125 MHz 16 bits
5.0 GT/s 500 MHz 8 bits
5.0 GT/s 250 MHz 16 bits
5.0 GT/s 125 MHz 32 bits
8.0 GT/s 1000 MHz 8 bits
8 0 GT/s
8.0 500 MHz 16 bits
8.0 GT/s 250 MHz 32 bits

• Extended
E t d d ffor Gen3,
G 3 but
b t still
till supports:
t
– Variable clock
– Variable data
• New 32-bit data width supported for Gen2/Gen3
PCI Express 3.0
3 0 Areas of Change

Application

Digital Controller will have

A li ti
Application Transaction to handle 2x data:
Digital Controller - Change LTSSM
Transaction Link - Double the data path
- Double the clock
Link Physical - Removal of “K” codes
Physical
Physical Interface
Logical (PIPE)
PIPE

Physical Coding
Electrical PCS Layer
y
S bl
Sub-layer

Mechanical
Electrical
S b bl k
Sub-block

Rx Tx
Lane
Summary

11
Complete DesignWare IP Solution
for PCI Express 3.0
Complete PCI Express 3.0 • Complete solution: controllers, PHY, VIP
IP Solution • Doubles data transfer speed to 8.0 GT/s
• Backwards compatible with PCIe 1 1.1
1 and 2
2.0
0
• Endpoint
Digital • Root port • Comprehensive suite of digital controllers
Controllers • Dual Mode – Endpoint, Root Complex, Dual Mode
• Switch/Bridge
S it h/B id (RC/EP), Switch and Bridge, SR-IOV
– Internal data path options of 32, 64 &128
• 3.0* (8.0 Gb/s) – Support for x1,
x1 x2,
x2 x4,
x4 x8 and x16
PHY • 2.0 (5.0 Gb/s)
• 1.1 (2.5 Gb/s) – AMBA® 3 AXI™ Bridge and AMBA 2 AHB™
Bridge
• R b t PHY IP in
Robust i Development
D l t
• Master – Will meet final PCIe 3.0 specs in areas such
Verification IP • Slave
as jitter, margin, receive sensitivity
• Monitor
– Advanced built-in diagnostics and ATE
capabilities
Note: PCI Express 3.0 specification is currently at 3.0. All DesignWare IP is currently under development
Thank you
y
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