Experiment 1: I-V Characteristics of PMOS and NMOS Transistors
Date: August 7, 2025
Aim
To plot the current-voltage (I-V) characteristics of NMOS and PMOS transistors. From the plots, we will identify and
analyze the different regions of operation (cutoff, linear/triode, and saturation).
Software Required
The simulation and analysis for this experiment were conducted using circuit simulation software running on the CentOS
operating system.
Theory
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a voltage-controlled device. Its drain current (𝐼 𝐷 ) is
controlled by the gate-to-source voltage (𝑉𝐺𝑆 ) and the drain-to-source voltage (𝑉𝐷𝑆 ). A MOSFET can operate in three
distinct regions.
NMOS Transistor
For an n-channel MOSFET (NMOS), with threshold voltage 𝑉𝑡 ℎ :
Cutoff Region: The transistor is OFF.
𝑉𝐺𝑆 < 𝑉𝑡 ℎ =⇒ 𝐼𝐷 ≈ 0
Linear (Triode) Region: The transistor acts like a voltage-controlled resistor.
𝑉𝐺𝑆 > 𝑉𝑡 ℎ , 𝑉𝐷𝑆 < (𝑉𝐺𝑆 − 𝑉𝑡 ℎ )
𝑊 2
(𝑉𝐺𝑆 − 𝑉𝑡 ℎ )𝑉𝐷𝑆 − 12 𝑉𝐷𝑆
𝐼 𝐷 = 𝜇 𝑛 𝐶𝑜𝑥
𝐿
Saturation Region: The drain current is relatively independent of 𝑉𝐷𝑆 and mainly controlled by 𝑉𝐺𝑆 .
𝑉𝐺𝑆 > 𝑉𝑡 ℎ , 𝑉𝐷𝑆 ≥ (𝑉𝐺𝑆 − 𝑉𝑡 ℎ )
𝑊
(𝑉𝐺𝑆 − 𝑉𝑡 ℎ ) 2 1 + 𝜆𝑉𝐷𝑆
𝐼 𝐷 = 21 𝜇 𝑛 𝐶𝑜𝑥
𝐿
where 𝜆 is the channel-length modulation parameter.
PMOS Transistor
For a p-channel MOSFET (PMOS), the conditions are complementary. Here, the threshold voltage 𝑉𝑡 ℎ 𝑝 is negative, and
current flows from source to drain (conventional current leaves the drain). Using magnitude for clarity:
Cutoff Region: The transistor is OFF.
𝑉𝐺𝑆 > 𝑉𝑡 ℎ 𝑝 =⇒ 𝐼𝐷 ≈ 0
Linear (Triode) Region: The transistor acts like a voltage-controlled resistor.
𝑉𝐺𝑆 < 𝑉𝑡 ℎ 𝑝 , 𝑉𝐷𝑆 > (𝑉𝐺𝑆 − 𝑉𝑡 ℎ 𝑝 )
(Expressions for 𝐼 𝐷 are analogous, but with hole mobility 𝜇 𝑝 .)
Saturation Region: The drain current depends mainly on 𝑉𝐺𝑆 .
𝑉𝐺𝑆 < 𝑉𝑡 ℎ 𝑝 , 𝑉𝐷𝑆 ≤ (𝑉𝐺𝑆 − 𝑉𝑡 ℎ 𝑝 )
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Circuit Diagrams
NMOS Circuit
The circuit used to measure the I-V characteristics for the NMOS transistor is shown below. DC voltage sources are swept
with positive values.
Figure 1: Circuit diagram for measuring NMOS characteristics.
PMOS Circuit
The circuit used to measure the I-V characteristics for the PMOS transistor is shown below. DC voltage sources are swept
with negative values.
Figure 2: Circuit diagram for measuring PMOS characteristics.
Observations and Graphs
NMOS Observations
The output characteristics (𝐼 𝐷 vs. 𝑉𝐷𝑆 ) for various values of 𝑉𝐺𝑆 were plotted for the NMOS transistor. The graph shows
that for a fixed 𝑉𝐺𝑆 > 𝑉𝑡 ℎ , the drain current initially increases with 𝑉𝐷𝑆 (linear region) and then becomes nearly constant
(saturation region).
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(a) I-V characteristic with varying 𝑉𝐷𝑆 . (b) I-V characteristic with varying 𝑉𝐺𝑆 .
Figure 3: NMOS transistor characteristics.
PMOS Observations
The output characteristics (𝐼 𝐷 vs. 𝑉𝐷𝑆 ) for the PMOS transistor show a complementary behavior. As the magnitude of
the negative 𝑉𝐷𝑆 increases for a fixed negative 𝑉𝐺𝑆 , the drain current magnitude increases and then saturates.
Figure 4: I-V characteristic curves for the PMOS transistor.
Conclusion
The I-V characteristics for both NMOS and PMOS transistors were successfully plotted and analyzed. The plots clearly
demonstrate the distinct regions of operation for each device type, and the observed behavior aligns with the theoretical
models of MOSFET operation. The separation of the circuits and graphs provides a clear comparison between the two
transistor types.
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Experiment 2: Noise Margin and Delay Measurement of a CMOS Inverter
Date: August 21, 2025
Aim
To compute the noise margins (LOW and HIGH) and propagation delay of a CMOS inverter using DC (static) and transient
(time-domain) analysis. From the DC transfer characteristic we will extract 𝑉𝐼 𝐿 , 𝑉𝐼 𝐻 , 𝑉𝑂𝐿 , 𝑉𝑂𝐻 and determine 𝑁 𝑀 𝐿 and
𝑁 𝑀𝐻 . From transient response to a step input, we will measure 𝑡 𝑝𝐿𝐻 , 𝑡 𝑝𝐻 𝐿 and the average propagation delay 𝑡 𝑝 .
Software Required
The simulation and analysis for this experiment were conducted using circuit simulation software running on the LTSpice.
Theory
A CMOS inverter consists of a p-channel MOSFET (PMOS) connected to 𝑉𝐷𝐷 and an n-channel MOSFET (NMOS)
connected to ground. The inverter implements the logical NOT operation: when input is LOW, output is HIGH and vice
versa.
DC Transfer Characteristic
The static behavior of a CMOS inverter is captured by its voltage transfer characteristic (VTC) 𝑉𝑂𝑈𝑇 versus 𝑉𝐼 𝑁 . Important
voltages on the VTC are defined as follows:
• 𝑉𝐼 𝐿 : Maximum input voltage still recognized as a LOW (defined where 𝑑𝑉𝑂𝑈𝑇
𝑑𝑉𝐼 𝑁 = −1 on the low-to-high slope
approaching the logic-0 side).
• 𝑉𝐼 𝐻 : Minimum input voltage recognized as a HIGH (defined where 𝑑𝑉𝑂𝑈𝑇
𝑑𝑉𝐼 𝑁 = −1 on the high-to-low slope
approaching the logic-1 side).
• 𝑉𝑂𝐿 : Output LOW voltage (typically the low-level output, near 0 V).
• 𝑉𝑂𝐻 : Output HIGH voltage (typically near 𝑉𝐷𝐷 ).
Noise margins are then defined as:
𝑁 𝑀 𝐿 = 𝑉𝐼 𝐿 − 𝑉𝑂𝐿
𝑁 𝑀𝐻 = 𝑉𝑂𝐻 − 𝑉𝐼 𝐻
A larger noise margin means better tolerance to noise on the input signal.
Transient Response and Delay Metrics
When a CMOS inverter drives a capacitive load 𝐶 𝐿 , the output transitions take finite time. Key timing metrics are:
• Propagation delay high-to-low (𝑡 𝑝𝐻 𝐿 ): Time interval from the input 50% point during a falling input edge to the
output 50% point during the corresponding falling output edge.
• Propagation delay low-to-high (𝑡 𝑝𝐿𝐻 ): Time from input 50% point during a rising input edge to output 50% point
during the corresponding rising output edge.
• Average propagation delay (𝑡 𝑝 ):
𝑡 𝑝𝐿𝐻 +𝑡 𝑝𝐻 𝐿
𝑡𝑝 = 2
• Contamination delay (𝑡 𝑐𝑑 ): The minimum possible delay (often measured from input 10% to output 90% or other
definitions depending on tool/setup). In most lab exercises the emphasis is on propagation delays.
The delay depends on the drive strength of the transistors (device sizes 𝑊/𝐿), the load capacitance 𝐶 𝐿 , and 𝑉𝐷𝐷 . For
an approximate RC model, delay scales as 𝑡 ∼ 𝑅𝑒𝑞 𝐶 𝐿 where 𝑅𝑒𝑞 is the equivalent on-resistance during the transition.
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Circuit Diagram
Figure 5: Schematic of a CMOS inverter driving a capacitive load 𝐶 𝐿 .
Observations and Graphs
DC Transfer Characteristic
Plot the VTC and include markers for 𝑉𝐼 𝐿 and 𝑉𝐼 𝐻 , and horizontal lines for 𝑉𝑂𝐻 and 𝑉𝑂𝐿 . Show noise margins computed
with the measured values.
Figure 6: Voltage transfer characteristic of the CMOS inverter with 𝑉𝐼 𝐿 , 𝑉𝐼 𝐻 , 𝑉𝑂𝐿 and 𝑉𝑂𝐻 indicated.
Conclusion
The DC (VTC) and transient analyses were used to determine the noise margins and propagation delays of a CMOS
inverter. The measured 𝑉𝐼 𝐿 , 𝑉𝐼 𝐻 , 𝑉𝑂𝐿 and 𝑉𝑂𝐻 yield the noise margins 𝑁 𝑀 𝐿 and 𝑁 𝑀𝐻 , indicating the input noise
tolerance. Transient measurements with a specified capacitive load produced 𝑡 𝑝𝐿𝐻 and 𝑡 𝑝𝐻 𝐿 values which can be averaged
to obtain the inverter propagation delay 𝑡 𝑝 ; these delays scale with the output load and transistor sizing.
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Experiment 3: AC and Transient Analysis of Common-Source Amplifier
Date: August 28, 2025
Aim
To perform AC and transient analysis of a Common-Source (CS) amplifier and evaluate its frequency response, gain, and
time-domain behavior.
Software Required
The simulation and analysis for this experiment were conducted using circuit simulation software LTspice.
Theory
A Common-Source (CS) amplifier is one of the most widely used MOSFET amplifier configurations. It provides voltage
amplification with high gain. In this configuration:
• The input signal is applied to the gate.
• The output is taken from the drain.
• The source is connected to ground (directly or through a small resistance).
The small-signal voltage gain is approximately given by:
𝐴𝑣 = −𝑔𝑚 𝑅 𝐷
where 𝑔𝑚 is the transconductance of the MOSFET and 𝑅 𝐷 is the drain resistance. The negative sign indicates a 180◦
phase shift between input and output.
AC Analysis
AC analysis helps determine the frequency response of the amplifier. By sweeping input frequency, the gain (𝐴𝑣 in dB)
vs. frequency plot can be obtained. Key parameters:
• Mid-band gain
• Lower cut-off frequency ( 𝑓 𝐿 )
• Upper cut-off frequency ( 𝑓 𝐻 )
• Bandwidth (𝐵𝑊 = 𝑓 𝐻 − 𝑓 𝐿 )
Transient Analysis
Transient analysis shows how the amplifier responds to time-domain signals (e.g., sine waves or pulses). It helps to
observe:
• Amplification of input waveform
• Phase reversal
• Distortion (if any)
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Circuit Diagram
Figure 7: Schematic of a Common-Source Amplifier with load resistance 𝑅 𝐷 and coupling capacitors.
Observations and Graphs
AC Analysis
The frequency response of the CS amplifier is obtained by sweeping frequency.
Figure 8: AC analysis of the CS amplifier showing mid-band gain and bandwidth.
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Transient Analysis
The time-domain response of the amplifier to a sinusoidal input is shown below.
Figure 9: Transient response showing amplified and phase-reversed output.
Conclusion
From AC analysis, the mid-band gain, lower and upper cut-off frequencies, and bandwidth of the CS amplifier were
determined. From transient analysis, the amplifier’s time-domain response was observed, confirming the amplification
and 180◦ phase reversal between input and output.
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Experiment 4: Design of a Full Adder Using MOS Transistors and Transient
Analysis
Date: September 4, 2025
Aim
To design a full adder using MOS transistors and to verify its functionality through transient analysis.
Software Required
The design and simulation were carried out using circuit simulation software on the LTSpice operating system.
Theory
A 1-bit full adder takes three inputs ( 𝐴, 𝐵, 𝐶𝑖𝑛 ) and produces two outputs: Sum (𝑆) and Carry-out (𝐶𝑜𝑢𝑡 ).
𝑆 = 𝐴 ⊕ 𝐵 ⊕ 𝐶𝑖𝑛 𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶𝑖𝑛 + 𝐵𝐶𝑖𝑛
CMOS Implementation Strategy
• Static CMOS (pull-up/pull-down) logic: Realize 𝐶𝑜𝑢𝑡 as a majority gate with complementary networks. Implement
𝑆 using cascaded XORs: 𝑆 = ( 𝐴 ⊕ 𝐵) ⊕ 𝐶𝑖𝑛 .
• Transmission-Gate (TG) XOR: A compact and fast XOR can be built using transmission gates and inverters;
cascading two such XORs yields 𝑆. 𝐶𝑜𝑢𝑡 can be formed with static CMOS logic or TG multiplexing.
• Notes: Static CMOS provides full logic swing and good noise margins. TG-based XORs reduce series stack depth
and can improve speed at the cost of clocked/transmission devices (still full rail with complementary control).
Truth Table
𝐴 𝐵 𝐶𝑖𝑛 𝑆 𝐶𝑜𝑢𝑡
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Circuit Diagram
The transistor-level schematic of the full adder is shown below.
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Figure 10: Full adder circuit diagram using MOS transistors.
Observations and Waveforms
Transient analysis was performed by applying pulse waveforms to inputs 𝐴, 𝐵, and 𝐶𝑖𝑛 . The outputs 𝑆 and 𝐶𝑜𝑢𝑡 were
observed and verified against the truth table.
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Figure 11: Transient analysis waveforms of the full adder.
Conclusion
The full adder was successfully designed and simulated at the MOS transistor level. Transient analysis confirmed that the
outputs 𝑆 and 𝐶𝑜𝑢𝑡 matched the expected truth table for all input combinations.
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