UCC21755-Q1

SLUSEM9A – SEPTEMBER 2022 – REVISED JUNE 2024

UCC21755-Q1 Automotive 10A Source/Sink Reinforced Isolated Single Channel Gate

Driver for SiC/IGBT with Active Protection, Isolated Analog Sensing and High-CMTI
1 Features The input side is isolated from the output side with
SiO2 capacitive isolation technology, supporting up to
• 5.7kVRMS single-channel isolated gate driver
1.5kVRMS working voltage, 12.8kVPK surge immunity
• AEC-Q100 Qualified with the following results:
with longer than 40-years isolation barrier life, as
– Device temperature grade 1: -40°C to +125°C
well as providing low part-to-part skew, and >150V/ns
ambient operating temperature range
common mode noise immunity (CMTI).
• Functional Safety Quality-Managed
– Documentation available to aid functional safety The UCC21755-Q1 includes the state-of-art protection
system design features, such as fast overcurrent and short circuit
• SiC MOSFETs and IGBTs up to 2121Vpk detection, fault reporting, active Miller clamp, and
• 33V maximum output drive voltage (VDD-VEE) input and output side power supply UVLO to optimize
• ±10A drive strength and split output SiC and IGBT switching behavior and robustness.
• 150V/ns minimum CMTI The isolated analog to PWM sensor can be utilized
• 200ns response time fast DESAT protection with for easier temperature or voltage sensing, further
5V threshold increasing the drivers' versatility and simplifying the
• 4A internal active Miller clamp system design effort, size, and cost.
• 400mA soft turn-off when fault happens Device Information
• Isolated analog sensor with PWM output for PART NUMBER PACKAGE(1) BODY SIZE (NOM)
– Temperature sensing with NTC, PTC, or UCC21755-Q1 DW (SOIC-16) 10.3mm × 7.5mm
thermal diode
– High voltage DC-link or phase voltage (1) For all available packages, see Section 13.
• Alarm FLT on overcurrent and reset from RST/EN
• Fast enable/disable response on RST/EN
• Reject <40ns noise transient and pulse on input AIN 1 16 APWM
pins 15
DESAT 2 VCC
• 12V VDD UVLO with power good on RDY ISOLATION BARRIER
• Inputs/outputs with over- or under-shoot transient COM 3 14 RST/EN
voltage immunity up to 5V OUTH 4 13 FLT
• 130ns (maximum) propagation delay and 30ns
(maximum) pulse/part skew VDD 5 12 RDY
• SOIC-16 DW package with creepage and OUTL 6 11 ,1Å
clearance distance > 8mm
CLMPI 7 10 IN+
• Operating junction temperature –40°C to 150°C
VEE 8 9 GND
2 Applications
• Traction inverter for EVs Not to scale
• On-board charger and charging pile
• DC/DC converter for HEV/EVs Device Pin Configuration

3 Description
The UCC21755-Q1 is a galvanic isolated single
channel gate driver designed for SiC MOSFETs
and IGBTs up to 2121V DC operating voltage with
advanced protection features, best-in-class dynamic
performance, and robustness. UCC21755-Q1 has up
to ±10A peak source and sink current.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.1 Overview................................................................... 22
2 Applications..................................................................... 1 7.2 Functional Block Diagram......................................... 23
3 Description.......................................................................1 7.3 Feature Description...................................................23
4 Pin Configuration and Functions...................................3 7.4 Device Functional Modes..........................................29
5 Specifications.................................................................. 4 8 Applications and Implementation................................ 30
5.1 Absolute Maximum Ratings........................................ 4 8.1 Application Information............................................. 30
5.2 ESD Ratings............................................................... 4 8.2 Typical Application.................................................... 30
5.3 Recommended Operating Conditions.........................4 9 Power Supply Recommendations................................42
5.4 Thermal Information....................................................5 10 Layout...........................................................................42
5.5 Power Ratings.............................................................5 10.1 Layout Guidelines................................................... 42
5.6 Insulation Specifications............................................. 5 10.2 Layout Example...................................................... 43
5.7 Safety Limiting Values.................................................6 11 Device and Documentation Support..........................44
5.8 Electrical Characteristics.............................................7 11.1 Device Support........................................................44
5.9 Switching Characteristics............................................9 11.2 Documentation Support.......................................... 44
5.10 Insulation Characteristics Curves........................... 10 11.3 Receiving Notification of Documentation Updates.. 44
5.11 Typical Characteristics.............................................11 11.4 Support Resources................................................. 44
6 Parameter Measurement Information.......................... 15 11.5 Trademarks............................................................. 44
6.1 Propagation Delay.................................................... 15 11.6 Electrostatic Discharge Caution.............................. 44
6.2 Input Deglitch Filter................................................... 16 11.7 Glossary.................................................................. 44
6.3 Active Miller Clamp................................................... 17 12 Revision History.......................................................... 44
6.4 Undervoltage Lockout (UVLO)..................................17 13 Mechanical, Packaging, and Orderable
6.5 Desaturation (DESAT) Protection............................. 20 Information.................................................................... 45
7 Detailed Description......................................................22

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4 Pin Configuration and Functions

AIN 1 16 APWM
DESAT 2 15 VCC

ISOLATION BARRIER
COM 3 14 RST/EN
OUTH 4 13 FLT
VDD 5 12 RDY
OUTL 6 11 ,1Å
CLMPI 7 10 IN+
VEE 8 9 GND

Not to scale

Figure 4-1. UCC21755-Q1 DW SOIC (16) Top View

Table 4-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if
AIN 1 I
unused.
DESAT 2 I Desaturation current protection input. Tie to COM if unused.
COM 3 P Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET
OUTH 4 O Gate driver output pullup
Positive supply rail for gate drive voltage. Bypass with a >10-µF capacitor to COM to support specified gate
VDD 5 P
driver source peak current capability. Place decoupling capacitor close to the pin.
OUTL 6 O Gate driver output pulldown
Internal Active Miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or
CLMPI 7 I
tie to VEE if unused.
Negative supply rail for gate drive voltage. Bypass with a >10-µF capacitor to COM to support specified gate
VEE 8 P
driver sink peak current capability. Place decoupling capacitor close to the pin.
GND 9 P Input power supply and logic ground reference
IN+ 10 I Non-inverting gate driver control input. Tie to VCC if unused.
IN– 11 I Inverting gate driver control input. Tie to GND if unused.
Power good for VCC-GND and VDD-COM. RDY is open-drain configuration and can be paralleled with other
RDY 12 O
RDY signals.
Active low fault alarm output upon overcurrent or short circuit. FLT is in open-drain configuration and can be
FLT 13 O
paralleled with other faults.
The RST/EN serves two purposes:
1) Enables or shuts down the output side. The FET is turned off by a regular turn-off, if pin EN is set to low;
2) Resets the DESAT condition signaled on the FLT pin if the pin RST/EN is set to low for more than 1000
RST/EN 14 I
ns. A reset of signal FLT is asserted at the rising edge of pin RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable or shutdown the output side. The
FET is turned off by a regular turn-off, if pin EN is set to low. Tie to IN+ for automatic reset.
Input power supply from 3 V to 5.5 V. Bypass with a >1-µF capacitor to GND. Place decoupling capacitor
VCC 15 P
close to the pin.
APWM 16 O Isolated analog sensing PWM output. Leave floating if unused.

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5 Specifications
5.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC VCC - GND –0.3 6 V
VDD VDD - COM –0.3 36 V
VEE VEE - COM –17.5 0.3 V
VMAX VDD - VEE –0.3 36 V
DC GND–0.3 VCC V
IN+, IN-, RST/EN
Transient, less than 100 ns (2) GND–5.0 VCC+5.0 V
DESAT COM–0.3 VDD+0.3 V
AIN Reference to COM –0.3 5 V
DC VEE–0.3 VDD V
OUTH, OUTL, CLMPI
Transient, less than 100 ns (2) VEE–5.0 VDD+5.0 V
RDY, FLT, APWM GND–0.3 VCC V
IFLT, IRDY FLT and RDY pin input current 20 mA
IAPWM APWM pin output current 20 mA
TJ Junction Temperature –40 150 °C
Tstg Storage Temperature –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and
this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) Values are verified by characterization on bench.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per AEC Q100-002(1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 ±1500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC VCC-GND 3 5.5 V
VDD VDD-COM 13 33 V
VEE VEE-COM -16 0 V
VMAX VDD-VEE 33 V

IN+, IN-, Reference to GND, High level input voltage 0.7xVCC VCC V
RST/EN Reference to GND, Low level input voltage 0 0.3xVCC V
AIN Reference to COM 0.6 4.5 V
tRST/EN Minimum pulse width that reset the fault 1000 ns
TA Ambient temperature –40 125 °C
TJ Junction temperature –40 150 °C

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5.4 Thermal Information

UCC21755-Q1
THERMAL METRIC(1) DW (SOIC) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 68.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.5 °C/W
RθJB Junction-to-board thermal resistance 32.9 °C/W
ΨJT Junction-to-top characterization parameter 14.1 °C/W
ΨJB Junction-to-board characterization parameter 32.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

5.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation (both sides) 985 mW
VCC = 5V, VDD-COM = 20V, COM-VEE =
PD1 Maximum power dissipation (side-1) 5V, IN+/– = 5V, 150kHz, 50% Duty Cycle 20 mW
for 10nF load, Ta = 25℃
PD2 Maximum power dissipation (side-2) 965 mW

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air >8 mm
Shortest terminal-to-terminal distance across the
CPG External creepage(1) >8 mm
package surface
DTI Distance through the insulation Minimum internal gap (internal clearance) > 17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material Group According to IEC 60664–1 I
Rated mains voltage ≤ 300 VRMS I-IV
Overvoltage Category per IEC 60664–1 Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
(2)
DIN V VDE 0884-11 (VDE V 0884-11): 2017-01
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
AC voltage (sine wave); time-dependent dielectric
1500 VRMS
VIOWM Maximum isolation working voltage breakdown (TDDB) test
DC voltage 2121 VDC
VTEST = VIOTM, t = 60 s (qualification test) 8000 VPK
VIOTM Maximum transient isolation voltage VTEST= 1.2 × VIOTM, t = 1 s (100% production
8000 VPK
test)
Test method per IEC 62368-1, 1.2/50 µs
VIOSM Maximum surge isolation voltage(3) waveform, VTEST = 1.6 × VIOSM = 12800 VPK 8000 VPK
(qualification)

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5.6 Insulation Specifications (continued)

PARAMETER TEST CONDITIONS VALUE UNIT
Method a: After I/O safety test subgroup 2/3, Vini
=VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 ≤5
VPK, tm = 10 s
Method a: After environmental tests subgroup
qpd Apparent charge(4) 1,Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM ≤5 pC
= 3394 VPK, tm = 10 s
Method b1: At routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s; ≤5
Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
CIO Barrier capacitance, input to output(5) VIO = 0.5 × sin (2πft), f = 1 MHz ~1 pF
VIO = 500 V, TA = 25°C ≥ 1012
RIO Insulation resistance, input to output(5) VIO = 500 V, 100°C ≤ TA ≤ 125°C ≥ 1011 Ω
VIO = 500 V at TS = 150°C ≥ 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VISO Withstand isolation voltage VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% 5700 VRMS
production)

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques
such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

5.7 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A
failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
overheatthe die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA = 68.3°C/W, VDD = 15 V, VEE = -5V,
61
TJ = 150°C, TA = 25°C
IS Safety input, output, or supply current mA
RθJA = 68.3°C/W, VDD = 20 V, VEE = -5V,
49
TJ = 150°C, TA = 25°C
RθJA = 68.3°C/W, VDD = 20 V, VEE = -5V,
PS Safety input, output, or total power 1220 mW
TJ = 150°C, TA = 25°C
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Information
table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value
for each parameter: TJ = TA + RqJA ´ P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA ´ PS, where TJ(max) is the
maximum allowed junction temperature. PS = IS ´ VI , where VI is the maximum supply voltage.

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5.8 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD–COM = 20 V, 18 V or 15 V, COM–VEE = 5 V, 8 V or 15 V,
(1)(2)
CL = 100pF, –40°C<TJ<150°C (unless otherwise noted) .
Parameter TEST CONDITIONS MIN TYP MAX UNIT
VCC UVLO THRESHOLD AND DELAY
VVCC_ON 2.55 2.7 2.85 V
VVCC_OFF VCC - GND 2.35 2.5 2.65 V
VVCC_HYS 0.2 V
tVCCFIL VCC UVLO deglitch time 10 µs
tVCC+ to OUT VCC UVLO on delay to output high 28 37.8 50 µs
IN+ = VCC, IN– = GND
tVCC- to OUT VCC UVLO off delay to output low 5 10 15 µs
tVCC+ to RDY VCC UVLO on delay to RDY high 30 37.8 50 µs
RST/EN = VCC
tVCC- to RDY VCC UVLO off delay to RDY low 5 10 15 µs
VDD UVLO THRESHOLD AND DELAY
VVDD_ON 10.5 12 12.8 V
VVDD_OFF VDD - COM 9.9 10.7 11.8 V
VVDD_HYS 0.8 V
tVDDFIL VDD UVLO deglitch time 5 µs
tVDD+ to OUT VDD UVLO on delay to output high 2 5 8 µs
IN+ = VCC, IN– = GND
tVDD- to OUT VDD UVLO off delay to output low 5 10 µs
tVDD+ to RDY VDD UVLO on delay to RDY high 10 15 µs
RST/EN = VCC
tVDD- to RDY VDD UVLO off delay to RDY low 10 15 µs
VCC, VDD QUIESCENT CURRENT
OUT(H) = High, fS = 0Hz, AIN=2V 2.5 3 4 mA
IVCCQ VCC quiescent current
OUT(L) = Low, fS = 0Hz, AIN=2V 1.45 2 2.75 mA
OUT(H) = High, fS = 0Hz, AIN=2V 3.6 4 5.9 mA
IVDDQ VDD quiescent current
OUT(L) = Low, fS = 0Hz, AIN=2V 3.1 3.7 5.3 mA
LOGIC INPUTS - IN+, IN- and RST/EN
VINH Input high threshold 1.85 2.31 V
VINL Input low threshold VCC=3.3V 0.99 1.52 V
VINHYS Input threshold hysteresis 0.33 V
IIH Input high level input leakage current VIN = VCC 90 uA
IIL Input low level input leakage current VIN = GND -90 uA
RIND Input pins pull down resistance 55 kΩ
RINU Input pins pull up resistance 55 kΩ
IN+, IN– and RST/EN deglitch (ON
TINFIL fS = 50kHz 28 40 60 ns
and OFF) filter time
TRSTFIL Deglitch filter time to reset FLT 500 650 800 ns
GATE DRIVER STAGE
IOUTH Peak source current 10 A
CL = 0.18µF, fS = 1kHz
IOUTL Peak sink current 10 A
ROUTH (3) Output pull-up resistance IOUTH = -0.1A 2.5 Ω
ROUTL Output pull-down resistance IOUTL = 0.1A 0.3 Ω
VOUTH High level output voltage IOUTH = -0.2A, VDD = 18V 17.5 V
VOUTL Low level output voltage IOUTL= 0.2A 60 mV
ACTIVE PULLDOWN
IOUTL(typ) = 0.1×IOUTL(typ),
VOUTPD Output active pull down on OUTL 1.5 2.0 2.5 V
VDD=OPEN, VEE=COM

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5.8 Electrical Characteristics (continued)

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD–COM = 20 V, 18 V or 15 V, COM–VEE = 5 V, 8 V or 15 V,
(1)(2)
CL = 100pF, –40°C<TJ<150°C (unless otherwise noted) .
Parameter TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL ACTIVE MILLER CLAMP
VCLMPTH Miller clamp threshold voltage Reference to VEE 1.5 2.0 2.5 V
VEE +
VCLMPI Output low clamp voltage ICLMPI = 1A V
0.5
ICLMPI Output low clamp current VCLMPI = 0V, VEE = –2.5V 4.0 A
RCLMPI Miller clamp pull down resistance ICLMPI = 0.2A 0.6 Ω
tDCLMPI Miller clamp ON delay time CL = 1.8nF 15 50 ns
SHORT CIRCUIT CLAMPING
OUT = High, IOUT(H) = 500mA,
VCLP-OUT(H) VOUTH–VDD 0.9 V
tCLP=10µs
OUT = High, IOUT(L) = 500mA,
VCLP-OUT(L) VOUTL–VDD 1.8 V
tCLP=10µs
VCLP-CLMPI VCLMPI-VDD OUT = High, ICLMPI= 20mA, tCLP=10µs 1.0 V
DESAT PROTECTION
ICHG Blanking capacitor charge current VDESAT = 2.0V 430 500 570 µA
IDCHG Blanking capacitor discharge current VDESAT = 6.0V 10.0 15.0 mA
VDESAT Detection threshold 4.6 5 5.47 V
tDESATLEB Leading edge blank time 150 200 450 ns
tDESATFIL DESAT deglitch filter 50 140 230 ns
DESAT propagation delay to OUTL
tDESATOFF 150 200 300 ns
90%
tDESATFLT DESAT to FLT low delay 400 580 750 ns
INTERNAL SOFT TURN OFF
ISTO Soft turn-off current on fault condition VDD-VEE = 20 V, OUTL = 8 V 250 400 570 mA
ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)
VAIN Analog sensing voltage range 0.6 4.5 V
IAIN Internal current source VAIN=2.5V, -40°C< TJ< 150°C 196 203 209 uA
fAPWM APWM output frequency VAIN=2.5V 380 400 420 kHz
BWAIN AIN-APWM Bandwidth 10 kHz
VAIN=0.6V 86.5 88 89.5 %
DAPWM APWM Duty Cycle VAIN=2.5V 48.5 50 51.5 %
VAIN=4.5V 7.5 10 11.5 %
FLT AND RDY REPORTING
VDD UVLO RDY low minimum holding
tRDYHLD 0.55 1 ms
time
tFLTMUTE Output mute time on fault Reset fault through RST/EN 0.55 1 ms
RODON Open drain output on resistance 30 Ω
IODON = 5mA
VODL Open drain low output voltage 0.3 V
COMMON MODE TRANSIENT IMMUNITY
CMTI Common-mode transient immunity 150 V/ns

(1) Currents are positive into and negative out of the specified terminal.
(2) All voltages are referenced to COM unless otherwise notified.
(3) For internal PMOS only. Refer to Driver Stage for effective pull-up resistance.

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5.9 Switching Characteristics

VCC = 5.0 V, 1-µF capacitor from VCC to GND, VDD - COM = 20V, 18V or 15V, COM - VEE = 3 V, 5 V or 8 V, CL = 100pF,
-40℃<TJ<150℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPDLH Propagation delay time low-to-high 60 90 130 ns
tPDHL Propagation delay time low-to-high 60 90 130 ns
PWD Pulse width distortion (tPDHL-tPDLH) 30 ns
tsk-pp Part to part skew Rising or falling propagation delay 30 ns
tr Driver output rise time CL = 10nF 33 ns
tf Driver output fall time CL = 10nF 27 ns
fMAX Maximum switching frequency 1 MHz

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5.10 Insulation Characteristics Curves

Figure 5-1. Reinforced Isolation Capacitor Life Time Projection

80 1400
VDD=15V; VEE=-5V
VDD=20V; VEE=-5V 1200
Safety Limiting Current (mA)

Safety Limiting Power (mW)

60
1000

800
40
600

400
20

200

0 0
0 25 50 75 100 125 150 0 20 40 60 80 100 120 140 160
Ambient Temperature (oC) Safe
Ambient Temperature (oC) Safe

Figure 5-2. Thermal Derating Curve for Limiting Current per Figure 5-3. Thermal Derating Curve for Limiting Power per VDE
VDE

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5.11 Typical Characteristics

22 22
VDD/VEE = 18V/0V VDD/VEE = 18V/0V
Peak Output Current High, I OUTH (A)

20 20

Peak Output Current Low, I OUTL (A)

VDD/VEE = 20V/-5V VDD/VEE = 20V/-5V
18 18

16 16

14 14

12 12

10 10

8 8

6 6

4 4
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) D016
Temperature (qC) D017
Figure 5-4. Output High Drive Current vs Temperature Figure 5-5. Output Low Driver Current vs Temperature
6 4
VCC = 3.3V VCC = 3.3V
VCC = 5V VCC = 5V
5.5 3.5

5 3
IVCCQ (mA)

IVCCQ (mA)

4.5 2.5

4 2

3.5 1.5

3 1
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) D015
Temperature (qC) D014

IN+ = High IN- = Low IN+ = Low IN- = Low

Figure 5-6. IVCCQ Supply Current vs Temperature Figure 5-7. IVCCQ Supply Current vs Temperature
5 6
VDD/VEE = 18V/0V VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V VDD/VEE = 20V/-5V
4.5 5.5

4 5
IVCCQ (mA)

IVDDQ (mA)

3.5 4.5

3 4

2.5 3.5

2 3
30 70 110 150 190 230 270 310 -60 -40 -20 0 20 40 60 80 100 120 140 160
Frequency (kHz) D018
Temperature (qC) D012
Figure 5-8. IVCCQ Supply Current vs Input Frequency IN+ = High IN- = Low
Figure 5-9. IVDDQ Supply Current vs Temperature

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5.11 Typical Characteristics (continued)

6 10
VDD/VEE = 18V/0V VDD/VEE = 18V/0V
VDD/VEE = 20V/-5V 9 VDD/VEE = 20V/-5V
5.5
8
5
7
IVDDQ (mA)

IVDDQ (mA)
4.5 6

5
4
4
3.5
3

3 2
-60 -40 -20 0 20 40 60 80 100 120 140 160 30 70 110 150 190 230 270 310
Temperature (qC) D013
Frequency (kHz) D019

IN+ = Low IN- = Low Figure 5-11. IVDDQ Supply Current vs Input Frequency
Figure 5-10. IVDDQ Supply Current vs Temperature
4 14

VDD UVLO Threshold, VDD_ON (V)

13.5
VCC UVLO Threshold, V CC_ON (V)

3.5
13

12.5
3
12

2.5 11.5

11
2
10.5

1.5 10
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) Temperature (qC) D002
D001
Figure 5-12. VCC UVLO vs Temperature Figure 5-13. VDD UVLO vs Temperature

100 100
Propagation Delay High-Low, t PDHL (ns)
Propagation Delay Low-High, t PDLH (ns)

90 90

80 80

70 70

60 60

50 50
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) Temperature (qC) D022
D021

VCC = 3.3V VDD=18V CL = 100pF VCC = 3.3 V VDD=18 V CL = 100 pF

RON = 0Ω ROFF = 0Ω RON = 0 Ω ROFF = 0 Ω
Figure 5-14. Propagation Delay tPDLH vs Temperature Figure 5-15. Propagation Delay tPDHL vs Temperature

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5.11 Typical Characteristics (continued)

60 60

50 50
Rise Time, t r (ns)

Fall Time, t f (ns)

40 40

30 30

20 20

10 10
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) D023
Temperature (qC) D024

VCC = 3.3 V VDD=18 V CL = 10 nF VCC = 3.3 V VDD=18 V CL = 10 nF

RON = 0 Ω ROFF = 0 Ω RON = 0 Ω ROFF = 0 Ω
Figure 5-16. tr Rise Time vs Temperature Figure 5-17. tf Fall Time vs Temperature
3 2.5

2.75 2.25

2.5 2
VCLP-OUT(H) (V)
VOUTPD (V)

2.25 1.75

2 1.5

1.75 1.25

1.5 1
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) Temperature (qC) D025
D008

Figure 5-18. VOUTPD Output Active Pulldown Voltage vs Figure 5-19. VCLP-OUT(H) Short Circuit Clamping Voltage vs
Temperature Temperature

2 2.6
Miller Clamp Threshold Voltage, VCLMPTH (V)

1.75 2.45

2.3
1.5
VCLP-OUT(L) (V)

2.15
1.25
2
1
1.85
0.75
1.7
0.5
1.55

0.25 1.4
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) D026 Temperature (°C) D007
Figure 5-20. VCLP-OUT(L) Short Circuit Clamping Voltage vs Figure 5-21. VCLMPTH Miller Clamp Threshold Voltage vs
Temperature Temperature

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5.11 Typical Characteristics (continued)

8.5 18

Miller Clamp ON Delay Time, tDCLMPI (ns)

Peak Clamp Sink Current, ICLMPI (A)

7.5 17

6.5 16

5.5 15

4.5 14

3.5 13

2.5 12

1.5 11

0.5 10
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (qC) D011
Temperature (°C) D010
Figure 5-22. ICLMPI Miller Clamp Sink Current vs Temperature Figure 5-23. tDCLMPI Miller Clamp ON Delay Time vs Temperature

DESAT Propagation Delay to OUT(L) 90%, tDESATOFF (ns)

420
Leading Edge Blanking Time, tDESATLEB (ns)

300
380
290
340 280

300 270
260
260
250
220
240
180 230

140 220
210
100
-60 -40 -20 0 20 40 60 80 100 120 140 160 200
Temperature (°C) D002 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (°C)
Figure 5-24. tDESATLEB DESAT Leading Edge Blanking Time vs D003

Temperature Figure 5-25. tDESATOFF DESAT Propagation Delay to OUT(L) 90%

vs Temperature
DESAT Sense to /FLT Low Delay, tDESATFLT (ns)

320
680
310
DESAT Deglitch Filter, tDESATFIL (ns)

660
300
640
290
620
280
600 270
580 260
560 250

540 240

520 230
220
500 -60 -40 -20 0 20 40 60 80 100 120 140 160
-60 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C)
Temperature (°C) D005
D004
Figure 5-27. tDESATFIL DESAT Deglitch Filter vs Temperature
Figure 5-26. tDESATFLT DESAT Sense to /FLT Low Delay Time vs
Temperature

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5.11 Typical Characteristics (continued)

560 20

DESAT Discharge Current, IDCHG (mA)

550 19
DESAT Charging Current, ICHG (PA)

540
18
530
17
520
510 16
500 15
490 14
480
13
470
460 12
450 11
440 10
-60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160
Temperature (°C) D008 Temperature (qC) D009
Figure 5-28. ICHG DESAT Charging Current vs Temperature Figure 5-29. IDCHG DESAT Discharge Current vs Temperature

6 Parameter Measurement Information

6.1 Propagation Delay
6.1.1 Non-Inverting and Inverting Propagation Delay
Figure 6-1 shows the propagation delay measurement for non-inverting configurations. Figure 6-2 shows the
propagation delay measurement with the inverting configurations.

50% 50%

IN+

tPDLH tPDHL

,1Å

90%

10%
OUT

Figure 6-1. Non-Inverting Logic Propagation Delay Measurement

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IN+

,1Å 50% 50%

tPDLH tPDHL

90%
OUT
10%

Figure 6-2. Inverting Logic Propagation Delay Measurement

6.2 Input Deglitch Filter

To increase the robustness of gate driver over noise transient and accidental small pulses on the input pins, for
example, IN+, IN–, RST/EN, a 40-ns deglitch filter filters out the transients and ensures there is no faulty output
responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than the input deglitch
filter width, TINFIL, there are no responses on the OUT drive signal. Figure 6-3 and Figure 6-4 show the IN+ pin
ON and OFF pulse deglitch filter effect. Figure 6-5 and Figure 6-6 show the IN– pin ON and OFF pulse deglitch
filter effect.

IN+

tPWM < TINFIL tPWM < TINFIL

IN+

,1Å ,1Å

OUT

OUT

Figure 6-3. IN+ ON Deglitch Filter Figure 6-4. IN+ OFF Deglitch Filter

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IN+ IN+

,1Å
tPWM < TINFIL tPWM < TINFIL

,1Å

OUT

OUT

Figure 6-5. IN– ON Deglitch Filter Figure 6-6. IN– OFF Deglitch Filter

6.3 Active Miller Clamp

6.3.1 Internal On-Chip Active Miller Clamp
For a gate driver application with a unipolar bias supply or a bipolar supply with a small negative turn-off voltage,
an active Miller clamp can help add a additional low impedance path to bypass the Miller current and prevent the
high dV/dt introduced unintentional turn-on through the Miller capacitance. Figure 6-7 shows the timing diagram
for an on-chip internal Miller clamp function.

IN
(µ,1+¶ Å µ,1Ŷ)

tDCLMPI

VCLMPTH
OUT

HIGH

CLMPI LOW
Ctrl.

Figure 6-7. Timing Diagram for Internal Active Miller Clamp Function

6.4 Undervoltage Lockout (UVLO)

Undervoltage lockout (UVLO) is one of the key protection features designed to protect the system in case of bias
supply failures on VCC, primary side power supply, and VDD, secondary side power supply.
6.4.1 VCC UVLO
The VCC UVLO protection details are discussed in this section. Figure 6-8 shows the timing diagram illustrating
the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

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IN
(µ,1+¶ Å µ,1Ŷ)

tVCCFIL

t9&&Å WR 287 VVCC_ON

VCC
VVCC_OFF

VDD

COM
VEE
tVCC+ to OUT
90%
VCLMPTH
OUT 10%

tVCC+ to RDY t9&&Å WR 5'< tRDYHLD

Hi-Z
RDY

VCC

APWM

Figure 6-8. VCC UVLO Protection Timing Diagram

6.4.2 VDD UVLO

The VDD UVLO protection details are discussed in this section. Figure 6-9 shows the timing diagram illustrating
the definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

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IN
(µ,1+¶ Å µ,1Ŷ)

tVDDFIL
VDD
t9''Å WR 287
VVDD_ON
VVDD_OFF

COM

VEE

VCC

tVDD+ to OUT

VCLMPTH
OUT
10% 90%

tVDD+ to RDY t9''Å WR 5'< tRDYHLD

RDY Hi-Z

APWM VCC

Figure 6-9. VDD UVLO Protection Timing Diagram

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6.5 Desaturation (DESAT) Protection

6.5.1 DESAT Protection with Soft Turn-OFF
DESAT function is used to detect VDS for SiC-MOSFETs or VCE for IGBTs under overcurrent conditions. Figure
6-10 shows the timing diagram of DESAT operation with soft turn-off during the turning on transition.

IN
(‘IN+’
‘IN ’)

VDESAT

tDESATLEB tDESATLEB
tDESATFIL
DESAT

tDESATOFF

90%

GATE
VCLMPTH

tDESATFLT
tFLTMUTE

Hi-Z
FLT

tRSTFIL tRSTFIL
RST/EN

HIGH
Hi-Z
OUTH
LOW

Hi-Z
OUTL
LOW

Figure 6-10. DESAT Protection with Soft Turn-OFF During Turn-ON Transition

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Figure 6-11 shows the timing diagram of DESAT protection while the power device is already turned on.

IN
(µ,1+¶ Å µ,1Ŷ)

VDESAT

tDESATLEB
tDESATFIL
DESAT

tDESATOFF

90%

GATE
VCLMPTH

tDESATFLT
tFLTMUTE

Hi-Z
FLT

tRSTFIL tRSTFIL
RST/EN

HIGH
Hi-Z
OUTH
LOW

Hi-Z
OUTL
LOW

Figure 6-11. DESAT Protection with Soft Turn-OFF While Power Device is ON

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7 Detailed Description
7.1 Overview
The device is an advanced isolated gate driver with state-of-art protection and sensing features for SiC
MOSFETs and IGBTs. The device can support up to 2121-V DC operating voltage based on SiC MOSFETs
and IGBTs, and can be used to above 10-kW applications such as HEV/EV traction inverter, motor drive,
on-board and off-board battery charger, solar inverter, and so forth. The galvanic isolation is implemented by
the capacitive isolation technology, which can realize a reliable reinforced isolation between the low voltage
DSP/MCU and high voltage side.
The ±10-A peak sink and source current of the device can drive the SiC MOSFET modules and IGBT modules
directly without an extra buffer. The driver can also be used to drive higher power modules or parallel modules
with external buffer stage. The input side is isolated with the output side with a reinforced isolation barrier based
on capacitive isolation technology. The device can support up to 1.5-kVRMS working voltage, 12.8-kVPK surge
immunity with longer than 40 years isolation barrier life. The strong drive strength helps to switch the device fast
and reduce the switching loss, while the 150-V/ns minimum CMTI ensures the reliability of the system with fast
switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting, so the
conduction loss can be reduced.
The device includes extensive protection and monitor features to increase the reliability and robustness of the
SiC MOSFET and IGBT based systems. The 12-V output side power supply UVLO is suitable for switches with
gate voltage ≥ 15 V. The active Miller clamp feature prevents the false turn on causing by Miller capacitance
during fast switching. The device has the state-of-art DESAT detection time, and fault reporting function to the
low voltage side DSP/MCU. The soft turn off is triggered when the DESAT fault is detected, minimizing the short
circuit energy while reducing the overshoot voltage on the switches.
The isolated analog to PWM sensor can be used as switch temperature sensing, DC bus voltage sensing,
auxiliary power supply sensing, and so on. The PWM signal can be fed directly to DSP/MCU or through a
low-pass filter as an analog signal.

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7.2 Functional Block Diagram

7 CLMPI
IN+ 10

55kQ PWM Inputs MOD DEMOD Output Stage

t
4 OUTH
INt 11 ON/OFF Control
STO
55kQ

VCC
6 OUTL
VCC 15

VCC Supply UVLO

5 VDD
GND 9

UVLO
LDO[s for VEE,
3 COM
COM and channel
ISOLATION BARRIER

RDY 12

8 VEE

FLT 13 Fault Decode

DESAT Protection 2 DESAT

Fault Encode
RST/EN 14
50kQ

Analog 2 PWM

APWM 16 PWM Driver 1 AIN

DEMOD MOD

7.3 Feature Description

7.3.1 Power Supply
The input side power supply VCC can support a wide voltage range from 3 V to 5.5 V. The device supports
both unipolar and bipolar power supply on the output side, with a wide range from 13 V to 33 V from VDD to
VEE. The negative power supply with respect to switch source or emitter is usually adopted to avoid false turn
on when the other switch in the phase leg is turned on. The negative voltage is especially important for SiC
MOSFET due to its fast switching speed.
7.3.2 Driver Stage
The device has ±10-A peak drive strength and is suitable for high power applications. The high drive strength
can drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer
stage. The device can also be used to drive higher power modules or parallel modules with extra buffer stage.
Regardless of the values of VDD, the peak sink and source current can be kept at 10 A. The driver features

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an important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in
LOW state. The split output of the driver stage is depicted in Figure 7-1. The driver has rail-to-rail output by
implementing a hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET,
and an N-Channel MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on
resistance RNMOS is the same as ROL. The hybrid pull-up structure delivers the highest peak-source current
when it is most needed, during the Miller plateau region of the power semiconductor turn-on transient. The ROH
in Figure 7-1 represents the on-resistance of the pull-up P-Channel MOSFET. However, the effective pull-up
resistance is much smaller than ROH. Because the pullup N-Channel MOSFET has much smaller on-resistance
than the P-Channel MOSFET, the pullup N-Channel MOSFET dominates most of the turn-on transient, until the
voltage on OUTH pin is about 3 V below VDD voltage. The effective resistance of the hybrid pullup structure
during this period is about 2 x ROL. Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The
low pullup impedance results in strong drive strength during the turn-on transient, which shortens the charging
time of the input capacitance of the power semiconductor and reduces the turn on switching loss. The output
pull-up and pull-down resistance can be found in the Electrical Characteristics table.
The pulldown structure of the driver stage is implemented solely by a pulldown N-Channel MOSFET. This
MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pulldown impedance not only
results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering
the Miller effect.

VDD

ROH
Isolation Barrier

RNMOS
OUTH
Input
Anti Shoot-
Signal
through OUTL
Circuitry

ROL

Figure 7-1. Gate Driver Output Stage

7.3.3 VCC and VDD Undervoltage Lockout (UVLO)

The device implements the internal UVLO protection feature for both input and output power supplies VCC and
VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The output
only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not only
reduces the power consumption of the driver itself during low power supply voltage condition, but also increases
the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the gate-source
voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD value, the
conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the power
stage. The device implements 12-V threshold voltage of VDD UVLO, with 800-mV hysteresis. This threshold
voltage is suitable for both SiC MOSFET and IGBT.

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The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity
of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak
transient current from the power supply, which can result in sudden voltage drop of the power supply. With
hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal
switching transients.
The timing diagrams of the UVLO feature of VCC and VDD are shown in Figure 6-8, and Figure 6-9. The RDY
pin on the input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO
condition, the RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to
VCC to indicate the power good. The AIN-APWM function stops working during the UVLO status. The APWM
pin on the input side will be held LOW.
7.3.4 Active Pulldown
The device implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the
VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature
can prevent the output be false turned on before the device is back to control.

VDD

OUTL

Ra

Control
Circuit

VEE

COM

Figure 7-2. Active Pulldown

7.3.5 Short Circuit Clamping

During short circuit condition, the Miller capacitance can cause a current sinking to the OUTH/OUTL/CLMPI
pin due to the high dV/dt and boost the OUTH/OUTL/CLMPI voltage. The short circuit clamping feature of the
device can clamp the OUTH/OUTL/CLMPI pin voltage to be slightly higher than VDD, which can protect the
power semiconductors from a gate-source and gate-emitter overvoltage breakdown. This feature is realized by
an internal diode from the OUTH/OUTL/CLMPI to VDD.

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VDD

D1 D2 D3

OUTH
Control
Circuitry OUTL

CLMPI

Figure 7-3. Short Circuit Clamping

7.3.6 Internal Active Miller Clamp

Active Miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In
applications which the device can be in synchronous rectifier mode, the body diode conducts the current
during the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the
same and the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal
pull-down impedance of UCC21755-Q1 can provide a strong pulldown to hold the OUTL to VEE. However,
external gate resistance is usually adopted to limit the dV/dt. The Miller effect during the turn on transient
of the other power semiconductor can cause a voltage drop on the external gate resistor, which boost the
gate-source or gate-emitter voltage. If the voltage on VGS or VGE is higher than the threshold voltage of the
power semiconductor, a shoot through can happen and cause catastrophic damage. The active Miller clamp
feature of UCC21755-Q1 drives an internal MOSFET, which connects to the device gate. The MOSFET is
triggered when the gate voltage is lower than VCLMPTH, which is 2 V above VEE, and creates a low impedance
path to avoid the false turn on issue.

VCLMPTH
VCC OUTH

+
3V to 5.5V
±
CLMPI
Isolation barrier

Control
IN+ Circuitry
µC OUTL
MOD DEMOD

IN-
VEE

VCC
COM

Figure 7-4. Active Miller Clamp

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7.3.7 Desaturation (DESAT) Protection

The UCC21755-Q1 implements a fast overcurrent and short circuit protection feature to protect the IGBT module
from catastrophic breakdown during fault. The DESAT pin has a typical 5-V threshold with respect to COM, the
source or emitter of the power semiconductor. When the input is in a floating condition or the output is held in
low state, the DESAT pin is pulled down by an internal MOSFET and held in the LOW state, which prevents the
overcurrent and short circuit fault from false triggering. The internal current source of the DESAT pin is activated
only during the driver ON state, which means the overcurrent and short circuit protection feature only works
when the power semiconductor is in the ON state. The internal pulldown MOSFET helps to discharge the voltage
of the DESAT pin when the power semiconductor is turned off. The UCC21755-Q1 features a 200-ns internal
leading edge blanking time after the OUTH switches to high state. The internal current source is activated to
charge the external blanking capacitor after the internal leading edge blanking time. The typical value of the
internal current source is 500 µA.

VDD
Deglitch Filter

DESAT R D HV
+
DESAT Fault
–

C BLK
+
VDESAT
–
Control
Logic
COM

Figure 7-5. DESAT Protection

7.3.8 Soft Turn-Off

The device initiates a soft turn-off when the overcurrent and short circuit protection are triggered. When the
overcurrent and short circuit faults occur, the IGBT transits from the active region to the desaturation region very
quickly. The channel current is controlled by the gate voltage and decreases softly; thus, the overshoot of the
IGBT is limited and prevents the overvoltage breakdown. There is a tradeoff between the overshoot voltage and
short circuit energy. The turn-off speed should be slow to limit the overshoot-voltage, but the shutdown time
should not be too long that the large energy dissipation can breakdown the device. The 400-mA soft turn-off
current of the device ensures the power switches are safely turned off during short circuit events. Figure 6-10
shows the soft turn-off timing diagram.

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VDD

DESAT R DHV
Deglitch Filter +
–

CBLK
+
VDESAT
–
Control
Logic
COM

Soft Turn-off OUTL

VEE

Figure 7-6. Soft Turn-Off

7.3.9 Fault (FLT), Reset and Enable (RST/EN)

The FLT pin of UCC21755-Q1 is open drain and can report a fault signal to the DSP/MCU when the fault is
detected through the DESAT pin. The FLT pin is pulled down to GND after the fault is detected, and is held low
until a reset signal is received from RST/EN. The device has a fault mute time tFLTMUTE, within which the device
ignores any reset signal.
The RST/EN is pulled down internally by a 50-kΩ resistor, and is thus disabled by default when this pin is
floating. It must be pulled up externally to enable the driver. The pin has two purposes:
• To reset the FLT pin. If the RST/EN pin is pulled low for more than tRSTFIL after the mute time tFLTMUTE, then
the fault signal is reset and FLT returns to a high impedance state upon the next rising edge applied to the
RST/EN pin.
• To enable and shut down the device. If the RST/EN pin is pulled low for longer than tRSTFIL, the driver is
disabled and OUTL is activated to pull down the gate of the IGBT or SiC MOSFET. The pin must be pulled up
externally to enable the part; otherwise, the device is disabled by default.
7.3.10 Isolated Analog to PWM Signal Function
The device features an isolated analog to PWM signal function from AIN to APWM pin, which allows the isolated
temperature sensing, high voltage dc bus voltage sensing, and so on. An internal current source IAIN in AIN
pin is implemented in the device to bias an external thermal diode or temperature sensing resistor. The device
encodes the voltage signal VAIN to a PWM signal, passing through the reinforced isolation barrier, and output
to APWM pin on the input side. The PWM signal can either be transferred directly to DSP/MCU to calculate
the duty cycle, or filtered by a simple RC filter as an analog signal. The AIN voltage input range is from 0.6
V to 4.5 V, and the corresponding duty cycle of the APWM output ranges from 88% to 10%. The duty cycle
increases linearly from 10% to 88% while the AIN voltage decreases from 4.5 V to 0.6 V. This corresponds
to the temperature coefficient of the negative temperature coefficient (NTC) resistor and thermal diode. When

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AIN is floating, the AIN voltage is 5 V and the APWM operates at 400 kHz with approximately 10% duty cycle.
The accuracy of the duty cycle is ±3% across temperature without one time calibration. The accuracy can be
improved using calibration. The accuracy of the internal current source IAIN is ±3% across temperature.
The isolated analog to PWM signal feature can also support other analog signal sensing, such as the high
voltage DC bus voltage, and so on. The internal current source IAIN should be taken into account when designing
the potential divider if sensing a high voltage.

UCC217xx
In Module or
VCC VDD
Discrete
13V to
+
+ 33V
3V to 5.5V ±
±

Isolation barrier
APWM AIN
+
µC DEMOD MOD Rfilt

OSC
Cfilt

GND
COM Thermal NTC or
Diode PTC

Figure 7-7. Isolated Analog to PWM Signal

7.4 Device Functional Modes

Table 7-1 lists the device function.
Table 7-1. Function Table
INPUT OUTPUT
OUTH/
VCC VDD VEE IN+ IN- RST/EN AIN RDY FLT CLMPI APWM
OUTL
PU PD PU X X X X Low HiZ Low Low Low
PD PU PU X X X X Low HiZ Low Low Low
PU PU PU X X Low X HiZ HiZ Low Low Low
PU Open PU X X X X Low HiZ HiZ HiZ HiZ
PU PU Open X X X X Low HiZ Low Low Low
PU PU PU Low X High X HiZ HiZ Low Low P*
PU PU PU X High High X HiZ HiZ Low Low P*
PU PU PU High High High X HiZ HiZ Low Low P*
PU PU PU High Low High X HiZ HiZ High HiZ P*

PU: Power Up (VCC ≥ 2.85 V, VDD ≥ 13.1 V, VEE ≤ 0 V); PD: Power Down (VCC ≤ 2.35 V, VDD ≤ 9.9 V); X:
Irrelevant; P*: PWM Pulse; HiZ: High Impedance

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8 Applications and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The device is very versatile because of the strong drive strength, wide range of output power supply, high
isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working voltage and
12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus voltage up to
2121 V. The device can be used in both low power and high power applications such as the traction inverter in
HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies, and so on.
The device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device directly
without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows
the driver to have more control to the power semiconductor and saves the cost and space of the board design.
The device can also be used to drive very high power modules or paralleled modules with external buffer stage.
The input side can support power supply and microcontroller signal from 3.3 V to 5 V, and the device level shifts
the signal to output side through reinforced isolation barrier. The device has wide output power supply range
from 13 V to 33 V and support wide range of negative power supply. This allows the driver to be used in SiC
MOSFET applications, IGBT application, and many others. The 12-V UVLO benefits the power semiconductor
with lower conduction loss and improves the system efficiency. As a reinforced isolated single channel driver, the
device can be used to drive either a low-side or high-side driver.
The device features extensive protection and monitoring features, which can monitor, report and protect the
system from various fault conditions.
• Fast detection and protection for the overcurrent and short circuit fault. The semiconductor is shutdown when
the fault is detected and FLT pin is pulled down to indicate the fault detection. The device is latched unless
reset signal is received from the RST/EN pin.
• Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and
short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is
limited.
• UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to
be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is
back to normal operation mode once the power supply is out of the UVLO status. The power good status can
be monitored from the RDY pin.
• Analog signal seensing with isolated analog to PWM signal feature. This feature allows the device to sense
the temperature of the semiconductor from the thermal diode or temperature sensing resistor, or dc bus
voltage with resistor divider. A PWM signal is generated on the low voltage side with reinforced isolated
from the high voltage side. The signal can be fed back to the microcontroller for the temperature monitoring,
voltage monitoring, and and so on.
• The active Miller clamp feature protects the power semiconductor from false turn on.
• Enable and disable function through the RST/EN pin
• Short circuit clamping
• Active pulldown
8.2 Typical Application
Figure 8-1 shows the typical application of a half bridge using two UCC21755-Q1 isolated gate drivers. The half
bridge is a basic element in various power electronics applications such as traction inverter in HEV/EV to convert
the DC current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion
system. The topology can also be used in motor drive applications to control the operating speed and torque of
the AC motors.

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UCC 217XX

UCC 217XX

1
2
3
PWM UCC 217XX
4
5
3-Phase 6
Input µC 1
2 M
3 UCC 217XX
APWM
4
5
6
FLT
UCC 217XX

UCC 217XX

Figure 8-1. Typical Application Schematic

8.2.1 Design Requirements

The design of the power system for end equipment should consider some design requirements to ensure the
reliable operation of the device through the load range. The design considerations include the peak source and
sink current, power dissipation, overcurrent and short circuit protection, AIN-APWM function for analog signal
sensing, and so on.
A design example for a half bridge based on IGBT is given in this subsection. The design parameters are shown
in Table 8-1.
Table 8-1. Design Parameters
PARAMETER VALUE
Input Supply Voltage 5V
IN-OUT Configuration Noninverting
Positive Output Voltage VDD 15 V
Negative Output Voltage VEE –5 V
DC Bus Voltage 800 V
Peak Drain Current 300 A
Switching Frequency 50 kHz
Switch Type IGBT Module

8.2.2 Detailed Design Procedure

[Link] Input Filters for IN+, IN-, and RST/EN
In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With
the strong drive strength of the device, the dV/dt can be high, especially for SiC MOSFET. Noise cannot only

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be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal PCB
layout and coupled capacitance.
The device features a 40-ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40 ns can
be filtered out from the input pins. For noisy systems, external low-pass filter can be added externally to the
input pins. Adding low-pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and
increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should
be tied to GND if only IN+ is used for noninverting input to output configuration. The purpose of the low-pass
filter is to filter out the high frequency noise generated by the layout parasitics. While choosing the low-pass filter
resistors and capacitors, both the noise immunity effect and delay time should be considered according to the
system requirements.
[Link] PWM Interlock of IN+ and IN-
The device features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg shoot
through issue. As shown in Table 7-1, the output is logic low while both IN+ and IN- are logic high. When only
IN+ is used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other switch
in the phase leg can be sent to the IN- pin. As shown in Figure 8-2, the PWM_T is the PWM signal to top side
switch, the PWM_B is the PWM signal to bottom side switch. For the top side gate driver, the PWM_T signal is
given to the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom side gate driver, the PWM_B
signal is given to the IN+ pin, while PWM_T signal is given to the IN- pin. When both PWM_T and PWM_B
signals are high, the outputs of both gate drivers are logic low to prevent the shoot through condition.

IN+ RON
OUTH
IN-
OUTL
ROFF
Microcontroller

PWM_T

PWM_B

IN+ RON
OUTH
IN-
OUTL
ROFF

Figure 8-2. PWM Interlock for a Half Bridge

[Link] FLT, RDY, and RST/EN Pin Circuitry

Both FLT and RDY pin are open-drain output. The RST/EN pin has 50-kΩ internal pulldown resistor, so the driver
is in OFF status if the RST/EN pin is not pulled up externally. A 5-kΩ resistor can be used as pullup resistor for
the FLT, RDY, and RST/EN pins.
To improve the noise immunity due to the parasitic coupling and common-mode noise, low-pass filters can be
added between the FLT, RDY, and RST/EN pins and the microcontroller. A filter capacitor between 100 pF to
300 pF can be added.

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3.3V to 5V
VCC
15
0.1µF 1µF

GND
9
IN+
10
INt
11
Micro-controller

5kQ 5kQ 5kQ

(MCU)

FLT
12
100pF
13
RDY
100pF

RST/EN
100pF 14

APWM
16

Figure 8-3. FLT, RDY, and RST/EN Pins Circuitry

[Link] RST/EN Pin Control

RST/EN pin has two functions. It is used to enable or shutdown the outputs of the driver and to reset the fault
signaled on the FLT pin after DESAT is detected. RST/EN pin needs to be pulled up to enable the device; when
the pin is pulled down, the device is in disabled status. By default the driver is disabled with the internal 50-kΩ
pulldown resistor at this pin.
When the driver is latched after DESAT is detected, the FLT pin and output are latched low and need to be reset
by the RST/EN pin. The microcontroller must send a signal to RST/EN pin after the fault to reset the driver. The
driver will not respond until after the mute time tFLTMUTE. The reset signal must be held low for at least tRSTFIL
after the mute time.
This pin can also be used to automatically reset the driver. The continuous input signal IN+ or IN- can be applied
to RST/EN pin. There is no separate reset signal from the microcontroller when configuring the driver this way. If
the PWM is applied to the noninverting input IN+, then IN+ can also be tied to RST/EN pin. If the PWM is applied
to the inverting input IN-, then a NOT logic is needed between the PWM signal from the microcontroller and the
RST/EN pin. Using either configuration results in the driver being reset in every switching cycle without an extra
control signal from microcontroller tied to RST/EN pin. One must ensure the PWM off-time is greater than tRSTFIL
in order to reset the driver in cause of a DESAT fault.

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3.3V to 5V 3.3V to 5V
VCC VCC
15 15
0.1µF 1µF 0.1µF 1µF

GND GND
9 9
IN+ IN+
10 10
Micro-controller

Micro-controller
INt INt
(MCU)

(MCU)
5kQ 5kQ 11 5kQ 5kQ 11
FLT FLT
12 12
100pF 100pF
13 13
RDY RDY
100pF 100pF
RST/EN RST/EN
14 14
APWM APWM
16 16

Figure 8-4. Automatic Reset Control

[Link] Turn-On and Turn-Off Gate Resistors

The device features split outputs OUTH and OUTL, which enables the independent control of the turn-on and
turn-off switching speeds. The turn-on and turn-off resistances determine the peak source and sink current,
which control the switching speed. Meanwhile, the power dissipation in the gate driver should be considered to
ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:

VDD VEE
Is ource _ pk min(10A, )
ROH _ EFF RON RG _ Int
VDD VEE
Isink _ pk min(10A, )
ROL ROFF RG _ Int (1)

Where
• ROH_EFF is the effective internal pullup resistance of the hybrid pullup structure, shown in Figure 7-1, which is
approximately 2 x ROL, about 0.7 Ω. This is the dominant resistance during the switching transient of the pull
up structure.
• ROL is the internal pulldown resistance, about 0.3 Ω.
• RON is the external turn-on gate resistance.
• ROFF is the external turn-off gate resistance.
• RG_Int is the internal resistance of the SiC MOSFET or IGBT module.

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VDD

+ Cies=Cgc+Cge
ROH_EFF VDD Cgc
OUTH RON t

RG_Int
OUTL ROFF

ROL + Cge
VEE
VEE t

COM

Figure 8-5. Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:
• Qg = 3300 nC
• RG_Int = 1.7 Ω
• RON=ROFF= 1 Ω
The peak source and sink current in this case are:

VDD VEE
Is ource _ pk min(10A, ) | 5.9A
ROH _ EFF RON RG _ Int
VDD VEE
Isink _ pk min(10A, ) | 6.7A
ROL ROFF RG _ Int (2)

Using 1-Ω external gate resistance, the peak source current is 5.9 A, the peak sink current is 6.7 A. The
collector-to-emitter dV/dt during the turn-on switching transient is dominated by the gate current at the Miller
plateau voltage. The hybrid pullup structure ensures the peak source current at the Miller plateau voltage, unless
the turn-on gate resistor is too high. The faster the collector-to-emitter, Vce, voltage rises to VDC, the smaller
the turn-on switching loss. The dV/dt can be estimated as Qgc/Isource_pk. For the turn-off switching transient,
the drain-to-source dV/dt is dominated by the load current, unless the turn-off gate resistor is too high. After
Vce reaches the DC bus voltage, the power semiconductor is in SATURATION mode and the channel current
is controlled by Vge. The peak sink current determines the dI/dt, which dominates the Vce voltage overshoot
accordingly. If using relatively large turn-off gate resistance, the Vce overshoot can be limited. The overshoot can
be estimated by:

'Vce Lstray ˜ Iload / ((ROFF ROL RG _Int ) ˜ Cies ˜ ln(Vplat / Vth )) (3)

Where
• Lstray is the stray inductance in power switching loop, as shown in Figure 8-6.
• Iload is the load current, which is the turn-off current of the power semiconductor.
• Cies is the input capacitance of the power semiconductor.
• Vplat is the plateau voltage of the power semiconductor.
• Vth is the threshold voltage of the power semiconductor.

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LDC

Lc1
Lstray=LDC+Le1+Lc1+Le1+Lc1

RG
Lload
t
+

Le1 +
VDC
t

Lc2
VDD
Cgc
Cies=Cgc+Cge
OUTH RG

OUTL
Cge
COM
Le2

Figure 8-6. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The
power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

PDR PQ PSW (4)

PQ is the quiescent power loss for the driver, which is Iq × (VDD-VEE) = 5 mA × 20 V = 0.100 W. The quiescent
power loss is the power consumed by the internal circuits, such as the input stage, reference voltage, logic
circuits, and protection circuits when the driver is switching, when the driver is biased with VDD and VEE, and
the charging and discharging current of the internal circuit when the driver is switching. The power dissipation
when the driver is switching can be calculated as:

1 ROH _ EFF ROL

PSW ˜( ) ˜ (VDD VEE) ˜ fsw ˜ Qg
2 ROH _ EFF RON RG _ Int ROL ROFF RG _ Int (5)

Where
• Qg is the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD.
• fsw is the switching frequency.
In this example, the PSW can be calculated as:

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1 ROH _ EFF ROL

PSW ˜( ) ˜ (VDD VEE) ˜ fsw ˜ Qg 0.505W
2 ROH _ EFF RON RG _ Int ROL ROFF RG _ Int (6)

Thus, the total power loss is:

PDR PQ PSW 0.10W 0.505W 0.605W (7)

When the board temperature is 125°C, the junction temperature can be estimated as:

Tj Tb \ jb ˜ PDR | 150 o C (8)

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency
is ~50 kHz to keep the gate driver in the thermal limit. By using a lower switching frequency or increasing
external gate resistance, the gate driver can be operated at a higher switching frequency.
[Link] Overcurrent and Short Circuit Protection
A standard desaturation circuit can be applied to the DESAT pin. If the voltage of the DESAT pin is higher than
the threshold VDESAT, the soft turn-off is initiated. A fault will be reported to the input side to DSP/MCU. The
output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin. The state-of-art
overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC MOSFET and IGBT.
If DESAT pin is not in use, it must be tied to COM to avoid overcurrent fault false triggering.
• Fast reverse recovery high voltage diode is recommended in the desaturation circuit. A resistor is
recommended in series with the high voltage diode to limit the inrush current.
• A Schottky diode is recommended from COM to DESAT to prevent driver damage caused by negative
voltage.
• A Zener diode is recommended from COM to DESAT to prevent driver damage caused by positive voltage.
[Link] Isolated Analog Signal Sensing
The isolated analog signal sensing feature provides a simple isolated channel for the isolated temperature
detection, voltage sensing, and so on. One typical application of this function is the temperature monitor of the
power semiconductor. Thermal diodes or temperature sensing resistors are integrated in the SiC MOSFET or
IGBT module close to the dies to monitor the junction temperature. The device has an internal 200-μA current
source with ±3% accuracy across temperature, which can forward bias the thermal diodes or create a voltage
drop on the temperature sensing resistors. The sensed voltage from the AIN pin is passed through the isolation
barrier to the input side and transformed to a PWM signal. The duty cycle of the PWM changes linearly from
10% to 88% when the AIN voltage changes from 4.5 V to 0.6 V and can be represented using Equation 9.

DAPWM (%) 20 * VAIN 100 (9)

[Link].1 Isolated Temperature Sensing
A typical application circuit is shown in Figure 8-7. To sense temperature, the AIN pin is connected to the
thermal diode or thermistor which can be discrete or integrated within the power module. A low-pass filter is
recommended for the AIN input. Since the temperature signal does not have a high bandwidth, the low-pass
filter is mainly used for filtering the noise introduced by the switching of the power device, which does not require
stringent control for propagation delay. The filter capacitance for Cfilt can be chosen between 1 nF to 100 nF and
the filter resistance Rfilt between 1 Ω to 10 Ω according to the noise level.
The output of APWM is directly connected to the microcontroller to measure the duty cycle dependent on the
voltage input at AIN, using Equation 9.

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UCC217xx
In Module or
VCC VDD
Discrete
13V to
+
+ 33V
3V to 5.5V ±
±

Isolation barrier
APWM AIN
+
µC DEMOD MOD Rfilt

OSC
Cfilt

GND
COM Thermal NTC or
Diode PTC

Figure 8-7. Thermal Diode or Thermistor Temperature Sensing Configuration

When a high-precision voltage supply for VCC is used on the primary side of the device, the duty cycle output
of APWM may also be filtered and the voltage measured using the microcontroller's ADC input pin, as shown in
Figure 8-8. The frequency of APWM is 400 kHz, so the value for Rfilt_2 and Cfilt_2 should be such that the cutoff
frequency is below 400 kHz. Temperature does not change rapidly, thus the rise time due to the RC constant of
the filter is not under a strict requirement.

UCC217xx
VDD In Module or
VCC Discrete
+ 13V to
+ ± 33V
3V to 5.5V
±
Isolation barrier

APWM AIN
+
µC DEMOD MOD Rfilt_1
Rfilt_2
OSC Cfilt_1
Cfilt_2

GND
COM Thermal NTC or
Diode PTC

Figure 8-8. APWM Channel with Filtered Output

The example below shows the results using a 4.7-kΩ NTC, NTCS0805E3472FMT, in series with a 3-kΩ resistor
and also the thermal diode using four diode-connected MMBT3904 NPN transistors. The sensed voltage of
the 4 MMBT3904 thermal diodes connected in series ranges from about 2.5 V to 1.6 V from 25°C to 135°C,
corresponding to 50% to 68% duty cycle. The sensed voltage of the NTC thermistor connected in series with the
3-kΩ resistor ranges from about 1.5 V to 0.6 V from 25°C to 135°C, corresponding to 70% to 88% duty cycle.
The voltage at VAIN of both sensors and the corresponding measured duty cycle at APWM is shown in Figure
8-9.

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2.7 90

2.4 Thermal Diode VAIN 84

NTC VAIN
Thermal Diode APWM
2.1 NTC APWM 78

APWM (%)
1.8 72
VAIN (V)

1.5 66

1.2 60

0.9 54

0.6 48
20 40 60 80 100 120 140
Temperature (qC) VAIN

Figure 8-9. Thermal Diode and NTC VAIN and Corresponding Duty Cycle at APWM

The duty cycle output has an accuracy of ±3% throughout temperature without any calibration, as shown in
Figure 8-10 but with single-point calibration at 25°C, the duty accuracy can be improved to ±1%, as shown in
Figure 8-11.
1.5
Thermal Diode APWM Duty Error
NTC APWM Duty Error
1.25

1
APWM Duty Error (%)

0.75

0.5

0.25

-0.25
20 40 60 80 100 120 140
Temperature (qC) APWM

Figure 8-10. APWM Duty Error Without Calibration

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0.8
Thermal Diode APWM Duty Error
NTC APWM Duty Error

0.6
APWM Duty Error (%)

0.4

0.2

-0.2
20 40 60 80 100 120 140
Temperature (qC) APWM

Figure 8-11. APWM Duty Error with Single-Point Calibration

[Link].2 Isolated DC Bus Voltage Sensing

The AIN to APWM channel may be used for other applications such as the DC-link voltage sensing, as shown in
Figure 8-12. The same filtering requirements as given above may be used in this case, as well. The number of
attenuation resistors, Ratten_1 through Ratten_n, is dependent on the voltage level and power rating of the resistor.
The voltage is finally measured across RLV_DC to monitor the stepped-down voltage of the HV DC-link which
must fall within the voltage range of AIN from 0.6 V to 4.5 V. The driver should be referenced to the same point
as the measurement reference; thus, in the case shown below, the UCC21755-Q1 is driving the lower IGBT
in the half-bridge and the DC-link voltage measurement is referenced to COM. The internal current source IAIN
should be taken into account when designing the resistor divider. The AIN pin voltage is:

RLV _ DC
VAIN n
˜ VDC RLV _ DC ˜ IAIN
RLV _ DC ¦R atten _ i
i 1 (10)
Ratten_1

Ratten_2

UCC217xx
VCC VDD

Ratten_n
+ 13V to
+ 33V
3V to 5.5V ±
±
Isolation barrier

CDC
APWM
+
µC DEMOD MOD AIN Rfilt
Rfilt_2
Cfilt RLV_DC
OSC
Cfilt_2
COM
GND

Figure 8-12. DC-Link Voltage Sensing Configuration

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[Link] Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a noninverting current buffer (such as the NPN/PNP buffer shown in
Figure 8-13) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/
D45VH10 pair is up to 20-A peak.
In the case of an overcurrent detection, the soft turn-off (STO) is activated. External components must be added
to implement STO instead of normal turn-off speed when an external buffer is used. CSTO sets the timing for soft
turn-off and RSTO limits the inrush current to below the current rating of the internal FET (10A). RSTO should be
at least (VDD-VEE)/10. The soft turn-off timing is determined by the internal current source of 400 mA and the
capacitor CSTO. CSTO is calculated using Equation 11.

ISTO ˜ t STO
CSTO
VDD VEE (11)
• ISTO is the internal STO current source, 400 mA.
• tSTO is the desired STO timing.

VDD VDD

ROH

RNMOS OUTH Cies=Cgc+Cge

Cgc Cgc

RG_1 RG_2 RG_Int

RG_Int

OUTL
Cge Cge

ROL
CSTO

COM
RSTO

VEE

Figure 8-13. Current Buffer for Increased Drive Strength

8.2.3 Application Curves

Figure 8-14. PWM Input (yellow) and Driver Output (blue)

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Ste p Input (0.6 V to 4.5 V)

APWM Output

Figure 8-15. AIN Step Input (green) and APWM Output (pink)

9 Power Supply Recommendations

During the turn-on and turn-off switching transient, the peak source and sink current is provided by the VDD
and VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause
a voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of
decoupling capacitors are recommended at the power supplies. Considering the device has ±10-A peak drive
strength and can generate high dV/dt, a 10-µF bypass cap is recommended between VDD and COM, VEE
and COM. A 1-µF bypass cap is recommended between VCC and GND due to less current comparing with
output side power supplies. A 0.1-µF decoupling cap is also recommended for each power supply to filter out
high frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and
should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system
parasitics of PCB layout.
10 Layout
10.1 Layout Guidelines
Due to the strong drive strength of the device, careful considerations must be taken in PCB design. Below are
some key points:
• The driver should be placed as close as possible to the power semiconductor to reduce the parasitic
inductance of the gate loop on the PCB traces.
• The decoupling capacitors of the input and output power supplies should be placed as close as possible
to the power supply pins. The peak current generated at each switching transient can cause high dI/dt and
voltage spike on the parasitic inductance of PCB traces.
• The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If
the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close
as possible to the source or emitter terminal of the power device package to separate the gate loop from the
high power switching loop.
• Use a ground plane on the input side to shield the input signals. The input signals can be distorted by
the high frequency noise generated by the output side switching transients. The ground plane provides a
low-inductance filter for the return current flow.
• If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use
the ground plane on the output side to shield the output signals from the noise generated by the switch
node; if the gate driver is used for the high side switch, which the COM pin is connected to the switch node,
ground plane should not overlap with any low-side circuitry, and it should be routed independently from the
source/emitter power path.
• If ground plane is not used on the output side, separate the return path of the DESAT and AIN ground loop
from the gate loop ground which has large peak source and sink current.
• No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise
coupling between the input and output side which can contaminate the isolation barrier.
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10.2 Layout Example

Figure 10-1. Layout Example

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Isolation Glossary
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (September 2022) to Revision A (June 2024) Page

• Changed device temperature grade................................................................................................................... 1
• Deleted ESD classifications from Features........................................................................................................ 1
• Deleted ESD classifications from Specifications................................................................................................ 4

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[Link] SLUSEM9A – SEPTEMBER 2022 – REVISED JUNE 2024

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 45

Product Folder Links: UCC21755-Q1
 PACKAGE OPTION ADDENDUM

[Link] 18-Jul-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

UCC21755QDWRQ1 Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 UCC21755Q
UCC21755QDWRQ1.A Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 UCC21755Q
UCC21755QDWRQ1.B Active Production SOIC (DW) | 16 2000 | LARGE T&R - Call TI Call TI -40 to 125

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 25-Jul-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC21755QDWRQ1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 25-Jul-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC21755QDWRQ1 SOIC DW 16 2000 353.0 353.0 32.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

[Link]
 PACKAGE OUTLINE
DW0016B SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

[Link]
 EXAMPLE BOARD LAYOUT
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65) SEE
SEE DETAILS
DETAILS
1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9
R0.05 TYP R0.05 TYP
(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DW0016B SOIC - 2.65 mm max height
SOIC

SYMM SYMM
16X (2) 16X (1.65)

1 1
16 16

16X (0.6) 16X (0.6)

SYMM SYMM

14X (1.27) 14X (1.27)

8 9 8 9

R0.05 TYP R0.05 TYP

(9.3) (9.75)

IPC-7351 NOMINAL HV / ISOLATION OPTION

7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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