INTRODUCTION TO SEQUENTIAL LO! Q Digital electronics is classified into combinational logic and sequential logic. Q) In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. Q) For a change in input, the output occurs immediately. ;—> Combinational ‘int output Logic > : variables Circuit oh Combinational Circuit- Block DiagramINTRODUCTION TO SEQUENTIAL LO! Q There are many applications in which digital outputs are required to be generated in accordance with the sequence in which the input signals are received. The requirement can’t be satisfied with combinational circuits. In sequential logic circuits, it consists of combinational circuits to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing binary information either 1 or 0. The information stored in the memory elements at any given time defines the present state of the sequential circuit.INTRODUCTION TO SEQUENTIAL LOGIC Q The present state and the external circuit determine the output and the next state of sequential circuits. Q) Thus in sequential circuits, the output variables depend not only on the present input variables but also on the past history of input variables. Inputs Sequential Circuit- Block DiagramINTRODUCTION TO SEQUENTIAL LOGIC Combinational vs Sequential Circuit | [Link] ‘Combinational logic Sequential logic The output variable, at all times | The output variable depends not only on 1 | depends on the combination of the present input but also depend upon the Input variables. past history of inputs. Memory unit is required to store the past 2M it is not required Ee history of input variables. 3 Faster in speed Slower than combinational circuits. 4 | Easy to design Comparatively difficult to design. 5 | Eg. MUX, Decoder, Parallel adder | Eg. Counter, Shift RegisterAPPLICATIONS OF SEQUENTIAL LOGIC CIRCUIT » Major application of sequential circuits is to build up the memory unit, from small memory card to a huge computer memory » Other applications of sequential logic circuits includes: » Counters » Shift registers » Analog to digital and digital to analog converters » Used as registers inside microprocessors and controllersMODULES, Latches and Flip-Flops are the basic building blocks of the most sequential circuits. Latches are used for a sequential device that checks all of its inputs continuously and changes its outputs accordingly at any time independent of clocking signal. Enable signal is provided with the latch. When enable signal is active output changes occur as the input changes. But when enable signal is not activated input changes do not affect the output. Flip-Flop is used for a sequential device that normally samples its inputs and changes its outputs only at times determined by clocking signal. DIGITAL LOGIC DESIGNSR Latch using NOR The simplest type of latch is the set-reset (SR) latch. It can be constructed from either two NOR gates or two NAND gates. The two NOR gates are cross-coupled so that the output of NOR gate 1 is connected to one of the inputs of NOR gate 2 and vice versa. The latch has two outputs Q and Q’ and two inputs, set and reset. Before going to analyze the SR latch, we recall that a logic 1 at any input of a NOR gate forces its output to a logic 0. Let us understand the operation of this circuit for various input/ output possibilities. MODULES, DIGITAL LOGIC DESIGNSR Latch using NOR Case 1: Case 1: S= 0 and R=0 (Initially, (Initially, Q= 0 and Q’= 1) R (Reset) & Reset) © MODULES, DIGITAL LOGIC DESIGNSR Latch using NOR Case 2: S=O and R=1 Case 3: S= 1 and R=0 R (Reset) 1 MODULES, DIGITAL LOGIC DESIGNSR Latch using NOR Case 4: S= 1 and R= 1 Q) When R and S both are at logic 1, they force the outputs of both NOR gates to the low state, i.e., (Q=0 and Q’=0). Q) So, we call this an indeterminate or prohibited state, and represent this condition in the truth table as an asterisk (*). This condition also violates the basic definition of a latch that requires Q to be complement of Q’. Thus in normal operation this condition must be avoided by making sure that 1’s are not applied to both the inputs simultaneously. MODULES, DIGITAL LOGIC DESIGN 11SR Latch using NOR Present state_| Next state Qasr ° State No Change (NC) Reset Set Indeterminate* Truth table MODULES, DIGITAL LOGIC DESIGNSR Latch using NAND Q The SR latch can also be implemented using NAND gates. The inputs of this Latch are S and R. Q To understand how this circuit functions, recall that a low on any input to a NAND gate forces its output high. S (Set) R (Reset) Logic Symbol SR latch using NAND gates MODULES, DIGITAL LOGIC DESIGNSR Latch using NAND State Indeterminate* Set Reset No Change (NC) Truth table MODULES, DIGITAL LOGIC DESIGNGated Latch using NAND 1 In the SR latch, the output changes occur immediately after the input changes i.e, the latch is sensitive to its $ and R inputs all the time. Q A latch that is sensitive to the inputs only when an enable input is active. Such a latch with enable input is known as gated SR latch. Q The circuit behaves like SR latch when EN= 1. It retains its previous state when EN= 0. MODULES, DIGITAL LOGIC DESIGNGated Latch using NAND | [ >» SR Latch with enable input using NAND gates MODULES, DIGITAL LOGIC DESIGN 16—~-~seooneecennensenseesettensettceteseesneneeMeIaZtaetaetestseseetetseteeetetteeteeeerena— Gated Latch using NAND On State 0 No Change (NC) Reset Set Indeterminate * No Change (NC) oofs aa ale ee ele x ete ule ele He ole Truth table MODULES, DIGITAL LOGIC DESIGNGated Latch using NAND Input and output waveforms MODULES, DIGITAL LOGIC DESIGNQa MODULES, D- Latch using NAND In SR latch, when both inputs are same (00 or 11), the output either does not change or it is invali In many practical applications, these input conditions are not required. These input conditions can be avoided by making them complement of each other. Therefore, only two input conditions exists, either S=o and R=1 or S=1 and R=0. This modified SR latch is known as D latch. DIGITAL LOGIC DESIGND- Latch using NAND MODULES, DIGITAL LOGIC DESIGN eeD- Latch using NAND Ques State 0 Reset 1 Set Q, | No Change (NC) Truth table Le} Input and output waveforms MODULES, DIGITAL LOGIC DESIGN 21Flip flops Q The basic 1-bit digital memory circuit is known as a flip-flop. Flip- Flops are synchronous bistable devices (has two outputs Q and Q’). Q In this case, the term synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK), i.e., changes in the output occur in synchronization with the clock. It can have only two states, either the 1 state or the 0 state. J} —Normat output Inputs 0'} Inverted output Block diagram of flip-flopFlip flops Flip-flops can be obtained by using NAND or NOR gates. If Qis 1 Ze, Set, then Q’ is 0; if Q is 0 ie, Reset, then Q’ is 1. That means Q and Q’ cannot be at the same state simultaneously. There are different types of flip-flops depending on how their inputs and clock pulses cause transition between two states. We will discuss four different types of flip-flops SR, D, JK, and T. Basically D, J-K, and T are three different modifications of the S-R flip-flop._—-~~~==r nse ooSSDEnESOORieSlaGsSSiaesbSlAtehtdtSenenenenmnnssseeneeerer==e Triggering of Flip flops C1 There are two types of level triggered latches: > (). Positive level triggered: The output of the latch responds to the input changes only when the enable input is (HIGH). Rites enaies ony when of pats HGH > (ii). Negative level triggered: The output of the latch responds to the input changes only when the enable input is 0 (LOW).Triggering of Flip flops C1 Edge Triggering: In the edge triggering the output responds to the changes in the input only at the positive or negative edges of the clock pulse at the clock input. (Positive edge triggering: Here the output responds to the changes in the input only at the positive edge of the clock pulse at the clock input. se fF | | OQ (i. Negative edge triggering: Here the output responds to the changes in the input only at the negative edge of the clock pulse at the clock input.When S is HIGH and R is LOW, the Q output goes HIGH on the triggering edge of the clock pulse, and the Flip-Flop is SET. When S is LOW and R is HIGH, the Q output goes LOW on the triggering edge of the clock pulse, and the Flip-Flop is RESET. When both $ and R are LOW, the output does not change from its prior state. An invalid condition exists when both S and R are HIGH.Taputs | Present tate | Nextstate LS esiaeeseer cra eee sce) Dp | ¥l2 g 2 | Nochange (NC) rm e to] t 8 Reset) curt 1 [0 ° 1 | i |e : sets) L : FS : * | indeterminate () | Reet) — P w | ale ¢ 2 | Nochange «so (a Trath able era | asa Naso State Present State | _NextState S[R[_ On = ee sae T [ofo| Q | NoChange WO) 7 : 71 t}of[o Reset ° i i|o tiipfer 1 Set 1 ° o | 1 1b x Indeterminate * a a a | (d) Characteristic table A characteristic equation ‘Exetation able the cimplifiod ||The excitation table vied 10 find the Flip-Flop input OF Ihe || conditions thet will couse the required transition, when the present state (Qn) and the next state (@n+1) are known. 47Tnputs | Present state | Newtstate 2 snp eens Ons = 0] 0 ° Bad " tléls t o | Nochange «N0) opt ° ° ees H 7 Reset ®) itis] 3 i sa) 1]a ° x t (813 y % | Tadeterminate () [22 : 8 | Nochange oC) Tah Tae Kmy ; RQa S\_00_01 1110 of o [MM] oo TTX 1X a (e) Characteristic equation Qui $+ R'Qu Electronic Hardware System Design 282 a e a Ay q s BOQ In D Flip-Flop, the basic SR Flip-Flop is used with complemented inputs. Q To eliminate the undesirable condition of the indeterminate state in the RS Flip-Flop is to ensure that inputs $ and R are never equal to 1 at the same time. This is done by D Flip-Flop. Q The D (delay or data) Flip-Flop has one input called delay input and clock pulse input. q (4) Using SR flipflop (b) Graphic symbol 30‘Truth fable For D Flip-Fi waveforms of clocked DQe 0 0 1 z D 0 1 0 1 0 Characteristic equation: Qaei= D. [Characteristic table Table 11.8. Excitation table of a D flip-op. Next state D ay) ° 1 ° 1Q JK means Jack Kilby, Texas Instrument (Tl) Engineer, who invented IC in 1958. Q._ JK flip-flop is built using only NAND gates. JK Flip-Flop has two inputs J(set) and K(reset).i x x fa nlo ola no ofp Qe 0 1 0 a 0 1 0 i 0 1pexpen ele ole olla x xia nloolmnlo ola ® mole ole ole of» of (c) Truth table State 1 0 0 (e) Characteristic equation Qui JO K'Qs36