Department of Electronics and Communication Engineering

Subject code : EC3352

Subject name : Digital System and Design
Regulation : 2021
Year & Sem : II & III

QUESTION BANK

UNIT- I DIGITAL FUNDAMENTALS

PART-A
1. State De Morgan's theorem. (or) State De Morgan's Law and write any one application.
(A/M 18, N/D 17, N/D 15, M/J 14, M/J 13, A/M 11)
De Morgan suggested two theorems that form important part of Boolean algebra. They are,
1) The complement of a product is equal to the sum of the complements.
(AB)' = A' + B'
2) The complement of a sum term is equal to the product of the complements. (A + B)' = A'B'
Application: useful in the implementation of the basic gate operations with alternative gates.
2. Sketch the waveform of each inverter output in the given diagram. (N/D 17)

3. What is meant by maxterm and true max term ? (A/M 18)

Each and Individual term in standard POS form is called as maxterm.

Maxterm (standard sum term) A sum (OR) of n Boolean variables, uncomplemented or
complemented but not repeated, in a Boolean function of n variables.

4. What is the basic priciple used in order to check or generate the proper parity bit in a
given code word? (A/M 18)

Parity bit is defined as the addition of extra bit in order to make as a odd or even parity for
detecting the errors in the codes.

5. Convert the given decimal numbers to their binary equivalent 108.364, 268.025
(A/M 17)
108.364 = 01101100 268.025 = 0000000100001100
6. Show how to connect NAND gate to get AND and OR gate? (A/M 17)

AND using NAND

OR using NAND

7. Simplify the following expression X.Y +X(Y+Z)+Y(Y+Z). (N/D 16)

X.Y +X(Y+Z)+Y(Y+Z) = XY+XY+XZ+Y+YZ

= X(Y+Z)+Y(1+YZ)

8. Why totem pole outputs cannot be connected together? (N/D 16)

Totem pole outputs cannot be connected together because such a connection might
produce excessive current and may result in damage to the devices

9. Prove that Boolean theorems. (M/J 16)

(a) x + x = x
= x+x
=x
(b) x+xy = x
= x(1+y)
=x

10. Define noise margin. (M/J 16)

Noise margin is the amount by which a signal exceeds the minimum amount for proper
operation. In a digital circuit, the noise margin is the amount by which the signal exceeds the
threshold for a proper '0' or '1'.

11. Express the function Y=A+B’C in a Cannonical POS. (N/D 15)

Y= A+B’C = A(B+B’)(C+C’ ) + B’C(A+A’ )
= ABC + ABC’+AB’C + AB’C’ + AB’C + A’B’C
= ABC + AB’C + ABC’ +AB’C’ + A’B’C

12. Convert Y = A+BC'+AB+A'BC

Y= A(B+B')(C+C')+ AB(C+C')+A'BC
= AB+AB'(C+C') + ABC+ABC'+A'BC
= ABC+ABC'+AB'C+AB'C'+ABC+ABC'+A'BC
=ABC+ABC'AB'C+AB'C'+A'BC
13. Simplify the following Boolean expression into one literal W’X(Z’+YZ)+X(W+Y’Z).
(N/D 14)
W’X(Z’ + Y’Z) + X(W + W’YZ) to 1 literals
= W’XZ’ + W’XY’Z + WX + W’XYZ
= WX + W’XZ’ + W’XZ = WX + W’X = X

14. Convert 0.35 to equivalent hexadecimal number. (N/D 14)

Decimal 0.35 = Hexadecimal 0.599

15. State distributive law. (N/D 13)

The distributive property states that AND ing several variables and OR ing the result with
a single variable is equivalent to OR ing the single variable with each of the the several variables
and then AND ing the sums. The distributive property is:
A+BC= (A+B) (A+C)
A.(B+C)= (A.B) + (A.C)

16. What is a prime implicant? (N/D 13)

A prime implicant is a product term obtained by combining the maximum possible
number of adjacent squares in the map.

17. What are called don’t care conditions? (M/J 13)

In some logic circuits certain input conditions never occur, therefore the corresponding
output never appears. In such cases the output level is not defined, it can be either high or low.
These output levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care
conditions or incompletely specified functions.

18. Simplify the given Boolean expression F=x’+xy+xz’+xy’z’. (N/D 12)

X’Y’ + Y’Z + XZ + XY + YZ’ = X’Y’ + XZ + YZ’
= X’ Y’ + Y’ Z(X + X’) + XZ + XY + Y Z’
= X’ Y’ + X Y’ Z + X’ Y’ Z + XZ + XY + Y Z’
= X’ Y’ (1 + Z) + X Y’ Z +XZ + XY + Y Z’
= X’ Y’ + XZ(1 + Y’) + XY + Y Z’
= X’ Y’ + XZ + XY (Z + Z’)+ Y Z’
= X’ Y’ + XZ + XY Z +Y Z’ (1 + X)
= X’ Y’ + XZ(1 + Y) + Y Z’ = X’ Y’ + XZ + Y Z’

19. Which gates are called as the universal gates? What are its advantages?
The NAND and NOR gates are called as the universal gates. These gates are used to
perform any type of logic application.
20. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from
input to output when the signals change in value. It is expressed in ns.
PART-B
[Link] the following expression : using tabulation method. (A/M 18)
f = ∑ m ( 0,1,2,8,9,15,17,21,24,25,27,31)
2. A stair case light is controlled by two switches, one is at the top of the stairs and other at the
bottom of the stairs : (A/M 18)
i) Make a truth table for the system
ii) Write the logic equation in the SOP form
iii) Realize the circuit using AOI logic
iv) Realize the circuit using minimum number of a) NAND Gates b) NOR Gates
3. i) Simplify the Boolean expression using laws and rules of Boolean algebra
Z = [ AB' (C+BD) + (AB')].C. (N/D 17)
ii) Define SOP and POS [Link] the Boolean expression
AB'C + B'CD+AC,D to SOP form.
4. i) Implement the Boolean expression using minimum number of 3 input NAND gate
f(A,B,C,D) = ∑ (1,2,3,4,7,89,10,12). (N/D 17)
5. (i) State and prove De morgan’s theorem (A/M 17)
(ii) Find a MinSOP and MinPOS for
F=b’c’d+acd’+a’b’c+a’bc’d.
6. (i) Find the MSOP representation for F(A,B,C,D,E) = m(1,4,6,10,20,22,24,26)+d(0,11,16,27)
using K-map method. Draw the circuit of the minimal expression using only NAND gates.
(ii) With neat circuit diagram, explain the function of 3-input TTL NAND gates. (N/D 16)
7. What are the advantages of using tabulation method? Determine the minimal sum of products
for the Boolean expression F = ∑ (1,2,3,7,8,9,10,11,14,15) using tabulation method. (N/D 16)
8. Simplify the following Boolean function by using Quine- Mccluskey method and verify the
result using K-map F( A, B, C , D ) = ∑ (0, 2, 3, 5, 7, 9, 11, 13, 14). (M/J 16)
9. (i) Draw and explain Tri-state TTL inverter circuit diagram with its operation. (N/D 12)
(ii) Implement the following function using NAND and inverter gates.
F = AB + A’B’ + B’C. (M/J 16)
10. (i) Minimize the following logic function using K-maps and realize using NAND and NOR
gates. F(A,B,C,D) = ∑ m(1,3,5,8,9,11,15)+d(2,13)
(ii) Show that if all the gate in a two-level OR-AND gate network are replaced by NOR gate,
the output function does not change. (N/D 14)
11. (i) Realize NOT, OR, AND gates using universal gates. (A/M15)
(ii) Discuss about the basic operation of TTL NAND gate. (N/D 14)
12. (i) Simplify T(x,y,z) = (x+y)[(x’(y’+z’))’]+x’y’+x’z’.
(ii) Simplify the following Boolean function and draw the logic diagram
f(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14). (A/M15)
13. Simplify the given Boolean function using tabulation method
F(A,B,C,D,E)=∑ m (0,1,4,5,16,17,21,25,29). (A/M15)
14. (i) Convert the following function into Product of Maxterms
F(A,B,C) = (A+B')(B+C)(A+C').
(ii) Using QuineMcClusky method, simplify the given function.
F(A,B,C,D)= ∑m(0,2,3,5,7,9,11,13,14). (N/D 14)
15. (i) Draw the multi level two input NAND circuit for the following expression:
F=(AB'+CD')E + BC(A+B).
(ii) Draw & explain Tri-state TTL inverter circuit diagram & explain its operation. (N/D 14)
16. (i) Given Y(A,B,C,D) = ∑ m(0,1,3,5,6,7,10,14,15) draw the K-map and obtain the simplified
expression. Realize the minimum expression using basic gates.
(ii) Implement the expression Y(A,B,C) = ∑ m(0,2,4,5,6) using only NOR-NOR logic.
(iii) Implement EXOR gate using only NAND gates. (M/J 14)
17. Simplify the following function using tabulation method
Y(A,B,C,D)= ∑ m (0,1,2,5,6,7,8,9,10,14) and implement using only NAND gates. (M/J 14)
18. (i) Simplify xy+x’z+yz.
(ii) Simplify the following expression using K-map method.
Y= ∑ m(7,9,10,11,12,13,14,15). (N/D 13)
19. (i) Write short notes on don’t care conditions.
(ii) Explain about NAND and NOR implementations. (N/D 13)
20. Minimize the given switching function using Quine-Mccluskey method.
F(x1,x2,x3,x4) = ∑(0,5,7,8,9,10,11,14,15). (M/J 13)

UNIT - II COMBINATIONAL CIRCUIT DESIGN

PART-A

[Link] the logic diagram of 4bit parallel subtractor. (A/M 18)

2. Draw the full adder circuit using half adder. (N/D 17)

3. Write the function of magnitude comparator. (N/D 17)

Magnitude comparator is a hardware electronic device that takes two numbers as input in
binary form and determines whether one number is greater than, less than or equal to the other
number.

4. Draw the truth table and the logic circuit of half adder. (A/M17)

5. Compare the function of decoder and encoder. (A/M17)

Encoder: An encoder is a digital circuit that performs the inverse operation of a decoder.
An encoder has 2n input lines and n output lines.
Decoder: A decoder is a multiple-input, multiple-output logic circuit which converts
coded inputs into coded outputs, where the input and output codes are different.
6. Write about the design procedure for combinational circuits. (N/D 16, M/J 16)
 The problem definition
 Determine the number of available input variables & required O/P variables. Assigning
letter symbols to I/O variables
 Obtain simplified Boolean expression for each O/P.
 Obtain the logic diagram.

7. Draw the logic diagram and truth table of full adder. (N/D 16)

Logic diagram and truth table of full adder.

8. Draw the combinational circuit that converts 2 coded inputs into 4 coded outputs. (M/J
16)

9. Define Half adder and full adder. (N/D 15, M/J 13)
The logic circuit that performs the addition of two bits is a half adder. The circuit that
performs the addition of three bits is a full adder.

10. What is priority Encoder? (N/D 15, M/J 14)

A priority encoder is an encoder circuit that includes the priority function. In
priorityencoder, if 2 or more inputs are equal to 1 at the same time, the input having the
highestpriority will take precedence.
11. Draw the logic circuit of 2 bit comparator using logic gates. (A/M 15, M/J 14)

12. Write down the difference between demultiplexer and decoder.(A/M 15)
A demux simply selects an output line, nothing more. It's a glorified switch. A decoder takes
n inputs, and uses those inputs to determine which of the 2^n output lines is high.

13. Give the logic expression for the sum and carry in full adder circuit. (A/M 15)
1. Sum = A + B + Cin
2. Carry=BCin + ACin + AB

14. Give examples for combinational circuits. (A/M 15, N/D 13)
Half Adder, Full adder, Multiplexer, Demultiplexer, encoder, decoder.

15. Construct 4- bit parallel adder/subtractor using full adders and XOR gates. (N/D 14)

16. List out various applications of Multiplexer. (N/D 13)

[Link] routing
[Link] to serial convertion
[Link] Sequence
[Link] function generation.
17. Design a single bit magnitude comparator to compare two words A and B.(A/M 11)

18. Write the logic expression for the difference and borrow of a half subtractor.(A/M 11)
Difference= AB'+A'B
Borrow=A'B

19. Define encoder and Decoder?

 A decoder is a multiple - input multiple output logic circuit that converts codedinputs into
coded outputs where the input and output codes are different.
 An encoder has 2n input lines and n output lines. In encoder the output lines generate the
binary code corresponding to the input value.

20. Define multiplexer.

Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.

PART-B

1. Implement the following Boolean function using an 8:1 Multiplexer considering D as the input
and A,B,C as selection lines : F (A, B,C,D) = AB'+BD+B'CD' (A/M 18)
2. With a neat diagram explain in detail about the working of a 4 bit look ahead carry adder. Also
mention its advantage over conventional adder. (A/M 18)
3. Design a 4 bit BCD Adder using full adder and explain its structure and compute the circuit to
add 1001 and 0101. Write the sum and carry output of the given binary number. (N/D 17)
4. Explain the operation and need of priority encoder. (N/D 17)
5. Design a 5x32 decoder using 3x8 decoder and summerize how many decoders required
designing. (N/D 17)
6. Implement Y = (A+C) (A+D’) (A+B+C’) using NOR gates only. (A/M 17)
7. (i) Why does a good logic designer minimize the use of NOT gates?
(ii) Show that if all the gates in a two level AND-OR gate networks are replaced by NAND
gates the output function does not change. (A/M 17)
8. (i) Design and explain 1 of 8 demultiplexer.
(ii) What is parity checker? (N/D 16)
9. Describe the operation of 3-bit magnitude comparator. (N/D 16)
10. (i) Design a 4-bit magnitude comparator with 3 outputs : A>B, A=B, A<B.
(ii) Design a 4 bit binary to gray code converter. (M/J 16)
11. (i) Implement the following Boolean functions using 8x1 Multiplexers
F(A,B,C,D) = ∑m(1,3,4,11,12,13,14,15) (M/J 16, A/M 11)
(ii) Explain the concept of carry look ahead adder with neat logic diagram. (M/J 16)
12. Explain with neat diagram the function of Binary multiplier
(i) using shift method
(ii) parallel multiplier. (N/D 15)
[Link] a BCD to excess 3 code converter using minimum number of NAND gates. (N/D 15)
14. Design a combinational circuit that converts a 4 bit Gray code to a 4 bit binary number.
(A/M 15)
15. Detail the following (i) BCD adder (A/M 15, N/D 12, A/M 11)
(ii) Magnitude comparator. (A/M 15)
16. (i) Design a 4 bit decimal adder using 4-bit binary adders.
(ii) Implement the following Boolean functions using Multiplexers
F(A,B,C,D) = ∑m(0,1,3,4,8,9,15). (N/D 14)
17. (i) Design a 4-bit magnitude comparator with three outputs: A>B, A=B and A<B.
(ii) Construct a 4 bit even parity generator circuit using gate. (N/D 14)
18. (i) Design 3:8 decoder using basic gates
(ii) Design a binary to gray code convertor. (M/J 14)
19. (i) Design a full subtractor using demultiplexer
(ii) Explain the working of carry-look ahead adder. (M/J 14)
20. Draw the logic diagram of BCD-decimal decoder and explain its operations. (N/D 13)
21. Draw the block schematic of magnitude comparator and explain its operations. (N/D 13)

UNIT -III SYNCHRONOUS SEQUENTIAL CIRCUITS

PART-A

1. Bring out the difference between synchronous & asynchronous sequential circuits (or)
Give the comparison between synchronous & asynchronous sequential circuits? (A/M 18,
M/J 16)

Synchronous circuits Asynchronous circuits

Memory elements are clocked flip-flops Memory elements are either unlocked flip -
flops or time delay elements.
Easier to design More difficult to design

2. A binary ripple counter is required to count upto 16,[Link] many flip-flops are
required? If the clock frequency is 8.192MHz, what is the frequency at the ouput of
MSB? (A/M 18)

16,38310 = 0b11111111111111
0000000000000000
By comparing there are 15 changes the output value is 15.
Clock frequency = 8.192 MHZ = 8192KHZ
Frequency at output of MSB = 8192/512 = 16KHZ
3. Draw the NOR gate latch and write its truth table. (N/D 17)

4. Write the difference between synchronous & Asynchronous counters. (N/D 17, N/D 14,
M/J 14)
Synchronous counter Asynchronous counter
In this type there is no connection between In this type of counter flip-flops are
output of first flip-flop and clock input of connected in such a way that output of
the next flip – flop. 1stflip-flop drives the clock for the next
flipflop.
All the flip-flops are clocked All the flip-flops are Not clocked
simultaneously. Simultaneously

5. State the difference between Mealy and Moore model sequential circuits. (N/D 17)
Mealy model Moore model
Its output is a function of present state Its output is a function of present state as
only. well as present input.
An input change does not affect the Input changes may affect the output of the
output. circuit.
Mealy model requires more number of It requires less number of states for
states for implementing same function. implementing same function.

6. Derive the characteristic equation of a D flip flop. (A/M17)

The characteristic equation for D flip-flop is Qn+1 = D. The output Qn+1 is delayed by one
clock period. Thus D flip-flop is also known as delay flip-flop.

7. What is the primary disadvantage of asynchronous counter? (A/M17)

 An extra “re-synchronizing” output flip-flop may be required.
 To count a truncated sequence not equal to 2n, extra feedback logic is required.
 Counting a large number of bits, propagation delay by successive stages may become
undesirably large.
 This delay gives them the nickname of “Propagation Counters”.
 Counting errors occur at high clocking frequencies.
 Synchronous Counters are faster and more reliable as they use the same clock signal for
all flip-flops.
8. Define race around condition in flipflop? (N/D 16)
In the JK latch, the output is feedback to the input, and therefore changes in the output results
change in the input. Due to this in the positive half of the clock pulse if J and K are both high
then output toggles continuously. This condition is known as race around condition.

9. Draw D-latch (Transparent latch) with truth table. (N/D 16, M/J 16)

10. What are the classifications of sequential circuits? (N/D 15)

The sequential circuits are classified on the basis of timing of their signals into two
types. They are, 1) Synchronous sequential circuit.
2) Asynchronous sequential circuit.

11. What is edge-triggered flip-flop? (N/D 15)

The problem of race around condition can solved by edge triggering flip flop. The term
edge triggering means that the flip-flop changes state either at the positive edge or negative edge
of the clock pulse and it is sensitive to its inputs only at this transition of the clock.

[Link] the truth table of RS flip-flop.(A/M 15)

13. What is the minimum no of flipflop needed to design a counter of modulus 60?(A/M 15)
2^(n-1)<= N <= 2^n
for 60, 2^6 = 64
So we need 6 flipflops

14. Define Latches. (N/D 13)

 It is a memory cell which is capable of storing one bit of information either logic 1 or
logic 0.
 This sequential circuit also called a latch since one bit of information can be latched.

15. Define Digital clock. (N/D 13)

A digital clock is a type of clock that displays the time digitally (i.e. in numerals or other
symbols), as opposed to an analog clock, where the time is indicated by the positions of rotating
hands.
16. Convert D flipflop toT flipflop. (M/J 13, N/D 12)

17. Design a 3-bit ring counter and find the mod of the designed counter. (N/D 12)

18. Write the characteristic equation of a JK flipflop. (A/M 11)

Q(n+1) = J Qn'+ K'Qn

19. What is meant by flip-flop and types?

Latch with the additional control input is called as flipflop. The additional control input is
either clock or enable input.
Types:
 SR flipflop
 JK flipflop
 D flipflop
 T flipflop

20. Define registers.

A register is a group of flip-flops flip-flop can store one bit information. So an n-bit
register has a group of n flip-flops and is capable of storing any binary information/number
containing n-bits.
 PART-B

1. Explain in detail about the ring counter with its logic diagram, state diagram and its sequence
table. (A/M 18)
2. Discuss in detail about pulse triggered SR flipflop also draw the ouput waveform of this
flipflop and explain it with an example. (A/M 18)
3. Design a JK counter that goes through states 3,4,6,7 and 3. Is the counter self starting? Modify
the circuit such that whenever it goes to an invalid state it comebacks to state 3. (A/M 18)
4. A clocked sequential circuit with single input and output x and z respectively, produces an
output z = 1, whenever the input x completes the sequence 1011 and overlapping is allowed:
i) Obtain the state diagram
ii) Obtain its minimum state table and design the ciruit with D fliplflops. (A/M 18)
5. Draw RS flipflop circuit and explain its operation with truth table and suggest how to
eliminate the undetermined stage. Write some RS flipflop applications. (N/D 17)
6. Discuss the design steps of Asynchronous sequential circuits. (N/D 17)
7. Design a 2's complement circuit with shift register and [Link] binary number is shifted
out from one side and its 2'complement shifted into other side of the shift register. (N/D 17)
8. Design and explain the working of a synchronous mod-3 counter. (A/M 17)
Using SR flipflops design a parallel counter which counts in the sequence 000, 111, 101, 110,
010, 000 (A/M 17)
9. (i) Explain the operation of JK flip-flop with neat diagram.
(ii) Explain the operation of serial-in-serial-out shift register. (N/D 16)
10. Design synchronous MOD-6 counter. (N/D 16)
11. Design a 3 bit synchronous counter using D flipflop. (M/J 16, N/D 14)
12. (i) Draw and explain the 4-bit SISO, SIPO, PISO and PIPO shift register with its waveforms.
(ii) Realize D flip-flop using SR flip-flop. (M/J 16)
13. (i) Explain the operation of JK flip-flop with neat diagram. (N/D 15, A/M 15)
(ii) Explain the operation of master slave flip flop and show how the race around condition is
eliminated. (N/D 15)
14. Explain the operation of synchronous MOD 6 counter. (N/D 15)
15. With a neat sketch describe a 3 bit synchronous up/down counter. Draw the timing
waveform. (A/M 15,N/D 13)
16. Design a sequential circuit with two D FFs A and B and one input x. When x = 0, the state of
the circuit remains the same. When x=1, the circuit gas through the state transitions from 00-
01-11-10-00-01. (A/M 15)
17. Explain the differences between a state table, a characteristics table and an excitation table.
(N/D 14)
18. Design the sequential circuit specified by the following state diagram using T flip flops.
Check whether your design is self correctable. (N/D 14)
19. Design a sequential circuit that has 3 flip flops A,B and C, one input x and one output y. The
circuit is to be designed by treating the unused states as don’t care conditions. Use JK
flipflops in the design. (M/J 14)
20. Design a moore type sequence detector to detect a serial input sequence of 101. (M/J 14)
21. (i) Draw the block diagram of SR-FF and explain.
(ii) Explain about triggering of flip-flops. (N/D13)
 UNIT-IV ASYNCHRONOUS SEQUENTIAL CIRCUITS
PART A
1. What is memory expansion and why is it required? (A/M 18)
Expanded memory, is a technique for utilizing more than 1MB of main memory in DOS -based
computers. The limit of 1MB is built into the DOS operating system. The upper 384K is reserved for
special purposes, leaving just 640K of conventional memory for programs.

2. A certain memory has a capacity of 32K x [Link] many bits are there in each word?
How many words are being stored and how many memory cells does this memory contain?
(A/M 18)

1 byte = 8 bits, 1 word = 32 bits,

Total bits = 32Kx16 = 512000 bits
640000 words are stored.
3. Distinguish between a flowchart and an ASM chart. (A/M 18, A/M 15, M/J 13)

Flowchart ASM chart

A flowchart is a convenient way to A special flowchart that has been
specify the sequence of procedural steps developed specifically to define digital
and decision paths for an algorithm. hardware algorithms is called ASM chart.
A conventional flow chart describes the An ASM chart describes the sequence of
sequence of procedural steps and as well as the timing relationship
decision paths for an algorithm without between the states of a sequential
concern for their time relationship controller and the events that occur while
going from one state to next.

4. What are Hazards and give it types? (A/M 18, N/D 17, N/D 16, A/M 16, N/D 13, A/M 13)
The unwanted switching transients (glitches) that may appear at the output of a circuit is
called Hazards.
Types are [Link] Hazard
Static 1 Hazard
Static 0 Hazard
2. Dynamic Hazard
5. What is the memory capacity of random access memory if it has 10 bit address lines.
(N/D 17)
We have 2^10 words, each 16 bits wide.
1B is 8 bits (as usual).
2 ^ 10 x 2 = 2 ^ 11 bytes
= 2048 bytes
6. What are the steps for the analysis of asynchronous sequential circuit? (A/M 17)
The procedure to analyze is as follows:
 Determine the next secondary state and output equations from given sequential circuit.
 Construct the state table.
 Construct the transition table.
 Construct output map.
7. What is the significance of state assignment? (A/M 17)
 In synchronous circuits-state assignments are made with the objective of circuit reduction
 Asynchronous circuits-its objective is to avoid critical races
8. Define critical race and non critical race. (N/D 16, 14)
 If the final stable state depends on the order in which the state variable changes,
the race condition is harmful and it is called a critical race.
 If the final stable state that the circuit reaches does not depend on the order in
which the state variable changes, the race condition is not harmful and it is called
a non critical race.

9. Define critical race and give their different methods of critical race free state assignment.
(A/M 16)
If the final stable state depends on the order in which the state variable changes, the race
condition is harmful and it is called a critical race.
There are 2 methods
1. Shared row state assignment [Link] hot state assignment

10. Draw the general model of ASM. (N/D 15)

11. What is static 1 hazard and static 0 hazard? (N/D 15)

The unwanted switching transients (glitches) that may appear at the output of a circuit is
called Hazards.
 output goes momentarily 0 when it should remain at 1
 output goes momentarily 1 when it should remain at 0

12. Distinguish between a combinational logic circuit and a sequential logic circuit. (A/M
15)
Combinational logic Sequential logic
Combinational logic (sometimes also Sequential logic is a type of logic
referred to as time-independent logic ) is circuit whose output depends not only on
a type of digital logic which is the present value of its input signals but
implemented by Boolean circuits, where on the sequence of past inputs.
the output is a pure function of the
present input only
 13. What is the most important consideration in making state assignments for synchronous
network ? (A/M 15)
State Reduction & Assignment. Sometimes certain properties of sequential circuits may
be used to reduce the number of gates and flip-flops during the design. Sometimes certain
properties of sequential circuits may be used to reduce the number of gates and flip-flops during
the design.

14. Define ASM chart. List of its three basic elements. (N/D 14)
A special flowchart that has been developed specifically to define digital hardware
algorithms is called ASM chart. Three basic elements are,
 State Box
 Decision box
 Conditional box

15. What is critical race condition in asynchronous sequential circuit? (N/D 14)
If the final stable state depends on the order in which the state variable changes, the race
condition is harmful and it is called a critical race.

16. What is state diagram? Give an example. (A/M 14)

In addition to graphical symbols, tables or equations, flip-flops can also be represented
graphically by a state diagram. In this diagram, a state is represented by a circle, and the
transition between states is indicated by directed lines (or arcs) connecting the circles. An
example of a state diagram is shown in Figure 3 below.

17 Write the VHDL code for half adder. (A/M 14)

ENTITY half_adder is Half Adder

PORT(a,b:IN BIT; s,c :OUT BIT);
ND half_adder;
ARCHITECTURE half_adder_beh OF half_adder IS
BEGIN
s <= a XOR b; -- Implements Sum for Half Adder
c <= a AND b; -- Implements Carry for Half Adder
END half_adder_beh;
18. What is synchronous sequential circuits? (N/D 13)
 A Synchronous Sequential circuit is a circuit in which flip-flops are tied to a common
clock.
 Memory elements are clocked flip-flops
 Easier to design
 Shift registers and counters are two examples.

19. Differentiate fundamental mode and pulse mode asynchronous sequential circuits? (N/D
12)

Fundamental mode Pulse mode

Input variables changes if the circuit is
Inputs are pulses width of pulses are long
stable inputs are levels, not pulses only
for circuit to respond to the input pulse
one input can change at a given time.
width must not be so long that it is still
present after the new state is reached.
Delay lines are used as memory Pulses should not occur simultaneously on
elements. two or more input lines.

20. Design a 3 input AND gate using verilog. (N/D 12)

Module AND_3 (A,B,C,Y);

Input A, B, C;
Output Y;
Assign Y = A&B&C;
End module
21. What are the basic building blocks of a algorithmic state machine chart? (A/M 11)
The basic building blocks of algorithmic state machine chart are:
 State Box
 Decision box
 Conditional box
22. What are the two types of asynchronous circuits? (A/M 11)
 1. Fundamental mode circuits
 2. Pulse mode circuits
23. Define state table.
For the design of sequential counters we have to relate present states and next states. The
table, which represents the relationship between present states and next states, is called state
table.
24. Under what circumstances asynchronous circuits are preferred?
Asynchronous circuits can operate faster than synchronous circuits and hence they are
preferred when speed is an important criteria.
 PART-B

1. (i) Summarize the design procedure for asynchronous sequential circuit.

(ii) Derive the state table of a serial binary adder. (A/M 17)
2. What is the objective of state assignment in asynchronous circuit? Give the hazard free
realization for the Boolean function f(A, B, C, D) = M(0, 2, 6, 7, 8, 10, 12) (A/M 17)
3. Explain the steps involved in the design of asynchronous sequential circuit. (N/D 16)
4. Design an asynchronous circuit that will output only the second pulse received and ignore any
other pulse. (N/D 16)
5. Design an asynchronous sequential circuit with two inputs X1 and X2 and with one output Z.
When X1 is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The
output Z will remain 1 until X1 returns to 0. (A/M 16)
6. Construct the transition table, state table and state diagram for the more sequential circuit.
(A/M 16)
7. Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1
when T=1 and c moves from 1 to 0. Otherwise the output is 0. (N/D 15)
8. Explain the different methods of race free state assignment. (N/D 15)
9. (i) Write the verilog code for full adder and JK FF. (A/M 15)
(ii) Explain the different types of hazards. Design a hazard free circuit for y = x1x2+x2’x3.
10. With ASM chart design a binary multiplier. (A/M 15)
11. (i) What is a hazard in an asynchronous sequential circuits? Define static hazard, dynamic
hazard and essential hazard. (N/D 14, N/D 12)
(ii) Write and verify the HDL structural description of the four-bit register with parallel load.
Use a 2x1 multiplexer for the flip-flop inputs. Include an asynchronous clear input.
(N/D 14)
12. Design an asynchronous sequential circuit with inputs A and B and an output Y. Initially and
at any time if both the inputs are 0, the output, Y is equal to 0. When A or B becomes 1, Y
becomes 1. When the other input also becomes 1, Y becomes 0. The output stays at 0 until
circuit goes back to initial state. (N/D 14)
13. Design a T flip-flop using logic gates. Derive the state table, state diagram, primitive flow
table and transition table and merger graph. Draw the logic circuit. (A/M 14)
14. Design a asynchronous sequential circuit that has 2 inputs x1 and x2 and one output z. When
x1 = 0, output is 0. The change in x2 that occurs while x1 is 1 will cause output z=1. The output z
will remain 1 until x1 returns to 0. (A/M 14)
15. Design a serial binary adder using delay flip-flop. (N/D 13)
16. List out various problems arises in synchronous circuits. Explain any two problems in detail.
(N/D 13)
17. Design a hazard free asynchronous circuit that changes state whenever the input goes logic 1
to logic 0. (A/M 13)
 UNIT-V MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS
PART-A
1. Write the types of programmable logic devices. (N/D 17, M/J 16)
 Programmable Logic Array (PLA)
 Programmable Array Logic (PAL)
 Generic Logic Array (GLA)
 Complex Programmable Logic Device (CPLD)
 Field Programmable Gate Array (FPGA)

2. How does ROM retain information? (A/M 17)

ROM is used to store the binary code for the sequence of instructions that the computer to
carry out and data such as look up tables. This is because this type of information does not
change.

3. Differentiate between PAL and PLA. (A/M 17, M/J 13, A/M 11)

[Link] PLA PAL

1. Both AND and OR arrays are OR array is fixed and AND
programmable. array is programmable.
2. Costliest and complex than PAL Cheaper and simpler.
and PROMs.
3. AND array can be programmed AND array can be
to get desired minterms. programmed to get desired
minterms.
4. Any Boolean functions in SOP Any Boolean functions in SOP
form can be implemented using form can be implemented
PLA. using PLA.

4. Briefly explain EEPROM. (N/D 16)

EEPROM(Electrically Erasable Programmable Read Only Memory) EEPROM also use
MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated
floating gate in the device. EEPROM allows selective erasing at the register level rather than
erasing all the information since the information can be changed by using electrical signals.
5. What is programmable logic array? How it differs from ROM? (N/D 16, N/D 15)
A programmable logic array (PLA) is a kind of programmable logic device used to
implement combinational logic circuits. ... It has 2^N AND Gates for N input variables and for
M outputs from PLA, there should be M OR Gates, each with programmableinputs from all of
the AND gates.

6. How Bipolar RAM cell is differ from MOSFET RAM cell. (M/J 16)
In Bipolar RAM cell the memory cell is implemented by TTL. It stores 1 bit of
information. It is nothing but a flipflop.
In MOSFET RAM cell enhancement mode MOSFET transistors are used to make this
RAM cell. It is very similar to TTL cell.

8. What is Read and Write operation? (N/D 15)

 The Write operation stores data into a specified address into the memory and the
 Read operation takes data out of a specified address in the memory.
9. What is the basic difference between the RAM & ROM circuitry ? (A/M 15)

6. Compare static and dynamic RAM cell. (A/M 15)

[Link] SRAM DRAM

1. Stores data till the power is Stores data only for few
supplied. milliseconds even when power is
supplied.
2. Uses an array of 6 transistors for Uses a single transistor and
each memory cell capacitor for each memory cell.
3. Does not refreshes the memory Needs to refresh the memory cell
cell after each reading of the
capacitor.
4. Data access is faster Data access is slower

7. Y=AB'+AB Implement using ROM.

8. Compare and contrast EEPROM and flash memory. (N/D 14)

EEPROM Flash memory

EEPROM(Electrically Erasable They are high density read/write
Programmable Read Only Memory) memories that are non-volatile, which
EEPROM also use MOS circuitry. Data means datacan be stored indefinitely
is stored as charge or no charge on an with out power.
insulated layer or an insulated floating
gate in the device. EEPROM allows The traditional memory technologies
selective erasing at the register level such as ROM, PROM, EEPROM
rather than erasing all the information individually exhibits one of these
since the information can be changed by characteristics, but no single
using electrical signals. technology has all of them except the
flash memory.
9. What is field programmable logic array? (N/D 14)
The second type of PLA is called a field programmable logic array. The user by means of
certain recommended procedures can program the PLA.

10. List the advantages of PLDs. (M/J 14)

 Lower Power Requirements
 Less Costly Assembly Processes
 Higher Reliability
 Availability Of Design Software
 Less Board Space, Faster

11. Draw the structure of a static RAM cell. (M/J 14)

12. What is volatile and Non volatile memory? (N/D 13)

Volatile memory Non volatile memory

Any type of memory requires some The contents of memory is not lost even
power to store the binary information. when the power is removed from the
All information’s are lost when the memory.
power is removed.

13. List the advantages of RAM. (N/D 13)

 Fast access of data.
 High Ram capacity increase the speed of the system
 It helps fast start up and shut down of the computer.
 It is a volatile memory of the system.

14. What are the different types of programmable logic devices? (M/J 13)
1. Read only memory
2. Programmable logic Array
3. Programmable Array Logic

15. Draw the logic diagram of SRAM and BRAM cell. (N/D 12)

BRAM SRAM
16. How the memories are classified? (N/D 12)
Memories are classified into
 Volatile memory
 Non-volatile memory

17. Implement the Exclusive Or Function Using ROM. (A/M 11)

18. Define Static RAM and dynamic RAM.

 Static RAM use flip flops as storage elements and therefore store data indefinitely as long
as dc power is applied.
 Dynamic RAMs use capacitors as storage elements and cannot retain data very long
without capacitors being recharged by a process called refreshing.

19. What are the types of ROM?

[Link]
[Link]
[Link]

20. Define bit, byte and word.

The smallest unit of binary data is bit. Data are handled in a 8 bit unit called byte. A
complete unit of information is called a word which consists of one or more bytes.

21. Why RAMs are called as Volatile?

RAMs are called as Volatile memories because RAMs lose stored data when the power is
turned OFF.

22. Define Cache memory.

It is a relatively small, high-speed memory that can store the most recently used
instructions or data from larger but slower main memory.

23. Define address of a memory and Capacity of a memory.

 The location of a unit of data in a memory is called address.
 It is the total number of data units that can be stored.
 PART-B

1. Write the program table to implement a BCD to excess 3 code conversion using a PLA.
(A/M 18)
2. Explain in detail about the working of bipolar SRAM cell and single transistor DRAM cell
with neat sketches. (A/M 18)
3. Explain the TTL circuit with open collector output. (N/D 17)

4. (i) Compare static RAM and Dynamic Ram (A/M 17)

(ii) Implement the switching functions
z1 = ab’d’e + a’b’c’e’+ bc+de
z2 = a’c’e
z3 = bc+de+c’d’e’+bd and z4 = a’c’e+ce using a 5*8*4 PLA.
5. (i) Distinguish between Boolean addition and binary addition.
(ii) Design a combinational circuit using a ROM that accepts a 3 bit number and generates an
output binary number equal to the square of the given number. (A/M 17)
6. Differentiate static and dynamic RAM. Draw the circuits of one cell of each and explain its
working principle. (N/D 16, N/D 15)
7. Write short notes on (i) PAL (ii) FPGA. (N/D 16, M/J 16, N/D 15, N/D 13)
8. Implement the following function using PLA.
F1(x,y,z) = ∑m(1,2,4,6)
F2(x,y,z) = ∑m(0,1,6,7)
F3(x,y,z) = ∑m(2,6) (M/J 16)
9. (i) Explain memory READ and WRITE operation with neat timing diagram.
(ii) Explain the organization of ROM with relevant diagrams. (M/J 16, A/M 15, M/J 14)
10. Give an account for classification of memories. (A/M 15, N/D 13)
11. Explain the structure of PAL and PLA. How a combinational logic function is implemented
in PAL and PLA? Explain with an example for each. (A/M 15)
12. (i) Write short notes on EAPROM and static RAM cell using MOSFET.
(ii) Using eight 64x8 ROM chips with an enable input and a decoder, construct a 512 x 8
ROM. (N/D 14)
13. (i) Implement a 3 bit up/down counter using PAL devices.
(ii) Implement binary to Gray code converter using PROM devices. (N/D 12)