Computer Architecture.

2nd year, Bachelor's Degree in Computer Engineering

Memory Management

1.- (5.3 Patterson 2011) The following table shows a list of 32-bit memory address references:
a.- 1, 134, 212, 1, 135, 213, 162, 161, 2, 44, 41, 221
b.- 6, 214, 175, 214, 6, 84, 65, 174, 64, 105, 85, 215

1.1. Given a direct-mapped cache with 16 blocks of a single word, indicate for each
one of the references, the binary address, the tag, and the index. Also indicate whether it is a fault or a
Correct, assuming that the cache is initially empty.

Solution:

Label block Word

1 0000 0000 0000 0000 0000 0000 0000 0001 --
134 0000 0000 0000 0000 0000 0000 1000 0110 --
212 0000 0000 0000 0000 0000 0000 1101 0100 --
1 0000 0000 0000 0000 0000 0000 0000 0001 -- Hit
135 0000 0000 0000 0000 0000 0000 1000 0111 --
…….

1.2. Given a direct-mapped cache with 8 blocks of 2 words, indicate for each of the
references, the binary address, the label, and the index. Also indicate if it is a failure or a success,
assuming that the cache is initially empty.
 Label block Word

1 0000 0000 0000 0000 0000 0000 0000 000 1

134 0000 0000 0000 0000 0000 0000 1000 011 0 HIT
212 0000 0000 0000 0000 0000 0000 1101 010 0
1 0000 0000 0000 0000 0000 0000 0000 000 1
135 0000 0000 0000 0000 0000 0000 1000 011 1 HIT

1.3. Be a direct mapping cache with a capacity of 8 words with a main memory
addressed with 32 bits. Optimize your design for the previous references. Consider three possible
cache designs: C1 with one-word blocks, C2 with two-word blocks, and C3 with blocks
of 4 words. Which one is the best in terms of failure frequency? If the failure stop is 25
C1 has an access time of 2 cycles, C2 of 3 cycles, and C3 of 5 cycles. Which is the best?
design?
___________________________________________________________________
with blocks of one word
Label block Word

1 0000 0000 0000 0000 0000 0000 0000 0 001 --

134 0000 0000 0000 0000 0000 0000 1000 0 110 --
212 0000 0000 0000 0000 0000 0000 1101 0 100 --
1 0000 0000 0000 0000 0000 0000 0000 0 001 -- Hit
135 0000 0000 0000 0000 0000 0000 1000 0 111 --
…….
 ___________________________________________________________________
C2: with blocks of 2 words cache with 4 blocks

Label block Word

1 0000 0000 0000 0000 0000 0000 0000 0 00 1

134 0000 0000 0000 0000 0000 0000 1000 0 11 0
212 0000 0000 0000 0000 0000 0000 1101 0 10 0
1 0000 0000 0000 0000 0000 0000 0000 0 00 1-- Hit
135 0000 0000 0000 0000 0000 0000 1000 0 11 1-- Hit
…….

C3: with blocks of 4 words cache with 2 blocks

Label block Word

1 0000 0000 0000 0000 0000 0000 0000 0 0 01

134 0000 0000 0000 0000 0000 0000 1000 0 1 10
212 0000 0000 0000 0000 0000 0000 1101 0 1
1 0000 0000 0000 0000 0000 0000 0000 0 0 Hit
135 0000 0000 0000 0000 0000 0000 1000 0 1 11
…….

a)
Miss hit
penalization
C1 25 cycles 2 cycles
C2 25 cycles 3 cycles
C4 25 cycles 5 cycles

C1: 1 hit time memory=25*11+2*12=299

C2: 3 hits time memory=25*9 +3*12=261
C4: 2 hits time memory=25*10+4*12=298

1.4. Given the following parameters for different direct-mapped caches:

Cache Size Block size (initial design) Cache access time
a. 64KB 1 word 1 cycle
b. 64KB 2 words 2 cycles
Calculate the total number of bits in the cache assuming 32-bit addresses.
Given this total size, determine the size closest to the given size of the cache of
direct correspondence with blocks of 16 words, with this size being equal to or greater than the given.
Explain why the second cache may provide worse performance.

a) Cache size = blocks * (block size + tag size + validity size)

In this case, 64KB = 2144 bytes/word = cache size = 219bits=29Kbits=512 Kbits
If 2 is defined14blocks of a word (initial design) in cache then not available
space to store information, labels, and validity bits

If blocks of 16 words are defined 1K 10 bits address blocks

Labels of 32-10-4-2=16 bits cache size (bits) = 210* (24* 32+16+1)=529Kbits

2. (5.4 Patterson 2011) In a direct-mapped cache with 32-bit addresses, the bits of the
Address is used as indicated in the table:
Label Index Displacement
a. 31-10 9-4 3-0
b. 31-12 11-5 4-0
2.1 What size, in words, does the cache line have?
a. 4 words of 32 bits where bytes can be addressed
b. 8 words of 32 bits where bytes can be addressed
2.2 How many entries does the cache have?
64 cache lines, or blocks
b. 128 cache lines, or blocks

2.3 What is the relationship between the total number of bits in the cache and the number of storage bits?

Cache size = 26* (22* 32+12+1)=8.8Kbits

Data 4*32=128 bits

Labels+control=13 bits

Data/cache ratio=128/141=0.907
90.7% of the cache stores data, while the other 9.3% stores tags and control.

2.4 Given the following access sequence expressed as byte addresses

0, 4, 16, 132, 232, 160,1024, 30, 140, 3100, 180, 2180
Determine the hits and misses in cache accesses.
Label Index Displacement
31-10 9-4 3-0
0 0000 0000 0000 0000 0000 00 00 0000 0000
4 0000 0000 0000 0000 0000 00 00 0000 0100 Hit
16 0000 0000 0000 0000 0000 00 00 0001 0000
132 0000 0000 0000 0000 0000 00 00 1000 0100
232 0000 0000 0000 0000 0000 00 00 1110 1000
160 0000 0000 0000 0000 0000 00 00 1010 0000
1024 0000 0000 0000 0000 0000 01 00 0000 0000 <= Replace block
30 0000 0000 0000 0000 0000 00 00 0001 1110 Hit
140 0000 0000 0000 0000 0000 00 00 1000 1100 Hit
3100 0000 0000 0000 0000 0000 11 00 0001 1100 <= Replace block
180 0000 0000 0000 0000 0000 00 00 1011 0100
2080 0000 0000 0000 0000 0000 10 00 0010 0000

2.5 Accuracy rate = 0.25

3. Let it be a set associative cache with a total of 64 partitions (or blocks); 4 partitions per
set. If the main memory contains 4K blocks of 128 words each, indicate how many bits, of a
main memory address would be used for the tag field. (This architecture is not MIPS)
Solution:

MP address tamaño MP = 2221027words 19 bits address MP

Cache: sets=64/4= 16 sets addressed with 4 bits

Words within the block=128 7 bits address a word in the block
Label set word
00010001 1010 0001111
So: Label=19-4-7=8 bits

4. It is a cache memory that stores 2048 words organized in 2 sets of blocks of 4 words. If
the main memory has a size of 128K x 32 bits. Indicate how the cache information is stored, and
What is the total size of the cache.

Solution:
In MC 2048 words / 4 words/block = 29bloques = 211words in MC

17 bits address MP, 14 tag field, 1 set field bit, and 2 word field bits

Label Set Word

14 bits 1 bit 2 bits
o 0 11

Size MC=29blocks *(22(32 bits + 14 bits + 1 bit) = 9152 bytes

Main 128K x 32 bits = 27210words = 215mapped blocks in two sets

M Cache M Principal
Set 0 Block 0 Block 2 … Block 215-2
Of 256 blocks
Set 1 Block 1 Block 3 … Block 215-1
Of 256 blocks

5. Let there be a main memory of 64Kx16 bits, and a cache memory with direct mapping of 1K words.
If the block size is 4 words, indicate the format of the main memory addresses, and the
number of bits (and their function) in each cache entry.

Solution:
MP => 64K = 21616-bit words; 16-bit addresses; blocks in MP =216/4=214blocks
Cache Blocks 210/4=28

Label block Word

0000 00 00 0000 00 00

6. Below is a chain of 19-bit address references given as word addresses:

1, 4, 8, 5, 20, 17, 19, 56, 9, 11, 4, 43, 5, 6, 9, 17.
Assuming a direct-mapped cache with 16 blocks of one word that is initially empty,
label each reference in the list as a hit or miss and show the final content of the cache. (Solution
similar to exercise 2.4)
 Ref Label block Word Hit/Miss
1 0000 0000 0000 000 0 001
4 0000 0000 0000 000 0 100
8 0000 0000 0000 000 1,000
5 0000 0000 0000 000 0 101
20 0000 0000 0000 001 0 100
17 0000 0000 0000 001 0 001
19 0000 0000 0000 001 0 011
56 0000 0000 0000 011 1 000
9 0000 0000 0000 000 1 001
11 0000 0000 0000 000 1 011
4 0000 0000 0000 000 0 100
43 0000 0000 0000 010 1 011
5 0000 0000 0000 000 0 101 Hit
6 0000 0000 0000 000 0 110
9 0000 0000 0000 000 1 001 Hit
17 0000 0000 0000 001 0 001 Hit

Success rate = 3/16

7. Using the reference chain from exercise 6, show the hits and misses and the final content of the cache.
direct correspondence with blocks of four words and a total size of 16 words.

M Cache
Ref Label [Link].
1 0000 0000 0000 0000 001
4 0000 0000 0000 0000 100 block Label Word
8 0000 0000 0000 0001 000 selected
5 0000 0000 0000 0000 101Hit 00 0000 0000 0000 000 000110 11
20 0000 0000 0000 0010 100 0000 0000 0000 001 00011011
17 0000 0000 0000 0010 001 01 0000 0000 0000 000 00 0110 11
19 0000 0000 0000 0010 011Hit 0000 0000 0000 001 0001 10 11
56 0000 0000 0000 0111 000 0000 0000 0000 000 00 01 1011
9 0000 0000 0000 0001 001 10 0000 0000 0000 000 0001 10 11
11 0000 0000 0000 0001 011Hit 0000 0000 0000 011 0001 10 11
4 0000 0000 0000 0000 100 0000 0000 0000 000 00011011
43 0000 0000 0000 0101 011 0000 0000 0000 010 00 01 1011
5 0000 0000 0000 0000 101Hit 0000 0000 0000 000 000110 11
6 0000 0000 0000 0000 110Hit 11
9 0000 0000 0000 0001 001
17 0000 0000 0000 0010 001Hit

Success rate=6/16

8. Using the reference string from exercise 6, show the hits and misses and the final content of the cache
for a two-block set associative cache of one word and a total size of 16 words.
Assuming LRU replacement policy.

Sets of two blocks,

Total number of sets = 16 blocks of one word / 2 blocks per set = 8 sets three bits to index the set
 Ref Label Set M Cache
1 0000 0000 0000 0000001
4 0000 0000 0000 0000100 Conj. Label block1 Block2 label
8 0000 0000 0000 0001000 000 0000 0000 0000 0001 0000 0000 0000 0111
5 0000 0000 0000 0000101 001 0000 0000 0000 0000 0000 0000 0000 0010
20 0000 0000 0000 0010100 0000 0000 0000 0001
17 0000 0000 0000 0010001 010
19 0000 0000 0000 0010011 011 0000 0000 0000 0010 0000 0000 0000 0001
56 0000 0000 0000 0111000 0000 0000 0000 0101
9 0000 0000 0000 0001001 100 0000 0000 0000 0000 0000 0000 0000 0010
11 0000 0000 0000 0001011 101 0000 0000 0000 0000
4 0000 0000 0000 0000100 hit 110 0000 0000 0000 0000
43 0000 0000 0000 0101011 111
5 0000 0000 0000 0000101hit
6 0000 0000 0000 0000110
9 0000 0000 0000 0001001hit
17 0000 0000 0000 0010001

9. Using the reference chain from exercise 6, show the hits and misses and the final content of the cache.
for a fully associative cache with word-sized blocks and a total size of 16 words. Assume
LRU replacement.

10. Using the reference chain from exercise 6, show the hits and misses and the final content of the cache.
for a fully associative cache with blocks of four words and a total size of 16 words.
Assume LRU replacement.

11. A single-processor computer with a main memory of 1M word has a cache memory of
direct correspondence of 4K words with blocks of 16 words. Assuming that the cache memory is
initially empty, indicate the number of cache misses that occur if the processor generates the
memory access sequence:
ABC13h, CDC14h, ABC1Fh, AB305h, ABC14h, CDC1Fh, AB306h, CAC13h, CDC1Ah, CA00h, CAC1Fh.
For that same sequence, indicate the cache block frames in which each position is loaded.
main memory to which it is intended to access.

12. Consider a virtual memory system with a 40-bit virtual address, 16KB pages, and address
36-bit physics. What is the total size of the page table for each process of this machine?
assuming that the validity, protection, occupation, and use bits require a total of 4 bits and that they are used
all virtual pages? Assuming that the disk addresses are not stored in the page table.
13. Cache C1 is direct-mapped with 16 one-word blocks. Cache C2 is direct-mapped
directly with 4 blocks of four words. Assume that the penalty for failures for C1 is 8 clock cycles
and for C2 it is 11 clock cycles. Assuming that the caches are initially empty, find a chain
for reference so that C2 has a lower failure rate but uses more cycles in cache failures than
C1. Use word addresses.

14. Consider three machines with different cache configurations and different failure rate measurements:
Cache 1: Direct correspondence with single word blocks. The instruction failure rate is 4.
for 100 and the data failure rate of 8 percent. The clock period is 10 ns.
[Link] 2: Direct correspondence with blocks of four words. The instruction failure rate is
of 2 percent and the data failure rate of 4 percent. The clock frequency is 10 ns.
[Link] 3: Two-way set associative with four-word blocks. The failure rate of
Instructions are at 2 percent and the data failure rate is at 4 percent. The clock frequency is 12 ns.

For these machines, half of the instructions contain a data reference. Assume that the penalty
Cache misses is 6+Block size. The CPI for this workload was measured on a machine with
cache 1 and found it was 2.0. Determine which machine uses more cycles on cache misses. Determine
Which machine is faster and which is slower.

Solution:

Cache 1 Cache 2 Cache 3

Direct correspondence Direct correspondence Associative by sets
Block=1 word Block=4 word Sets of two blocks
4% Failure rate I=2% Block=4 word
Failure rate D=8% Failure rate D=4% Failure rate I=2%
10 ns 10 ns Failure rate D=4%
CPI=2 12 ns
It is assumed: 50% of the instructions reference data. Penalty for failure = 6 + block size.

Cache 1
Penalty decision=6+1 cycles=7 cycles
For every N instructions with their N/2 data references, the following penalties are incurred.
Penalty cycles mem = N * (0.04*7 + 0.08*7*0.5) = 0.56 * N 56% of the execution time is spent on
memory accesses

A program with N instructions spends 0.56 N cycles managing memory. Then

CPI = 2 cycles per instruction = CPU cycles + 0.56 memory cycles

CPU cycles = 1.44 = CPI CPU (this will be common for the other machines)

Execution time1 = 2 * N * 10ns = 20 N ns

Cache2
Penalty cycles = 7 + 4 = 11
Penalty cycles = N * (0.02 + 0.04 * 0.5) * 11 = 0.44N

CPI=1.44+0.44=1.88
Execution time2 = 1.88 * N * 10ns = 18.8 N ns the fastest

Cache3
Penalty cycles = 7 + 4 = 11
Penalty cycles = N*(0.02 + 0.04*0.5)*11 = 0.44N

CPI=1.44+0.44=1.88
Execution time2 = 1.88 * N * 12ns = 22.56 N ns