GATEWAY INSTITUTE of ENGINEERING & TECHNOLOGY (GIET), Delhi NCR

Department of Computer Science

Course File
Practical Subject Name DIGITAL SYSTEM DESIGN LAB

Practical Subject Code ESECE201D

Program [Link]

Branch CSE

Session 2025-2026

Semester 3rd sem

Prepared by Mr. Ashok Saini

Approved by

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 INDEX
Sr. No. Page No.
1 Vision and Mission of the Institute 3
2 Vision and Mission of the Department 3
3 Program Educational Objectives (PEOs) 3
4 Program Outcomes (POs) 4
5 Program Specific Outcomes (PSOs) 5
6 Syllabus 6
7 Course Outcomes (COs) 6
8 COs – POs MAPPING 6
9 Assessment Plan 10
10 Assessment Instrument Mapping With Cos 10
11 Student List 11
12 Lecture Plan 12

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 1. Vision of Institute
To evolve into a world-class institution that delivers industry-relevant education, empowering students to thrive
globally.

Mission of Institute
 To produce skilled professionals with profound intellectual depth rooted in Indian knowledge,
promoting outcome-based education via Industry–Academia Collaboration.
 To equip students with advanced technical and life skills grounded in ethical values, emphasising
industrial consultancy, innovation, and research excellence.
 To foster human capital through multidisciplinary learning and prioritising entrepreneurship for global
sustainability.
 To enhance faculty growth through recognition, skill development, and a nurturing workplace culture.


2. Vision of Department
To create globally competent professionals by imparting quality technical education, research aptitude and
analytical skills to meet challenges in IT industry, thus contribute to the welfare of society.

Mission of Department
M1:To nurture students with knowledge and programming skills of different IT domains necessary for
development and testing of quality software solutions.
M2:To provide an integrated, responsive and comprehensive academic ecosystem with enhanced
teaching and learning to promote intellect and excellence in research.
M3:To mentor students with applied problem solving and critical thinking leading to innovative and
sustainable solutions to societal problems.
M4:To collaborate and exchange expertise with industry, research organizations and academic
institutions.

3. Program Educational Objectives (PEO)

PEO1: The graduates will have core competencies in IT fundamentals necessary to solve hardware, software
and integrated engineering problems relevant to IT industries.
PEO2: The graduates will be proficiently engaged in development of IT products and services to cater to the
industry needs or perform as innovators or entrepreneurs.

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PEO3: The graduates will successfully pursue higher education or career paths in research.
PEO4: The graduates will professionally function with social awareness, responsibility and ethical norms.

4. Program Outcomes (POs)

PO1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex engineering
problems.

PO2: Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.

PO3: Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and
environmental considerations.

PO4: Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data and
synthesis of the information to provide valid conclusions.

PO5: Modern tool usage: Create, select and apply appropriate techniques, resources and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.

PO6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.

PO7: Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.

PO8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.

PO9: Individual and team work: Function effectively as an individual and as a member or leader
in diverse teams, and in multidisciplinary settings.

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PO10: Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations and give
and receive clear instructions.

PO11: Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments.

PO12: Life-long learning: Recognize the need for and have the preparation and ability to engage
in independent and life-long learning in the broadest context of technological change.

5. Program Specific Outcomes (PSOs)

PSO1:Logic Design and Minimization

Apply the concepts of Boolean algebra to realize, simplify, and optimize digital circuits using
universal gates and Karnaugh Maps (up to 6 variables).
PSO2: Combinational and Sequential Circuit Implementation
Design, implement, and verify the functionality of combinational circuits (MUX, DEMUX,
encoders, decoders, code converters) and sequential circuits (flip-flops, counters –
synchronous/asynchronous, up/down, and decade).
PSO3: Hardware Description Language Proficiency
Develop and simulate digital systems using VHDL, including logic gates, arithmetic circuits
(adder/subtractor), converters, and other combinational/sequential designs with different modeling
styles.
PSO4: Practical Problem-Solving Skills
Demonstrate the ability to analyze, model, and test digital design problems through hardware
implementation and simulation tools, preparing for real-world applications in embedded systems
and VLSI design.

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 6. Course Outcomes (COs)
CO1: Apply Boolean algebra, universal gates, and Karnaugh Map techniques to realize and
minimize logic functions.

CO2: Design and verify combinational and sequential digital circuits including multiplexers,
demultiplexers, flip-flops, and counters.

CO3: Develop and implement digital systems using VHDL for logic gates, arithmetic circuits,
code converters, encoders, and decoders.

CO4: Analyze, simulate, and test digital circuit designs to demonstrate practical problem-solving
skills for real-time applications.

7. CO-PO Mapping

Co PO PO PO PO PO PO PO PO PO PO PO PO PS PS PS PS
s 1 2 3 4 5 6 7 8 9 10 11 12 O1 O2 O3 O4

CO
3 3 2 2 1 – – – – 1 – – 3 2 – 1
1:

CO
3 3 3 2 2 – – – 1 2 – – 2 3 – 2
2:

CO
3 2 3 2 3 – – – – 3 – – 2 2 3 3
3:

CO
3 3 3 3 2 – – – 1 3 – 2 2 2 3 3
4:

Correlation Levels: High-3, Medium-2, Low-1

8. SYLLABUS

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 ESECE201D Database management systems Lab
L T P Credit PCA PES Total Time
- 0 2 15 10 25 -
Purpose To bridge theortical knowledge with practical application, enabling student to
understand digital logic, design complex combinational and sequential circuits,
use HDLs for simulation and realize these design on FPGA arrays.
Course Outcomes
CO1 Understand basic logic function with the help of universal gates
CO2 Design and analyze synchronous and asynchronous sequential logic circuit
CO3 Apply VHDL for the description of digital system and components

List of experiments:

1. Realizations of logic function with the help of Universal Gates.

2. To realize and minimize logic functions using 5 and 6 variables K-Map method.
3. To verify the operation of multiplexer and De – multiplexer.
4. To verify the truth table of S-R, J-K, T and D – flip-flops.
5. To design and verify the operation of 3 – bit Synchronous Up/Down Counter.
6. To design and verify the operation of bit Synchronous Decade counter using J – K Flip-Flop.
7. To design and verify operation of 4-bit Asynchronous counter.
8. To simulate VHDL code for realizing logic gates.
9. To write VHDL code for realizing adder and subtractor circuit using different modeling styles.
10. To design and simulate VHDL code for code converters.
11. To design and simulate VHDL code for encoder and decoder circuits.

Justification of CO-PO and CO-PSO Mapping

(1- Low, 2- Medium, 3-High)

Mapping (1/2/3) Justification

CO1-PO1 3 Engineering knowledge

CO1-PO2 3 Problem analysis

CO1-PO3 2 Design/development of solutions

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CO1-PO4 2 Conduct investigations of complex problems

CO1-PO5 1 Modern tool usage

CO1-PO6 -- No direct relation

CO1-PO7 -- No direct relation

CO1-PO8 -- No direct relation

CO1-PO9 -- No direct relation

CO1-PO10 1 Communication

CO1-PO11 -- No direct relation

CO1-PO12 1 Life-long learning

CO1-PSO1 3 Logic Design and Minimization

CO1-PSO2 2 Combinational and Sequential Circuit Implementation

CO1-PSO3 -- Hardware Description Language Proficiency

CO1-PSO4 1 Practical Problem-Solving Skills

CO2-PO1 3 Engineering knowledge

CO2-PO2 3 Problem analysis

CO2-PO3 3 Design/development of solutions

CO2-PO4 2 Conduct investigations of complex problems

CO2-PO5 2 Modern tool usage

CO2-PO6 -- No direct relation

CO2-PO7 -- No direct relation

CO2-PO8 -- No direct relation

CO2-PO9 1 Individual and team work

CO2-PO10 2 Communication

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CO2-PO11 -- No direct relation

CO2-PO12 -- No direct relation

CO2-PSO1 2 Logic Design and Minimization

CO2-PSO2 3 Combinational and Sequential Circuit Implementation

CO2-PSO3 -- No direct relation

CO2-PSO4 2 Practical Problem-Solving Skills

CO3-PO1 3 Engineering knowledge

CO3-PO2 2 Problem analysis

CO3-PO3 3 Design/development of solutions

CO3-PO4 2 Conduct investigations of complex problems

CO3-PO5 3 Modern tool usage

CO3-PO6 -- No direct relation

CO3-PO7 -- No direct relation

CO3-PO8 -- No direct relation

CO3-PO9 -- No direct relation

CO3-PO10 3 Communication

CO3-PO11 -- No direct relation

CO3-PO12 -- No direct relation

CO3-PSO1 2 Logic Design and Minimization

CO3-PSO2 2 Combinational and Sequential Circuit Implementation

CO3-PSO3 3 Hardware Description Language Proficiency

CO3-PSO4 3 Practical Problem-Solving Skills

CO4-PO1 3 Engineering knowledge

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CO4-PO2 3 Problem analysis

CO4-PO3 3 Design/development of solutions

CO4-PO4 3 Conduct investigations of complex problems

CO4-PO5 2 Modern tool usage

CO4-PO6 -- No direct relation

CO4-PO7 -- No direct relation

CO4-PO8 -- No direct relation

CO4-PO9 1 Individual and team work

CO4-PO10 3 Communication

CO4-PO11 -- No direct relation

CO4-PO12 2 Life-long learning

CO4-PSO1 2 Logic Design and Minimization

CO4-PSO2 2 Combinational and Sequential Circuit Implementation

CO4-PSO3 3 Hardware Description Language Proficiency

CO4-PSO4 3 Practical Problem-Solving Skills

9. ASSESSMENT PLAN

[Link]. Assessment Instruments Marks

1. Continuous Lab Assessment 15
2. End Semester Lab Assessment 10

10. ASSESSMENT INSTRUMENT MAPPING WITH

COs

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 [Link]. Assessment Instruments CO CO2 CO3
1
1. Continuous Assessment Y Y Y
2. End Semester Lab Y Y Y
Assessment

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 11. STUDENTS ROLL LIST
S.N
[Link] Roll No Student Name o Roll No Student Name
1 24010001001 ABHISHEK 30 24010001031 MANAV DAHIYA

2 24010001002 ABHISHEK 31 24010001032 MANISH DAHIYA

3 24010001004 AMAN YADAV 32 24010001033 MAYANK

4 24010001005 AMIT 33 24010001034 MINAKSHI

5 24010001006 AMIT 34 24010001035 NAKUL BHARDWAJ

6 24010001007 ANAMIKA 35 24010001036 NISHA

7 24010001008 ANSH YADAV 36 24010001037 PRINCE MUNARIA

8 24010001009 ARYA 37 24010001038 PRIYA

9 24010001010 ARYAN 38 24010001040 RITESH

10 24010001011 AVINEESH ARORA 39 24010001041 RIYA SINGH

11 24010001012 CHINTU 40 24010001042 ROHIT ROHILLA

24010001013 CHIRAG VERMA SAURAV DRALL

12 41 24010001043

24010001014 DAKSH SONI NAUGAIN

13 42 24010001047

24010001015 DHRUV SOURAV

14 43 24010001048

15 24010001016 DIMPLE SHARMA 44 24010001049 SUCHETA

16 24010001017 DISHA 45 24010001050 TAMANNA

17 24010001018 HARSH 46 24010001051 TANISHA

18 24010001019 HIMANSHU YADAV 47 24010001052 TANU

19 24010001020 JATIN PRATAP SINGH 48 24010001053 TARUN DAHIYA

20 24010001021 JEEYA NAIN 49 24010001054 VANSH

21 24010001022 KAJAL 50 24010001055 VANSHU DUHAN

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 22 24010001023 KARTIK KAUSHIK 51 24010001057 VINAY KUMAR

23 24010001024 KASHAK 52 24010001058 VISHU DUHAN

24 24010001025 KOMAL 53 24010001059 YASH

25 24010001026 KRISHI 54 24010001060 YASH

26 24010001027 KRISHNA DHARMASYA 55 24010001061 YASH KUMAR

24010001028 KUNAL KUMAR

27 PANCHAL 56 LEET SHIVANI GUPTA

28 24010001029 LAKSHAY 57 LEET PRIYANKA

29 24010001030 LAKSHAY 58 LEET LAKSHAY BHUTANI

12. LAB PLAN

Subject: Digital System Design Lab Subject code: ESECE201D

Session: 2025-26 Semester: III

SN Topic Group CO Panned Date Actual Date

Mapped

112. Realizations of logic function with the G1 CO1 01-08-25

help of Universal Gates. G2 25-07-25
213. To realize and minimize logic functions G1 CO1 08-08-25
using 5 and 6 variables K-Map method. G2 05-08-25
314. To verify the operation of multiplexer G1 CO1 29-08-25
and De – multiplexer. G2 26-08-25
415. To verify the truth table of S-R, J-K, T G1 CO1 05-09-25
and D – flip-flops. G2 02-10-25
516. To design and verify the operation of 3 G1 CO1
– bit Synchronous Up/Down Counter. 12-09-25

G2 16-10-25

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 617. To design and verify the operation of bit G1 CO2 19-09-25
Synchronous Decade counter using J – G2
K Flip-Flop. 23-09-25

18.
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19. To design and verify operation of 4-bit G1 CO2 26-09-25
Asynchronous counter.
G2 30-09-25
820. To simulate VHDL code for realizing G1 CO3 3-10-25
logic gates. G2 07-10-25
921. To write VHDL code for realizing adder G1 CO3 10-10-25
and subtractor circuit using different G2
modeling styles. 14-10-25

1022. To design and simulate VHDL code for G1 CO3 17-10-25

code converters. G2 04-11-25

1123. To design and simulate VHDL code for G1 CO3 07-11-25

encoder and decoder circuits. G2 11-11-25

Programs Beyond Syllabus

1 G1

2 G1

CONTINUOUS LAB ASSESSMENT

END SEMESTER LAB ASSESSMENT

INTERNAL AWARD SHEET

OVERALL CO ATTAINMENT (CONSIDERING UNIVERSITY MARKS)

OVERALL PO & PSO ATTAINMENT

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(*Excel sheets of above mentioned will be appended separately)

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