Operating System Fundamentals
Prof. Santanu Chattopadhyay
IIT Kharagpur
Assignment 10 (Week 10)
Q1. In a paged virtual memory system, when does a TLB miss occur?
(A) When the CPU's request for an address translation is found in the TLB.
(B) When the CPU needs to access a page table entry and it is not found in the TLB.
(C) When the CPU tries to access a page that is not in main memory.
(D) When the physical address is not valid.
Answer: (B) When the CPU needs to access a page table entry and it is not found in the TLB.
Q2. The time required for an address translation with a TLB hit is much lower than without a
TLB. If a system has a TLB access time of 20 ns, a memory access time of 100 ns, and a TLB
hit ratio of 80%, what is the effective memory access time?
(A) 100 ns
(B) 120 ns
(C) 140 ns
(D) 160 ns
Answer: (C) 140 ns
Q3. Consider a computer system that uses segmentation for memory management. The
following segmentation table is used for a given process:
Segment number Base Address (in decimal) Limit (in bytes)
0 1000 500
1 2500 200
2 4000 800
3 5200 300
If the CPU generates a logical address (<segment number, offset>) of (2, 600), what is the
corresponding physical address?
(A) 3100
(B) 4600
(C) 5800
(D) Invalid addresses
Answer: (B) 4600
Q4. What is the result of increasing the page size in a virtual memory system?
(A) It increases the number of page faults but decreases internal fragmentation
(B) It decreases the number of page faults but increases internal fragmentation
(C) It increases the number of page faults but increases internal fragmentation
(D) It decreases both the number of page faults and internal fragmentation
Answer: (B) It decreases the number of page faults but increases internal fragmentation.
Q5. The theme of demand paging, i.e., bring a page into main memory (RAM) only when it is
needed results in which of the following?
(A) Less I/O needed, no unnecessary I/O
(B) Less memory needed, more users are served
(C) Faster response
(D) All of the above
Answer: (B) Less memory needed, more users are served
Q6. The Effective Memory Access time for the Demand paging scheme is directly affected
by
(A) Degree of multi-programming
(B) Number of pages
(C) Number of frames
(D) Page fault rate
Answer: (D) Page fault rate
Q7. An instruction of a processor is of size 6 memory words. The minimum number of pages
(assume, page size is 4 KB) that must be in the memory so that fetching the instruction does
not generate a page fault is
(A) 1
(B) 2
(C) 4
(D) 8
Answer: (B) 2
[Link] a system with a 6 bit virtual address space, and 16 byte pages/frames. The
mapping from virtual page numbers to physical frame numbers of a process is (0,8), (1,3),
(2,11), and (3,1). Translate the virtual address 40, i.e., 101000 to physical addresses (answer
in decimal).
(A) 180
(B) 182
(C) 184
(D) None of the above
Answer: (C) 184
Q9. What is "thrashing" in a demand paging system?
(A) A situation where the effective access time is higher than the page fault time
(B) The continuous swapping of pages between memory and disk, resulting in very low CPU
utilization
(C) An error that occurs when a program tries to access a non-existent page
(D) The process of pre-loading pages into memory before they are needed
Answer: (B) The continuous swapping of pages between memory and disk, resulting in very
low CPU utilization.
Q10. Which of the following is TRUE when the page size in a system is increased while
keeping everything else (including the total size of main memory) the same.
(A) TLB hit rate decreases
(B) TLB hit rate increases
(C) TLB hit rate remains same
(D) None of the above.
Answer: (B) TLB hit rate increases
