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EC3552- VLSI AND CHIP DESIGN
UNIT-4
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Memory Timing: Definitions
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Memory Architecture: Decoders
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M bits M bits
S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 A1 Word 2
cell cell
words AK2 1
N SN 2 2 Decoder
Word N 2 2 Word N 2 2
SN 2 1
Word N 2 1 Word N 2 1
K 5 log2N
Input-Output Input-Output
(M bits) (M bits)
Intuitive architecture for N x M memory Decoder reduces the number of select signals
Too many select signals:
N words == N select signals
K = log2N
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Array-Structured Memory Architecture
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Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
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Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks
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Block address activates only 1 block => power savings
12 CAM
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13 Memory Timing: Approaches
DRAM Timing SRAM Timing
Multiplexed Adressing Self-timed
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Memory Core
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Read-Only Memory Cells
BL BL BL
VDD
WL
WL WL
1
BL BL BL
WL WL
WL
0
GND
Diode ROM MOS ROM 1 MOS ROM 2
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SRAM Characteristics
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1-Transistor DRAM Cell
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Write: C S is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
CS
V = VBL – V PRE = V BIT – V PRE ------------
C S + CBL
Voltage swing is small; typically around 250 mV.
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DRAM Cell Observations
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• 1T DRAM requires a sense amplifier for each bit line, due to charge
redistribution read-out.
• DRAM memory cells are single ended in contrast to SRAM cells.
• The read-out of the 1T DRAM cell is destructive; read and refresh operations are
necessary for correct operation.
• Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be
explicitly included in the design.
• When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss
can be circumvented by bootstrapping the word lines to a higher value than VDD
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19 Memory Periphery
▪ Decoders
▪ Sense Amplifiers
▪ Input/Output Buffers
▪ Control / Timing Circuitry
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Hierarchical Decoders
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Multi-stage implementation improves performance
• • •
WL 1
WL 0
A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2 A 3 A 2A 3 A 2A 3 A 2A 3
• • •
NAND decoder using
2-input pre-decoders
A1A0 A0 A1 A3A2 A2 A3
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21 4-input pass-transistor based column decoder
BL 0 BL 1 BL 2 BL 3
S0
A0
S1
S2
A1 S3
2-input NOR decoder
D
Advantages: speed (tpd does not add to overall memory access time)
Disadvantage: Large transistor count
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4-to-1 tree based column decoder
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BL 0 BL 1 BL 2 BL 3
A0
A0
A1
A1
D
Advantages: Number of devices drastically reduced
Dis advantages: Delay increases quadratically ;
prohibitive for large decoders
Solutions: progressive sizing
combination of tree and pass transistor approaches
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23 Sense Amplifiers
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Sense Amplifiers
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make V as small
C V as possible
tp = ----------------
Iav
large small
Idea: Use Sense Amplifer
small
transition s.a.
input output
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Differential Sense Amplifier
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VDD
M3 M4
y Out
bit M1 M2 bit
SE M5
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26 Voltage Regulation
Most memories require some form of on-chip voltage regulation. The operation of a sophisticated
memory requires a number of voltage references and supply levels, which includes:
1. Boosted word line voltage
2. Half-VDD
3. Reduced Internal supply
4. Negative Substrate Bias
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Voltage Regulator
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V DD
M drive
V REF V DL
Equivalent Model
V bias
V REF
-
M drive
+
V DL
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