EEE 2103

Electronics I

Field Effect Transistors (FETs)

Course Teachers:

Dr. Md. Tashfiq Bin Kashem, Assistant Professor, Department of EEE, AUST
Mr. Shameem Hasan, Assistant Professor, Department of EEE, AUST

Reference: This presentation has been prepared from “Microelectronic circuits (7th edition) by Adel S. Sedra
and Kenneth C. Smith”
 Introduction

• Two major types of three- • MOSFET technology

terminal semiconductor
devices:
• It allows placement of
approximately 2 billion
• metal-oxide- transistors on a single
semiconductor field- IC
effect transistor • backbone of very
(MOSFET) large scale
• Bipolar Junction integration (VLSI)
Transistor (BJT)
• It is considered
• MOSFET’s are: preferable to BJT
technology for many
• Smaller in size applications.
• Easy of manufacture
• Utilizes lesser power

2
 5.1. Device Structure and Operation

▪ Figure 5.1. shows general structure of the n-channel enhancement-type

MOSFET

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-section. Note
that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide layer (tox) is in the range of 1 to
10nm.
3
 two n-type doped
5.1. Device Structure and regions (drain, source)
Operation
layer of SiO2 separates
source and drain

metal, placed on top of

SiO2, forms gate
electrode

one p-type doped region

Figure 5.1: Physical structure of the enhancement-type NMOS transistor: (a) perspective view, (b) cross-
section. Note that typically L = 0.03um to 1um, W = 0.1um to 100um, and the thickness of the oxide layer
(tox) is in the range of 1 to 10nm. 4
 5.1. Device Structure and Operation

▪ The name MOSFET is derived ▪ The device is composed of two

from its physical structure. pn-junctions, however they
▪ However, many MOSFET’s do maintain reverse biasing at all
not actually use any “metal”, times.
polysilicon is used instead. “This” ▪ Drain will always be at positive
has no effect on modeling / voltage with respect to source.
operation as described here.
▪ Another name for MOSFET is
insulated gate FET, or IGFET.

5
 5.1.2. Operation with Zero Gate Voltage

▪ With zero voltage applied to gate,

two back-to-back diodes exist in
series between drain and source.
▪ “They” prevent current
conduction from drain to source
when a voltage vDS is applied
yielding very high resistance
(1012ohms)

Figure 5.1: Physical structure

6
 5.1.3. Creating a Channel for Current Flow

▪ If (1) source and drain are

grounded and (2) positive
voltage is applied to gate

➢ Step 1: vGS is applied to the gate

terminal, causing a positive build
up of positive charge along metal
electrode.

➢ Step 2: This “build up” causes free

holes to be repelled from region of
Figure 5.2: The enhancement-type NMOS transistor
p-type substrate under gate. with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate beneath
the gate 7
 • if (1) source and drain are grounded and (2) positive voltage is
applied to gate?

▪ Step 3: This “migration” results in

the uncovering of negative
bound charges, originally
neutralized by the free holes.

▪ Step 4: The positive gate voltage

also attracts electrons from the n+
source and drain regions into the
channel.

Figure 5.2: The enhancement-type NMOS transistor

with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate beneath
the gate 8
 this induced channel is also
known as an inversion
• if (1) source and drain are grounded and
layer
(2) positive voltage is applied to gate?

▪ Step 5: Once a sufficient number

of “these” electrons accumulate,
an n-region is created connecting
the source and drain regions.

▪ Step 6: This provides path for

current flow between D and S.

Figure 5.2: The enhancement-type NMOS transistor

with a positive voltage applied to the gate. An n
channel is induced at the top of the substrate beneath
the gate 9
 Vtn is used for n-type
5.1.3. Creating a Channel for MOSFET, Vtp is used for
Current Flow p-channel

▪ Threshold voltage (Vt) – is the ▪ Effective / overdrive voltage – is

minimum value of vGS required to the difference between vGS applied
form a conducting channel between and Vt.
drain and source. Threshold voltage (5.1) vOV  vGS − Vt
typically ranges between 0.3 - 1V.
▪ Field-effect – when positive vGS is ▪ Oxide capacitance (Cox) – is the
applied, an electric field develops capacitance of the parallel plate
between the gate electrode and capacitor per unit gate area (F/m2)
induced n-channel – the
conductivity of this channel is  ox is permittivity of SiO2 =3.45E−11( F /m )
affected by the strength of field tox is thickness of SiO2 layer

▪ SiO2 layer acts as dielectric  ox

(5.3) C ox = in F / m2
(5.2) tox 10
 5.1.3. Creating a • The gate and the channel region of the MOSFET form a
parallel-plate capacitor, with the oxide layer acting as the
Channel for capacitor dielectric.
• The positive gate voltage causes positive charge to
Current Flow accumulate on the top plate of the capacitor (the gate
electrode).
• The corresponding negative charge on the bottom plate is
formed by the electrons in the induced channel.
• It is this field that controls the amount of charge in the
channel, and thus it determines the channel conductivity
and, in turn, the current that will flow through the channel
when a voltage 𝑣𝐷𝑆 is applied.
• This is the origin of the name “field-effect transistor” (FET).
▪ Main requirement for n-channel to
form?
▪ Ans: The voltage across the “oxide” ▪ Magnitude of electron charge contained
layer must exceed Vt. in the channel?
▪ For example, when vDS = 0V W and L represent width and length of channel respectively

▪ the voltage at every point along (5.2) Q = C ox (WL ) vOV in C

channel is zero.
▪ Q: Effect of vOV on n-channel?
▪ the voltage across the oxide
Ans: As vOV grows, so does the depth of
layer is uniform and equal to vGS
the n-channel as well as its conductivity.
11
 5.1.4. Applying a small vDS
action: divide both sides by L
▪ Calculation of electron drift velocity
Ans: Note that vDS establishes an (5.2) Q = C ox (WL ) vOV in C
electric field E across length of n-
channel, this may calculate e-drift Q
velocity. (5.4) = C oxWvOV in C / m
L

vDS
(5.5) E = in V / m
L
(5.6) e-drift velocity =
V m2 m
 =  n E in =
m Vs s

𝑄
𝑖𝐷 =
𝑡𝑖𝑚𝑒

𝑄
𝑖𝐷 = × 𝐷𝑟𝑖𝑓𝑡 𝑣𝑒𝑙𝑜𝑐𝑖𝑡𝑦
𝐿 12
 5.1.4. Applying a small vDS
▪ For small values of vDS, procedure calculate iDS (aka. iD)?
Ans: Equation 5.7
▪ Origin of this equation?
Ans: Current is defined in terms of charge per unit length of n-channel as
well as electron drift velocity.
n represents mobility of electrons at surface of the
n-channel in m2 /Vs

 nvDS 
(5.7) iD = ( C oxWvOV )   in A
charge per unit
 L 
length of electron
n -channel drift velocity
in C /m in m2 /Vs

▪ How to calculate charge per unit length of n-channel (Q/unit Length)?

▪ For small values of vDS, one can still assume that voltage between gate and
n-channel is constant (along its length) – and equal to vGS. Therefore,
effective voltage between gate and n-channel remains equal to vOV.
Therefore, (5.2) from previous slide applies.
13
 5.1.4. Applying a small vDS
▪ Observation from equation (5.7)?
Ans: For small values of vDS, the n-channel acts like a variable resistance
whose value is controlled by vOV.

 W 
(5.7) iD = ( nC ox ) vOV  vDS in A
 L 
𝑖𝐷
vDS 1 𝑔𝐷𝑆 =
(5.8a) rDS = = in  𝑣𝐷𝑆

( nCox )   vOV
iD W
process
 L 
transconductance aspect
parameter ratio

▪ rDS is dependent on three factors:

▪ Process transconductance parameter for NMOS 𝒌′𝒏 = µnCox >> which is
determined by the manufacturing process
▪ Aspect ratio (W/L) – which is dependent on size requirements / allocations
▪ Overdrive voltage (vOV) – which is applied by the user
▪ MOSFET transconductance parameter, 𝒌𝒏 14
• Increasing 𝑣𝐺𝑆 above the threshold voltage Vt enhances the channel, hence it is names as
enhancement-mode operation and enhancement-type MOSFET
 5.1.5. Operation as vDS is Increased
▪ Relationship between iD and vDS, when vDS increases beyond “small
values”?
Ans: The relationship between them ceases to be linear.

▪ How can this non-linearity be explained?

➢ Step 1: Assume that vGS is held constant at value greater than Vt

➢ Step 2: Also assume that vDS is applied and appears as voltage

drop across n-channel.

➢ Step 3: Note that as we travel along the channel from source to

drain, the voltage (measured relative to the source) increases from
zero to vDS . Gate to Drain voltage vGD decreases from the source
end of channel to the drain end, where
vGD = vGS – vDS
vGD = Vt + vOV – vDS
16
 avOV avDS

The voltage differential

between both sides of n-
channel increases with vDS.

Figure 5.5: Operation of the e-NMOS transistor as vDS is increased. 17

 note the average value note that we can define total
charge stored in channel |Q|
as area of this trapezoid

Q = ( vOV − 12 vDS ) L

Figure 5.6(a): For a MOSFET with vGS = Vt + vOV application of vDS causes the voltage drop
along the channel to vary linearly, with an average value of vDS at the midpoint. Since vGD > Vt,
the channel still exists at the drain end. (b) The channel shape corresponding to the situation18
in
(a). While the depth of the channel at the source is still proportional to vOV, the drain end is not.
 How can this non-linearity be explained?

 vOV with vOV − 12 vDS 

action: replace

 W 
▪ Step 4: Define iDS in (5.7) iD = ( nC ox ) ( vOV − 12 vDS )  vDS
terms of vDS and  L 
vOV.  
 W
 (  n C ox ) ( v OV − 2 DS ) DS
1
v v if vDS  vOV
iD is dependent on the apparent  L
(5.7) iD =  W 2 1
vOV (not vDS inherently) which
 (  C
n ox ) ( v OV ) otherwise
does not change after vDS > vOV  L 2
 if vDS vOV then vDS =vOV

 W
 (  n C ox ) ( v OV − 2 DS ) DS
1
v v if vDS  vOV
(5.14) iD =  L in A
 1 W

( nC ox ) vO2 V otherwise
2 L

triode vs. saturation region 19

 saturation occurs
once vDS > vOV

 W
 triode: (  C
n ox ) ( v OV − 2 DS ) DS
1
v v if vDS  vOV
(5.14) iD =  L in A
 saturation: 1 (  C ) W v 2 otherwise
 2
n ox
L
OV 20
 pinch-off does not mean
5.1.6. Operation for vDS >> blockage of current
vOV
▪ In section 5.1.5, we assume that
n-channel is tapered but channel
pinch-off does not occur.

▪ Trapezoid doesn’t become

triangle for vGD > Vt

▪ If vDS > vOV , then MOSFET enters

saturation region. Any further
increase in vDS has no effect on
iD. Figure 5.8: Operation of MOSFET with vGS = Vt
+ vOV as vDS is increased to vOV. At the drain
▪ Any increase in 𝑉𝐷𝑆 , above 𝑉𝐷𝑆(𝑠𝑎𝑡)
end, vGD decreases to Vt and the channel depth
appears as a voltage drop across the at the drain-end reduces to zero (pinch-off).
depletion region. At this point, the MOSFET enters saturation
more of operation. Further increasing vDS
(beyond vOV) has no effect on the channel21 shape
and iD remains constant.
 5.1.7. p-Channel
MOSFET
▪ Figure 5.9(a) shows cross-sectional view
of a p-channel enhancement-type
MOSFET.
▪ structure is similar but “opposite” to
n-channel
▪ complementary devices – two devices
such as the p-channel and n-channel
MOSFET’s.
▪ To induce a channel for current flow
between source and drain, a negative
voltage is applied to the gate, that is,
between gate and source.
▪ Now, to cause a current to flow in the p
channel, a negative voltage is applied to
the 𝑉𝐷𝑆

Figure 5.9(a): Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor shown
in Figure 5.1(b), except that all semiconductor regions are reversed in polarity. (b) A negative voltage vGS of
magnitude greater than |Vtp| induces a p-channel, and a negative vDS causes a current iD to flow from source
to drain. 22
 5.1.7. p-Channel
MOSFET
▪ Main differences between n-channel
and p-channel MOSFET
▪ Negative (not positive) voltage
applied to gate “closes” the
channel
▪ Allowing path for current flow
▪ Threshold voltage (previously
represented as Vt) is represented
as Vtp
▪ |vGS| > |Vtp| to close channel
▪ Process transconductance
parameters are defined
differently
k’p = µpCox
kp = µpCox(W/L) Figure 5.9(a): Physical structure of the PMOS transistor.
Note that it is similar to the NMOS transistor shown in Figure
▪ The rest, essentially, is the 5.1(b), except that all semiconductor regions are reversed in
polarity. (b) A negative voltage vGS of magnitude greater
same, but with reverse polarity. 23
than |Vtp| induces a p-channel, and a negative vDS causes a
current iD to flow from source to drain.
 5.1.7. p-Channel MOSFET
▪ PMOS technology originally dominated the MOS field (over
PMOS). However, as manufacturing difficulties associated
with NMOS were solved, NMOS took over.

▪ NMOS is advantageous over PMOS because electron

mobility µn is 2 - 4 times greater than hole mobility µp.

▪ Complementary MOS (CMOS) technology – is

technology which allows fabrication of both N and PMOS
transistors on a single chip.

24
 5.1.8. Complementary MOS (CMOS)
▪ CMOS employs MOS transistors of both polarities.
▪ More difficult to fabricate.
▪ More powerful and flexible
▪ Now more prevalent than NMOS or PMOS

25
Figure 5.10: Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a
separate n-type region, known as an n well. Another arrangement is also possible in which an n-type
body is used and the n device is formed in a p well. Not shown are the connections made to the p-type
body and to the n well; the latter functions as the body terminal for the p-channel device.

n-well is added to allow

p-type semiconductor
generation of p-channel
provides the MOS body (and
allows generation of n-
channel) SiO2 is used to isolate
NMOS from PMOS 26
 5.1.9. Subthreshold Region

▪ The above description of the n-channel MOSFET operation

implies that for 𝑉𝐺𝑆 < 𝑉𝑡 , no current flows and the device is
cut off.
▪ This is not entirely true, for it has been found that for
values of 𝑉𝐺𝑆 smaller than but close to 𝑉𝑡 , a small drain
current flows.
▪ In this subthreshold region of operation, the drain current
is exponentially related to 𝑉𝐺𝑆 , much like the 𝒊𝑪 vs. 𝒗𝑩𝑬
relationship of a BJT.

27
 Recapitulation!

n represents mobility of electrons at surface of the

▪ The equation used to n-channel in m2 /Vs
define iD depends on
 nvDS 
relationship btw vDS (5.7) iD = ( C oxWvOV )   in A
and vOV. charge per unit
 L 
▪ vDS << vOV length of
n -channel
electron
drift velocity
in C /m in m2 /Vs
▪ vDS < vOV
W
▪ vDS => vOV (5.14) iD = ( nC ox ) (vOV − 12 vDS )vDS in A
L
▪ vDS >> vOV
1 W 2
(5.17) iD = ( nC ox ) vOV in A
2 L
1 W 2
This
(5.23 = (not
) iD has ) vcovered
nC oxbeen OV ( 1 + vDS ) in A
yet!
2 L
28
5.2. Current-Voltage
Characteristics
▪ Figure 5.11. shows an n-channel
enhancement MOSFET.
▪ There are four terminals:
▪ Drain (D)
▪ Gate (G)
▪ Body (B) and
▪ Source (S).
▪ Although, it is assumed that body
and source are connected.
▪ Arrowheads designate “normal”
direction of current flow
▪ Note that, in part (b), we designate
current as D→S.
▪ No need to place arrow with B.
Figure 5.11 (a): Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol
with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n
channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the
effect of the body on device operation is unimportant.
28
5.2.2. iD-vDS Characteristics
• At top of table, it
shows circuit
consisting of
NMOS transistor
and two dc
supplies (vDS, vGS)

• At first set vGS to

desired constant
• Secondly, vary vDS.

Figure 5.12: The relative levels of the

terminal voltages of the enhancement
NMOS transistor for operation in the triode
region and in the saturation region.
30
(5.14) As vGS increases, so do the (1)
saturation current and (2) beginning of
the saturation region ▪ When MOSFET’s
are employed to
design amplifier,
they will be
operated in
saturation region.
▪ In saturation, the
drain current (iD) is
dependent on vGS
but independent of
vDS
▪ In effect, it becomes
a voltage-controlled
current source. This
is key for
amplification.

Figure 5.13: The iD – vDS characteristics for an enhancement-type NMOS

transistor

31
 ▪ Eq (5.21) is nonlinear with respect to
5.2.2. The iD - vGS vOV , however, this is not of concern
now.
Characteristics

▪ In effect, it becomes a voltage-

controlled current source
(VCCS).
▪ This is key for amplification.
2
vOV
1 W 
(5.21) iD = kn   ( vGS − Vtn )
2

2  L 
this relationship provides
basis for application of
MOSFET as amplifier

Figure 5.14: The iD-vGS characteristic of an NMOS transistor operating in the saturation region. The iD-vOV
characteristic can be obtained by simply re-labeling the horizontal axis, that is, shifting the origin to the point
vGS = Vtn.
32
 5.2.2. iD - vGS Characteristics

▪ The view of transistor as VCCS

is exemplified in figure 5.15.
▪ This circuit is known as the
large-signal equivalent
circuit.
▪ Current source is ideal.
▪ Infinite output resistance
represents independent, in
saturation, of iD from vDS..
Figure 5.15: Large-signal equivalent-circuit model
note that, in this circuit, iD is of an n-channel MOSFET operating in the
saturation
completely independent of vDS
(because no shunt resistor
exists) 33
5.2.4. Finite Output Resistance in Saturation
▪ In previous section, it is assumed, in saturation, iD is independent of vDS.
▪ Therefore, a change DvDS causes no change in iD.
▪ This implies that the incremental resistance RS is infinite.
▪ It is based on the idealization that, once the n-channel is pinched off,
changes in vDS will have no effect on iD.
▪ The problem is that, in practice, this is not completely true.
▪ Effect of increased vDS have on n-channel once pinch-off has occurred:
▪ It will cause the pinch-off point to move slightly away from the drain & create
new depletion region.
▪ Voltage across the (now shorter) channel will remain at (vOV).
▪ However, the additional voltage applied at vDS will be seen across the “new”
depletion region.
▪ This voltage accelerates electrons as they reach the drain end, and sweep
them across the “new” depletion region.
▪ However, at the same time, the length of the n-channel will decrease. It is
known as channel length modulation.
34
 5.2.4. Finite Output
Resistance in Saturation

▪ How do we account for “this

Figure 5.16: Increasing vDS beyond vDSsat
effect” in iD? causes the channel pinch-off point to move
▪ Ans: Refer to (5.23). slightly away from the drain, thus reducing the
effective channel length by DL
valid when vDS vOV

1 W 2
(5.17) iD = ( nCox ) vOV in A
2 L
1 W 2
(5.23) iD = ( nC ox ) vOV (1 + vDS ) in A
2 L
valid when vDS vOV

▪ Addition of finite output Figure 5.18: Large-Signal Equivalent Model

resistance (ro). of the n-channel MOSFET in saturation,
incorporating the output resistance ro. The
output resistance models the linear
35
dependence of iD on vDS and is given by (5.23)
5.2.4. Finite Output Resistance in Saturation
−1
 i 
(5.24) ro =  D 
 vDS  vGS =constant
−−−−−−−−−−−−−−−−−−−−−−−−−−−−
▪ How is ro defined?  (5.23)

▪ Step 1: Note that ro is the iD  1 W 2 
(5.23) =  ( nC ox ) vOV (1 + vDS ) 
1/slope of iD-vDS vDS vDS  2 L 
characteristic.  
▪ Step 2: Define relationship  (5.23)

iD  1 W 2 
between iD and vDS using (eq5.23) =  (  C ) v ( 1 + v )
DS 
vDS vDS  2
n ox OV
L 
(5.23).  
▪ Step 3: Take derivative of iD 1 W
(eq5.23) = ( nC ox ) vO2 V 
this function. vDS 2 L
▪ Step 4: Use above to −−−−−−−−−−−−−−−−−−−−−−−−−−−−
define ro. −1
▪ Note that ro may be defined in 1 W 2 
(eq5.25) ro =  ( nC ox ) vOV 
terms of iD, where iD does not  2 L  vGS =constant
take into account channel 1 VA
(eq5.24) ro = =
length modulation.  iD iD 36
5.2.4. Finite Output Resistance in Saturation
▪  is a device parameter with the
unit of V -1, the value of which
depends on manufacturer’s design
and manufacturing process.
▪ Much larger for newer tech’s
▪ Figure 5.17 demonstrates the
effect of channel length modulation
on vDS-iD curves
▪ In short, we can draw a
straight line between VA and
saturation.
▪ 𝑉𝐴 α channel length (L) that the Figure 5.17: Effect of vDS on iD in the saturation
designer selects for a MOSFET. region. The MOSFET parameter VA depends on
▪ We can isolate the dependence of the process technology and, for a given process,
is proportional to the channel length L.
𝑉𝐴 on L by expressing it as
𝑉𝐴 = 𝑉𝐴′ 𝐿
▪ where 𝑉𝐴′ is entirely process-
technology dependent, with the
dimensions of volts per micron.
▪ Typically, it falls in the range of 5
37
V/μm - 50V/μm.
5.2.5. Characteristics of the p-channel MOSFET
▪ Characteristics of the p-channel MOSFET
are similar to the n-channel, however with
many signs reversed.

Figure 5.19 (a) Circuit symbol for the p-channel

enhancement-type MOSFET. (b) Modified
symbol with an arrowhead on the source lead.
(c) Simplified circuit symbol for the case where
the source is connected to the body.

Considering the channel length saturation

effect:

where λ and 𝑉𝐴 (the Early

voltage for the PMOS
transistor) are by convention
negative quantities, hence we
use |λ| and | 𝑉𝐴 |. 38
 5.2.5. Characteristics of the p-channel
MOSFET
➢ Finally, we should note that for
a given CMOS fabrication
process λn and λp are
generally not equal, and
similarly for 𝑉𝐴𝑛 and 𝑉𝐴𝑝

➢ To turn a PMOS transistor on,

the gate voltage has to be
made lower than that of the
source by at least Vtp.

➢ To operate in the triode region,

Figure 5.20 The relative levels of the terminal
the drain voltage has to
voltages of the enhancement-type PMOS transistor
exceed that of the gate by at for operation in the triode region and in
least Vtp. the saturation region.

➢ Otherwise, the PMOS

operates in saturation.
39
 Summary
▪ The enhancement-type MOSFET is current the most widely used semiconductor device. It
is the basis of CMOS technology, which is the most popular IC fabrication technology at
this time. CMOS provides both n-channel (NMOS) and p-channel (PMOS) transistors,
which increases design flexibility. The minimum MOSFET channel length achievable with a
given CMOS process is used to characterize the process.

▪ The overdrive voltage |VOV| = |VGS| - |Vt| is the key quantity that governs the operation of
the MOSFET. For amplifier applications, the MOSFET must operate in the saturation
region.

▪ In saturation, iD shows some linear dependence on vDS as a result of the change in channel
length. This channel-length modulation phenomenon becomes more pronounced as L
decreases. It is modeled by ascribing an output resistance ro = |VA|/ID to the MOSFET
model. Although the effect of ro on the operation of discrete-circuit MOS amplifiers is
small, that is not the case in IC amplifiers.

▪ The essence of the use of MOSFET as an amplifier is that in saturation vGS controls iD in
the manner of a voltage-controller current source. When the device is DC biased in the
saturation region, a small-signal input (vGS) may be amplified linearly.

40