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OPC accuracy improvement through

deep-learning based etch model

Weina Shi, Liang Zhu, Yuqian Chen, Jiao Huang, Jinze

Wang, et al.

Weina Shi, Liang Zhu, Yuqian Chen, Jiao Huang, Jinze Wang, Qian Xie, Bilun
Zhang, Yunfei Xi, Wenhao Pan, Yuanxia Zheng, Yongfa Fan, Jin Cheng, Yu
Zhao, Leiwu Zheng, "OPC accuracy improvement through deep-learning
based etch model," Proc. SPIE 12056, Advanced Etch Technology and
Process Integration for Nanopatterning XI, 1205607 (25 May 2022); doi:
10.1117/12.2613926

Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California,

United States

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 OPC accuracy improvement through deep-learning based etch model
Weina Shia, Liang Zhua, Yuqian Chenb, Jiao Huangb, Jinze Wangb, Qian Xieb, Bilun Zhangb, Yunfei Xib, Wenhao Panb,
Yuanxia Zheng*c, Yongfa Fanc, Jin Chengc, Yu Zhaoc, Leiwu Zhengc

a
ChangXin Memory Technologies, Inc. Hefei, Anhui, China
b
ASML China (Shenzhen), 3023 Chuangye Road, Nanshan District, Shenzhen, Guangdong, China
c
ASML US, 80 W Tasman, San Jose, CA 95131

*[email protected]; phone +01(669)265-3200

ABSTRACT

This paper demonstrates a full-chip OPC correction flow based on deep-learning etch model in a DUV litho-etch
case. The flow leverages SEM metrology (eP5 fast E-beam tool, ASML-HMI) to collect massive data, automated
metrology software (MXP, ASML-Brion) to extract high quality gauges, and deep-learning etch modeling (Newron etch,
ASML-Brion) to capture complicated etch behaviors.
The model calibration and verification are performed using a combined data from a test and real chip wafer to
ensure sufficient pattern coverage. The model performance of Newron etch is benchmarked against a term-based etch
model, wherein Newron etch model shows significant accuracy improvement in the model calibration (>50% for test
patterns and >35% for real chip pattern). The Newron etch model is proven stable with a comparable performance in the
model verification. Particularly, strong loading effects from underlying sublayer are observed in the full chip wafer, and
effectively captured by the Newron etch with a sublayer-aware model form.
The calibrated Newron etch model is successfully applied in a model-based etch OPC tape-out with new mask
design rules but the same litho-etch process conditions. Compared to the term-based model, Newron etch also shows
significant accuracy improvement.

Keywords: AEI, litho-etch bias, deep learning etch model, sublayer aware, high-quality EP gauges, fast metrology flow,
OPC model accuracy and stability, etch OPC

1. INTRODUCTION
Optical proximity correction (OPC) has been successfully applied in the photolithography manufacturing to improve
the accuracy. As the critical dimension (CD) shrinkage prevails in advanced nodes, the etch process has become highly
complicated and the complexity of litho-etch bias behaviors becomes a significant error source in the semiconductor
manufacturing[1-2]. Such challenge leads to the development of etch OPC solutions, in which both lithography and etch
process must be optimized simultaneously. Similar to the optical behaviors, the etch process also has the strong
proximity effect, which makes the litho-etch bias highly pattern dependent in the advanced nodes[3]. Traditionally, etch-
bias rule tables have been used to compensate the litho-etch bias with a loose CD requirements[4-5], but failed in the
advanced nodes with stringent CD control requirements, especially for complex 2D patterns of strong loading effects.
Hence, the model based etch OPC solution began to enter the stage of its history [6-7]. Contrary to the lithography
process, the fundamental physical principles behind the etch process are way more complicated and can be difficult to
fully describe in etch models. Term-based etch models such as variable etch bias (VEB) [8] from Mentor Graphics and
effective etch bias (EEB) [9] from ASML-Brion, have provided a much more reliable etch OPC solution than the etch-
bias rule tables, but still cannot fully meet the growing demands for the model accuracy in the advance nodes,
particularly when handling large volume data and complex etch processes like non-linear etch behaviors caused by
multiple etch steps or inter-layer interference.
In this paper, a deep-learning based etch model (Newron etch, ASML-Brion) is proposed to improve the prediction
accuracy of litho-etch OPC model. Benefited by the rapid development of computing power and data scale, the machine
learning technology has achieved remarkable success on a wide variety of applications [10-12]. In the field of model

Advanced Etch Technology and Process Integration for Nanopatterning XI, edited by
Julie Bannister, Nihar Mohanty, Proc. of SPIE Vol. 12056, 1205607
© 2022 SPIE · 0277-786X · doi: 10.1117/12.2613926

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 based OPC, ASML-Brion’s deep-learning Newron etch model is able to provide a significantly improved fitting power
for large volume data, as well as the complex etch loading effects from sublayers. A DUV litho-etch case is used to
demonstrate the Newron etch model’s performance, using a workflow: (1) raw SEM collection, (2) gauge extraction
from SEM, (3) model calibration, and (4) model verification.

2. DATA PREPARATION
In this work, the calibration and verification data were collected combining two wafers (the test wafer and real chip
wafer) to ensure sufficient pattern coverage. The two wafers used the same lithography (DUV and PTD resist), and the
same reactive ion etch (RIE) process. The test wafer only contains repeating patterns, including 1D and 2D patterns such
as line/space, line-end to line-end, and line to line-end patterns as shown in Figure 1a-c. The real chip wafer contains
productive patterns; particularly in Figure 1d, an underlying sublayer coexists with the primary layer which introduced
strong loading effects to the etch behaviors, as will be discussed later.

Figure 1. Model calibration and verification data including: (a) line/space, (b) line-end to line-end, (c) line to line-end, d)
real chip patterns with the sublayer. Patterns (a)-(c) are from the test wafer.
Figure 2 shows the modeling workflow combining SEM metrology (eP5 fast E-beam tool, ASML-HMI), automated
metrology software (MXP, ASML-Brion), and deep-learning etch modeling (Newron etch, ASML-Brion). The fast E-
beam tool eP5 was used to rapidly obtain massive metrology data with a reasonable turn-around time; both ADI (after-
resist development-inspection) and AEI (after-etch-inspection) gauges were measured for the same patterns. The MXP
software was utilized to automate the processing of large volume SEM images; as shown in Figure 3, multiple SEM
images from the same pattern are averaged to reduce the SEM noise and the contour is extracted with high accuracy,
based on which CD and EP gauges are measured. Particularly in Figure 2, the above-mentioned sublayer can be well
identified in the SEM image, which shows strong correlation to the local CD variation of the primary layer pattern; MXP
is able to distinguish the primary layer contour from the sublayer without interference. More details about the etch
modeling will be discussed later.

Figure 2. Integrated modeling workflow with eP5, MXP and Newron etch model.

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 Figure 3. (a) raw SEM image shows noisy profiling along the yellow cutline; (b) MXP averaged image shows high signal-
noise-ratio.

3. MODEL CALIBRATION AND RESULTS

As an apple-to-apple comparison, two different models, term-based model and Newron etch model, were calibrated
on the same CD and EP dataset. Note that both the term-based and Newron etch models are sublayer-aware to cover the
sublayer loading effects. Table 1 illustrates the gauge data configurations for the model calibration (CAL) and
verification (VER). Both CAL and VER data include large volume CD/EP gauges from the test and real chip patterns to
ensure a sufficient pattern coverage. Compared to CD gauges, EP gauges can provide even better pattern coverages and
reduce the risk of overfitting.
Table.1 Gauge data configurations for CAL and VER.
Test wafer Real chip wafer
1D_CD 1D_EP 2D_CD 2D_EP Product_CD Product_EP

CAL gauges 536 852 1010 30009 749 37570

VER gauges 85 390 40 8934 53 88514

3.1 Overall model accuracy

The overall model error is evaluated by the root-mean-square (RMS) in Figure 4, which summarizes the calibration
and verification results for the term-based and Newron etch models. The Newron etch model shows a much better
accuracy than the term-based model, with >50% RMS reduction for the test patterns and >30% for the real chip patterns.
Such improvement of the Newron etch model demonstrates a high fitting power of the deep-learning algorithm, and
points to a high potential in the model based etch OPC applications of the next generation node. Another key highlight is
that the Newron etch model shows comparable accuracy performance between the CAL and VER results, indicating that
the Newron model is stable and not overfitted.

Figure 4. Model accuracy benchmark for the term-based and Newron etch models.

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 3.2 CD/Pitch Etch Bias Trend
Apart from the overall model error (RMS), through CD/pitch analysis of etch bias trend is a useful metric to
evaluate the model’s fitting power. The etch bias is the difference between the AEI_CD and ADI_CD, that is, etch_bias
= AEI_CD – ADI_CD. In Figure 5, the real etch bias trend for the line/space patterns in CAL data is compared with the
term-based and Newron etch models, respectively. Various litho target_CD and pitches are included for more systematic
analysis. The term-based model roughly captures the through-pitch etch bias trend, but the obvious model errors
particularly at low target_CD regions indicate insufficient through-CD accuracy. On the other hand, the Newron etch
model well follows both through-CD and -pitch trends for the etch bias with a high model accuracy; such good capture
of the etch bias trend is the foundation of reliable model prediction as will be discussed later.

Figure 5 Through-CD and -pitch trends of line/space patterns comparing the real etch bias with (a) the term-based model,
and (b) Newron model.

3.3 Contour comparison with wafer data

Another useful metric of model evaluation is contour-to-contour (C2C) comparison to check the model accuracy and
contour stability. Figure 6 shows one example of C2C comparison for the real chip patterns in VER data. The MXP
extracted contour serves as the ground truth of wafer contour. Together, the model contours from the term-based model
and the Newron etch model are aligned with respect to the layout mask. Compared to the term-based model, the Newron
etch model prediction is more consistent with the wafer contour geometry with smaller edge placement error (EPE),
indicating that the Newron etch model is stable and accurate. For example, at some locations, the term-based model
contour shows large EPE ~6nm, while only ~2.6nm for the Newron etch model contour. Such reduction of EPE
contributes to the above-mentioned accuracy improvement in the Newron etch model.

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 Figure 6 Test pattern contour-to-contour comparison for MXP contour (blue), Newron etch model contour (red) and term-
based model contour (green).

3.4 Sublayer loading effects

As mentioned above, there are underlying sublayers on the real chip wafer. During the plasma etch, if the underlying
sublayer is also exposed to the plasma, the local etch behavior of the primary layer may be affected because: (1)
geometrical change due to the existence of the neighboring sublayer structures, which affects the local plasma diffusion
and/or plasma particle visibility; (2) distinct material loading effects caused by the neighboring sublayer materials, which
affect the local plasma density and/or the etch by-products. In this study, only short range proximity sublayer effects
have been observed (<200nm). Note that sometimes the material loading effects from the sublayer can be long range
proximity (>1um).

Figure 7. (a) GDS layout for 1D dense pattern with the same ADI target_CD and pitch; the sublayer only partially covers the
lines; (b) SEM image after the etch for the same location in (a) Simulation result with sublayer. (c) Simulation result without
sublayer.
Figure 7a shows one example of 1D line pattern with a coexisting sublayer. The target_CD and pitch are uniform
for the whole pattern, so the ADI_CD is relatively constant for all lines due to the insensitivity of the lithography to
sublayers. But the non-uniform distribution of the underlying sublayer results in different etch behaviors across the

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 sublayer. In the post-etch SEM (Figure 7b), the line CD within the sublayer region is ~60.6nm, while the non-sublayer
line CD ~66.1nm; in other words, the sublayer loading is ~5.5nm. Such loading effect cannot be captured by a Newron
etch model with an image input only from the primary layer (see Figure 7c). To capture the sublayer loading effects,
ASML-Brion’s Newron etch model utilizes a modeling flow with dual image inputs (primary layer image + sublayer
image) for the deep-learning CNN as shown in Figure 8. Assisted by the sublayer awareness in Newron etch, the
sublayer loading effect is mostly compensated (see Figure 7d), and the model accuracy is improved by ~30% for CD
gauges and ~13% for EP (see Figure 8).

Figure 8. Dual image inputs (primary layer + sublayer) in Newron etch to improve the model accuracy.

3.5 Application for etch OPC tape-out

The Newron etch model’s performance is further evaluated in its application for a model-based etch OPC tape-out as
shown in Figure 9. In this workflow, a tape-out mask (labeled as “tape-out wafer”) with new design rules was used, but
the litho-etch process conditions were the same as the above-mentioned test and real chip wafers. The OPC correction of
the tape-out wafer was performed based on the Newron etch model. Figure 10 demonstrates that compared to the term-
based model, the Newron etch model is superior on the tape-out wafer with >20% improvement in the model verification
accuracy and much smaller EPE in the model contour.

Figure 9. Workflow of the etch model application in model-based etch OPC tape-out.

Figure 10. Model accuracy and contour comparison between the term-based and Newron etch models.

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 4. CONCLUSION
A combinatory workflow integrating eP5 metrology, MXP automated data extraction and deep-learning Newron
etch model is demonstrated in a DUV litho-etch case to improve the OPC model accuracy. Compared to the term-based
model, the Newron model shows significant improvement in the model calibration and prediction. The Newron etch
model shows stable model contours with a high accuracy in mimicking the metrology ground truth. Particularly, the
sublayer-awareness in the Newron etch model form allows for capturing the strong sublayer loading effects, and further
enhancing the model accuracy. The resultant Newron etch model is successfully applied in a etch model-based OPC
tape-out in the real production with a superior performance. In sum, this study proves that the deep-learning based etch
OPC is a promising direction for the semiconductor research and manufacturing.

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