DIGITAL DESIGN AND COMPUTER

ORGANIZATION –3RD SEMESTER BCS302

Course Objectives :
• To demonstrate the functionalities of binary logic system
• To explain the working of combinational and sequential
logic system
• To realize the basic structure of computer system
• To illustrate the working of I/O operations and
processing unit
 DIGITAL DESIGN AND COMPUTER
ORGANIZATION –3RD SEMESTER BCS302

Course Outcomes :
• CO1:Apply the K–Map techniques to simplify various Boolean expressions.
• CO2: Design different types of combinational and sequential circuits along with
Verilog programs.
• CO3: Describe the fundamentals of machine instructions, addressing modes and
Processor performance.
• CO4: Explain the approaches involved in achieving communication between
processor and I/O devices.
• CO5:Analyze internal Organization of Memory and Impact of cache/Pipelining on
Processor Performance.
 DIGITAL DESIGN AND COMPUTER
ORGANIZATION –3RD SEMESTER BCS302

CIE & SEE Marks

• Weightage: CIE – 50 marks (50%), SEE – 50 marks (50%) → Total = 100 marks.
Passing Marks:
• CIE: 40% of 50 = 20 marks
• SEE: 35% of 50 = 18 marks
• Combined Total: Minimum 40% of 100 = 40 marks (CIE + SEE together)
CIE Split
Theory: 25 marks
• 2 Internal Tests – 40( 15 marks) (Two tests of 40 marks each, 1-hour duration).
• Other assessments – 10 marks (assignments, quizzes etc.).
• Must score 40% of 25 = 10 marks in theory CIE to qualify.
 CONTINUOUS INTERNAL EVALUATION (CIE) –
PRACTICAL COMPONENT (IPCC)

Practical: 25 marks
Total Marks: 25
• 15 marks – Continuous evaluation of experiments & laboratory
records
• 10 marks – Laboratory test after completion of all sessions
• Evaluation of Each Experiment

• Each experiment/program (including viva-voce) evaluated on the

same day
• Each lab report evaluated for 10 marks
• Total marks of all experiments scaled down to 15 marks
 CONTINUOUS INTERNAL EVALUATION (CIE) –
PRACTICAL COMPONENT (IPCC)

Practical: 25 marks
• Laboratory Test
• Conducted after completing all experiments
• Duration 2–3 hours
• Conducted for 50 marks, scaled down to 10 marks
• Final CIE Marks (Practical)
• Scaled-down marks of write-up evaluations + test marks = 25 marks
• Minimum qualifying marks: 40% of 25 = 10 marks
 SEMESTER END EXAMINATION
(SEE) – IPCC (THEORY)

• Conducted by University as per the scheduled timetable

• Duration: 3 hours
• Common Question Paper for the course

Question Paper Pattern

• Total Questions: 10 (each for 20 marks)
• From Each Module: 2 questions per module
• Each question may have a maximum of 3 sub-questions
• Covers a mix of topics from that module
•
 SEMESTER END EXAMINATION
(SEE) – IPCC (THEORY)

Answering Pattern
• Students must answer 5 full questions
• Select one full question from each module
Marks & Scaling
• Total marks scored will be scaled down to 50 marks
• Theory portion: has both CIE and SEE components
• Practical portion: only CIE
• Questions in SEE may also include practical-component-related
questions
 SUGGESTED LEARNING
RESOURCES:

Books
• 1. M. Morris Mano & Michael D. Ciletti, Digital Design With an Introduction to
Verilog Design, 5e,Pearson Education.
• 2. Carl Hamacher, ZvonkoVranesic, Saf watZaky, Computer Organization, 5th
Edition, Tata McGrawHill.
• Web links and Video Lectures (e-Resources):
[Link]
INTRODUCTION

❖Binary logic uses variables with only two values (0 and 1).

❖These values can also represent true/false, yes/no, or on/off states.

❖It forms the basis of Boolean algebra, which governs operations on

binary values.
❖Boolean algebra provides the rules for manipulating binary variables.

❖It is essential for digital logic circuits and binary signal processing.

❖This concept underpins the design and analysis of modern

computing systems.
WHAT IS BINARY LOGIC?

• Variables take exactly two values: 0 or 1

• Also called logical values: true/false, yes/no
• Used in digital systems & circuits
 DEFINITION OF BINARY LOGIC

Definition: Binary logic consists of binary variables and a set of logical operations.

•Variables: Represented by letters (A, B, C, x, y, z, etc.).

•Values: Each variable can take only two distinct values — 1 and 0.

•Basic Operations:

•AND
•OR
•NOT

Result: Each operation produces a binary output (often denoted by z).

 BASIC GATES

1. AND Operation 2. OR Operation

• Symbol: Dot (·) or no operator at all • Symbol: Plus sign (+).
(xy).
Example: 𝑥 + 𝑦 = 𝑧→ “x OR y equals z.”
Example: 𝑥 ⋅ 𝑦 = 𝑧 or 𝑥𝑦 = 𝑧→ “x AND • Logic:
y equals z.”
• 𝑧 = 1if 𝑥 = 1or 𝑦 = 1 or both are 1.
• Logic: • If 𝑥 = 0 and 𝑦 = 0, then 𝑧 = 0.
• 𝑧 = 1 only if 𝑥 = 1 and 𝑦 = 1.
Otherwise, 𝑧 = 0.
 BASIC GATES

3. NOT Operation (Complement)

• Symbol: Prime (x′) or overbar (𝑥.)
᪄
Example: 𝑥′ = 𝑧 or 𝑥᪄ = 𝑧“ →NOT x equals z.”
• Logic:
• If 𝑥 = 1, then 𝑧 = 0.
• If 𝑥 = 0, then 𝑧 = 1.

• Other name: Complement Operation (changes 1 to 0 and 0 to 1).

BASIC LOGICAL OPERATIONS

• Three fundamental operations:

• AND (·)
• OR (+)
• NOT (′ or overbar)
 TRUTH TABLES

• A truth table lists all possible combinations of input variables and their corresponding
outputs.
• It shows the relationship between input values (x and y) and the result (z).
• For AND and OR, list all possible input pairs of x and y; for each pair, write the output.
• Truth tables for AND, OR, and NOT clearly demonstrate how each logical operation works.
 BINARY LOGIC VS. BINARY
ARITHMETIC

• Binary logic resembles binary arithmetic, but they are not the same.
• AND is similar to multiplication, and OR is similar to addition in appearance.
• The symbols used for AND (·) and OR (+) are the same as multiplication and
addition.
• Key difference:
• Arithmetic variable → a number that may have many digits.
• Logic variable → always single-bit, either 1 or 0.
• Example:
• In binary arithmetic: 1 + 1 = 10(2 in decimal).
• In binary logic: 1 + 1 = 1(“1 OR 1 equals 1”).
 LOGIC GATES

Definition: Logic gates are electronic circuits that operate on one or more input signals
produce a single output signal.

Analog vs Digital Signals:

•Electrical signals naturally exist as analog (continuous range of values).
•In digital systems, these signals are interpreted as binary values (0 or 1).

Binary Representation:
•Example: Logic 0 = 0 V, Logic 1 = 3 V.
•Each logic level has an acceptable voltage range.
 LOGIC GATES

Operation of Logic Circuits:

• Input terminals accept binary signals within the allowable range.
• Output terminals produce binary signals within the specified range.
• The intermediate region is crossed only during state transitions.

Information Processing:
•Any information (computing/control) can be processed by passing binary signals
through combinations of logic gates.
•Each binary signal represents a specific binary variable.

Interpretation:
•When a physical signal is in a given range, it is interpreted as either a logic 0 or logic
1.
 GRAPHIC SYMBOLS AND GATE
BEHAVIOR
• Gate Symbols:
• The three basic logic gates — AND,
OR, and NOT — have
standardized graphic symbols
(shown in Fig. 1.4).
• These symbols represent
hardware blocks producing logic-
1 or logic-0 outputs based on input
conditions.
TIMING DIAGRAMS:

Input Signals:
For AND and OR gates with two inputs (x and y),
possible input combinations: 00, 01, 10, 11.
Outputs depend on these combinations (shown in Fig.
1.5).

Timing Diagrams:
Show the idealized response of each gate to
all input combinations over time.
Horizontal axis = time;
Vertical axis = signal level.
Low level = logic 0, high level = logic 1.
In reality, transitions between logic values are
fast but not instantaneous.
 CONTINUED

Gate Behavior:
•AND Gate → Output is 1 only if both inputs are 1.
•OR Gate → Output is 1 if any input is 1.
•NOT Gate (Inverter) → Output is the opposite (complement) of the input.
•Inverter Name:
•NOT gate is called an inverter because it inverts the logic sense of the input
signal (shown clearly in timing diagrams).
 CONTINUED

AND & OR Gates with More than Two Inputs

• Multiple Inputs:
• Logic gates can have more than two inputs.
• Three-Input AND Gate:
• Output = logic 1 only if all three inputs are logic 1.
• Output = logic 0 if any one input is logic 0.
• Four-Input OR Gate:
• Output = logic 1 if any one (or more) of the inputs is logic 1.
• Output = logic 0 only if all four inputs are logic 0.
 BASIC THEOREMS AND PROPERTIES
OF BOOLEAN ALGEBRA

•Definition:

•The duality principle states that every algebraic expression deducible

from the postulates of Boolean algebra remains valid if the operators
and identity elements are interchanged.

•Operators & Identity Elements:

•OR AND (swap the operators).
•1 0 (swap the identity elements).
 BASIC THEOREMS AND PROPERTIES
OF BOOLEAN ALGEBRA

• Two-Valued Boolean Algebra:

• The set 𝐵= {1, 0}.
• Identity elements are also 1 and 0.
• Applications:
• To obtain the dual of an algebraic expression:
• Interchange OR and AND.
• Replace 1’s by 0’s and 0’s by 1’s.
 BASIC THEOREMS AND PROPERTIES
OF BOOLEAN ALGEBRA
• Postulates [Link]:
• Postulates are basic axioms of Boolean algebra — they do not require proof.
• Theorems are derived from the postulates and therefore must be proven.
• Duality of Theorems:
• Theorems are often listed in pairs; each theorem is the dual of the one paired
with it.
• This reflects the duality principle of Boolean algebra.
• Proof Structure:
• Proofs for theorems with one variable are usually presented first.
• Each step of a proof cites the postulate number that justifies it.
 BASIC THEOREMS AND PROPERTIES
OF BOOLEAN ALGEBRA

• Table 2.1:
• Lists six theorems of Boolean algebra.
• Lists four postulates of Boolean algebra.
• Importance:
• These theorems and postulates form the foundation for more
complex Boolean expressions and simplifications.
•Observation: Theorem 1(b) is the dual of theorem 1(a).
•Proof relationship: Every step in the proof of 1(b) is the dual of the corresponding
step in the proof of 1(a).
•General rule: You can obtain a dual theorem by interchanging AND OR and 1
0 everywhere in the original theorem and its proof.
BOOLEAN OPERATOR
PRECEDENCE

Precedence Operator Meaning

Evaluate first
1 Parentheses ()
(grouping).
Complement
2 NOT ¬ or ' (highest unary
operator).
3 AND · Conjunction.
Disjunction (lowest
4 OR +
precedence).
 INTRODUCTION

•Boolean algebra is the mathematical foundation of digital

logic design.
•It deals with binary variables (0 and 1) and logical
operations like AND, OR, NOT.
•Understanding basic theorems helps in simplifying logic
expressions and designing efficient circuits.
•Duality principle is a key property that allows easy
derivation of equivalent expressions by interchanging AND
OR and 0 1.
 DUALITY PRINCIPLE IN BOOLEAN
ALGEBRA
1. Widely used in logic simplification and circuit design.
Example (Optional on Slide):
Original: 𝐴 + 0 = 𝐴
Dual: 𝐴 ⋅ 1 = 𝐴
BOOLEAN FUNCTIONS

• Formed using binary variables, constants, and logic

operations
• Example: 𝐹1 = 𝑥 + 𝑦᪄ 𝑧
• 𝐹1 = 1if 𝑥 = 1OR 𝑦 = 0and 𝑧 = 1
LOGIC CIRCUIT

Convert algebraic expression → Logic Diagram

• Inverter for 𝑦᪄
• AND gate for 𝑦᪄ 𝑧
• OR gate for 𝑥 + 𝑦᪄ 𝑧
 MULTIPLE REPRESENTATIONS

•One truth table → one

function
•But many algebraic forms
possible
•Same function can be
simplified using Boolean laws
F2 = x`y`z + x`yz + xy` = x`z(y`
+ y) + xy` = x`z + xy`
Simplification Benefits
• Fewer gates and connections

• Lower cost, higher speed

• Easier to implement and test
ALGEBRAIC MANIPULATION IN
BOOLEAN ALGEBRA
Concept
• Boolean expressions → implemented with logic gates
• Term → needs a gate
• Literal → single variable (complemented or not)
• Goal: reduce terms and literals to simplify the circuit
 TERMS & LITERALS EXAMPLE

• Example circuit (Fig.

2.2a): 3 terms, 8
literals
• Simplified circuit (Fig.
2.2b): 2 terms, 4
literals
• Fewer terms/literals
→ fewer gates &
inputs
 CANONICAL FORMS

Boolean functions expressed as a sum of minterms or product of

maxterms are said to be in canonical form
• Sum of Minterms (SOM): Formed from 1s in the truth table
• Product of Maxterms (POM): Formed from 0s in the truth table
• Both SOM and POM = canonical forms
DIGITAL LOGIC GATES

• Concept
• Boolean functions use AND, OR, NOT as basic operations
• Other gates are also possible & practical in digital design
• Factors in gate choice:
• Feasibility & cost of implementation
• Extensibility to multiple inputs
• Properties like commutativity & associativity
• Ability to implement Boolean functions alone or with other gates
• Eight Standard Logic Gates
• Complement (NOT / inverter)
• Transfer (buffer)
• AND
• OR
• NAND
• NOR
• Exclusive-OR (XOR)
• Equivalence (XNOR)

• NAND and NOR – Universal Gates

1. NAND & NOR = complements of
AND and OR
2. Easy to build with transistors
3. Any Boolean function can be
implemented using only NAND or
only NOR gates
4. Widely used in ICs for cost and
simplicity
 POSITIVE AND NEGATIVE
LOGIC
Binary Signals
• Inputs/outputs of gates have two signal levels (except during transitions)
• One level represents Logic 1, the other Logic 0
• High level = H, Low level = L
• Logic Assignments
Positive Logic:
H = Logic 1, L = Logic
0
Negative Logic:
L = Logic 1, H = Logic
0
The terms “positive” and
“negative” refer to the
assignment, not actual
voltages
PURPOSE OF MANIPULATION

• Achieve a simpler circuit

• Save hardware cost
• Improve speed and reliability
 METHODS OF SIMPLIFICATION

1. Algebraic manipulation using Boolean rules

2. Map method (Karnaugh map) for up to 5 variables
3. Computer minimization programs for complex circuits
BOOLEAN FUNCTIONS TO MINIMUM NO
OF LITERALS
SUMMARY

• Boolean algebra simplifies digital circuit design

• Truth tables, algebraic expressions, and logic diagrams are
interrelated
• Simplification = optimized hardware
 3.1 GATE-LEVEL MINIMIZATION

Concept
• Gate-level minimization = finding an optimal gate-level implementation
of Boolean functions
• Objective: minimum number of gates and inputs → simpler, cheaper, faster
circuit

•Directly affects cost, size, and performance of digital systems

•Foundation of digital circuit optimization
•Helps designers understand how to simplify logic manually
 CHALLENGES

• Manual minimization becomes hard with more than a few inputs

• Complexity increases exponentially with number of variables
• Need structured methods and tools
 WHY MINIMIZE BOOLEAN
FUNCTIONS?

• Complexity of logic gates = directly related to complexity of Boolean expression

• Truth table is unique, but algebraic expressions can vary
• Simplification → fewer gates and inputs → cheaper, faster circuits
• Limits of Algebraic Simplification
• No fixed step-by-step rules
• Manual manipulation can be awkward & error-prone
• Need a structured graphical method
WHAT IS A KARNAUGH MAP?

• Also called K-map

• Pictorial form of a truth table
• Made of squares, each square = one minterm
• Boolean function = sum of minterms → highlighted
squares
HOW IT WORKS

• Group adjacent 1s (or 0s for maxterms) in powers of 2

• Recognize patterns to derive simplified expressions
• Result always in Sum of Products (SOP) or Product of
Sums (POS) form
BENEFITS OF K-MAPS

• Visual method → easy to spot simplifications

• Reduces number of terms and number of literals
• Directly produces a simpler gate-level circuit
• Handles up to 5 or 6 variables manually
TWO-VARIABLE KARNAUGH MAP
(K-MAP)
Structure of a 2-Variable K-Map
• Two variables → x and y
• Total minterms = 22 = 4
• K-map consists of 4 squares
• Each square = one minterm (m₀, m₁, m₂, m₃)
 VARIABLE ASSIGNMENT

•Rows represent x’ and x Representing Functions on K-Map

•Columns represent y’ and y •Place 1s in squares for minterms included in
the function
•Place 0s or leave blank for others

y’
y (1)
(0)
x’
m₀ m₁
(0)
x
m₂ m₃
(1)
VARIABLE ASSIGNMENT

• Rows: x’ (0), x (1)

• Columns: y’z’ (00), y’z (01), yz (11), yz’ (10)
• Each cell = one minterm 𝑚0 to 𝑚7
 THREE-VARIABLE KARNAUGH MAP
(K-MAP)
Structure of 3-Variable K-Map
• Three variables → x, y, z
• Total minterms = 23 = 8
• Map consists of 8 squares
• Squares arranged in Gray-code order (only one bit
changes between adjacent squares)
x\yz 00 (y’z’) 01 (y’z) 11 (yz) 10 (yz’)
x’ m₀ m₁ m₃ m₂
x m₄ m₅ m₇ m₆
 ADJACENT SQUARES

• Any two adjacent

squares differ by only one
variable
(primed/unprimed)
• Horizontal or vertical
adjacency (not diagonal)
• Adjacent minterms can be
combined to remove
differing variable
 EXAMPLE

Simplify the Boolean function For the Boolean function

F = AC + AB + ABC + BC
F (x, y, z) = (2, 3, 4, 5)
(a) Express this function as a sum of
Simplify the Boolean function
minterms.
F (x, y, z) = (3, 4, 6, 7) (b) Find the minimal sum-of-products
Simplify the Boolean function expression.

F (x, y, z) = (0, 2, 4, 5, 6)
FOUR-VARIABLE K-MAP

Structure of 4-Variable K-Map

• Variables: w, x, y, z
• Total minterms = 24 = 16
• Map consists of 16 squares (cells)
• Rows & columns arranged in Gray code sequence (only
one bit changes at a time)
VARIABLE ASSIGNMENT MAP

wx\yz 00 (y’z’) 01 (y’z) 11 (yz) 10 (yz’)

00 (w’x’) m₀ m₁ m₃ m₂
01 (w’x ) m₄ m₅ m₇ m₆
11 (wx ) m₁₂ m₁₃ m₁₅ m₁₄
10 (wx’) m₈ m₉ m₁₁ m₁₀
IDENTIFYING MINTERMS

• Combine row number + column number in binary

• Convert to decimal = minterm number
• Example: Row 11 & Column 01 → 1101₂ = 13 → cell =
m₁₃
 ADJACENCY IN 4-VARIABLE K-
MAP

• Adjacent squares share

three identical
variables (differ in one
variable only)
• Map edges wrap around
(top with bottom, left
with right)
• Example: m₀ adjacent to
m₂, m₃ adjacent to m₁₁
GROUPING RULES

Group Size Literals in Result

1 square 4 literals
2 adjacent squares 3 literals
4 adjacent squares 2 literals
8 adjacent squares 1 literal
16 squares Function = 1 (no variables)
KEY SIMPLIFICATION POINTS

• Larger groups → fewer literals

• Use edge-wrapping to form bigger groups
• Group horizontally, vertically, but not diagonally
• Aim for largest possible groups first
WHY USE 4-VARIABLE K-MAPS

• Visual simplification of complex functions

• Produces simpler Boolean expressions
• Minimizes gates and inputs in circuit design
• Simplify the Boolean function
• F (w, x, y, z) = (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
 KEY DEFINITIONS

Implicant: An implicant can be defined as a product/minterm term in Sum of Products

(SOP) or sum/maxterm term in Product of Sums (POS) of a Boolean function.
For example, consider a Boolean function,
F = AB + ABC + BC. Implicants are AB, ABC, and BC.
• Prime Implicant (PI):
Largest possible grouping of adjacent squares (power of 2)
→ Cannot be combined further.
• Essential Prime Implicant (EPI):
A PI that covers at least one minterm not covered by any other PI
→ Must be included in the final expression.
PRIME IMPLICANTS IN K-MAPS

Why We Group Squares

• Cover all minterms of the function
• Minimize the number of terms in the expression
• Avoid redundant terms (already covered minterms)
• Sometimes multiple simplified expressions are possible
 PRIME IMPLICANTS EXPLAINED

A prime implicant is a product term obtained by combining the maximum

possible number of adjacent squares in the map.

The prime implicants of a function can be obtained from

the map by combining all possible maximum numbers of
squares.
1. This means that a single 1 on a map represents a prime
implicant if it is not adjacent to any other 1’s.
2. Two adjacent 1’s form a prime implicant, provided that they are
not within a group of four adjacent squares.
3. Four adjacent 1’s form a prime implicant if they are not within a
group of eight adjacent squares.
4. Eight adjacent 1’s form a prime implicant if they are not within a
group of sixteen adjacent squares,
 ESSENTIAL PRIME
IMPLICANTS EXPLAINED
• These are those subcubes(groups) that cover at least one minterm that can't be
covered by any other prime implicant. Essential prime implicants(EPI) are
those prime implicants that always appear in the final solution.

• After finding all PIs, identify which are essential

• Essential = covers at least one unique
minterm
• Non-essential PIs may still be required to cover
remaining minterms
 Finding Prime Implicants
1. Simplify the following Boolean function using a K-
Map and identify all prime implicants:
f(A, B, C, D) = ∑(0, 1, 2, 5, 8, 9, 10, 14)
2. Identification of Prime and Essential Prime
Implicants
- For the following Boolean function, identify all prime
implicants and essential prime implicants:
f(A, B, C, D) = ∑(4, 5, 6, 7, 12, 13, 14, 15)
3. Minimization with Don't Care Conditions
- Given the Boolean function with don't care conditions, use a
K-Map to minimize it:
f(A, B, C) = ∑(0, 1, 2, 5, 7) + d(3, 6)
4. Finding Essential Prime Implicants
- For the following function, find the essential prime implicants
using a K-Map:
f(A, B, C, D) = ∑(1, 3, 7, 11, 15) + d(0, 2, 5)
 PROCEDURE TO FIND SIMPLIFIED
EXPRESSION

1. Fill K-map with 1s for minterms.

2. Group maximum adjacent 1s → find all prime implicants.
3. Mark minterms covered by only one PI → essential prime implicants.
4. Combine all EPIs.
5. Add other PIs (if needed) to cover leftover 1s.
6. Write final simplified Boolean expression.
 NAND & NOR IMPLEMENTATION
IN DIGITAL CIRCUITS
• Why NAND/NOR Gates
• Easier to fabricate using electronic components.
• Basis for all IC digital logic families.
• Used extensively in practical digital designs.
UNIVERSAL GATES

• NAND and NOR gates are called universal gates.

• Any Boolean function can be implemented using only NAND or
only NOR gates.
 THE PROCEDURE FOR OBTAINING THE
LOGIC DIAGRAM FROM A BOOLEAN
FUNCTION IS AS FOLLOWS:

1. Simplify the function and express it in sum-of-products form.

2. Draw a NAND gate for each product term of the expression that has at least two
literals. The inputs to each NAND gate are the literals of the term. This procedure
produces a group of first-level gates.
3. Draw a single gate using the AND-invert or the invert-OR graphic symbol in the
second level, with inputs coming from outputs of first-level gates.
4. A term with a single literal requires an inverter in the first level. However, if the
single literal is complemented, it can be connected directly to an input of the second level
NAND gate.
 TWO LEVEL IMPLEMENTATION

• In Fig. 3.18 (c), the output NAND gate is

redrawn with the AND-invert graphic
symbol.
• In drawing NAND logic diagrams, the
circuit shown in either Fig. 3.18(b) or (c) is
acceptable.
• The one in Fig. 3.18(b) is in mixed notation
and represents a more direct relationship
• to the Boolean expression it implements.

F = ((AB)`(CD)`) `= AB + CD
EXAMPLE

Implement the following Boolean function with NAND gates:

• F (x, y, z) = (1, 2, 3, 4, 5, 7) SIMPLIFY USING K MAP
 MULTILEVEL NAND CIRCUITS

• In two-level logic, Boolean functions are implemented directly in sum-of-

products or product-of-sums form using AND–OR or OR–AND gates.
• In multilevel logic, the function is algebraically factorized to reduce the
number of gate inputs and wiring. The expression is first written using
AND, OR, and NOT operations, then arranged in multiple stages.
• Finally, the circuit can be converted into an all-NAND or all-NOR
implementation using DeMorgan’s theorems, because NAND and NOR are
universal gates.
 EXAMPLE
Step Expression Implementation

Original (two-level SOP) 𝐴𝐶𝐷 + 𝐴𝐵 + 𝐵𝐶 ′ 3 AND gates + 1 OR gate

Factorized (three-level) F = A (CD + B) + BC ’ Multiple smaller gates

•A Boolean expression can be implemented either

in standard sum-of-products (two levels) or as a
multilevel circuit with alternating AND/OR gates.
•In the example (Fig. 3.20), the circuit uses four
levels: AND → OR → AND → OR.

•Converting to NAND: Replace each AND gate

with an AND-invert symbol and each OR gate
with an invert-OR symbol.

•As long as there are two bubbles on the same

line (one at the output of a gate and one at the
input of the next), the logic remains
unchanged.

•If an input literal (such as B) ends up with an

extra bubble (extra inversion), you compensate by
using its complement (B′) at that point.
THE GENERAL PROCEDURE FOR CONVERTING A
MULTILEVEL AND–OR DIAGRAM INTO AN ALL-NAND
DIAGRAM USING MIXED NOTATION IS AS FOLLOWS:

1. Convert all AND gates to NAND gates with AND-invert graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic symbols.
3. Check all the bubbles in the diagram. For every bubble that is not
compensated by another small circle along the same line, insert an
inverter (a one-input NAND gate) or complement the input literal

F = (AB‘ + A‘B)(C + D‘)

F = (AB‘ + A‘B)(C + D‘) •The function in Fig. 3.21(a) is
implemented with three levels of
AND–OR gating.
•Conversion to NAND (mixed
notation) in Fig. 3.21(b):
•Every AND gate → AND-invert (NAND
symbol).
•Every OR gate → invert-OR (NOR-
type symbol).
•Extra bubbles at inputs C and D’
cause those inputs to be
complemented, so they must be
changed to C′ and D at those points.
•The bubble on the final NAND gate
output complements the entire output;
therefore an extra inverter (or NAND
with tied inputs) is added at the
output to restore the original (non-
inverted) logic level.
NOR IMPLEMENTATION •NOR is the dual of NAND — all
procedures for NAND logic have
corresponding duals for NOR logic.
•NOR gates are universal: any
Boolean function can be implemented
using only NOR gates.
•Complement: a one-input NOR acts
as an inverter.
•OR operation: done using two NOR
gates.
•AND operation: done using a NOR
gate with inverters at each input (by
DeMorgan’s theorem).
•Mixed notation:
•OR-invert symbol = OR followed by
complement.
•Invert-AND symbol = inputs
complemented, then AND.
•Both symbols describe the same NOR
operation because of DeMorgan’s
theorem.
 TWO-LEVEL IMPLEMENTATION

• A two-level NOR implementation is based on the product-of-sums (POS) form of a

function.
• The POS form is obtained from a Karnaugh map by grouping the 0’s and then complementing
the expression.
• In hardware:
• First level – OR gates produce each sum term.
• Second level – an AND gate multiplies the sum terms.
• Converting to NOR gates:
• Change each OR gate to a NOR gate (OR-invert symbol).
• Change the AND gate to a NOR gate (invert-AND symbol).
• Single literals feeding the second-level gate must be complemented to maintain logic
correctness.
• This procedure yields a full NOR implementation of a product-of-sums expression, as shown in
Fig. 3.24.
 EXAMPLE-IMPLEMENT USING NOR

1.F = (A + B)(C + D)E 2. F = (AB‘ + A‘B)(C + D‘)

 NOR IMPLEMENTATION

• In digital logic design, especially when working with only NOR (or NAND)
gates, we often want to see the equivalent logic in terms of basic AND-OR
logic (i.e., SOP form).
• A NOR diagram consists only of NOR gates (which are OR gates followed
by NOT gates). Each NOR gate can be rewritten using DeMorgan's
Theorems.
 DON’T-CARE CONDITIONS IN K-
MAPS
Concept
• Some input combinations never occur or are not specified in the design.
• For these combinations, the output value doesn’t matter.
• These are called Don’t-Care Conditions (X).
• Using X’s allows further simplification of Boolean expressions.
REPRESENTING DON’T-CARE
CONDITIONS ON K-MAPS

• 1 → Output must be 1.
• 0 → Output must be 0.
• X → Don’t-Care (can be treated as 0 or 1 to simplify).
WHY DON’T-CARE CONDITIONS
ARISE

• Unused binary codes (e.g., BCD: 0000–1001 valid, 1010–

1111 unused).
• Impossible or irrelevant input combinations.
• Unspecified states in sequential circuits.
HOW TO USE THEM

• Place X in K-map cells for don’t-care minterms.

• When grouping 1’s:
• You may include X’s to form larger groups.
• You may ignore X’s if they don’t help.

• The goal is always the largest groupings → minimum

expression.
PROCEDURE

• Fill K-map with 1s for specified minterms.

• Mark X for don’t-care minterms.
• Make largest possible groupings of 1’s and X’s
combined.
• Derive simplified Boolean expression.
Simplify the Boolean function
• F (w, x, y, z) = (1, 3, 7, 11, 15)
• which has the don’t-care conditions
• d (w, x, y, z) = (0, 2, 5)
 HARDWARE DESCRIPTION
LANGUAGE
1. Motivation for Using HDLs
• Manual circuit design is feasible only for very small circuits; practical circuits
require computer-based design tools.
• These tools reduce the risk of flawed designs, save time and cost, and
allow testing in software before fabrication.
2. What is an HDL?
• A computer-based language used to describe digital hardware in textual form.
• Similar to programming languages like C but oriented to hardware structures and logic
behavior.
• Can represent logic diagrams, truth tables, Boolean expressions, and high-level
behavior.
• Describes relationships between input and output signals.
 . ROLES OF HDLS

Documentation: Human- and machine-readable descriptions of digital systems; easy

to store, edit, and exchange.
Design Entry: Captures functionality in Boolean equations, truth tables, gate
netlists, or behavioral models.

Simulation & Verification: Predicts hardware behavior before fabrication using

test benches.
Logic Synthesis: Converts HDL models into a list of components and connections
(netlist) suitable for fabrication or PCB layout.
Timing Verification: Ensures circuits meet required speeds despite propagation delays.
Fault Simulation: Compares ideal vs. faulty circuits to develop test patterns ensuring
defect-free devices.
 ADVANTAGES OF USING HDLS

1. Faster design cycles and reduced prototyping cost.

2. Formal verification and simulation detect errors early.
3. Standardized exchange of designs between teams and tools.
4. Scalable for very large and complex integrated circuits.
 MODULES IN VERILOG

• A module is the fundamental descriptive unit in Verilog.

• It begins with the keyword module and ends with endmodule.
• Inside a module:
1. Inputs and outputs define the circuit’s interface with its environment.
2. Internal connections (wires) describe interconnections between gates.
3. The actual logic is implemented using primitives or other modules.
 KEYWORDS & SYNTAX RULES

• Verilog has ~100 keywords (e.g., module, endmodule, input, output, wire, and, or, not).
• Case sensitive: not ≠ NOT.
• Comments:
• Single-line: // comment text
• Multi-line: /* comment text */
• Blank spaces are ignored except inside identifiers, operators, or numbers.
• Identifiers (module names, wire names, etc.):
1. Use alphanumeric and underscore _.
2. Must start with a letter or underscore.
3. Case sensitive.
 Interface:

The port list connects the module to its environment (outside world).

Inputs vs Outputs:
Inputs get their values from the environment; outputs are determined by the
circuit’s internal logic.

•Syntax:
•Ports are listed inside parentheses ().
•Ports are separated by commas ,
•The statement ends with a semicolon ;.
Keywords Used input → declares input ports and output → declares output
ports
• wire → declares internal connections (like virtual wires inside your module)
 PRIMITIVE GATES AND
INSTANTIATION

• Predefined gates include and, or, not, etc.

• Each usage of a gate is an instantiation
(like using a physical gate on a board).
• Format: gate_name instance_name
(output, input1, input2, ...);
• Output must be listed first.
Example:
• or G3 (D, w1, E); // OR gate named G3,
output D, inputs w1 and E
 DECLARATION VS
INSTANTIATION

• Declaration = describing what the module is and how it

behaves (like a blueprint).
• Instantiation = using that blueprint to build a real block inside
another design.
• Predefined primitives (like and, not, or) are not declared by you;
they are already built into the language. You only instantiate them.
 ORDER OF STATEMENTS

• In Verilog (unlike C programs), the order of gate instantiations

does not represent sequence of execution.
• The HDL describes connections, not a step-by-step program.
 END OF MODULE

• Every module ends with endmodule.

• No semicolon after endmodule.
 THERE 3 TYPES OF MODELLING:

• Dataflow modeling describes a system in terms of how data flows through the
system.
• Behavioral modeling describes a system’s behavior or function in an algorithmic
fashion.
• Structural modeling describes a system in terms of its structure and
interconnections between components.
 Write a Verilog program for OR gate using i)dataflow modelling
ii)Behavioral modelling and iii)structural modelling.

// and_dataflow.v // and_behavioral.v
module and_behavioral (
module and_dataflow ( output reg y,
output y, input a, b
);
input a, b always @ (a or b)
); begin
if (a == 1'b1 && b == 1'b1)
assign y = a & b; y = 1'b1;
// Dataflow modeling else
y = 1'b0;
endmodule end
endmodule
 // Top-level: structural connection
// and_structural.v
module and_structural (
output y,
// Submodule: basic AND gate
input a, b
module and_gate_basic (
);
output y,
wire temp;
input a, b
);
// Instantiate the basic AND gate
assign y = a & b;
and_gate_basic U1 (.y(temp), .a(a), .b(b));
endmodule
// Connect output
assign y = temp;
endmodule
 SIMPLE EXAMPLE OF VERILOG MODULE
WITH PORTS AND PRIMITIVES
module Simple_Circuit (A, B, C, D, E);
output D, E; // Outputs
input A, B, C; // Inputs
wire w1; // Internal wire

and G1 (w1, A, B); // Gate instance: AND gate

not G2 (E, C); // Gate instance: NOT gate
or G3 (D, w1, E); // Gate instance: OR gate

endmodule
 WHY GATE DELAYS MATTER

• Real gates don’t switch instantly — they have a propagation

delay.
• In simulation, you may want to model these delays to predict real-
world timing behavior.
• Verilog lets you specify this delay so your simulation is more realistic.
 The # Symbol – Delay Operator

In Verilog, specify delays with a hash sign # followed by a

number:

and #5 G1 (w1, A, B); // AND gate with 5 time units of delay

This means: when A or B changes, w1 will update after 5 time

units.
 THE \TIMESCALE` DIRECTIVE

Before your module code, you specify the time unit and time
precision:

`timescale <time_unit>/<time_precision>

Example :
‘timescale 1ns/1ps
time_unit = 1 ns
time_precision = 1 ps (0.1ns smallest step for simulation)
All delay numbers now correspond to 1 ns units in this case.
#5 → 5 ns delay.
 EXAMPLE OF GATE DELAYS +
TIMESCALE
`timescale 1ns/1ps // Time unit = 1ns, precision =
1ps
module Simple_Circuit (A, B, C, D, E);
output D, E;
input A, B, C;
wire w1;

and #5 G1 (w1, A, B); // AND gate with 5ns delay

not #2 G2 (E, C); // NOT gate with 2ns delay
or #3 G3 (D, w1, E); // OR gate with 3ns delay
endmodule
SIMULATION TIMELINE EXAMPLE

• If at time 0ns A and B change:

• w1 changes at time 30 ns
• E changes at time 10 ns after C changes
• D changes at time 20 ns after either w1 or E changes
• This models the realistic behavior of your circuit in software.
 TEST BENCH

• In order to simulate a circuit with an HDL, it is necessary to apply

inputs to the circuit so that the simulator will generate an
output response.
• An HDL description that provides the stimulus to a design is
called a test bench
• A test bench is a module containing a signal generator and an
instantiation of the model that is to be verified.
 TEST BENCH

• Note that the test bench ( t_Simple_Circuit_prop_delay ) has no input

or output ports, because it does not interact with its environment
• prefix t_ concatenated with the name of the module that is to be
tested by the test bench
• Within the test bench, the inputs to the circuit are declared with
keyword reg and the outputs are declared with the keyword wire
• The module Simple_Circuit_prop_delay is instantiated with the instance
name M1. Every instantiation of a module must include a unique
instance name
 TEST BENCH

1. No hardware generators are used — HDL verification is done entirely in

software using a digital simulator.
2. Signal waveforms for inputs are modeled in Verilog using statements
that specify values and timing transitions.
3. The initial keyword starts a set of statements that execute once when
simulation begins.
4. These statements are grouped using begin ... end, forming a block
statement that executes sequentially (top to bottom).
5. Purpose — Used in testbenches to generate input waveforms for
simulation.
6. Delay control (#) — A delay value before a statement (e.g., #100)
postpones execution by that many simulation nanoseconds.
•Initially: A, B, C = 0 (binary 0).
•After 100 ns, all change to A, B, C = 1.
•Simulation ends at 200 ns.
•Simulation termination — The $finish
system task stops the simulation.
• using a test bench is similar to testing actual hardware by attaching signal generators
to the inputs of a circuit and attaching probes (wires) to the outputs of the circuit.
• (The interaction between the signal generators of the stimulus module and the
instantiated circuit module is illustrated in Fig. below .)
 TEST BENCH

•Waveform timing —
•Total duration: 200 ns.
•E is unknown (X) for first 10 ns, then 1 → 0 at 110 ns.
•D is unknown for first 30 ns, then 1 → 0 at 130 ns, and 0 → 1 at
150 ns.
Timing diagram (Figure above) visually shows how the simulator
produces these transitions over time — fully software-generated
waveforms.
COMBINATIONAL CIRCUITS IN HDL CAN BE
DESCRIBED IN THREE EQUIVALENT WAYS:

1. Using Boolean equations (assign statements)

2. Using circuit diagrams
3. Using truth tables
 USING BOOLEAN EQUATIONS

1. Combinational logic in Verilog can be described using

Boolean equations with continuous assignment
statements.
2. A continuous assignment uses the keyword assign,
followed by a Boolean expression that defines the logic
relationship.
•Operators used in Verilog Boolean expressions:
•& → AND
•| → OR
•~ → NOT (complement)
 EXAMPLE

•Example Boolean equations:

•E=A+BC+B′DE
•F=B′C+BC′D′
1. The circuit thus has four inputs (A, B, C, D) and two outputs (E, F).
2. These equations are implemented in Verilog using two assign statements.

1. The simulator continuously monitors inputs (A, B, C, D), and automatically

updates outputs (E, F) whenever any input changes.
2. This mechanism is called continuous assignment because the relationship
between inputs and outputs is permanent during simulation.
3. It behaves just like real combinational logic, having a gate-level
equivalent circuit — also called implicit combinational logic.
 USER-DEFINED PRIMITIVES

•Verilog provides built-in logic gates such as and, or, not, etc.
•These are called system primitives — predefined by the Verilog language.
•System primitives behave as basic gate-level components and do not need
to be defined by the user.
•Caution: Other programming or HDL languages may use the same words
(and, or, etc.) differently — their meaning in Verilog is specific to gate modeling.
•Users can define their own custom primitives, called User-Defined
Primitives (UDPs), to model specialized logic behavior.
•UDP circuits are described in tabular form, usually using a truth table to
define input-output relationships.
•UDP declarations use the keyword pair:

primitive ... endprimitive

 USER-DEFINED PRIMITIVES

• A UDP typically defines:

• Inputs and output
• Truth table specifying how output responds to input combinations
• UDP usage: helpful for describing small, custom logic functions that are
not built-in (e.g., special flip-flops, custom gates).
Example concept:
• A user-defined AND gate UDP could specify output 1 only when both
inputs are 1, expressed directly in a truth table.
• Purpose: UDPs allow precise, compact modeling of logic behavior
without using full structural or behavioral constructs.
 RULES FOR UDP CREATION

UDP Declaration
• A User-Defined Primitive begins with the keyword primitive followed by its name
and port list.
• It ends with the keyword endprimitive.
Output Specification
• A UDP must have exactly one output, and it must be listed first in the port list.
• The output is declared using the keyword output.
Input Specification
• There can be one or more inputs.
• Inputs are declared using the keyword input.
• The order of input declaration must match the order of inputs in each truth table
row.
 RULES FOR UDP CREATION

• Truth Table Definition

• The truth table is enclosed between table and endtable keywords.
• Each row represents one combination of inputs and its corresponding output.
• Input values are listed in order, followed by a colon (:), then the output value, ending
with a semicolon (;).
• Logic Values Used
• Typical values used in the table:
• 0 = logic 0
• 1 = logic 1
• x = don’t care (unknown)
• ? = don’t care (input can be either 0 or 1)
 RULES FOR UDP CREATION

• Execution Rule
• During simulation, the Verilog simulator refers
to the truth table to determine the output
value for any given input combination.
• Termination
• The UDP declaration ends with the keyword
endprimitive — no endmodule is used.
EXAMPLE -AND GATE

primitive and_udp (Y, A, B);

output Y;
input A, B;

table
// A B : Y
0 0 : 0;
0 1 : 0;
1 0 : 0;
1 1 : 1;
endtable
endprimitive
A User-Defined Primitive (UDP) can be instantiated inside other Verilog
modules, just like built-in system primitives (e.g., and, or, not).
Circuit_with_UDP_02467 (E, F, A, B, C, D);
This would build a circuit that behaves like the hardware represented in Figure
below
•While Verilog HDL uses UDPs for such truth-table-based definitions, other HDLs and
CAD systems may use different tabular methods to specify circuits.
•CAD tools can process these tables to generate optimized gate-level
implementations automatically.
•All predefined Verilog primitives (like and or not
, , combinational logic, not sequential
, etc.) describe only

logic.
•To model sequential behavior using a UDP:
•The output must be declared as a reg (to store state).
type

•The truth table must include a current state and a next state column.
•The general form becomes:
inputs : current_state : next_state

•This section concludes by summarizing Verilog HDL basics and simple combinational
modeling methods (gate-level, Boolean equations, and UDPs).
 SEQUENTIAL CIRCUIT-SR LATCH

primitive sr_latch (Q, S, R);

output reg Q; // Output must be 'reg' type for sequential UDP
input S, R;

table
// S R : current_state : next_state
0 0 : ? : -; // No change (hold previous state)
0 1 : ? : 0; // Reset (R = 1 forces Q = 0)
1 0 : ? : 1; // Set (S = 1 forces Q = 1)
1 1 : ? : x; // Invalid condition (both high)
endtable Instantiation Example
endprimitive module sr_latch_test (output Q, input S, R);
sr_latch U1 (Q, S, R); // Instantiate the UDP
endmodule
 SUMMARY

•A Verilog module is descriptive (not sequential); it describes what is connected to

what, not the execution order.

•Primitives are predefined in Verilog — you only instantiate them.

•Once declared, a module can be instantiated elsewhere (hierarchical design).

• The input–output behavior of the circuit is implicitly specified by the description

because the behavior of each logic gate is defined.
• Thus, an HDL-based model can be used to simulate the circuit that it represents.