Digital Logic and Sequential Circuits

Flip-Flop Applications
Edge-triggered (clocked) flip-flops are versatile devices used for:
 Counting
 Storing binary data
 Transferring binary data from one location to another
Flip-Flop Synchronization
Asynchronous signals not synchronized to the clock can cause unpredictable
results. Asynchronous signals often originate from human input (e.g., a
switch). Partial clock pulses can occur if a transition of the asynchronous
input happens while the clock signal is HIGH.
Solution: Use a D flip-flop to synchronize the asynchronous input. The
output Q of the D flip-flop will not go HIGH until the next negative-going
transition (NGT) of the clock. This HIGH at Q enables an AND gate, passing
complete clock pulses. When the input returns LOW, Q will not go LOW until
the next NGT of the clock, ensuring only complete pulses are passed.
Detecting an Input Sequence
An output is activated only when inputs are activated in a specific sequence.
For example, generating a HIGH output only if input A goes HIGH and then
input B goes HIGH at some later time. An AND gate alone is insufficient.
Data Storage and Transfer
Data (numerical values encoded in binary) are generally stored in groups of
flip-flops called Registers.
Asynchronous Transfer
In asynchronous transfer, the logic value stored in flip-flop A is transferred
and stored to flip-flop B upon the NGT of the Transfer Pulse. Asynchronous
transfer is also called Jam because data can be "jammed" into the flip-flop
even if its synchronous inputs are active.
Synchronous Transfer
Parallel Data Transfer
Data transfer from one register to another using D-type flip-flops. For
example, transferring data from Register X (X❑2, X❑1, X❑0) to Register Y (Y❑2,
Y❑1, Y❑0) simultaneously upon application of a TRANSFER pulse. This is a
Synchronous Transfer, referred to as a Parallel Transfer.
Serial Data Transfer using Shift Registers
A Shift Register is a group of flip-flops arranged so that binary numbers
stored in the flip-flops are shifted from one flip-flop to the next with each
clock pulse. Shift registers must use edge-triggered flip-flops with holding
time (t H ) less than one CLK-to-output propagation delay.
Frequency Division
Each JK flip-flop with J and K inputs at the 1 level will change states (Toggle)
whenever its CLK input goes NGT. If the output of one flip-flop is connected to
the clock input of the next, a frequency division is achieved.
If n is the number of flip-flops, then the output frequency from the last flip-
1
flop is n of the input frequency.
2
Counters
MOD-N Counter
MOD Counters are cascaded counter circuits that count to a set modulus
value before resetting. Mod number N indicates the number of states the
counter counts and is the dividing number of the counter, equal to 2n in the
counting sequence from 0 to 2n−1. Also, it indicates the frequency division
obtained from the last flip-flop by a factor of N .
Counting Operation
The same frequency divider can function as a Binary Counter, where the
states of the flip-flops represent a binary number equivalent to the number
of pulses that have occurred.
Registers
An n -bit Register consists of a group of n flip-flops capable of storing n bits of
binary information. The storage capacity of a register is the total number of
bits it can retain.
Basic Types of Data Movement in Shift Registers
 Serial in/shift right/serial out
 Serial in/shift left/serial out
 Serial in/parallel out
 Parallel in/serial out
 Parallel in/parallel out
 Rotate right
 Rotate left
Serial In/Serial Out Shift Registers
Accepts data serially (one bit at a time) on a single line and produces the
stored information on its output also in serial form. An SRG 4 designation
indicates a shift register with a 4-bit capacity.
Serial In/Parallel Out Shift Registers
Bits are entered serially, but data bits are taken out of the parallel outputs of
the register.
Parallel In/Serial Out Shift Registers
Bits are entered simultaneously on parallel lines. The serial output is the
same as in serial in/serial out shift registers once the data are completely
stored.
Parallel In/Parallel Out Shift Registers
Employs both parallel entry and parallel output of data methods.
Bidirectional Shift Registers
Data can be shifted either to the right or to the left, depending on the level
of a control line. Example: 74HC194.
Counters
Categories of Counter
 Synchronous Counters: CLK input of all flip-flops are triggered by a
common clock source.
 Ripple Counters: CLK input of some flip-flops are triggered by the
transition that occurs in other flip-flop outputs.
Types of Counters
  Up Counters: Proceeds from a value to the next larger value.
 Down Counters: Operates similarly except that it sequences from large
values to smaller values.
 Binary Counters: Sequences through a series of periodic binary digits
of a given bit length.
 BCD or Decade Counters: Sequences through the BCD digits: 0000,
0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, and 1001.
Binary Ripple Counter
The output of each flip-flop is connected to the CLK input of the next flip-flop
in sequence. The flip-flop holding the least significant bit receives the
incoming count pulses.
 Count Up: The flip-flop holding the least significant bit receives the
incoming count pulses (NGT). Each time that A❑n goes from 1 to 0, it
complements A❑n+1 .
 Count Down: A bit in any other position is complemented if its previous
least significant bit goes from 0 to 1 (PGT).
BCD Ripple Counters
A decimal counter follows a sequence of 10 states and returns to 0 after the
count of 9.
Synchronous Counters
Clock pulses are applied simultaneously to the inputs of all flip-flops. The
decision whether a flip-flop is to be complemented is determined from the
values of the data inputs.
 Synchronous Binary Counter: The first flip-flop is complemented with
every pulse. Other flip-flops are complemented when all the bits in the
lower significant positions are equal to 1.
 Synchronous Up-Down Binary Counter: A combined synchronous up-
down binary counter has an up control input and a down control input.
 Synchronous BCD Counter: Counts in binary-coded decimal from 0000
to 1001 and back to 0000.
Special Counters
Ring Counter
A circular shift register with only one flip-flop being set at any particular time
while all other flip-flops are cleared.
Johnson Counter
A switch-tail ring counter is a circular shift register with a circular connection
where the complemented output of the last flip-flop is connected to the input
of the first flip-flop. Also known as a Mobius counter.
Finite State Machines
A sequential circuit whose output occurs in a prescribed order of sequences
through a set of limited (finite) predetermined states controlled by a clock
and other control input signals.
 Counter as a State Machine: Counters are sequential circuits that have
a regular numeric count sequence of states (modulo) that could repeat
or stop automatically at some predetermined state.
  State Machine: Used to describe other kinds of sequential circuits that
may have an irregular counting pattern (may be any other arbitrary
sequence or sequences with unused states).
Sequential Logic Principle
The Next State Combinational Logic Circuit normally determines what the
output of the sequential circuit will be.
The Memory Element stores the next state value from the Next State
Combinational Logic Circuit and is connected to form a feedback path.
The Trigger determines when the memory element stores the next state
value, through either asynchronous or synchronous method.
General Models of Finite State Machines
 Mealy Model: The Mealy output is a function of both the present state
of the Flip-flops in the memory and present state of the External Input.
 Moore Model: The Moore output is a function of the Next State
Combinational Logic next state value. The Moore outputs shall never
be under the direct Influence of the External Inputs.
Finite State Machine Analysis
Consists of obtaining a state transition table and a state diagram of the time
sequence of inputs, outputs, and internal states.
 Next State Equation (Transition Equation): An algebraic representation
used for specifying the next-state condition of flip-flops in terms of the
present state of the flip-flop outputs and external inputs.
 Output Equation: An algebraic representation used for specifying the
logical output of sequential circuits that have a separate Output
Combinational Logic.
Finite State Machine Design
The design (synthesis) of a sequential circuit starts from a set of design
specifications and culminates in the realization of the Sequential Logic
Diagram.
1. From the worded description and design specifications of the desired
operation, derive the state diagram for the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states and transitions.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop Input equations and output equations.
7. Draw the logic diagram.
Algorithmic State Machines
ASMs are alternative forms of representations for Finite State Machines
(FSMs) that are suitable for designing complex sequential circuits with a
large number of inputs and outputs. ASMs are similar to flowcharts as
compared to FSMs that are expressed using state diagrams and state tables.
Interaction with Digital Hardware Components
The design logic of a digital system is concerned with designing the digital
circuits that perform the data-processing operations. It is also concerned with
designing the control circuits that determine the sequence in which the
various manipulations of data are performed.
 Data-processing path or DataPath Unit: Manipulates data in registers
according to the system's requirements (How and What).
 Control Unit: Issues a sequence of commands (When) to the DataPath
unit.