ASSIGNMENT
Microprocessor and Microcontroller (EC 302)
Time: 1 Hour
Section A – Very Short Answer
1. Write the formula for calculating the 8086 physical address using segment and offset registers.
2. State the size of the 8086 instruction queue in minimum and maximum mode.
3. What is the purpose of the Instruction Pointer (IP) in the 8086?
4. Which segment register is used for stack operations in the 8086?
5. Define “effective address” in indexed addressing.
6. Mention any one reason why the 8086 uses segmented memory architecture.
7. What is the size (in bits) of the data bus of 8086, and why is it significant?
8. Name two addressing modes that use the SI register.
9. Which unit of the 8086 performs instruction fetching?
10. Write the default segment used for string operations.
Section B – Short Problems
11. Compute the physical address for:
ES = 8B20H, DI = 1204H.
12. The contents are DS = 3000H, BX = 7C20H.
Find the physical address for the instruction: MOV AX, [BX].
13. Explain why two different segment:offset pairs may generate the same physical address.
14. With SS = 5000H and BP = 0A30H, compute the stack operand physical address.
15. Describe how the BIU and EU operate simultaneously to improve performance.
16. Calculate the next instruction pointer physical address for:
CS = 9000H, IP = 1F30H.
17. Differentiate between NEAR and FAR subroutine calls.
18. Explain why memory-to-memory data transfer is not permitted in most 8086 instructions.
19. An instruction requires 3 bytes. If the queue currently has 5 bytes, how many bytes must the
BIU fetch after the instruction enters the EU?
20. Describe the purpose of the prefetch queue and how it enhances pipeline performance.
Section C – Long Answer / Application
1
21. Consider the following instruction sequence (queue initially full):
Instruction Bytes Memory Access?
SUB AX, [BP+6] 3 Yes
INC CX 1 No
CALL FAR PTR ROUTINE 5 Yes (flush)
For each instruction, determine: (a) Remaining bytes in queue after execution begins (b) Bytes
fetched by BIU while EU executes (c) When the queue becomes empty and why
22. Explain in detail why FAR CALL and FAR RETURN cause pipeline flushing and performance
delays.
23. Given CS = 5A00H, IP = 8000H with instruction length = 4 bytes: (a) Compute the physical
address of the current instruction. (b) Compute the physical address of the next instruction.
(c) Explain how the prefetch queue handles sequential instruction fetching.
24. With DS = 2000H, evaluate the physical addresses accessed by each operand of the instruction:
MOV [BX+SI], AL
Given BX = 1000H and SI = 0020H.
25. Describe the steps involved when the EU executes an instruction requiring memory access,
starting from address calculation to data transfer.
26. Provide three reasons why segmentation supports modular programming in 8086-based systems.
27. Compute physical addresses for the following segment–offset pairs: (a) 4C20:2100 (b) 0020:9000
(c) 1000:FFFF Explain any unusual observation in part (c).
28. Compare the execution of the following instructions in terms of pipeline behavior and queue
usage: (a) MOV AX, BX (b) MOV AX, [SI] (c) JMP SHORT LABEL Discuss which instructions
cause queue flushing and why.
29. The instruction queue contains bytes:
A1 20 4B 8B 1E
The next instruction requires 2 bytes, and the one after requires 3 bytes. Explain how the BIU
replenishes the queue during these two executions.
30. Explain with a diagram (text description acceptable) the interaction between the EU and BIU
during a complete fetch–decode–execute cycle, including queue usage, memory access, and IP
updates.
