1

DIFFERENTIAL AMPLIFIERS

The Differential amplifier is the basic building block of Operational amplifiers; the
discussion of differential amplifiers in this chapter sets the ground work for analysis and design
procedures for the operational amplifiers. The analysis of the differential amplifiers not only
clarifies the operation of the OP-Amp but also makes the characteristics of the OP-Amp easy to
understand.
Let us consider the emitter biased circuit ;fig-1 shows two identical emitter biased
circuits in that transistor Q1 has the same characteristics as transistor Q2,RE1=RE2,Rc1=Rc2,and
the magnitude of +Vcc is equal to the magnitude of –VEE.

+ Vcc + Vcc

+ Vcc

Rc1 Rc2

R c1
C2 - Vo + R c2
C1 Ib2
Ib1 Q1
C1 C2 Ib2
Q2 B2
Ib1
B1 Q1 B2
B1 Q2
R in1
E1 E2 E1 E2 R in2
0 0
Vin1 Vin2
Re2
Re1 RE
- VEE - VEE 0
0 - VEE

Fig-1: Two identical emitter-biased circuits Fig-2: Dual i/p Balanced o/p Differential amplifier

Remember that the supply voltages +Vcc and –VEE are measured with respect to
ground. to obtain a single circuit such as the one in fig-2; we should reconnect these two circuits
as follows:
1. Reconnect +Vcc supply voltages of the two circuits since the voltages are of the same
polarity and amplitude. Similarly reconnect -VEE supply voltages.
2. Reconnect the emitter E1 of transistor Q1 to the emitter E2 of transistor Q2.(this
reconnection places RE1 in parallel with RE2 ).
3. Show the input signal Vin1 applied to the base B1 of transistor Q1 and Vin2 applied to the
base B2 of transistor Q2.
4. Label the voltage between the collectors C1 and C2 as output voltage (Vo).
Fig-2 is referred to as differential amplifier it amplifies the difference between the
two input signals Vin1 and Vin2 ,in that Rc1 =Rc2=Rc and the parallel combination of RE1 and RE2 is
denoted by RE.

Differential Amplifier Circuit Configurations:

The four differential amplifier configurations are the following

1. Dual input, balanced- output differential amplifier

2. Dual input, Unbalanced -output differential amplifier
3. Single input, balanced -output differential amplifier
4. Single input ,Unbalanced -output differential amplifier

The configurations listed are based on the No. of input signals used and the way an
output voltage is measured. If we use two input signals the configuration is said to be dual input
 2

otherwise single input and If the output voltage is measured between the two collectors it is
referred as balanced output because both collectors are at same dc potential with respect to
ground, If the output voltage is measured at one collector with respect to ground is referred as
Unbalanced output because collector at some potential are but ground at zero potential.
Differential amplifiers are widely used to compare the two input signals.

In the Analysis of D.A we use r-parameters instead of h-parameters for a number of

reasons:
1. The ac analysis of D.A with r-parameters is simpler and more straightforward.
2. The performance equations obtained are simple and easy to remember but with h-
parameters they are lengthy.
3. Unlike h-parameters, there is no need to manipulate the r-parameters at different operating
levels (means at different values IE ,VCE ).

DUAL INPUT BALANCED OUTPUT DIFFERENTIAL AMPLIFIER:

The circuit diagram of DIBO Differential Amplifier shown in fig -2.

Analysis of differential amplifier :

DC Analysis:
To determine the operating point values ICQ and VCEQ for the differential amplifier for fig-
2,we need to obtain a dc equivalent circuit .The dc equivalent circuit can be obtained simply by
reducing the i/p signals Vin1 and Vin2 to zero. The dc equivalent circuit thus obtained is shown in
fig -[Link] internal resistances of the input signals are denoted by Rin because, Rin1=[Link]
both emitter biased sections of the differential amplifier is symmetrical, we need to determine the
operating point (ICQ and VCEQ) for only one section .These ICQ and VCEQ values can then be used for
transistor Q2 also.

+ Vcc
<-- Ic
<-- Ic

Rc Rc

C1 C2

Ib1---> B2
B1 Q1 <-- Ib2
Q2
R in Vbe Vbe R in
E1 E2
Ie Ie

Vin1=0V Vin2=0V
<--2 Ie

RE

0 - VEE 0

[Link] equivalent circuit of the DIBO D.A

Apply KVL to the base-emitter loop of the transistor Q1, in fig-3.

-Rin IB – VBE – RE(2IE) + VEE = 0 -------(1)
But IB = IE/βdc ;
since , IC = IE , thus the current through transistor Q1 is determined directly from equation (1).

VEE−VBE
IE= IC = -------- (2)
2 ℜ+ Rin/ βdc
Where
VBE =0.6 V for silicon transistors
VBE =0.2 V for germanium transistors

Generally Rin/ βdc << 2 RE, therefore equation (2) can be rewritten as
 3

VEE−VBE
IE = ----- (3)
2ℜ

From equation (3) we see that the value of RE sets up the emitter current in transistors Q1
and Q2 for a given value of VEE .Note that the value of IE is independent of RC.

Next we shall determine the value of VCE:

The voltage at the emitter of Q1 is equal to –VBE if we assume the voltage drop
across the Rin to be negligibly small.

From the dc equivalent circuit,

VC =VCC – IC RC
and VCE = VC - VE
= VCC – IC RC –(–VBE)
= VCC + VBE – IC RC ------- (4)

Hence from equations (2) and (4) ,the operating point IE= ICQ and VCE= VCEQ.

Note : DC analysis equations (2) and (4) are applicable for all four configurations because all
are used the same biasing arrangement.

AC analysis :
To perform ac analysis we have to derive the expressions for the voltage gain Ad and
the input resistance of the D.A shown in fig-3.

1. Set the dc voltages +VCC and –VEE at zero.

2. Substitute the small signal T-equivalent models for the transistors.

Fig. 4 shows the resulting ac equivalent circuit of dual input balanced output Differential
amplifier.

- Vo +
Vc1 Vc2
Ic 1 re E1 E2 re Ic 2
C1 C2

Ie1---> <-- Ie2

B1 RE
Ib1--->

Rc R in 2
Ib2--->

Rc
R in 1 I II

V in 1 V in 2
I

0 0 0 0 0

Fig-4:DIBO DA AC Equivalent circuit

Voltage gain:
To derive the voltage gain we have to consider the following
1. IE1= IE2 ;so re1=re2 so the emitter resistance of Q1 and Q2 is simply denoted by re.
2. The voltage across each collector resistor is shown out of phase by 1800 with respect to the
input voltages Vin1 and Vin2.
3. Note the assigned polarity of V0 .this polarity simply indicates that the voltage at collector
C2 is assumed to be more positive with respect to that at collector C1 .
 4

Apply KVL to loop I and II we get,

Vin1 - Rin1 Ib1 - re Ie1- RE (Ie1+ Ie2) = 0 -------- (5)

Vin2 - Rin2 Ib2 - re Ie2-RE (Ie1+ Ie2) = 0 -------- (6)

Now by Substituting Ib1= Ie1 /βac , Ib2= Ie2/βac and by observing the equations, Rin1/βac ,
Rin2/βac values are very small therefore we neglect them, so the simplified equations are

(re +RE) Ie1 + (RE) Ie2 = Vin1 -------------- (7)

(RE ) Ie1 + (re +RE) Ie2 = Vin2 ----------(8)

Solve Ie1 and Ie2 by using Cramer’s rule we get

|VV ∈1∈2
RE
r e+ R E |
Ie1 = ¿ ¿ --------- (9a)

RE |
r e+R E RE
r e+ R E |
( r e+ R E ) V ∈1−(R E)V ∈2
= 2 2
(r e + R E) −( R E)

Ie2 =
|r e+R ER E V ∈1
V ∈2 | ---------- (9b)
|r e+R E
RE
RE
r e+ R E |
( r e+ R E ) V ∈2−( R E ) V ∈1
= 2 2
(r e+ R E) −(R E)

The output Voltage is, V0 = Vc2 - Vc1

= - Rc Ic2 - (- Rc Ic1) --------- (10)

= Rc Ic1 - Rc Ic2

= Rc(Ie1 - Ie2) since Ic≅ Ie

Now by Substituting the current relations Ie1 and Ie2 , equations we get,
Rc
V0 = (V ∈1−V ∈2 ¿ - ---------- (11)
re
and the differential gain,
Vo Rc
Ad = = --------- (12)
Vid re

Differential input resistance :

It is defined as the equivalent resistance that would be measured at either input

terminal with the other terminal grounded.
V ∈1
Ri1 = : at Vin2 =0 ---------- (13)
I b1
But Ib1 = Ie1 /βac ;
V ∈1. β ac
Ri1 =
Ie1
 5

By substituting Ie1 we get,

β ac ℜ(ℜ+2 ℜ)
Ri1 = ;
(ℜ+ ℜ)

we know that RE >> re , so (re +2 RE )= 2 RE, and (re +RE )= RE,

Therefore Ri1 =2βac re ----------- (14)

Similarly, Ri2 =2βac re ---------- (15)

Out put Resistance:

It is defined as the equivalent resistance that would be measured at either output
terminal with respect to ground.
R01 = R02 = Rc ------------- (16)

Inverting and Non-inverting inputs:

In the differential amplifier the input voltage Vin1 is called the non inverting input
terminal because positive voltage at this input terminal produces positive output voltage (V0).
Similarly, Vin2 is called inverting input terminal because positive voltage at this input terminal
produces negative output voltage (V0).

Common mode rejection ratio:

It is the ability of a differential amplifier is to reject common mode
signals .It is defined as the ratio of differential gain to the common mode gain.
Ad
CMRR =
Acm
Vocm
and Common mode gain is A cm=
Vcm

Ideally A cm to be zero that is Vocm =0V (or) CMRR =α.

DUALINPUT UN BALANCED OUTPUT DIFFERENTIAL AMPLIFIER:

The circuit shown in fig -5 is a Dual input un balanced Differential

Amplifier and the DC analysis is same as that of Dual input balanced output differential
amplifier.
i.e
VEE−VBE
IE = and
2 ℜ+ Rin/ βdc

VCE = VCC + VBE – IC RC

 6

+ Vcc

R c1 R c2

Vo
C1 C2

Ib1 B2 Ib2
B1 Q1
Q2
R in 1 R in 2
E1 E2

V in 1 V in 2

RE

0 - VEE 0
Fig-5: Dual i/p UnBalanced o/p Differential amplifier

Ac analysis :

To perform ac analysis we have to derive the expressions for the voltage gain Ad and the
input resistance of the D.A shown in fig-5.
1. Set the dc voltages +VCC and –VEE at zero.
2. Substitute the small signal T-equivalent models for the transistors.

Fig. 6 shows the resulting ac equivalent circuit of DIUBO Differential amplifier.

C1 Ic 1 re E1 E2 re Ic 2 C2

B1 RE
Rc
II R in 2
R in 1 Rc
I Vo

V in 1 V in 2

-
0 0 0 0 0

Fig-6:DIUBO DA AC Equivalent circuit

Voltage gain:

Apply KVL to loop I and II we get,

Vin1 - Rin1 Ib1 - re Ie1 - RE (Ie1+ Ie2) =0 ---------- (5)

Vin2 - Rin2 Ib2 - re Ie2 - RE (Ie1+ Ie2) =0 ---------- (6)

Now by Substituting Ib1= Ie1 /βac , Ib2= Ie2/βac and observing the equations,
Rin1/βac , Rin2/βac values are very small therefore we neglect them, so the simplified equations are

(re +RE) Ie1+ (RE) Ie2 = Vin1 ------------------ (7)

 7

(RE ) Ie1 + (re +RE) Ie2 = Vin2 -----------(8)

Solve Ie1 and Ie2 by using Cramer’s rule we get

Ie1 =
|VV ∈1∈2 RE
r e+ R E | ----------- (9a)
|
r e+R E
RE
RE
r e+ R E |
( r e+ R E ) V ∈1−(R E)V ∈2
= 2 2
(r e + R E) −( R E)

Ie2 =
|V ∈rRe +ER E 1 VV ∈1
∈2|
---------- (9b)
|r e+R RE E r eR+ER E|
( r e+ R E ) V ∈2−( R E ) V ∈1
= 2 2
(r e+ R E) −(R E)

The output voltage is V0= Vc2

= - Rc Ic2

= -Rc Ie2 since Ic ≅ Ie

( r e+ R E ) V ∈2−( R E ) V ∈1
V0 = - R c 2 2
(r e+ R E) −(R E)

( R E ) V ∈1− ( r e+ R E ) V ∈2
V0 = R c
r e (r e +2 R E)

we know that RE >> re , so (re +2 RE )= 2 RE, and (re +RE )= RE,

( R E ) V ∈1− ( R E ) V ∈2
Therefore V0 = Rc
r e (2 R E)

( R E ) (V ∈1−V ∈2)
V0 = R c ¿
2r e R E¿

(V ∈1−V ∈2)
= Rc
2r e

(V id)
= Rc
2r e

Vo Rc
And the differential gain, Ad = =
Vid 2r e

Differential input resistance:

Ri1 = Ri2 = 2βac re
Out put Resistance:
R01 = R02 = Rc
 8

SINGLE INPUT BALANCED OUTPUT DIFFERENTIAL AMPLIFIER:

The circuit shown in fig -7 is a Single input balanced output Differential

Amplifier and the DC analysis is same as that of Dual input balanced output differential amplifier.
i.e
VEE−VBE
IE = and
2 ℜ+ Rin/ βdc

VCE = VCC + VBE – IC RC

+ Vcc

Rc Rc
- Vo +

C1 C2

Ib1
B1 Q1 B2 Ib2
Q2
R in 1
E1 E2

V in 1

RE

0 - VEE 0

Fig-7: Single i/p Balanced o/p Differential amplifier

Ac analysis :

To perform ac analysis we have to derive the expressions for the voltage gain Ad and the
input resistance of the D.A shown in fig-7.

1. Set the dc voltages +VCC and –VEE at zero.

2. Substitute the small signal T-equivalent models for the transistors.

Fig. 8 shows the resulting ac equivalent circuit of SIBO Differential amplifier.

Vo

C1 Ic 1 re E1 E2 re Ic 2 C2

B1 II
Rc R in 2
I
R in 1 RE Rc

V in 1

0 0 0 0 0

Fig-8:SIBO DA AC Equivalent circuit

Voltage gain:

Apply KVL to loop I and II we get,

 9

Vin - Rin Ib1 - re Ie1 - RE iE = 0

Vin - Rin Ib1 - re Ie1 - re Ie2 = 0

Substituting current relations , iE = Ie1- Ie2 ; and Ib1= Ie1 /βac , Ib2= Ie2/βac and observing the
equations, Rin1/βac , Rin2/βac values are very small therefore we neglect them, so the simplified
equations are

(re +RE) Ie1 - (RE) Ie2 = Vin

(re) Ie1 + (re) Ie2 = Vin

Now by solving Ie1 and Ie2 we get,

Ie1 =
|VV∈¿−R
∈¿ r e |
E

|r e +r eR E −R E
re |
¿
= ( r e ) V ∈+(R E)V ∈ ( r e + R E ) r e+ r e R E ¿

V ∈( r e+ R E)
=
r e(r e+2 R E)

Ie2 = ¿¿ ---------- (9b)

¿
= ( r e + R E ) V ∈−( r e ) V ∈ ( r e+ R E ) r e +r e R E ¿

V ∈(R E)
=
r e(r e+2 R E)

The output Voltage is, V0 = Vc2 - Vc1

= - Rc Ic2 - (- Rc Ic1) --------- (10)

= Rc Ic1 - Rc Ic2

= Rc(Ie1 - Ie2) since Ic≅ Ie

Substituting the current relations Ie1 and Ie2 , equations we get ,

Rc
V0 = (V ∈¿
re

Vo Rc
And the differential gain, Ad = =
Vin re

Differential input resistance:

Ri1 = Ri2 = 2βac re
Out put Resistance:
R01 = R02 = Rc

SINGLE INPUT UN BALANCED OUTPUT DIFFERENTIAL AMPLIFIER:

 10

The circuit shown in fig -9 is a SIBO Differential Amplifier and the

DC analysis is same as that of SIBO differential amplifier.
i.e
VEE−VBE
IE = and
2 ℜ+ Rin/ βdc

VCE = VCC + VBE – IC RC

+ Vcc

Rc Rc

Vo
C2
C1
Ib1
B1 Q1 B2 Ib2
Q2
R in 1
E1 E2

V in 1

RE

0 - VEE 0
Fig-9: Single i/p UnBalanced o/p Differential amplifier

Ac analysis :

To perform ac analysis we have to derive the expressions for the voltage gain Ad and
the input resistance of the differential amplifier shown in fig-9.

1. Set the dc voltages +VCC and –VEE at zero.

2. Substitute the small signal T-equivalent models for the transistors.

Fig. 10 shows the resulting ac equivalent circuit of Single input unbalanced output Differential
amplifier.

Ic 1 re E1 E2 re Ic 2 C2
C1

B1
Rc II R in 2

R in 1 I Rc
RE Vo

V in 1

0 0 0 0 0

Fig-10:SIUBO DA AC Equivalent circuit

Voltage gain:
 11

Apply KVL to loop I and II we get,

Vin - Rin Ib1 - re Ie1- RE iE =0

Vin - Rin Ib1 - re Ie1- re Ie2 =0

Substituting current relations, iE = Ie1- Ie2 ; and Ib1= Ie1 /βac , Ib2= Ie2/βac and observing the
equations, Rin1/βac , Rin2/βac values are very small therefore we neglect them, so the simplified
equations are

(re +RE) Ie1 - (RE) Ie2 = Vin

(re) Ie1 + (RE) Ie2 = Vin

Now by solving Ie1 and Ie2 we get

Ie1 =
|VV∈¿−R
∈¿ r e |
E

|r e +r eR E −R E
re |
¿
= ( r e ) V ∈+(R E)V ∈ ( r e + R E ) r e+ r e R E ¿

V ∈( r e+ R E)
=
r e(r e+2 R E)

Ie2 = ¿¿ ---------- (9b)

¿
= ( r e + R E ) V ∈−( r e ) V ∈ ( r e+ R E ) r e +r e R E ¿

V ∈(R E)
=
r e(r e+2 R E)

The output Voltage is, V0 = Vc2

= Rc Ic2

= Rc(Ie2) since Ic≅ Ie

Substituting the current relations Ie2 , equations we get ,

Rc
V0 = (V ∈¿
2r e

Vo Rc
And the differential gain, Ad = =
Vin 2r e

Differential input resistance:

Ri = 2βac re
Out put Resistance:
R 0 = Rc

DIFFERENTIAL AMPLIFIER WITH SWAMPING RESISTOR:

The swamping resistor RE’ is connected in series with each emitter because it
reduces the dependence of the voltage gain of the D.A on the variations in re .The circuit diagram
of differential amplifier with swamping resistor shown in below fig-(11).
 12

+ Vcc

Rc Rc

- +
Vo
C C

B B
Q1 Q2

R in 1 E E R in 2

V in 1 V in 2
RE' RE'

0 RE 0

- VEE

Fig.11:DIBO Differential amplifier with swamping resistor

DC Analysis:
The emitter current in each transistor can be determined by writing KVL equation
around the base-emitter loop of [Link] Vin1 =Vin2=0 V.

- Rin IB – VBE –RE’IE - RE (2IE) + VEE = 0

But IB = IE/βdc ; since IC = IE thus the current through transistor Q1 is determined directly
from the above equation,
VEE −VBE
IE = '
2 ℜ+ R E + Rin / βdc

And VCE = Vcc +VBE - RcIC

Vo Rc
Differential gain Ad = =
Vid ℜ+ ℜ'

input resistance:
Ri1 = Ri1 =2βac (re +RE’)
Out put Resistance:
R01 = R02 = Rc
Thus RE’ reduces the voltage gain but increases input resistance

Constant Current Bias:

In the differential amplifier the combination of RE and –VEE is used to set up

the dc emitter current .We can also use the constant current bias circuit,which provides better
current stabilization and maintains the stable operating point .The circuit diagram of DIBO
Differential amplifier with constant current bias shown in fig .[Link] the circuit it is observed
that the resistor RE replaced with a Q3 transistor.
 13

+ Vcc

Rc Rc

- +
Vo
C C

B B
Q1
Q2
R in 1 E E R in 2

V in 1 I2 Ic3 V in 2

Q3
R2
0 0 R1 0

RE

- VEE

Fig.12 DIBO D.A with constant current bias

−R 2VEE
From the transistor Q3; VB3 =
R 1+ R 2

and V E3 = VB3 - VBE3

−R 2VEE
= - VBE3
R 1+ R 2

VE3−(−VEE)
Therefore IE3 ≅ IC3 =
ℜ

IC3 =
VEE− R 2
[ VEE
R 1+ R 2 ]
−VBE 3
ℜ

I C3
And hence IE1 = IE2 ≅
2

=
VEE− R 2
[ VEE
R 1+ R 2 ]
−VBE 3

2ℜ

Constant current bias with diode compensation for variations in VBE:

I2 Ic3

Q3
R2
D1
0 RE
D2

- VEE
Fig:13

VB3 = -VEE +2VD and

 14

V E3 = VB3 - VBE3

= -VEE +2VD - VBE3

VE3−(−VEE)
Therefore IE3 ≅ IC3 =
ℜ

2V D−VBE 3 VD
IC3 = ℜ
≅ IE3 =
ℜ [ if VD = VBE3]

Constant current bias using zener diode:

I2 Ic3

Q3
2

R2
Vz RE
0
1

- VEE
Fig.14

VB3 = -VEE + Vz and

VE3 = VB3 - VBE3

= -VEE + Vz - VBE3

VE3−(−VEE)
Therefore IE3 ≅ IC3 =
ℜ

V z−VBE 3
IC3 = ℜ
≅ IE3

And the value of R2 selected so that I2 ≅ 1.2 Iz

V EE−Vz
R 2=
I2

Current mirror circuit :

The circuit in which the output current is forced to equal the input current is said to
be a current mirror circuit .Thus in current mirror circuit the output current is the mirror image of
the input current. The block diagram and circuit diagrams are shown below fig15 (a) and (b).
 15

I2 --> VB3 Ic3

I source --> <-- I sink Q3 RE'

Current mirror R2
0
Q4

I source = Isink - VEE

Fig (a) Fig (b)

Assume Q3 and Q4 are identical transistors so their base-emitter voltages must be

same and their base and collector currents also be approximately equal.
VBE3 = VBE3

IC3 = Ic4

IB3 = IB4

Summing currents at node VB3 we obtain as

I2 = Ic4 + I

= Ic4 + 2IB4

= Ic3 + 2IB3

= Ic3 + 2(Ic3/βdc)

Therefore I2 = Ic3[1 + (2/βdc)] neglect (2/βdc)

Then I2 ≅ Ic3

The current I2 is obtained by writing KVL for the base – emitter loop of transistor Q3;

- R2 I2 - VBE3 + VEE = 0

V EE−VBE 3
And I2=
R2

Cascaded differential amplifiers:

Let us see how differential amplifier can be cascaded (connected in series). Fig.16
shows a typical two stage differential amplifier. The first stage is a dual-input, balanced out put
differential amplifier. The second stage is another differential amplifier driven by the output of
the first differential amplifier. A single ended (unbalanced) output is taken from this second stage.
Both stages use the emitter biasing technique to setup the emitter currents in the differential pairs.
 16

+ Vcc

R c1 R c2 R c4
R c3
Vo

- + Q5 C C
Vo B B
C C B
Non inv. i/p Q3 Q4
B B E R E'
Q1 E
Q2 R E'
E E

Inverting i/p RE 2
RE 1

- VEE

Fig.16 Cascaded differential amplifier

Level Translator:

1. In the cascaded differential amplifier, due to the direct coupling,the DC level at the
emitters rises from stage to stage .This increase in dc levels tends to shift the operating
point of the succeeding stages and therefore limits the output voltage swing and may even
distort the signal .For example in the cascaded differential amplifier the voltage at the
emitter of Q1 and Q2 of the first stage is -0.715V ,whereas that at the emitters of Q3 and Q4
of the second stage is 7.12V.

2. The voltage at the output terminal of the second stage increases .This dc level is
undesirable because it tends to limit the peak-peak output voltage swing without distortion
and also contributes to the error in the dc output signal.

Therefore final stage should be included to shift the output dc level at the second stage
down to about zero volts to ground such stage is referred to as a level translator.

Different level translator circuits shown below fig.19(a),(b),(c).

+ Vcc + Vcc

Q3 Q5

Input

Input B C 107A R

R1
Vo
R2

Q6
Vo D1

D2 RE
R2 0

- VEE
- VEE
fig .19(a) Emitter follower with voltage divider fig .19(b) Emitter follower with constant current bias
 17

+ Vcc

Q5

Input

Vo
R2

Q6

Q7
0

- VEE

fig .19(b) Emitter follower with current mirror