Elec Eng 2EI5
Electronic Devices & Circuits 1
Winter 2019
Term Test 2 – 3/26/19
INSTRUCTOR: Yaser M. Haddara
EXAMINATION TIME 1 HOUR
Please read the following very carefully and sign before starting
your work.
1. This test paper has 6 pages (including this page and the formula sheet) and 2 questions.
You can use the backs of these pages to do any rough work but your final answer should
be clearly indicated in the space provided. The space provided for each part is sufficient
to do all the work leading to a final answer.
2. JUSTIFY YOUR ANSWERS. “Correct” answers without steps shown may receive no
credit.
3. Questions are not equally weighted. The weight of each question is indicated with the
question.
4. By signing below, you acknowledge that you know and understand McMaster’s academic
honesty policies and commit to adhere to them.
________________________________________ _________________
Student Name ID
________________________________________
Signature
Student Name: Student Number:
You may use the following formulas in your work:
1. Diode model:
v i
iD I S exp D 1 vD nVT ln D 1
nVT IS
VT = 25 mV at room temperature. Default value for n is n = 1.
2. Rectifier circuits:
I LTout Vp Vp
Vr iDav I L 1 iDmax I L 1 2
C 2V 2V
r r
where I L is the average load current supplied by the capacitor, Tout is the period of the
output waveform, Vr is the peak‐to‐peak ripple, and V p is the peak output voltage.
3. n‐MOSFET model:
Region of
Assume Check
Operation
Cutoff i DS 0 vGS VTN
v DS
2
vGS VTN
i DS K n vGS VTN v DS 0 v DS vGS VTN
Linear
2
K vGS VTN
n vGS VTN 1 v DS
2
Saturation i DS
2 v DS vGS VTN 0
W W
K n K n e C ox
L L
For DC analysis, unless explicitly specified otherwise, assume 0
4. p‐MOSFET model:
Region of
Assume Check
Operation
Cutoff i SD 0 v SG VTP
v SD
2
v SG VTP
i SD K p v SG VTP v SD 0 v SD v SG VTP
Linear
2
Kp v SG VTP
iSD vSG VTP 1 vSD
2
Saturation
2 v SD v SG VTP 0
W W
K p K p h C ox
L L
For DC analysis, unless explicitly specified otherwise, assume 0
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5. NPN BJT:
Region of Operation Assume Check
Cutoff i B iC 0 v BE V BEon
v BC V BCon
Saturation v BE V BEon i B , iC 0
v BC V BCon iC i B
Linear vBE VBEon iB 0
V v BC V BCon
iC iB 1 CE
VA
Unless otherwise stated, assume VBEon = 0.7V, VBCon = 0.5V, VA =
6. PNP BJT:
Region of Operation Assume Check
Cutoff i B iC 0 v EB V EBon
vCB V CBon
Saturation v EB V EBon i B , iC 0
vCB V CBon iC i B
Linear vEB VEBon iB 0
V vCB V CBon
iC iB 1 EC
VA
Unless otherwise stated, assume VEBon = 0.7V, VCBon = 0.5V, VA =
7. MOSFET Small Signal Model Parameters:
1
VDS
2 I DS 1
gm 2 KI DS (1 VDS ) 2 KI DS ro λ
VGS VT I DS I DS
Valid for vgs 0.2 VGS VT here VT is the threshold voltage of the MOSFET
(For p‐MOSFET replace IDS with ISD, VDS with VSD, VGS with VSG)
8. BJT Small Signal Model Parameters:
IC V A VCE V A
gm r re ro (also recall )
VT gm gm IC IC 1
Valid for vbe 0.2VT here, VT is the thermal voltage, 25 mV at room temperature
(For PNP replace VCE with VEC)
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Question 1 (70 points)
Consider the circuit shown. Q1 has = 10. Q2 has = 4. Note that
since these values are small, any approximation that depends on
having a large value of will not be valid in this question.
(a) Choose a value for R such that I C 1 1mA . (40 points)
The current through R is equal to IE1.
Assuming both transistors are in forward active mode,
1 1
I E1 I 1.1I C 1 1.1mA and
1 C 1
VC 1 VB 2 V E 2 0.7 VE 1 1.4 1.4 V .
10 1.4
Therefore, R 7.8 k .
1.1
Since VC 2 VB 2 , Q2 is in forward active.
Since VC 1 VB1 , Q1 is in forward active.
(b) Determine I C 2 . (30 points)
From (a) we know that both transistors are in forward active.
IC 1
Therefore, I E 2 I B1 0.1mA .
1
2
Therefore, I C 2 I E 2 0.08mA .
2 1
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Question 2 (80 points)
In the circuit shown, R1 30k ,
R2 60k , R3 3k , R4 130 and
R5 1.8k . 100 .
It has been determined that the BJT is
operating in the forward active mode with
I C 2mA . This means that you do not need
to do DC analysis for this circuit (unless you
decide to do it just for fun, or because you
don’t trust my calculations and want to
check ).
(a) Determine the gain of this circuit. (50 points)
Hint: the only correct way to do this is to draw the small signal equivalent circuit and
analyze it.
The small signal equivalent circuit is shown below. I have used the T-model, but the pi-
model can also be used. (Answers using the pi-model are shown on the last page.)
From the circuit we can see:
vi
ie and vo ie R3 .
re R4
vo R3
Therefore, Av .
vi re R4
Also, re 0.012375k .
gm 40 I C
0.99 3
Therefore, Av 20.9 .
0.012375 0.13
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(b) Assuming the maximum allowed input amplitude for which the small signal approximation is
valid. (20 points)
We know that the small signal model is valid for vbe 5mV .
vbe re
From the circuit diagram in part (a) we find 0.087vi .
vi re R4
5mV
Therefore, the small signal approximation is valid for vi 57.5mV .
0.087
(c) If the input source has an internal resistance of 1k, what is the gain of the circuit? (Note
that since the source is capacitively coupled to the circuit, this change will not affect the DC
bias point. It will only affect the small signal analysis.) (10 points)
vo
From part (a) we know that 20.9 . This relationship does not change here. What changes
vb
as a result of the internal resistance is that we will now have vb vi .
To determine the new vb we need to determine the input resistance of the circuit.
vo
Again looking at the circuit in part (a) we found that re R4 0.142k .
ie
Therefore, the resistance looking into the base of the transistor is
vb vb v
1 b 14.4 k .
ib ie ie
1
Therefore, the input resistance is Rin 30 60 14.4 8.37k .
vo vo vb 8.37
Therefore, Av 20.9 18.7 .
vi vb vi 8.37 1
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Answer using pi-model
Writing a nodal equation at node e gives:
v ve
gm v . Also, we have ve vi v .
r R4
Plugging the second equation into the first one allows us to solve for
1
R4
v vi 0.087vi .
1 1
gm
r R4
Therefore, vo gm v R3 80 0.087vi 3 20.9vi .
0.087v v
Also, for part (c), we have v 0.087vi , therefore ib so that, as before, we can
r 14.4
write Rin 30 60 14.4 .
