Digital Fundamentals 11th Edition by Thomas Floyd ISBN 1292075988 Â Ž 978-1292075983 Ebook Universal PDF
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GLOBAL
EDITION
Digital Fundamentals
ELEVENTH EDITION
Thomas L. Floyd
Eleventh Edition Global Edition
Digital
Fundamentals
Thomas L. Floyd
Credits and acknowledgments for materials borrowed from other sources and reproduced, with permission, in this textbook appear on the appropriate page
within text.
The right of Thomas L. Floyd to be identified as the author of this work has been asserted by him in accordance with the Copyright, Designs and Patents
Act 1988.
Authorized adaptation from the United States edition, entitled Digital Fundamentals,11th edition, ISBN 978-0-13-273796-8, by Thomas L. Floyd, published
by Pearson Education © 2015.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic,
mechanical, photocopying, recording or otherwise, without either the prior written permission of the publisher or a license permitting restricted copying in
the United Kingdom issued by the Copyright Licensing Agency Ltd, Saffron House, 6–10 Kirby Street, London EC1N 8TS.
All trademarks used herein are the property of their respective owners. The use of any trademark in this text does not vest in the author or publisher any
trademark ownership rights in such trademarks, nor does the use of such trademarks imply any affiliation with or endorsement of this book by such owners.
A catalogue record for this book is available from the British Library
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3
4 Preface
Standard Features
• Full-colorformat
• Core fundamentals are presented without being intermingled with advanced or
peripheral topics.
• InfoNotes are sidebar features that provide interesting information in a condensed
form.
• Achapteroutline,chapterobjectives,introduction,andkeytermslistappearonthe
opening page of each chapter.
• Withinthechapter,thekeytermsarehighlightedincolorboldface.Eachkeytermis
defined at the end of the chapter as well as in the comprehensive glossary at the end
of the book. Glossary terms are indicated by black boldface in the text.
• Remindersinformstudentswheretoindtheanswerstothevariousexercisesand
problems throughout each chapter.
• Sectionintroductionandobjectivesareatthebeginningofeachsectionwithina
chapter.
• Checkupexercisesconcludeeachsectioninachapterwithanswersattheendofthe
chapter.
• Each worked example has a Related Problem with an answer at the end of the
chapter.
• Hands-On Tips interspersed throughout provide useful and practical information.
• Multisimiles(newerversions)onthewebsiteprovidecircuitsthatarereferencedin
the text for optional simulation and troubleshooting.
• Theoperationandapplicationoftestinstruments,includingtheoscilloscope,logic
analyzer, function generator, and DMM, are covered.
• Troubleshootingsectionsinmanychapters
• Introductiontoprogrammablelogic
• Chaptersummary
• True/Falsequizatendofeachchapter
• Multiple-choiceself-testattheendofeachchapter
• Extensivesectionalizedproblemsetsattheendofeachchapterwithanswerstoodd-
numbered problems at the end of the book.
• Troubleshooting,appliedlogic,andspecialdesignproblemsareprovidedinmany
chapters.
• CoverageofbipolarandCMOSICtechnologies.Chapter15isdesignedasa“loating
chapter” to provide optional coverage of IC technology (inside-the-chip circuitry) at
any point in the course. Chapter 15 is online at www.pearsonglobaleditions.com/floyd
3. Verilog tutorial
4. MultiSim tutorial
5. AlteraQuartusIItutorial
6. Xilinx ISE tutorial
7. Five-variable Karnaugh map tutorial
8. Hamming code tutorial
9. Quine-McCluskeymethodtutorial
10. Espresso algorithm tutorial
11. Selected VHDL programs for downloading
12. ProgrammingtheelevatorcontrollerusingAlteraQuartusII
Instructor Resources
• Image Bank This is a download of all the images in the text.
• Instructor’s Resource Manual Includes worked-out solutions to chapter problems,
solutions to Applied Logic Exercises, and a summary of Multisim simulation results.
• TestGen This computerized test bank contains over 650 questions.
• Download Instructor Resources from the Instructor Resource Center
To access supplementary materials online, instructors need to request an instructor
access code. Go to www.pearsonglobaleditions.com/floyd to register for an instruc-
tor access code. Within 48 hours of registering, you will receive a confirming e-mail
includinganinstructoraccesscode.Onceyouhavereceivedyourcode,locateyour
text in the online catalog and click on the Instructor Resources button on the left side
ofthecatalogproductpage.Selectasupplement,andaloginpagewillappear.Once
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CHAPTER
3
Logic Gates
FIGURE P-3
FIGURE P-4
Preface 7
with a Related Problem that reinforces or expands on the example by requiring the student
to work through a problem similar to the example. A typical worked example with Related
Problem is shown in Figure P-5.
Related Problem
Determine the waveforms Y1, Y2, Y3, Y4 and X if input waveform A is inverted.
EXAMPLE 5–15
Determine the output waveform X for the circuit in Example 5–14, Figure 5–34(a), directly from the output expression.
Solution
The output expression for the circuit is developed in Figure 5–35. The SOP form indicates that the output is HIGH when A
is LOW and C is HIGH or when B is LOW and C is HIGH or when C is LOW and D is HIGH.
A A+B
(A + B)C
B
X = (A + B)C + CD = (A + B)C + CD = AC + BC + CD
C
C
D CD
FIGURE 5–35
The result is shown in Figure 5–36 and is the same as the one obtained by the intermediate-waveform method in Example
5–14. The corresponding product terms for each waveform condition that results in a HIGH output are indicated.
BC
CD
AC AC
A
X = AC + BC + CD
FIGURE 5–36
Related Problem
Repeat this example if all the input waveforms are inverted.
It is standard practice to test a new circuit design to be sure that it is operating as specified.
New fixed-function designs are “breadboarded” and tested before the design is finalized.
The term breadboard refers to a method of temporarily hooking up a circuit so that its
operation can be verified and any design flaws worked out before a prototype unit is built.
(a) Oscilloscope display of CLK A and CLK B waveforms with (b) Oscilloscope display showing propagation delay that creates
After completing this section, you should be able to glitches indicated by the “spikes”. glitch on CLK A waveform
u Describe how the timing of a circuit can produce erroneous glitches FIGURE 7–62 Oscilloscope displays for the circuit in Figure 7–61.
u Approach the troubleshooting of a new design with greater insight and awareness
of potential problems
CLK
The circuit shown in Figure 7–61(a) generates two clock waveforms (CLK A and CLK B)
that have an alternating occurrence of pulses. Each waveform is to be one-half the fre-
Q
quency of the original clock (CLK), as shown in the ideal timing diagram in part (b). D
Q CLK A
Q
CLK C
CLK
Q
CLK A
Q CLK B
Q CLK A
D CLK B
Q (a) (b)
CLK C
Q FIGURE 7–63 Two-phase clock generator using negative edge-triggered flip-flop to
CLK A
CLK B eliminate glitches. Open file F07-63 and verify the operation.
CLK B
(a) (b)
FIGURE 7–61 Two-phase clock generator with ideal waveforms. Open file F07-61 and
verify the operation.
Glitches that occur in digital systems are very fast (extremely short in duration) and can be difficult to
see on an oscilloscope, particularly at lower sweep rates. A logic analyzer, however, can show a glitch
When the circuit is tested with an oscilloscope or logic analyzer, the CLK A and CLK B easily. To look for glitches using a logic analyzer, select “latch” mode or (if available) transitional
waveforms appear on the display screen as shown in Figure 7–62(a). Since glitches occur sampling. In the latch mode, the analyzer looks for a voltage level change. When a change occurs,
on both waveforms, something is wrong with the circuit either in its basic design or in the even if it is of extremely short duration (a few nanoseconds), the information is “latched” into the
way it is connected. Further investigation reveals that the glitches are caused by a race analyzer’s memory as another sampled data point. When the data are displayed, the glitch will show
as an obvious change in the sampled data, making it easy to identify.
condition between the CLK signal and the Q and Q signals at the inputs of the AND gates.
As displayed in Figure 7–62(b), the propagation delays between CLK and Q and Q create
a short-duration coincidence of HIGH levels at the leading edges of alternate clock pulses.
Thus, there is a basic design flaw.
The problem can be corrected by using a negative edge-triggered flip-flop in place of
the positive edge-triggered device, as shown in Figure 7–63(a). Although the propaga- SECTION 7–7 CHECKUP
tion delays between CLK and Q and Q still exist, they are initiated on the trailing edges
1. Can a negative edge-triggered J-K flip-flop be used in the circuit of Figure 7–63?
of the clock (CLK), thus eliminating the glitches, as shown in the timing diagram of
Figure 7–63(b). 2. What device can be used to provide the clock for the circuit in Figure 7–63?
8 Preface
Applied Logic Appearing at the end of many chapters, this feature presents a practical
application of the concepts and procedures covered in the chapter. In most chapters, this
feature presents a “real-world” application in which analysis, troubleshooting, design,
VHDL programming, and simulation are implemented. Figure P-7 shows a portion of a
typical Applied Logic feature.
Floor Counter
Applied Logic library ieee;
ieee.numeric_std_all is included to enable casting of
use ieee.std_logic_1164.all; unsigned identifier. Unsigned FloorCnt is converted to
Elevator Controller: Part 2 use ieee.numeric_std.all; std_logic_vector.
entity FLOORCOUNTER is UP, DOWN: Floor count
˛˚˚˝˚˚¸
direction signals
port (UP, DOWN, Sensor: in std_logic; Sensor: Elevator car floor
In this section, the elevator controller that was introduced in the Applied Logic in Chap-
ter 9 will be programmed for implementation in a PLD. Refer to Chapter 9 to review the FLRCODE: out std_logic_vector(2 downto 0)); sensor
elevator operation. The logic diagram is repeated in Figure 10–62 with labels changed to end entity FLOORCOUNTER; FLRCODE: 3-digit floor
facilitate programming. count
architecture LogicOperation of FLOORCOUNTER is
PanelCode signal FloorCnt: unsigned(2 downto 0) := “000”; Floor count is initialized to 000.
begin
Numeric unsigned FloorCnt is con-
process(UP, DOWN, Sensor, FloorCnt)
verted to std_logic_vector data type
1 begin
CallCode and sent to std_logic_vector output
FLRCODE 6= std_logic_vector(FloorCnt); FLRCODE.
J K
CallEn
if (Sensor’EVENT and Sensor = ‘1’) then
˛˚˚˝˚˚¸
Q
Not CallEn Sensor event high pulse causes the
CALL/REQ FF
if UP = ‘1’ and DOWN = ‘0’ then floor count to increment when UP
CLK
FloorCnt 6= FloorCnt + 1; is set high or decrement by one
elsif Up = ‘0’ and DOWN = ‘1’ then when DOWN is set low.
FloorCnt 6= FloorCnt - 1;
CLOSE
end if;
FRIN end if;
Request FlrCodeIn QOut end process;
SetCount
CLK CALL/REQ Code Register Sys Clk Clk Timer end architecture LogicOperation;
Enable
FlrCodeOut
Call
FRCLOUT FLRCALL/FLRCNT Comparator
FLRCALL/FLRCNT
Comparator library ieee;
STOP/OPEN use ieee.std_logic_1164.all;
FlrCodeCall
UP
use ieee.std_logic_arith.all;
Floor
Counter DOWN entity FLRCALLCOMPARATOR is
Sensor
FlrCodeCall, FlrCodeCnt:
CLK FLRCODE FlrCodeCnt port (FlrCodeCall, FlrCodeCnt: in std_logic_vector(2 downto 0);
¸˝˛
(Floorpulse) Compared values
UP, DOWN, STOP: Output UP, DOWN, STOP: inout std_logic;
control signals end entity FLRCALLCOMPARATOR;
FRCNT
architecture LogicOperation of FLRCALLCOMPARATOR is
UP DOWN
H0 7-segment begin
7-Segment
H1 display of
˛˚˚˝˚˚¸
H2
Decoder
floor number STOP 6= ‘1’ when (FlrCodeCall = FlrCodeCnt) else ‘0’; STOP, UP, and DOWN
UP 6= ‘1’ when (FlrCodeCall 7 FlrCodeCnt) else ‘0’; signals are set or reset
a-g
based on =, 7, and 6
DOWN 6= ‘1’ when (FlrCodeCall 6 FlrCodeCnt) else ‘0’; relational comparisons.
FIGURE 10–62 Programming model of the elevator controller. end architecture LogicOperation;
The VHDL program code for the elevator controller will include component definitions
for the Floor Counter, the FLRCALL/FLRCNT Comparator, the Code Register, the Timer,
the Seven-Segment Decoder, and the CALL/REQ Flip-Flop. The VHDL program codes
for these six components are as follows. (Blue annotated notes are not part of the program.)
FIGURE P-7
End of Chapter
The following features are at the end of each chapter:
• Summary
• Keytermglossary
• True/falsequiz
• Self-test
• Problemsetthatincludessomeorallofthefollowingcategoriesinadditiontocoreprob-
lems: Troubleshooting, Applied Logic, Design, and Multisim Troubleshooting Practice.
• AnswerstoSectionCheckups
• AnswerstoRelatedProblemsforExamples
• AnswerstoTrue/Falsequiz
• AnswerstoSelf-Test
End of Book
Thefollowingfeaturesareattheendofthebook.
• Answerstoselectedodd-numberedproblems
• Comprehensiveglossary
• Index
Preface 9
To the Student
Digital technology pervades almost everything in our daily lives. For example, cell phones
and other types of wireless communications, television, radio, process controls, automotive
electronics, consumer electronics, aircraft navigation— to name only a few applications—
depend heavily on digital electronics.
A strong grounding in the fundamentals of digital technology will prepare you for
the highly skilled jobs of the future. The single most important thing you can do is to
understand the core fundamentals. From there you can go anywhere.
In addition, programmable logic is important in many applications and that topic in
introduced in this book and example programs are given along with an online tutorial.
Ofcourse,efficienttroubleshootingisaskillthatisalsowidelysoughtafterbypotential
employers. Troubleshooting and testing methods from traditional prototype testing to more
advanced techniques such as boundary scan are covered.
To the Instructor
Generally, time limitations or program emphasis determines the topics to be covered in a
course. It is not uncommon to omit or condense topics or to alter the sequence of certain
topics in order to customize the material for a particular course. This textbook is specifi-
cally designed to provide great flexibility in topic coverage.
Certain topics are organized in separate chapters, sections, or features such that if they are
omitted the rest of the coverage is not affected. Also, if these topics are included, they flow
seamlessly with the rest of the coverage. The book is organized around a core of fundamental
topics that are, for the most part, essential in any digital course. Around this core, there are other
topics that can be included or omitted, depending on the course emphasis and/or other factors.
Even within the core, selected topics can be omitted. Figure P-8 illustrates this concept.
Programmable Logic
and
PLD programming
Core
Troubleshooting Applied Logic
Fundamentals
Integrated
Special Topics Circuit
Technologies
FIGURE P-8
CAS 935 — CAS li'îmoipnafçfi des avanies que les f,'ens des
villes faisaient (•iidiircr aux paysans qui y apportaient let produits de
l'élalilc et d(! la bergerie. K. Cui.i.nv. CASirs (Kmioç). — Un des prinn
Koioi. Zens Kasios sous les traits d'un jeune li(unm(> tenant une
grenade h la(pn-Ue on attribuait une signillcalion mystérieuse*.
Cette Kienade apparaît comuK- type sur les monnaies du ni^nie
l'élusiaciue '°; en Syrie, elle était le symbole du dieu /liinm(in", dont
on rappi'ocli.iit petit-Mre Qanon ou Zeus Kasios, et sur le(|U('l on
racontait une fable pareille !i celle d'.\iiOMS ". Le culte de ce dieu
syiien fut porté, sans doute par suite de relations conunerciales,
dans les pays situés près lie l'entrée de la mer .\ilrialiqiu>, h une
époijue qui n'est pas déterminée, mais qui ne doit pas être fort
ancienne. Dans la ville maritime de (}assiopé en Kpire, il y avait un
tem|ile célèbre de Jupiter Casiiis, où sacrifia Néron "; c'est poui- cela
qm- certaines monnaies de cette ville portent d'un cAté la tète de
Zeus et de l'autre un aigle sin- le foudre". .\ Caircyre, la ville de
C.assiopé possédait un autre temple du même dieu ". Il est
représenté sur des monnaies de cette ilo frappées au tem|)s de la
domination romaine '*, avec son nom ZKVr, kacioc, assis sur un
trrtne ù ilossier et tenant le sceptre (lig. 1:2(17). Sa llguie est
devenue alors complètement hellénique. Dans les fables helléniques
qui se filmèrent ;\ .\ntiochc, sous les Séleucidi's.pour revendi>, Syrù
cfnlnlr. ln»cr. ■«iniliiiucs, lUuurag, «• 1; liiin n«tMli>i-n«, n* «. — » f.
Irnornidnl, Lrllrrt D« >»liu«. o/i. r. p. loi ri tuif. ; V. L«n. ^«Oj riiil.
Hùl. Kol. V, lî, U. — • Ackill. T«l. III. — '• Tuchun, MnUilIn i/rj niImm,
p. ISl; lirqur» dr Kounr, .Uuanori .;. nnmn, p. 11. — Il f, truarintnl,
(>p. r. I. Il, p. îl3. — U niUif, Commtniar tu /fxiiif, Kiii, s ; MiKor», /»!-
' i -.-it..» égorgea aussi, sur le tombeau de leur mère. et Pélops, les
deux petits enfants jumeaux (|Ui ! c avait eus d'.Xgamemnon *.
.Mycènes et Ainyclées se disputaient la sépulture de Cassandre *.
Klle avait, sous le nom il'.Mexandra, un temple et son image à
.Vmyclées '•. .\ Leiictres, où son culte était lié h celui d'.\pollon
Caméen, clic avait aussi un temple et le nom d'.Mexandra ". La
légende de Cassandre était figurée sur plusieurs célèbres
monuments de l'art hellénique. Sur le coffre célèbre que Cypsélus,
au commencement du vu* siècle av. J.-C, avait consacré à (Hyinpie,
on voyait .\jax arrachant Cassandre de l'autel d'.VIhènè ". Une
peinture du Ptecile, à Athènes, qui était l'œuvre de Polygnote,
représentait les chefs des Grecs assemblés pour délibérer sur
l'attentat d'.Vjax ; Cassandre était présente dans la troupe des
femmes captives ". Le même l'olygnote, dans le Lesché de Delphes,
avait représenté .\jax debout, jurant qu'il était innocent de la chute
du Palladium. Cassandra était assise à terre, tenant entre ses mains
la statue do bois d'Athènè, qu'elle avait détachée de sa base lorsque
.\jax " l'avait elle-même arrachée de l'autel. Le sujet de la violence
faite par .\jax à Cassandre se retrouve sur un grand nombre de
monuments antiques qui nous sont parvenus. (In le voit sur un bas-
relief du Louvre ", sur un autre bas-relief du casin de la rilla
Borghèse " et sur un troisième qui est au musée d'.\r!es ". Les vases
[teints où est r»'présentée la même scène sont trop nombreux pour
être ici énumérés ". Le plus remarquable de tous est sans doute une
coupe dont la peiné■■: Crin». p II - I» Jokâi. Ut.. ,. . É. — I» Sir^.
XVI. p. ri«. Vo;. otf. Muilrr, Àm». i» n»tl. arrA. L II, ^ Il •( >.; rr.
L«Mcmu(, CautU »rcl.é*io. -- i«:», p. »T-ioo. . ^^^«SDIlA. < n«ua.
I. 15. tt.j r . - « >-.iA .%.ii. • r.u.. 11. It. _ V. 1». — I» i.l 1 ( : - li ;
■•!4« ->«l.r^ njpa, XIII, :. XUl, "i. \1. i:i cl %.-. Il;(. '< Id. III. !i. —
u id. ^'-»(v d# irmtfl. pi. «m, An-A. Xr': B. J«i.,dn laïaiiMiaU 4»
Ua<> aalarr ii) alaal la alBa v^H; *«r4» ..pL in-u
CAS 936 — CAS ture est ici reproduite (fig. 1208), qui
appartient à la collection Campana, aujounl'lini an musée du Louvre.
On y voit Cassandre qui s'csl, prri-ipiléc aux pieds de la slalue Fig.
i'iOS. r.assandiT et Ajax. d'Athènè et l'embrasse. Ajax vient de
l'atteindre et déjà porte la main sur elle, mais il ne la saisit pas avec
la brutalité que dans les autres représentations de la même scène
les artistes ne se sont pas fait faute d'exprimer; son regard est dirigé
vers l'image de la déesse. Il semble que l'auteur de cette peinture ait
voulu disculper d'avance le héros du sacrilège dont il eut à se laver
dans l'assemblée des chefs, selon la tradition suivie par Polygnote.
Au-dessus des deux personnages on lit leurs noms: aia2 et
kaïsanapa. Ils sont désignés de la môme manière dans une peinture
murale d'un tombeau de Vulci ". Des miroirs étrusques ™, un casque
de bronze du musée de Naples^\ des pierres gravées --, offrent des
répétitions du même épisode. Une peinture de Pompéi représente,
d'après quelques auteurs, Gassandre prédisant, en présence de
Priam, de Mentor et d'Astyanax, la ruine de Troie-'. A. France.
CASSIS [galea, rete]. CASTELLANI. — Le castellum ou poste fortifié
servait quelquefois de centre de réunion aux habitants de loci ou via,
villages ou bourgs ruraux, soumis à une organisation unique '. Les
habitants s'appelaient castellani ^ et avaient une circonscription
déterminée, des cérémonies et des réunions communes et des
magistrats locaux ', mais ils dépendaient en général d'une cité
voisine, dans le territoire de laquelle ils étaient compris, -et à
laquelle ils se '9N. Dcsyergers, VEtrurie, pi. xxii ; Monum. de l'Inst.
anh.yi, pl.xxiii, 5; GarruccI, Tavole fotograf. d. pitture vulcenti,
staccate da un îpogeo pressa Ponte délia Badin, Rome, 1866, pi. i, 2.
— 20 Gerhard, Etr. Spiegel, t. IV, 406, i et 2. — 21 Heydemann,
Iliicpersis, pi. m, 1. — 22 Winckelmann, Catul. de Stosch, 333, 334;
Gori, Mus. Flor. t. Il, pi. XXII, n» 3; Mus. Worslei. IV, 32; Mus. Borb.
XVI, 10; Chabiiuillet, Catalogue, n" 1825; Annal, de finst. arch. t. L;
Winckelmann, Cat. de Stosch, n- 337. — 23 panofka, Arch. Zeilimg,
1848, pi. xvi, p. 242; Raoul Rochelle, Choix de peint, de Pompéi,
X.YV; Id. Lettre à Raleandij. p. 25; cf. Helbig, Wandgemàlde von
Yesuo verschiittcten Stâdte, n. 1391 b. CASTELLANI. 1 L. Rubria, col.
2, liv. Il, 26, à2. — 2 Comparczles aux BUncinii ou castriani A^ bas-
empire, — 3 T. Paul. Sent, rccept. IV, 6, 2. — '> L. Jnlia municip. lin.
142-158, ap. Haubuld.il/onum. p. 129-132. — 5 proiitin. o;) Gromat.
veteres, éd. Lachmaiin, p. 35. — 6 Voy. le lexle dans le recueil de M.
Egger, Latini serm. relig. Paris, 1843, p. 184 et s.; Corp. insc. ht. 1,
199 ; Orelli-Henzen, 11, n" 3121 ; m, p. 270; el l'édition commciili
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