Introduction [1-3]

▪ Digital circuits are divided into two broad categories:

1. Combinational Logic Circuits
2. Sequential Logic Circuits
▪ Combinational Logic Circuit: In these circuits, the outputs at
any instant of time depend upon the inputs present at that instant
of time. This means there is no memory in these circuits.

inputs :: Combinational :: outputs

Logic
 Introduction [1-3]
▪ Sequential Logic Circuit: In these circuits, the outputs at any
instant of time depend upon the present inputs as well as past
inputs/outputs. This means that there are elements used to store
past information. These elements are known as memory.

inputs :: Combinational :: outputs

Logic
Memory

▪ A sequential logic system may have combinational logic sub-

systems.
 Analysis Procedure [1]
▪ A combinational circuit is given, analyze its function?

A A+B
B F1 = (A+B).(A'+B')

F2 = (A'+B')' = A.B
A'+B'
Steps: A B (A+B) (A'+B') F1 F2
1. Label the inputs and outputs. 0 0 0 1 0 0
0 1 1 1 1 0
2. Obtain the functions of intermediate 1 0 1 1 1 0
points and the outputs. 1 1 1 0 0 1

3. Draw the truth table.

4. Deduce the functionality of the circuit  half adder.
 Design Methods [1]
▪ Different combinational circuit design methods:
❖ Gate-level method (with logic gates)
❖ Block-level design method

▪ Design methods make use of logic gates and useful functional

blocks.
❖ These are available as Integrated Circuit (IC) chips.
 Design Methods [1]
▪ Type of IC chips (based on packing density):
❖ Small-scale integration (SSI): up to 12 gates
❖ Medium-scale integration (MSI): 12-99 gates
❖ Large-scale integration (LSI): 100-9999 gates
❖ Very large-scale integration (VLSI): 10,000-99,999 gates
❖ Ultra large-scale integration (ULSI): > 100,000 gates
▪ Main objectives of circuit design:
(i) Reduce cost
➢ Reduce number of gates (for SSI circuits)
➢ Reduce IC packages (for complex circuits)
(ii) Increase speed
(iii) Design simplicity (reuse blocks where possible)
 Half Adder [2]
▪ A logic circuit for the addition of two one-bit numbers is
referred to as an half-adder.
▪ Design procedure:
1) State Problem
Example: Build a Half Adder to add two bits
2) Determine and label the inputs & outputs of circuit.
▪ Example: Two inputs and two outputs labelled, as follows:

X Half S
Y Adder C
(X + Y)
X Y C S
3) Draw truth table. 0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Gate-level Design: Half Adder [2]
4) Obtain simplified Boolean function.
Example: C = X.Y
S = X'.Y + X.Y' = XY
X Y C S
5) Draw logic diagram. 0 0 0 0
0 1 0 1
X 1 0 0 1
S 1 1 1 0
Y

Half Adder
 Full Adder [2]
▪ Half-adder adds only two bits and there is no provision to add a
carry coming from the lower order bits when multibit addition is
performed.
▪ To add two binary numbers, we need to add 3 bits (including the
carry).
▪ Example:
1 1 1 carry
0 0 1 1 X
+ 0 1 1 1 Y
1 0 1 0 S

▪ Need Full Adder (as it can be made from two half-adders).

X
Full S
Y
Z
Adder C
(X + Y + Z)
 Full Adder [2]
▪ Truth table:
X Y Z C S Note:
0 0 0 0 0 Z - carry in (to the current position)
0 0 1 0 1 C - carry out (to the next position)
0 1 0 0 1
0 1 1 1 0 C
YZ
1 0 0 0 1 X
00 01 11 10
1 0 1 1 0 0 1
1 1 0 1 0
1 1 1 1
1 1 1 1 1
YZ
S
00 01 11 10
Using K-map, simplified SOP form: X
0 1 1
• C = X.Y + X.Z + Y.Z
1 1 1
• S = X'.Y'.Z + X'.Y.Z'+X.Y'.Z'+X.Y.Z
 Full Adder [3]
▪ Alternative formulas using algebraic manipulation:
C = X.Y + X.Z + Y.Z
= X.Y + X (Y+Y').Z + (X+X')YZ
= X.Y + X YZ+XY'Z + X YZ +X'YZ
= X.Y (1+Z) + (XY).Z
= X.Y + (XY).Z
S = X'.Y'.Z + X'.Y.Z' + X.Y'.Z' + X.Y.Z
= X'.(Y'.Z + Y.Z') + X.(Y'.Z' + Y.Z)
= X'.(YZ) + X.(YZ)'
= X(YZ) or (XY)Z
 Gate-level Design: Full Adder [3]
▪ Circuit for following formulas:
C = X.Y + (XY).Z
S = (XY)Z
X (XY)
Y S

(XY)

▪ Full Adder is made from two Half-Adders (+ OR gate).

 Full Adder [3]
▪ Circuit for following formulas:
C = X.Y + (XY).Z Block diagrams.
S = (XY)Z
X (XY)
X Sum X
Y Y Sum S
Y
Half Half
Adder Adder
(X.Y)
Carry Carry
C

Full Adder made from two Half-Adders (+ OR gate).

 Half Subtractor [2]
1) Obtain simplified Boolean function. X Y B D
0 0 0 0
B (Borrow) = X'.Y 0 1 1 1
D (Difference) = X'.Y + X.Y' = XY 1 0 0 1
2) Draw logic diagram. 1 1 0 0

X
D
Y

B
 Full Subtractor [2]
▪ A full subtractor is a
BOUT D
combinational circuit that X Y Bin
(Borrow) (Difference)
performs subtraction involving
three bits, namely minuend, 0 0 0 0 0
subtrahend, and borrow-in (Bin). 0 0 1 1 1
The logic symbol and truth table 0 1 0 1 1
are shown here. 0 1 1 1 0
Symbol: 1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 Full Subtractor [2]
• Draw K-maps using the previous truth table and determine
the simplified Boolean expressions-
 Full Subtractor [2]
▪ Draw the logic diagram.
▪ The implementation of full adder using 1 XOR gate, 3 AND
gates, 1 NOT gate and 1 OR gate is as shown below.
 Full Subtractor [3]
▪ Alternative formulas using algebraic manipulation:
Bout = X'.Y + X'. BIN + Y. BIN
= X'.Y + (X' + Y). BIN
= X'.Y + ((XY)' + X'.Y). BIN
= X'.Y + (XY)'. BIN + X'.Y. BIN
= X'.Y + (XY)'. BIN

D= X'.Y'.BIN + X'.[Link] ' + X.Y'.BIN ' + [Link]

= X' .(Y'.BIN + [Link] ') + X.(Y'.BIN ' + [Link])
= X'.(YBIN) + X.(YBIN)'
= X(YBIN) or (XY)BIN
 Full Subtractor [3]
▪ Circuit for following formulas:
BOUT = X'.Y + (XY)'.BIN
Diff = (XY)BIN

Full Subtractor made from two Half-Subtractors (+ OR gate).

 Full Subtractor [3]
▪ Circuit for following formulas:
BOUT = X'.Y + (XY)'.BIN
Diff = (XY)BIN Block diagrams.

Full Subtractor made from two Half-Subtractors (+ OR gate).

 Block-Level Design Method [1]
▪ More complex circuits can also be built using block-level
method.
▪ In general, block-level design method (as opposed to gate-level
design) relies on algorithms or formulae of the circuit, which
are obtained by decomposing the main problem to sub-problems
recursively (until small enough to be directly solved by blocks
of circuits).
▪ Simple examples using 4-bit parallel adder as building blocks:
(1) BCD-to-Excess-3 Code Conversion
(2) 16-Bit Parallel Adder
(3) Adder cum Subtractor

20
 Parallel Adders [1-3]
▪ Note that carry propagated by cascading the carry from one full
adder to the next.

▪ It is called Parallel Adder because inputs are presented

simultaneously (in parallel).

▪ It is also called Ripple-Carry Adder.

21
 4-bit Parallel Adder [1-3]
▪ Consider a circuit to add two 4-bit numbers together and a carry-
in, to produce a 5-bit result:
X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit
C5 C1
Parallel Adder

Black-box view of 4-bit

S4 S3 S2 S1 parallel adder

▪ 5-bit result is sufficient because the largest result is:

(1111)2+(1111)2+(1)2 = (11111)2
22
 4-bit Parallel Adder [1-3]
▪ SSI design technique should not be used.
▪ Truth table for 9 inputs very big, i.e. 29=512 entries:
X4X3X2X1 Y4Y3Y2Y1 C1 C5 S4S3S2S1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0 0 1
... ... ... ... ...
0 1 0 1 1 1 0 1 1 1 0 0 1 1
... ... ... ... ...
1 1 1 1 1 1 1 1 1 1 1 1 1 1

▪ Simplification is very complicated.

23
 4-bit Parallel Adder [1-3]
▪ Cascading 4 full adders via their carries, we get:
Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2

C5 FA FA FA FA C1

Input S4 S3 S2 S1

Output

24
 16-bit Parallel Adder [1-3]
▪ Larger parallel adders can be built by cascading the smaller
ones.
▪ Example: a 16-bit parallel adder can be constructed from four 4-
bit parallel adders:

X16..X13 Y16..Y13 X12..X9 Y12..Y9 X8..X5 Y8..Y5 X4..X1 Y4..Y1

4 4 4 4 4 4 4 4

C17 4-bit // C13 4-bit // C9 4-bit // C5 4-bit // C1

adder adder adder adder
4 4 4 4

S16..S13 S12..S9 S8..S5 S4..S1

A 16-bit parallel adder 25

 16-bit Parallel Adder [1-3]
▪ Shortened notation for multiple lines.

4 is a shortened
notation for
S4 .. S1 S4 S3 S2 S1

▪ 16-bit parallel adder ripples carry from one 4-bit block to the
next.
▪ Such ripple-carry circuits are “slow” because of long delays
needed to propagate the carries.

26
4-bit Parallel Adder Cum Subtractor [1-3]
▪ Subtraction can be performed through addition using 2’s-
complement numbers.
▪ Hence, we can design a circuit which can perform both
addition and subtraction, using a parallel adder.
X4 X3 X2 X1 Y4 Y3 Y2 Y1

4-bit adder
S: control signal
cum subtractor for add/subtract

Result: either X+Y or X-Y

27
4-bit Parallel Adder Cum Subtractor [1-3]
▪ The control signal S=0 means add
S=1 means subtract
▪ Recall that:

Subtraction
X-Y = X + (-Y)
= X + (2’s complement of Y)
= X + (1’s complement of Y) +1

Addition
X+Y = X + (Y)

28
4-bit Parallel Adder Cum Subtractor [1-3]
▪ Design requires:
(i) XOR Gates:

Y Y Y Y'
S=0 S=1

such that: output = Y when S=0

= Y' when S=1

(ii) S connected to carry-in.

29
4-bit Parallel Adder Cum Subtractor [1-3]
▪ Adder cum subtractor circuit:
Y4 Y3 Y2 Y1
S
X4 X3 X2 X1

C Cout 4-bit Cin

parallel adder Analysis:

If S=1, then
S4 S3 S2 S1 X + (1's complement of Y) +1
appears as the result.
A 4-bit adder cum subtractor
If S=0, then X+Y appears as
the result.
30
 Faster Circuits [1-3]
▪ Three ways of improving the speed of these circuits:
(i) Use better technology (e.g. ECL faster than TTL gates), but
faster technology is more expensive, needs more power, lower-
level of integrations.
(ii) Use gate-level designs to two-level circuits (use sum-of-
products/product-of-sums) but
(a) Complicated designs for large circuits.
(b) Product/sum terms need many inputs.
(iii) Use look-ahead techniques but there are additional costs
(hopefully reasonable).

31
 Look-Ahead Carry Adder [1, 3]
▪ Consider the full adder:
Xi Pi where intermediate signals
Yi Si are labelled as Pi, Gi, and
Gi defined as:
Ci+1 Pi = XiYi
Ci Gi = [Link]
The outputs, Ci+1, Si, in terms of Pi, Gi, Ci, are:
Si = Pi  Ci …(1)
Ci+1 = Gi + [Link] …(2)
If you look at equation (2),
Gi = [Link] is a carry generate signal
Pi = Xi  Yi is a carry propagate signal

32
 Look-Ahead Carry Adder [1, 3]
▪ For 4-bit ripple-carry adder, the equations to obtain four carry
signals are:
Ci+1 = Gi + [Link]
Ci+2 = Gi+1 + Pi+[Link]+1
Ci+3 = Gi+2 + Pi+[Link]+2
Ci+4 = Gi+3 + Pi+[Link]+3

▪ These formula are deeply nested, as shown here for Ci+2:

Ci
Pi
Ci+1
Gi

Pi+1
Ci+2
Gi+1

33
4-level circuit for Ci+2 = Gi+1 + Pi+[Link]+1
 Look-Ahead Carry Adder [1, 3]
▪ Nested formula/gates cause ripple-carry propagation delay.
▪ Can reduce delay by expanding and flattening the formula for
carries. For example, Ci+2
Ci+2 = Gi+1 + Pi+[Link]+1
= Gi+1 + Pi+1.(Gi + [Link] )
= Gi+1 + Pi+[Link] + Pi+[Link]

▪ New faster circuit for Ci+2

Ci
Pi
Pi+1
Gi Ci+2
Pi+1
Gi+1

34
 Look-Ahead Carry Adder [1, 3]
▪ Other carry signals can also be similarly flattened.
Ci+3= Gi+2 + Pi+2Ci+2
= Gi+2 + Pi+2(Gi+1 + Pi+1Gi + Pi+1PiCi)
= Gi+2 + Pi+2Gi+1 + Pi+2Pi+1Gi + Pi+2Pi+1PiCi
Ci+4 = Gi+3 + Pi+3Ci+3
= Gi+3 + Pi+3(Gi+2 + Pi+2Gi+1 + Pi+2Pi+1Gi + Pi+2Pi+1PiCi)
= Gi+3 + Pi+3Gi+2 + Pi+3Pi+2Gi+1 + Pi+3Pi+2Pi+1Gi + Pi+3Pi+2Pi+1PiCi

▪ Notice that formulae gets longer with higher carries.

▪ Also, all carries are two-level “sum-of-products” expressions,
in terms of the generate signals, Gs, the propagate signals, Ps,
and the first carry-in, Ci.
35
 Look-Ahead Carry Adder [1, 3]
▪ We employ the look-ahead formula in this look-ahead carry adder
circuit:

36
 Look-Ahead Carry Adder [1, 3]
▪ We employ the look-ahead formula in this look-ahead carry adder
circuit:

37
 Look-Ahead Carry Adder [1, 3]
▪ Delay time of n-bit CLAA = XOR + (AND + OR) + XOR

38
 Assignment
• BCD Adder

39
Non-Ideal Gate Behavior: Delay [1-3]
▪ Real gates have some delay.
▪ Outputs don’t change immediately after inputs change.

40
Primitive Device Delay Models [1-3]
▪ Every primitive logic gate has an intrinsic delay.
▪ A gate can be modeled as an ideal (zero-delay) gate and a
transport delay element.
a c*
t c
b
Ideal Time
gate delay

▪ Different models of transport delays:

• Unit/Nominal Delay
• Rise Fall Delay
• Ambiguous or Min/Max Delay
41
 Unit/Nominal Delay [1-3]
▪ Unit Delay: Assign to each gate in a circuit the same unit
delay.
▪ Nominal Delay: Delays are determined separately for each
type of gate e.g. one time unit for NOR and two time units for
XOR.
a

t t

42
 Rise/Fall Delay [1-3]
▪ There are different delays for 0 to 1 transition and 1 to 0
transition as follows.
▪ tPLH (Rise time): propagation delay from low to high.
▪ tPHL (Fall time): propagation delay from high to low.
a

tPLH tPHL
(rise time) (fall time)

43
Ambiguous or Min/Max Delay [1-3]
▪ Sometimes it is impossible to predict exact rise or fall time of
a signal.
▪ For worst-case performance analysis, {tmin, tmax} is specified
for each timing parameter.

c
tmin

tmax
44
 Inertial Delay [1-3]
▪ An input value must persist for some minimum duration of
time to provide the output with the needed inertia to change.
▪ The minimum duration is called inertial delay.
▪ Effect of inertial delay:
t a*
a
c* t c
b t
b*
Inertial Ideal Transport
delay gate delay

▪ Gate model with both inertial delay and transport delay:

a a

b b

c c
(a) Transport delay model (b) Inertial delay model
45
 Calculation of Circuit Delays [1-3]
▪ In general, given a logic gate with delay, t.
t1
t2 Logic
: : Gate
tn max (t1, t2, ..., tn ) + t

• If inputs are stable at times t1,t2,..,tn, respectively; then the

earliest time in which the output will be stable is:
max(t1, t2, .., tn) + t
▪ To calculate the delays of all outputs of a combinational circuit,
repeat above rule for all gates.

46
 Calculation of Circuit Delays [1-3]
▪ As a simple example, consider the full adder circuit where all
inputs are available at time 0. (Assume each gate has delay t.)

X 0 max(0,0)+t = t
max(t,0)+t = 2t
Y 0 S

t 2t max(t,2t)+t = 3t
C
0
Z

where outputs S and C, experience delays of 2t and 3t,

respectively.

47
 Calculation of Circuit Delays
▪ More complex example: 4-bits parallel adder.

Y4 X4 Y3 X3 Y2 X2 Y1 X1
C4 C3 C2
0 0 0 0 0 0 0 0

0
C5 FA FA FA FA C1

S4 S3 S2 S1

48
 Calculation of Circuit Delays
▪ Analyse the delay for the repeated block:
Xi 0 where Xi, Yi are
Full Si stable at 0t, while
Yi 0
mt Adder Ci+1 Ci is assumed to
Ci be stable at mt.
Performing the delay calculation gives:
Xi 0 max(0,0)+t = t
max(t,mt)+t
Yi 0 Si

t max(t,mt)+t
max(t,mt)+2t
Ci+1
mt
Ci

49
 Calculation of Circuit Delays
▪ Calculating:
When i=1, m=0: S1 = 2t and C2 = 3t.
When i=2, m=3: S2 = 4t and C3 = 5t.
When i=3, m=5: S3 = 6t and C4 = 7t.
When i=4, m=7: S4 = 8t and C5 = 9t.
▪ In general, an n-bit ripple-carry parallel adder will experience:
Sn = a+(n-1)*d
= 2t +(n-1)2t
=n(2t)
Cn+1 = 3t +(n-1)2t
=t +2nt
=(2n+1)t
Propagation delay of ripple-carry parallel adders is proportional
to the number of bits it handles. 50
 References
[1] M. Morris Mano and Michael D. Ciletti, “Digital Design with
an Introduction to the Verilog HDL”, 5th Edition, Pearson
Education, 2013.

[2] S. Salivahanan and S. Arivazhagan, “Digital circuits and

design”, Vikas Publishing House PVT Limited, Fifth edition.

[3] A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI,

Fourth Edition.

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