DUAL-MODE PUF AND RECYCLED IC DETECTION CIRCUIT USING

CADENCE TOOLS

PROJECT REPORT

Submitted by

BHUVANESHWARAN D (REGNO : 113122UG04014)

PRAVIN E (REG NO : 113122UG04076)

SRINATH R (REG NO : 113122UG04101)

in partial fulfillment for the award of the degree of

BACHELOR OF ENGINEERING

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

VEL TECH MULTI TECH Dr. RANGARAJAN Dr. SAKUNTHALA

ENGINEERING COLLEGE, AVADI, CHENNAI

ANNA UNIVERSITY: CHENNAI : 600 025

NOVEMBER 2025
 BONAFIDE CERTIFICATE

Certified that this project report “DUAL-MODE PUF AND RECYCLED IC

DETECTION USING CADENECE TOOLS” is the bonafide work of
BHUVANESHWARAN D (113122UG04014), PRAVIN E (113122UG04076),
SRINATH R (113122UG04101),Who carried out the project work under my
supervision for the partial fulfillment of the requirements for the award of the
degree of bachelor of engineering in Electronics And Communication Engineering.

SIGNATURE SIGNATURE
Dr. V. PRABHU., M.E., Ph. D. Mr. [Link].,M.E.
HEAD OF THE DEPARTMENT PROJECT SUPERVISOR
Electronics and Communication Electronics and Communication
Engineering Engineering
Vel Tech Multi Tech [Link] Vel Tech Multi Tech [Link]
Dr. Sakunthala Engineering College Dr. Sakunthala Engineering College
Avadi, Chennai-600 062. Avadi, Chennai-600 062.

II
 ACKNOWLEDGEMENT

We wish to express our sincere thanks to almighty and the people who extended
their help during the course of work

We are greatly and profoundly thankful to our honourable Chairman, Col. Prof.
Vel. Shri [Link] B.E.(ELEC), B.E.(MECH), M.S.(AUTO), [Link].,
and Vice Chairman, [Link] Rangarajan MBBS., for facilitating
us with this opportunity.

We take this opportunity to extend our gratefulness to our respectable

Chairperson and Managing Trustee Dr. Mrs. Rangarajan Mahalakshmi
Kishore B.E., M.B.A., for her continuous encouragement.

We also record our sincere thanks to our honourable Principal, [Link]

M.E., Ph.D., FIE, MIETE, MISTE. for his kind support to take up this project
and complete it successfully.

We would a like to express our special thanks to our Head of the department,Dr.
V. Prabhu., M.E.,Ph.D, and our Project Supervisor [Link].,M.E for
their moral support by taking keen interest on our project work and guided us all
long,till the completion of our project work.

Further, the acknowledgement would be incomplete if we would not mention a

word of thanks to our most beloved Parents for their continuous support and
encouragement all the way through the course that has led us to pursue the degree
and confidently complete the project work.

Signature of students:

BHUVANESHWARAN D

PRAVIN E

SRINATH R

iii
 CERTIFICATION OF EVALUATION

COLLEGE CODE/NAME : 1131-Vel Tech Multi Tech [Link]

[Link] Engineering College
DEPARTMENT : Electronics And Communication Engineering

SEM/YEAR : VII / IV
SUB CODE / NAME : 191EC77A / PROJECT WORK PHASE 1

S.N NAME OF THE TITLE OF THE NAME OF THE

STUDENTS PROJECT INTERNAL
O GUIDE
BHUVANESHWARAN D
1.
(113122UG04014)
DUAL-MODE PUF
PRAVIN E AND RECYCLED
2. [Link].,
(113122UG04076) IC DETECTION
M.E
SRINATH R CIRCUIT USING
3. CADENCE TOOLS
(113122UG04101)

This is to certify that the project entitled “DUAL-MODE PUF AND

RECYCLED IC DETECTION USING CADENECE TOOLS” is the
bonafide record of work under done by the above students who carried out the
project work under our guidance during the year 2025-2026 in partial
fulfillment of the award of Bachelor of Engineering degree in Electronics and
communication Engineering of Anna University Chennai.
Submitted for the Viva-voice held on……………………at Veltech Multi Tech
[Link] [Link] Engineering College

INTERNAL EXAMINER EXTERNALEXAMINER

iv
 ABSTRACT

This work presents a dual-mode hardware security architecture designed and

implemented using Cadence Virtuoso and Spectre tools to enhance the reliability and
authenticity of integrated circuits (ICs). The proposed design integrates a Ring
Oscillator (RO)-based Physical Unclonable Function (PUF) and an aging-aware
recycled IC detection mechanism within a unified framework. Sixteen ROs are
developed to exploit process variations, ensuring a unique hardware fingerprint for
each chip. In Mode 1, the frequency difference between selected oscillator pairs is
compared to generate a stable and unique Secure ID for authentication. In Mode 2,
the system detects recycled ICs by analyzing deviations between reference and
current frequencies obtained through software-based analysis. Simulation results
confirm accurate Secure ID generation and reliable detection of aging-induced
degradation. The architecture provides a compact, low-power, and secure solution for
modern VLSI hardware protection.

v
 TABLE OF CONTENTS

CHAPTER NO CONTENTS PAGE NO

LIST OF FIGURES viii

LISTOF TABLES ix

LIST OF ABBREVATIONS x

1 INTRODUCTION 1

1.1 Software design overview 1

1.2 Need for secure ICs 3
1.3 Objective of the project 4
1.4 Significance 5

2 LITERATURE REVIEW 7

2.1 Existing Literature 7

2.2 Challenges Identfied 13

2.3 Objectives of the work 14

3 EXISTING AND PROPOSED SYSTEM 15

3.1 Existing system 15

3.2 Proposed system 16

3.3 Operating mode 18
3.3.1 Application challenges 18
3.3.2 Counter measurement 19
3.3.3 Resposnse generation 19
3.4 Data flow 20

vi
4 SIMULATION RESULT AND ANALYSIS 22

4.1 Simulation environment and setup 22

4.1.1 Desgin environment 22

4.1.2 Desgin configuration 23

4.1.3 Simulation parameters 23

4.2 Simulation procedure 24

4.2.1 Schematic creation and verification 24

4.2.2 Biasing and boundary conditions 24

4.2.3 Simulation execution 25

4.3 Obtained simulation waveforms 25

4.3.1 Ring oscillator outputs 25

4.3.2 Multiplexer and counter outputs 26

4.4 MUX selection simulation 27

4.4.1 MUX1 and MUX2 configuration 27

4.4.2 Waveform observation 27

4.5 Simulation output of secure id in Mode 1 28

5 AGING-AWARE RING OSCILLATOR PUF FOR

RECYCLED TC DETECTION 30

5.1 Overview 30

5.1.1 Introduction 30

5.1.2 Objective of mode 31

5.1.3 Current work status 31

vii
 LIST OF FIGURES

FIGURE NO CONTENT PAGE NO

3.1 Integration of mode1and mode2 17

3.2 Secured ID generation 20

4.1 ROs with different frequency 26

4.2 ROs selection via MUX 28

4.3 Mode secure ID output 29

viii
 LIST OF TABLES

TABLE NO CONTENT PAGE NO

4.1 Simulation parameters 23

4.3 ROs frequency response 26

ix
 LIST OF ABBREVIATION

Complementary Metal-Oxide-Semiconductor
CMOS

CRP Challenge-Response Pair

DRC Desgin Rule Check

FPGA Field-Programmable Gate Array

FSM Finite State Machine

IC Integrated Circuit

LVS Layout Versus Schematic

MUX Multiplexer

PUF Physical Unclonable Function

RO Ring Oscillator

TRNG True Random Number Genaerator

x
 CHAPTER 1
INTRODUCTION
Applications involving critical systems, like communication, medical devices,
Defense electronics, and IoT platforms, are increasingly reliant on ICs. This has
raised concerns about hardware security and trust. Counterfeit and recycled ICs
flowing into the supply chain bear severe risks including performance degradation,
malfunction, and vulnerability to malicious attacks. Conventional ID-based protection
methodologies have store-based keys that are vulnerable to duplication, extraction,
and reverse engineering. Thus, intrinsic security mechanisms within hardware are
essential in ensuring chip authenticity without resorting to externally stored secrets.

PUFs exploit inevitable manufacturing variations within every IC for a robust

solution. Among different types of PUFs, Ring Oscillator-based ones have
advantages of simple structure, low power, and are easily integrated into standard
CMOS design flows. The implementation of a dual-mode RO-PUF architecture has
been presented in this paper with the help of Cadence Virtuoso and Spectre
simulation tools. Mode 1 generates the unique Secure ID by comparing the
frequencies of RO pairs, while Mode 2 detects the recycled ICs by analyzing the
delay degradation due to transistor aging. This work presents a lightweight, reliable,
and practical combined security solution suitable for modern VLSI systems.

1.1 SOFTWARE DESIGN OVERVIEW

In today’s technological era, integrated circuits (ICs) form the backbone of

almost every electronic system, ranging from communication equipment, automotive
electronics, and medical devices to defense applications and IoT-based platforms. As
these systems become increasingly complex and interconnected, the importance of
ensuring the reliability, authenticity, and trustworthiness of ICs has grown
significantly. However, the rapid globalization of semiconductor manufacturing and
the outsourcing of production to different vendors have introduced serious concerns
1
regarding hardware security and supply chain integrity. Counterfeit and recycled ICs
are increasingly finding their way into legitimate markets, creating major threats to
device performance, system reliability, and national security.

Counterfeit ICs often include recycled, remarked, or cloned chips that are
fraudulently sold as new. Recycled ICs, in particular, pose a subtle yet critical
challenge because they are extracted from old electronic products, reconditioned, and
reintroduced into the supply chain. These chips, though functional, have already
undergone operational stress, aging effects, and environmental degradation, which
significantly reduce their lifespan and performance. Their usage in sensitive
applications such as aerospace control systems, medical monitoring devices, or
defense electronics can lead to unpredictable failures with severe consequences.
Therefore, detecting recycled ICs and verifying chip authenticity have become crucial
to ensuring trustworthy electronic systems.

Conventional hardware protection mechanisms, such as cryptographic key

storage in non-volatile memory or the use of serial identification numbers, are no
longer sufficient to guarantee hardware trust. Stored keys can be duplicated, extracted,
or modified through invasive attacks, while serial numbers can be easily cloned. To
address these vulnerabilities, intrinsic hardware-based security methods have been
introduced, where the identity of a chip is derived from its own physical
characteristics. Physical Unclonable Functions (PUFs) are one such promising
technology that utilizes manufacturing variations introduced during fabrication to
generate unique identifiers for each chip. Since these variations are random and
uncontrollable, no two ICs can ever produce the same PUF response, making it
impossible to clone or predict the hardware identity.

Among the various types of PUFs, the Ring Oscillator-based PUF (RO-PUF)
has attracted significant attention due to its simplicity, low power consumption, and
ease of integration into standard CMOS design flows. RO-PUFs use frequency
differences between identically designed ring oscillators to generate unique responses

2
that serve as chip fingerprints. These frequency variations arise from minute
differences in transistor threshold voltages, oxide thickness, and channel dimensions
during manufacturing. The inherent randomness in such parameters ensures
uniqueness and unclonability across ICs. Therefore, RO-PUFs are widely regarded as
an efficient, lightweight, and reliable solution for on-chip authentication and anti-
counterfeiting applications.

This project focuses on developing a dual-mode hardware security architecture

using Cadence Virtuoso and Spectre simulation tools. The proposed design not only
authenticates genuine ICs using an RO-PUF structure but also detects recycled ICs
through an aging-based analysis mechanism. This dual-mode approach provides a
comprehensive solution that ensures both authentication and lifecycle integrity,
making it highly relevant for next-generation secure electronic systems.

1.2 NEED FOR SECURE ICs

The proliferation of counterfeit and recycled Integrated Circuits (ICs) in the

global semiconductor supply chain has become a major concern, as recycled chips
often pass functional tests despite exhibiting significant aging-related degradation.
These effects, such as threshold voltage shifts, mobility reduction, and increased
propagation delay, gradually deteriorate the performance and reliability of ICs [8].
When such degraded chips are unknowingly integrated into mission-critical systems,
they can lead to serious operational failures and compromise system integrity [7].
Existing security methods, including software-based cryptography and hardware-
level key storage, fail to detect recycled ICs effectively since stored keys or codes can
be extracted or duplicated through invasive attacks.

To overcome these limitations, Physical Unclonable Functions (PUFs) have

emerged as a more secure and intrinsic hardware security primitive by exploiting
natural process variations rather than stored data[3]. Among them, Ring Oscillator-
based PUFs (RO-PUFs) are widely adopted for their simplicity, compactness, and
scalability [1]. However, conventional RO-PUFs focus primarily on authentication
3
and uniqueness but do not address the identification of aged or recycled chips. Since
transistor aging mechanisms such as Bias Temperature Instability (BTI) and Hot
Carrier Injection (HCI) alter the delay characteristics of ring oscillators over time, the
frequency degradation of ROs can be utilized as a reliable indicator for recycled IC
detection [10].

The challenge lies in differentiating between frequency variations caused by

manufacturing process differences (used for authentication) and those induced by
transistor aging (used for recycled chip detection). Therefore, the proposed system
introduces an Aging-Aware RO-PUF that combines both process variation-based
authentication and aging analysis within a unified framework. Implemented and
simulated using Cadence Virtuoso and Spectre tools, this design allows precise
monitoring of frequency drifts between reference and stressed ROs to identify reused
ICs. This dual-mode architecture improves chip-level trustworthiness, ensures secure
authentication, and offers a low-cost, energy-efficient solution for detecting recycled
components in real-world semiconductor applications [9].

1.3 OBJECTIVES OF THE PROJECT

The primary objective of this project is to design and simulate a dual-mode

hardware security architecture using Cadence tools that can perform both chip
authentication and recycled IC detection efficiently. The design integrates a Ring
Oscillator-based Physical Unclonable Function (RO-PUF) with an aging analysis
mechanism in a single framework. The goal is to achieve a lightweight, reliable, and
energy-efficient hardware-level security solution suitable for integration into modern
VLSI systems.

In the proposed design, sixteen identical Ring Oscillators are implemented at

the circuit level using Cadence Virtuoso. These oscillators exploit natural process
variations that occur during manufacturing to produce unique frequency
characteristics for each IC. The outputs of the ROs are connected through
multiplexers, which select specific oscillator pairs based on unpredictable challenge
4
inputs generated by a True Random Number Generator (TRNG). This setup forms the
basis for generating challenge-response pairs used for authentication.

In Mode 1, the system operates as a traditional RO-PUF, where the frequency

differences between selected RO pairs are measured to generate a stable and unique
Secure ID. This ensures reliable chip authentication, as even chips fabricated from the
same design and process exhibit distinct frequency responses due to intrinsic
variations. In Mode 2, the design focuses on recycled IC detection by introducing
controlled delay degradation to simulate transistor aging. By analyzing the frequency
shifts caused by these aging effects, the system can identify whether a chip has been
previously used or exposed to stress conditions.

Through comprehensive simulations performed using Cadence Spectre, both

operational modes are validated in terms of reliability, stability, and aging sensitivity.
The ultimate objective is to establish a dual-function security system that ensures chip
authenticity while preventing the reuse of recycled ICs, contributing to enhanced
security and dependability in hardware systems.

1.4 SIGNIFICANCE

The significance of this project lies in its ability to provide a comprehensive

hardware security solution that addresses two critical challenges—chip authentication
and recycled IC detection—using a single, compact circuit design. The integration of
both mechanisms in one architecture reduces hardware overhead, minimizes cost, and
improves system efficiency. Unlike conventional PUFs, which focus solely on
authentication, the proposed dual-mode design extends functionality to detect
recycled ICs by leveraging the effects of transistor aging. This makes it an innovative
and practical approach to ensuring IC integrity throughout its lifecycle.

The project also demonstrates the use of Cadence Virtuoso and Spectre tools
for circuit-level design, simulation, and validation, reflecting the real-world process
of VLSI implementation. Cadence tools provide accurate modeling of transistor-level
5
variations and aging effects, ensuring the proposed system is not only theoretically
sound but also technologically feasible for fabrication. The dual-mode circuit’s
scalability and CMOS compatibility make it suitable for integration into a wide range
of applications, including IoT devices, automotive electronics, and defense systems.

By combining PUF-based authentication and aging-based detection, the project

contributes to advancing hardware trust and supply chain security. It provides a
lightweight alternative to complex cryptographic methods while maintaining
robustness against cloning and tampering. Moreover, the design’s ability to detect
aged or recycled chips enhances device reliability and prevents the circulation of
degraded components in the market.

Overall, this project presents a novel, reliable, and efficient solution for
modern VLSI security challenges. It strengthens the foundation of hardware trust,
supports the prevention of counterfeit chip usage, and offers valuable insights into
future hardware security research and industrial applications.

6
 CHAPTER 2

LITERATURE REVIEW

2.1 EXISTING LITERATURE

[1] A robust Ring Oscillator-based Physical Unclonable Function (RO-

PUF) architecture designed to enhance hardware-level cryptographic
security. Traditional RO-PUFs suffer from limited challenge-response pairs,
classifying them as weak PUFs. To overcome this, the authors propose a
Configurable Ring Oscillator PUF (RACRO-PUF) that uses a configurable
inversion unit composed of XOR, XNOR, and multiplexer circuits, enabling
more challenge variations without increasing hardware cost. The design was
implemented on a Xilinx FPGA and evaluated for key parameters such as
uniqueness, reliability, uniformity, randomness, and bit-aliasing, achieving
near-ideal values (around 50% for uniformity and 97% reliability). The
architecture effectively solves the parity problem found in earlier designs by
maintaining an odd number of inversions, ensuring continuous oscillation.
Moreover, it shows strong resistance to machine learning modeling attacks,
with prediction accuracy limited to 77%. The results confirm that RACRO-
PUF offers high security, scalability, and power efficiency, making it ideal
for cryptographic and IoT hardware applications.

[2] A Ring Oscillator-Based Physical Unclonable Function with

Enhanced Challenge–Response Pairs to Improve the Security of Internet of
Things Devices” by Marco Grossi [Link], The authors explore the use of
physical unclonable functions (PUFs) to enhance the security of IoT devices.
PUFs exploit inherent manufacturing randomness to generate unique device
fingerprints, and ring oscillator (RO)-based PUFs are particularly attractive
due to their simple design and ease of on-chip integration. Standard RO
PUFs generate responses by comparing oscillation frequencies, but they
7
offer a limited number of challenges–response pairs (CRPs), which
constrains security. The study proposes measuring both the oscillation
frequency and the duty cycle of each RO, leveraging their weak correlation
to produce a 2-bit response per RO pair. Circuit-level simulations and
experimental measurements confirm that this dual-parameter approach
effectively doubles the number of CRPs while maintaining high uniqueness,
achieving a value of 49.77%. This method demonstrates a practical and
efficient solution for improving authentication and cryptographic key
generation in portable and wearable IoT sensor systems.

[3] A Survey on PUF-based Hardware Security Primitives published in

IEEE Access provides an extensive review of various Physical Unclonable
Function (PUF) architectures and their applications in secure hardware
systems. It highlights the role of PUFs in generating unique, unclonable
identifiers for chip authentication and secure key generation. The study
analyzes different PUF types such as SRAM, Ring Oscillator, and Arbiter
PUFs, comparing their performance metrics including uniqueness, reliability,
and environmental stability. Furthermore, it discusses emerging challenges
like machine-learning attacks and outlines potential countermeasures. This
work offers valuable insights into the evolution of PUF-based security
primitives and their suitability for next- generation IoT and VLSI devices.

[4] A Self-Regulated and Reconfigurable CMOS PUF Featuring Zero-

Overhead Stabilization introduces a novel CMOS-based PUF design that
ensures authentication stability without requiring additional error correction
circuitry. The proposed architecture utilizes self-regulation mechanisms
within standard CMOS processes to counter process, voltage, and
temperature variations. By embedding a reconfigurable structure, the

8
design enhances entropy and reusability, making it suitable for multiple
authentication cycles. Simulation and hardware results demonstrate
improved response reliability and low power consumption, highlighting its
efficiency for integration in secure and energy-constrained embedded
systems.

[5] A High-Quality True Random Number Generator Based on Ring

Oscillator Arrays published in IEEE Transactions on Circuits and Systems
(2022) introduces a TRNG architecture leveraging ring oscillator arrays to
achieve high-quality randomness. The design exploits inherent process
variations and jitter noise between oscillators to generate unpredictable
random bits, ensuring strong entropy and robustness. This approach aligns
with the concept of using ring oscillators for random challenge generation in
authentication circuits, providing insights into integrating TRNG and PUF
modules for enhanced hardware security.

[6] Ring Oscillator-Based TRNG for Secure IoT Authentication

published in Sensors (MDPI, 2023) presents a True Random Number
Generator (TRNG) design utilizing ring oscillators to strengthen
authentication in IoT and embedded systems. The proposed system uses
process variations and metastability effects within oscillator arrays to
produce unpredictable random sequences essential for cryptographic
operations. With low power consumption and compact design, the
architecture ensures both high entropy and robustness against environmental
changes, making it ideal for secure and lightweight IoT authentication
applications.

9
[7] Aging-Resilient PUF for Secure Chip Identification published in
IEEE Transactions on Device & Materials Reliability (2023) explores a
Physical Unclonable Function (PUF) architecture designed to maintain
reliability under transistor aging effects. The authors propose circuit-level
compensation techniques that counter performance degradation caused by
bias temperature instability and hot- carrier injection. Experimental analysis
demonstrates that the PUF retains high uniqueness and stability over
extended operational lifetimes. This approach ensures consistent chip
authentication performance, making it suitable for long-term secure
hardware applications where aging-induced variations are critical.

[8] Reliability-Aware Integrated Circuit Aging Detection Using Delay

Sensors published in Microelectronics Reliability (2022) investigates a
delay-sensor-based framework for detecting aging effects in integrated
circuits. The study utilizes ring oscillator delay measurements to monitor
degradation caused by mechanisms such as bias temperature instability and
hot-carrier injection. Experimental results reveal that delay sensors
effectively quantify performance shifts over time, enabling early detection
of recycled or aged chips. This methodology aligns closely with aging-based
detection concepts, providing valuable insights for ensuring hardware
integrity and long-term reliability in VLSI systems

[9] A Survey of Recycled IC Detection Techniques Using Delay and

Aging Sensors published in IEEE Access (2021) provides a comprehensive
overview of existing methodologies for identifying recycled integrated
circuits. It emphasizes the role of delay and aging sensors, particularly ring
oscillator-based designs, in capturing performance degradation signatures
that occur over a chip’s operational lifespan. The

10
survey categorizes detection approaches based on sensing mechanisms,
calibration strategies, and implementation cost. The authors conclude that
aging-aware delay monitoring offers a practical and low-overhead solution
for detecting counterfeit and reused ICs, making it a critical technique for
hardware trust and supply chain security.

[10] An In- Depth Study of Ring Oscillator Reliability under Accelerated

Degradation and Annealing to Unveil Integrated Circuit Usage published in
Micromachines (2024) examines the effects of aging and stress on ring
oscillator (RO) reliability. By analyzing degradation and annealing behavior,
the study provides insights into long-term performance variations. These
findings are directly applicable to aging-based recycled IC detection and
reliability-aware RO-PUF designs, ensuring that authentication mechanisms
remain robust throughout device lifetimes.

[11] Integrating Lorenz Hyperchaotic Encryption with Ring Oscillator

Physically Unclonable Functions (RO- PUFs) for High-
Throughput IoT Applications in Electronics (2023) combines chaos- based
encryption with RO-PUFs to enhance security for IoT devices. The
integration increases unpredictability of challenge-response pairs and
strengthens resistance to modeling attacks. This approach offers a high-
throughput authentication solution suitable for resource-constrained
embedded systems.

[12] Ring- Oscillator- Based High- Speed True Random Number

Generator with a Minimal Footprint published in the Journal of Electrical
Systems (2024) presents a compact RO-TRNG design for FPGA and
embedded platforms. Exploiting inherent oscillator jitter, the system
produces high-quality random sequences with low hardware overhead,

11
making it ideal for secure challenge generation in RO-PUF-based
authentication circuits.

[13] A Configurable RO- PUF for Securing Embedded Systems

Implemented on Programmable Devices” in Sensors introduces a
reconfigurable RO-PUF module for embedded systems. The design allows
dynamic adjustment of challenge-response behaviour while maintaining
uniqueness and reliability. This architecture is particularly suitable for
secure authentication in FPGA- and microcontroller-based devices.

[14] Impact of the Flicker Noise on the Ring Oscillator- based

TRNGs published in IACR Transactions on Cryptographic Hardware and
Embedded Systems (TCHES, 2024) investigates how intrinsic oscillator
noise affects entropy and randomness in RO-TRNGs. The study quantifies
jitter and flicker noise effects, providing insights for designing robust TRNG
modules integrated with RO-PUFs for secure authentication.

[15] LDCPUF: A Novel FPGA-Based Physical Unclonable Function with

Ultra-Low Hardware Cost published in IEICE Electronics Express (2022)
presents a ring-oscillator-based PUF optimized for minimal hardware
utilization on FPGA platforms. The design achieves high uniqueness and
reliability while significantly reducing area and power overhead, making it
suitable for resource-constrained embedded and IoT devices. By focusing on
efficient circuit implementation without compromising security, this work
provides valuable insights for designing low-cost RO-PUF modules for chip
authentication application

12
 2.2 CHALLENGES IDENTIFIED

Despite significant advancements in RO-PUF and TRNG research, several

challenges remain in achieving robust hardware-level authentication. Standard RO-
PUF architectures often face limitations in the number of challenge-response pairs,
which restricts scalability and reduces security strength. Environmental variations,
including temperature and voltage fluctuations, as well as manufacturing process
differences, can degrade PUF uniqueness and reliability. Aging effects, such as bias
temperature instability and hot-carrier injection, further impact long-term stability
and pose challenges for consistent chip authentication. Integrating TRNGs for secure
random challenge generation introduces additional design complexity, including
sensitivity to flicker noise, oscillator jitter, and hardware overhead. Moreover,
balancing hardware cost, area, and power consumption is critical, particularly in
resource-constrained embedded and IoT devices.

Another challenge lies in maintaining robustness against machine learning and

modelling attacks, which can predict PUF responses if sufficient challenge-response
data is exposed. Ensuring high entropy and unpredictability in the generated
responses is therefore essential. Additionally, designing configurable RO-PUFs that
allow a large number of challenge-response pairs without significant area or power
overhead is difficult. The interaction between TRNGs and aging detection
mechanisms also adds complexity, as variations in oscillator behaviour can impact
both randomness quality and authentication reliability. These factors make the design,
simulation, and validation of RO-PUF + TRNG systems challenging, requiring
careful optimization and verification to ensure long-term security and practical
applicability in real-world embedded and IoT devices.

13
 2.3 OBJECTIVES OF THE WORK

The primary objective of this project is to design and implement a dual-mode

RO-PUF + TRNG system that provides secure, reliable, and high-entropy chip
authentication for embedded and IoT devices. The design focuses on maximizing the
number of challenge-response pairs while maintaining high uniqueness, robustness,
and reliability, ensuring that each device produces a distinct and unclonable
fingerprint.
Another key objective is to integrate aging-aware and recycled IC detection
mechanisms, allowing the system to maintain consistent authentication performance
over its operational lifetime despite transistor degradation, bias temperature
instability, and other aging effects. The project also aims to optimize hardware
efficiency, targeting minimal silicon area, low power consumption, and scalability so
that the system can be deployed in resource-constrained platforms without
compromising security.
Additionally, the work emphasizes the importance of robustness against
environmental variations such as voltage and temperature fluctuations, as well as
resistance to modelling and machine learning attacks that could potentially
compromise PUF-based authentication. The proposed design will be implemented
and validated using Cadence Virtuoso and Spectre simulations, providing accurate
circuit-level analysis under realistic process, voltage, and temperature conditions.
This ensures that the system is not only theoretically secure but also practically
applicable for real-world embedded and IoT applications, combining security,
efficiency, and reliability in a single integrated solution.

14
 CHAPTER 3

EXISTING AND PROPOSED SYSTEM

3.1 EXISTING SYSTEM

The existing hardware security systems for integrated circuits predominantly

employ Ring Oscillator-based Physically Unclonable Functions (RO-PUFs) and
aging-based detection techniques for recycled IC identification. RO-PUFs exploit
inherent manufacturing variations in the silicon to generate unique digital
fingerprints for each chip. When a specific challenge signal is applied, the system
produces a corresponding response, known as a Challenge-Response Pair (CRP).
These CRPs are extensively used for chip authentication in embedded systems and
IoT devices, ensuring that each device is uniquely identifiable and difficult to clone
or tamper with.

Traditional RO-PUF architectures consist of multiple ring oscillators, whose

oscillation frequencies are compared to generate a binary response. The frequencies
of these oscillators vary slightly due to uncontrollable process variations during
fabrication, creating a unique signature for every IC. Despite their effectiveness,
existing RO-PUF systems face several limitations, such as restricted scalability of
CRPs, sensitivity to environmental variations like temperature and voltage, and
susceptibility to aging effects over the operational lifetime of the device.
Consequently, authentication reliability may degrade under harsh operating
conditions.

In parallel, existing recycled IC detection systems leverage ring oscillator

arrays to monitor performance degradation caused by aging mechanisms, including
Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI). By observing
the shift in oscillation frequencies over time, these systems can determine whether
an IC has been previously used or stressed. This helps ensure that recycled or
previously deployed chips are not reintroduced into critical applications where
15
reliability is paramount. Typically, these systems involve dedicated delay sensors or
aging monitors to measure timing degradation and detect potential wear-out in the
device.

Despite the effectiveness of these individual systems, in existing

implementations, RO-PUFs and recycled IC detection modules operate
independently. RO-PUFs provide authentication but do not incorporate mechanisms
for high-quality random challenge generation or direct aging detection. Aging
detection systems can identify recycled ICs but do not perform dynamic device
authentication. Therefore, there is no single integrated system in traditional
approaches that simultaneously provides secure authentication, high-entropy
random challenge generation, and aging-based recycled IC detection.

3.2 PROPOSED SYSTEM

The proposed Mode 1 system is focused on secure authentication of

integrated circuits using a Ring Oscillator-based Physical Unclonable Function
(RO-PUF) integrated with a True Random Number Generator (TRNG). The system
leverages inherent process variations in silicon to generate unique signatures for
each IC, ensuring that cloned or counterfeit devices can be easily identified. By
exploiting the natural differences in transistor characteristics, the RO-PUF provides
a reliable hardware-based fingerprint for each chip.

The TRNG plays a crucial role in providing unpredictable challenge inputs,

which are fed to a multiplexer to dynamically select outputs from the 16-Ring
Oscillator array. Each RO produces a distinct frequency based on the process
variation of the specific IC. The selected outputs are then processed through a
comparator and encoder to produce a binary PUF response. This response serves as
a digital fingerprint of the IC and is compared against a stored reference or golden
response in the authentication controller.

16
 This system ensures tamper-resistant authentication, as the challenge-
response pairs are unpredictable and unique to each IC. Any cloned or tampered
chip will fail to reproduce the correct PUF response, thus providing a high level of
security. The entire system design, simulation, and verification are implemented
using Cadence Virtuoso tools, which allow precise circuit-level modeling of the RO
array, TRNG, and control logic, ensuring accurate performance evaluation.

Additionally, the system is scalable and modifiable. The number of ROs can
be increased to enhance uniqueness, and error-correction mechanisms can be
integrated to improve reliability under varying temperature and voltage conditions.
By combining RO-PUF with TRNG in Cadence, the proposed Mode 1 system offers
a robust solution for secure IC authentication in modern electronics.

FUNCTION OF BLOCK DIAGRAM:

Figure 3.1 Integration Of Mode 1 And Mode 2

17
3.3 OPERATING MODE

The Mode 1 PUF system operates in a single authentication mode, designed

to generate unique challenge-response pairs (CRPs) for secure IC identification. The
system exploits the inherent process variations in Ring Oscillators (ROs), making
the response deterministic for the same IC and challenge, while being unpredictable
across different ICs. This ensures a robust and unclonable identifier that cannot be
reproduced even if the design or layout is copied.

The operating mode is divided into three main phases: Challenge Application,
Counter Measurement, and Response Generation. Together, these phases ensure
reliable CRP generation and accurate authentication.

3.3.1 APPLICATION CHALLENGES

When an input challenge is applied, the MUX decodes the challenge bits and
selects the corresponding RO from the available array of oscillators. Each RO
produces oscillations at a frequency determined by uncontrollable manufacturing
process variations, such as differences in transistor dimensions, threshold voltages,
and wiring parasitic. These variations create a unique oscillation pattern for each IC.

The challenge input can be varied to access multiple ROs or different

oscillator combinations, enabling the system to generate a large number of
challenge-response pairs, which improves security against brute-force or modelling
attacks. The challenge selection mechanism is implemented using a dedicated MUX,
which ensures fast, deterministic, and repeatable RO selection without interference
from other oscillators.

18
3.3.2 COUNTER MEASUREMENT

Once an RO is selected, the counters begin measuring the number of

oscillations over a fixed time window, effectively digitizing the analog frequency
signal. The length of the measurement window is carefully chosen to balance
accuracy and speed, ensuring that each RO’s frequency is captured precisely while
minimizing latency.

The counters are implemented as high-resolution digital circuits capable of

handling high-frequency RO outputs. They temporarily store the measured value in
internal registers, which are then fed back through the MUX to generate the final
response. This approach converts the analog RO behaviour into a stable digital
signature, suitable for use in authentication protocols.

The system also ensures repeatability and stability by accounting for

environmental variations such as temperature and supply voltage. Cadence Virtuoso
simulations allow designers to verify that the counters and MUX selection maintain
consistent responses under different operating conditions, making the PUF output
reliable for real-world app

3.3.3 RESPONSE GENERATION

After counter measurements are complete, the MUX consolidates the outputs
from the selected RO and its corresponding counter to produce the final PUF
response. This response is a digital value that uniquely identifies the IC for the given
input challenge.
Multiple challenges can be applied sequentially to generate a wide set of CRPs,
which can be stored in a secure database for authentication purposes. The Mode 1
system ensures high entropy, unpredictability, and uniqueness of the responses,
providing strong protection against cloning, counterfeiting, or unauthorized IC access.

19
 The Mode 1 operation is lightweight, requires minimal additional hardware,
and is ideal for embedded and IoT devices, where secure, low-overhead
authentication is critical. Cadence-based simulation and verification allow designers
to fine-tune timing, RO selection, and counter parameters to achieve optimal
reliability and security.

3.4 DATA FLOW

In the Mode 1 system, the input challenge determines which RO is activated

through the MUX. The selected RO’s oscillation frequency is measured by the
counter, and the digitized count forms the response. By repeating this process with
different challenges, the system can generate multiple challenge-response pairs
(CRPs) for each IC.

Figure 3.2 Secure ID Generation

The MUX and counters together ensure that each response is both repeatable
for the same IC and unpredictable across different ICs. Cadence Virtuoso is used to
simulate the RO frequencies, MUX selection, and counter outputs to verify
uniqueness, randomness, and reliability of responses.

20
 The proposed architecture utilizes a TRNG/PRNG to generate random
challenges that select specific Ring Oscillator pairs through a MUX. The frequency
difference between the selected ROs is measured using counters and compared to
generate a unique Secure ID bit. This process leverages manufacturing variations to
ensure a reliable, unclonable, and hardware-efficient solution for secure chip
authentic.

21
 CHAPTER 4
SIMULATION RESULTS AND ANALYSIS

4.1 SIMULATION ENVIRONMENT AND SETUP

The proposed Mode 1 system was designed and simulated using Cadence
Virtuoso tools to verify the functionality of the Ring Oscillator-based Physical
Unclonable Function (RO-PUF) integrated with the True Random Number Generator
(TRNG). The entire circuit, including the RO array, TRNG, control logic, and
comparator, was developed at the schematic level using the Virtuoso Schematic
Editor. The design was simulated using the Spectre Simulator, where transient
analysis was performed to observe the oscillation frequency, phase difference, and
output response of each ring oscillator. The TRNG module was simulated to generate
unpredictable and high-entropy random bits that serve as dynamic challenges for the
RO-PUF. The setup ensured that all components operated synchronously under stable
supply and timing conditions. The simulation waveforms were analyzed in Virtuoso
Analog Design Environment (ADE) to verify the generation of unique and consistent
Challenge-Response Pairs (CRPs). This environment provided a reliable platform to
evaluate the system’s security performance, stability, and hardware efficiency under
different operating conditions.

4.1.1 DESIGN ENVIRONMENT

The Mode 1 architecture of the proposed system, based on a Ring Oscillator
Physically Unclonable Function (RO-PUF), was designed, simulated, and analyzed
using Cadence Virtuoso IC Design Suite. All schematic and simulation tasks were
carried out in the Spectre simulator environment, which provides accurate transistor-
level characterization. The aim of this simulation was to verify the oscillation
behavior, uniqueness, and stability of the PUF circuit under typical conditions.

22
4.1.2 DESIGN CONFIGURATION
The circuit comprises sixteen (16) ring oscillators, each designed using an odd
number of CMOS inverter stages to ensure sustained oscillation. Each oscillator’s
frequency is determined by the inverter delay, which varies naturally due to process
variations at the transistor level. Two multiplexers (MUX1 and MUX2) are used to
select pairs of oscillators for comparison, while a counter logic block counts
oscillations and generates a digital response bit based on which oscillator runs faster.
The design hierarchy includes:
 Ring Oscillator Array – 16 ROs producing frequency-dependent outputs.
 Multiplexer Network – selects two RO outputs for evaluation.
 Counter and Comparator Logic – produces one PUF response bit.

4.1.3 SIMULATION PARAMETERS

PARAMETER VALUE / DESCRIPTION

Simulation Tool Cadence Virtuoso (Spectre Simulator)
Supply Voltage 1.2V
Process Corner Typical-Typical (TT)
Temperature 27 °C
Analysis Type Transient Analysis
Simulation Time 1 µs – 10 µs (depending on oscillation
speed)
Output Nodes RO outputs (RO1–RO16), MUX outputs,
Counter output

Table 4.1 Simulation parameters

23
4.2 SIMULATION PROCEDURE
The simulation procedure for Mode 1 was performed using Cadence Virtuoso
to evaluate the functionality and reliability of the Ring Oscillator-based PUF
integrated with the TRNG. The schematic was designed by constructing multiple ring
oscillators using an odd number of inverter stages connected in a feedback loop to
generate oscillations, while the TRNG was implemented to produce random
challenges that controlled the selection of specific oscillator pairs. The simulation
was executed using the Spectre simulator under transient analysis to measure the
frequency differences between selected oscillators. These frequency variations were
compared using a comparator circuit to generate binary responses, forming
Challenge-Response Pairs (CRPs). The resulting output waveforms were observed
and analyzed in the Analog Design Environment (ADE) to verify the stability,
randomness, and uniqueness of the responses. The procedure confirmed that the
Mode 1 design provides reliable authentication with high entropy, minimal
correlation, and consistent response generation suitable for secure embedded
hardware applications.
4.2.1 SCHEMATIC CREATION AND VERIFICATION
The RO-PUF schematic was constructed by instantiating inverter chains and
interconnecting them to form oscillators. Each oscillator output was labeled distinctly
for frequency measurement. Design Rule Check (DRC) and Layout Versus
Schematic (LVS) verification were performed to ensure design correctness before
simulation.
4.2.2 BIASING AND BOUNDARY CONDITIONS
Each oscillator was connected to a common VDD (1.2 V) and ground. Control
signals for multiplexers were assigned to select various oscillator pairs
[Link] counter logic was initialized to zero before starting the transient
simulation.

24
4.2.3 SIMULATION EXECUTION
Transient simulation was run to observe the oscillatory waveforms. Each ring
oscillator was monitored individually to record its oscillation frequency. MUX
outputs were also observed to verify proper switching between oscillator pairs.
Finally, the counter output was analyzed to confirm correct binary generation based
on frequency comparison.

4.3 OBTAINED SIMULATION WAVEFORMS

The obtained simulation waveforms for Mode 1 clearly demonstrate the
successful operation of the Ring Oscillator-based PUF and its response generation
mechanism. During the transient simulation in Cadence Virtuoso, each ring oscillator
produced a distinct oscillation frequency due to inherent process variations. When a
challenge input was applied through the TRNG, the multiplexer selected specific
oscillator pairs for comparison. The waveform output showed two oscillating signals
with slight frequency differences, and the comparator output toggled accordingly to
produce a stable digital bit (‘0’ or ‘1’) representing the final PUF response. The
observed results confirmed that each challenge generated a unique and repeatable
response. The stable amplitude and phase difference in the waveforms validated the
reliability of the designed PUF under normal operating conditions, ensuring accurate
authentication performance and consistent CRP generation.

4.3.1 RING OSCILLATOR OUTPUTS

Each ring oscillator exhibited a periodic waveform whose frequency differed
slightly from others. These variations arise from device-level process fluctuations,
validating the randomness property of the [Link] distinct frequencies of RO1–
RO16 confirm that no two oscillators behave identically, even under identical supply
and environmental conditions.

25
 Figure 4.1 ROs With Different Frequency

Oscillator MUX Frequency (MHz) Remarks

Ro0 1 201 Stable
Ro1 2 207 Slightly faster
Ro2 1 194 Slow Response
Ro3 2 205 Medium
… … … …
Ro15 1 198 Moderate speed
Table 4.3 ROs Frequency Response

4.3.2 MULTIPLEXER AND COUNTER OUTPUTS

The multiplexer waveform illustrates the systematic selection of two ring
oscillators at a time, enabling precise frequency comparison. During each selection
cycle, the counter evaluates the oscillation period difference between the chosen
oscillators and generates a corresponding logic level (‘1’ or ‘0’) based on which
oscillator exhibits a higher frequency. This logical outcome represents the response
bit associated with the applied challenge input.

26
 The observed waveform confirms proper synchronization between the
multiplexer control signals and the counter operation, validating the reliable
functioning of the frequency comparison mechanism within the PUF architecture.
4.4 MUX SELECTION SIMULATION
The MUX selection simulation for Mode 1 was carried out in Cadence
Virtuoso to verify the proper functioning of the challenge–response selection
mechanism in the Ring Oscillator-based PUF. In this setup, multiple ring oscillators
were connected to a multiplexer, where the selection lines were driven by challenge
inputs generated through the TRNG. The transient simulation confirmed that, based
on each applied challenge, the MUX accurately selected the corresponding pair of
ring oscillators for frequency comparison. The waveform clearly displayed a change
in the output path whenever a new challenge was applied, indicating dynamic
switching between oscillator outputs. This ensured that different RO pairs were
compared for each challenge, producing unique and unclonable response bits. The
MUX operation was stable, with no signal overlap or delay glitches, validating its
correct integration and timing synchronization within the overall PUF circuit.

4.4.1 MUX1 and MUX2 Configuration

To evaluate selection behavior, MUX1 is configured to select RO1, and MUX2
is configured to select RO0. The selected outputs are observed at the MUX output
terminals and compared through the counter circuit. This setup verifies that the
multiplexer logic correctly routes the oscillator signals to the comparison module.

4.4.2 WAVEFORM OBSERVATION

The waveform clearly shows that MUX1 follows the oscillation of RO1 and
MUX2 follows RO0. Both signals maintain square-wave characteristics with distinct
frequency differences. This confirms that the MUX selection control is functioning
properly and that the circuit is able to select and compare any pair of oscillators as
required.

27
 Figure 4.2 ROs Selection via MUX

4.5 SIMULATION OUTPUT OF SECURE ID IN MODE 1

In Mode 1 operation, the system functions as a Physical Unclonable Function
(PUF) to generate a unique and stable Secure ID for each integrated circuit. The
output is derived from the comparison of oscillation frequencies between selected
pairs of ring oscillators, where the counter produces binary values (‘1’ or ‘0’) based
on the higher frequency within each pair. These binary responses are sequentially
combined to form the final Secure ID, which serves as the digital fingerprint of the
chip. The waveform output validates consistent response generation for multiple
challenge inputs, confirming the uniqueness and repeatability of the PUF. This
demonstrates the circuit’s ability to produce tamper-resistant authentication codes,
ensuring reliable hardware-level security and preventing unauthorized device
replication.

28
 Figure 4.3 Mode 1 Secure ID Output

The simulation waveform illustrates the Mode 1 operation of the proposed Ring
Oscillator-based PUF system. The top signal represents the system clock driving the
frequency comparison process, while the lower signals correspond to the individual
bits of the generated 8-bit Secure ID (secure_id[7:0]). As the simulation progresses,
each bit transitions based on the output of the frequency comparison between selected
ring oscillator pairs. These transitions reflect the binary decisions made by the
counter module, producing a stable digital signature once all comparisons are
complete. The console output confirms the final 8-bit Secure ID value of 10010110,
which validates correct functionality of the authentication process. The clear timing
alignment and steady logic transitions demonstrate accurate synchronization between
oscillator selection, counter evaluation, and ID generation within the Mode 1
configuration.

29
 CHAPTER 5
AGING-AWARE RING OSCILLATOR PUF FOR RECYCLED IC
DETECTION
5.1 OVERVIEW
The Aging-Aware Ring Oscillator PUF for Recycled IC Detection is
designed to identify reused or aged chips by monitoring the degradation in
transistor performance over time. In this system, multiple ring oscillators are
used, each composed of an odd number of inverters connected in a feedback
loop. As integrated circuits age due to stress factors such as Negative Bias
Temperature Instability (NBTI) and Hot Carrier Injection (HCI), the delay of
transistors increases, leading to a measurable frequency shift in the oscillators.
By comparing the frequency differences between a reference RO (unstressed)
and an aged RO (stressed), the system can detect whether a chip has undergone
significant aging. The proposed circuit, implemented using Cadence Virtuoso,
leverages this aging-induced frequency variation as a signature to distinguish
between new and recycled ICs. This method ensures a low-cost, on-chip, and
non-invasive solution for hardware security and authenticity verification.
5.1.1 INTRODUCTION
Following the successful completion of Mode 1, which verified the
operation of the Ring Oscillator-based PUF hardware model, Mode 2 focuses on
a software-oriented extension for detecting recycled or reused ICs. Instead of
physical aging stress models, Mode 2 utilizes simulation-based frequency data
analysis. The frequencies of individual ring oscillators obtained from Cadence
simulations are stored as reference values representing a fresh IC condition.
During subsequent simulation runs or data evaluations, the current frequencies
are computed and compared with their reference counterparts. Any measurable
deviation serves as an indicator of device reuse or operational degradation.

30
 5.1.2 OBJECTIVE OF MODE 2
The main objective is to create a software framework that can
automatically process frequency outputs from the simulated RO-PUF, compare
them with the baseline dataset, and determine whether the IC behavior aligns
with that of a new or recycled device.
freq_dev = ((f_ref - f_current) / f_ref) * 100
This approach provides a lightweight and practical method for reliability
verification without requiring physical aging experiments. It also complements
the existing PUF structure by adding a software-driven analysis layer for device
health and authenticity assessment.
5.1.3 CURRENT WORK STATUS
The Mode 2 development is currently in progress. Frequency data from
the Cadence simulation of the sixteen ring oscillators are being extracted and
processed using a software analysis environment (such as MATLAB, Python, or
Excel)
The comparison logic, threshold evaluation, and deviation classification
algorithms are being refined to ensure accurate differentiation between fresh
and potentially recycled ICs. Preliminary results show consistent correlation
between simulated data and analytical predictions, confirming the effectiveness
of the proposed software-based detection method.

31
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