Scribd
Upload
14 views6 pages

Interfacing of Dma Controller With Risc-V Processor at System On Chip (Soc) Level

The document outlines a course curriculum focused on interfacing a DMA controller with a RISC-V processor at the system on chip (SoC) level. It includes modules on SoC verification, RISC-V processor design, and DMA controller architecture, with hands-on practice and industry guidance. Each module has a specified duration and covers various aspects of processor architecture, verification techniques, and debugging processes.

Uploaded by

BT21EC026 Siddharth Jha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
14 views6 pages

Interfacing of Dma Controller With Risc-V Processor at System On Chip (Soc) Level

The document outlines a course curriculum focused on interfacing a DMA controller with a RISC-V processor at the system on chip (SoC) level. It includes modules on SoC verification, RISC-V processor design, and DMA controller architecture, with hands-on practice and industry guidance. Each module has a specified duration and covers various aspects of processor architecture, verification techniques, and debugging processes.

Uploaded by

BT21EC026 Siddharth Jha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

INTERFACING OF DMA CONTROLLER

WITH RISC-V PROCESSOR AT


SYSTEM ON CHIP(SOC) LEVEL
Course Curriculum
Phone Number
+91-9599745251

Visit Our Website


[Link]
SOC Level verification - Module 1
Duration - 14 days (weekly 6 hours)
➢ ASIC vs FPGA
➢ SOC Architecture and Methodology
➢ Different blocks involved in the SOC
➢ Functionality of Each block
➢ Teams involvement in the SOC Verification
➢ SOC over traditional IC
➢ SOC Verification Flow
➢ IP Verification
➢ Sub-system Verification
➢ SOC Verification
➢ Overview on SOC Level Verification involved with Processor verification
32-bit risc-v processor design - Module 2
Duration - 1 month (weekly 6 hours)
➢ History of RISC-V Processor
➢ Overview RISC-V Instruction Set Architecture
➢ RISC-V Pipeline Architecture
➢ Detailed Explanation of RV32I Instruction types
➢ Instruction set and Addressing modes
➢ Detailed Explanation of Registers and Instruction Formats
➢ R-Type, I-Type, S-Type, B-Type, J-Type, Instructions
➢ Instruction pipeline Hazards
➢ Detailed Explanation on Data Hazards, Control Hazards of RISC-V Pipeline
➢ Hands on Practice on Assembly Programs
➢ RISC-V Execution Stages and Pipeline
➢ In depth of Graphic processors
➢ Case study on GPU Architectures
32-bit risc-v processor design - Module 3
Duration - 1 month (weekly 6 hours)
➢ ALU Datapath for R-Type, I-Type, S-Type, B-Type, J-Type
➢ RTL Design of RISC-V Processor
➢ Verification of RISC-V Processor using SV | UVM
➢ Detailed explanation DMA Controller Architecture
➢ DMA Controller Architecture, Address mapping
➢ Hands on Design development by each team
➢ RTL Design of DMA Controller and UVM Verification
➢ Interfacing RISC-V 16 bit Processor with DMA Controller
➢ SV | UVM Verification of RISC-V with DMA Controller
SOC Level verification - Module 4
Duration - 14 days (weekly 6 hours)
➢ Pre Silicon & Post Silicon Verification at SOC Level
➢ Different teams involvement
➢ Post Silicon debugging
➢ DFT vs DFD
➢ How to develop feature wise test plan, How to create the test cases
➢ Options in [Link]
➢ Switches required to avoid errors
➢ CPP options, Run commands
➢ What are the main steps to be followed which debugging error
➢ Importance of Regression
➢ How to run the Regression
➢ Test execution steps
➢ How to check TESTPASS/TESTFAIL, Error Signature, TESTID, TESTLOCATION
Course assistance

Live Session
Theory & Labs

Hands on
Experience

Industry
Guidance

24/7 Tool
Access

Mock
interviews

You might also like