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P-Channel DMOS FET TP2540 Datasheet

Supertex Inc.'s TP2540 is a P-Channel Enhancement-Mode Vertical DMOS FET characterized by a low threshold voltage, high input impedance, and fast switching speeds, making it suitable for various applications including logic level interfaces and solid-state relays. The device features low on-resistance and is free from thermal runaway, ensuring reliability in operation. It is available in multiple package options with specific electrical characteristics and maximum ratings outlined for optimal performance.
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0% found this document useful (0 votes)
34 views6 pages

P-Channel DMOS FET TP2540 Datasheet

Supertex Inc.'s TP2540 is a P-Channel Enhancement-Mode Vertical DMOS FET characterized by a low threshold voltage, high input impedance, and fast switching speeds, making it suitable for various applications including logic level interfaces and solid-state relays. The device features low on-resistance and is free from thermal runaway, ensuring reliability in operation. It is available in multiple package options with specific electrical characteristics and maximum ratings outlined for optimal performance.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Supertex inc.

TP2540
P-Channel Enhancement-Mode
Vertical DMOS FET
Features General Description
►► Low threshold (-2.4V max.) This low threshold, enhancement-mode (normally-off)
►► High input impedance transistor utilizes a vertical DMOS structure and Supertex’s
►► Low input capacitance (60pF typical) well-proven, silicon-gate manufacturing process. This
►► Fast switching speeds combination produces a device with the power handling
►► Low on-resistance capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
►► Free from secondary breakdown
Characteristic of all MOS structures, this device is free
►► Low input and output leakage
from thermal runaway and thermally-induced secondary
breakdown.
Applications
►► Logic level interfaces - ideal for TTL and CMOS Supertex’s vertical DMOS FETs are ideally suited to a wide
►► Solid state relays range of switching and amplifying applications where very
►► Battery operated systems low threshold voltage, high breakdown voltage, high input
►► Photo voltaic drives impedance, low input capacitance, and fast switching speeds
►► Analog switches are desired.
►► General purpose line drivers
►► Telecom switches

Ordering Information Product Summary


Part Number Package Option Packing RDS(ON) ID(ON) VGS(th)
BVDSS/BVDGS
(max) (min) (max)
TP2540N3-G 3-Lead TO-92 1000/Bag
TP2540N3-G P002 -400V 25Ω -2.4A -0.4V
TP2540N3-G P003
Pin Configuration
TP2540N3-G P005 3-Lead TO-92 2000/Reel
TP2540N3-G P013 DRAIN
TP2540N3-G P014
TP2540N8-G TO-243AA (SOT-89) 2000/Reel DRAIN
-G denotes a lead (Pb)-free / RoHS compliant package. SOURCE SOURCE
Contact factory for Wafer / Die availablity.
DRAIN
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.
GATE GATE
Absolute Maximum Ratings TO-92 TO-243AA (SOT-89)
Parameter Value
Drain-to-source voltage BVDSS Product Marking
Drain-to-gate voltage BVDGS
SiTP YY = Year Sealed
Gate-to-source voltage ±20V 2 5 4 0 WW = Week Sealed
Operating and storage temperature -55OC to +150OC YYWW = “Green” Packaging
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous Package may or may not include the following marks: Si or
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground. TO-92
Typical Thermal Resistance W = Code for week sealed
TP5DW
Package θja = “Green” Packaging
TO-92 132OC/W Package may or may not include the following marks: Si or
TO-243AA (SOT-89)
TO-243AA (SOT-89) 133OC/W

Doc.# DSFP-TP2540 Supertex inc.


B081613 [Link]
TP2540
Thermal Characteristics
ID ID Power Dissipation
Package IDR† IDRM
(continuous)† (pulsed) @TA = 25OC

TO-92 -86mA -600mA 0.74W -86mA -600mA


TO-243AA (SOT-89) -125mA -1.2A 1.6‡ -125mA -1.2A
† ID (continuous) is limited by max rated Tj .
‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm.

Electrical Characteristics (T = 25°C unless otherwise specified)


A

Sym Parameter Min Typ Max Units Conditions


BVDSS Drain-to-source breakdown voltage -400 - - V VGS = 0V, ID = -2.0mA
VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID= -1.0mA
∆VGS(th) Change in VGS(th) with temperature - - 4.8 mV/ C
O
VGS = VDS, ID= -1.0mA
IGSS Gate body leakage - - -100 nA VGS = ± 20V, VDS = 0V
- -10 μA VGS = 0V, VDS = Max Rating
IDSS Zero gate voltage drain current - VDS = 0.8 Max Rating,
- -1.0 mA
VGS = 0V, TA = 125°C
-0.2 -0.3 - VGS = -4.5V, VDS = -25V
ID(ON) On-state drain current A
-0.4 -1.1 - VGS = -10V, VDS = -25V
20 30 VGS = -4.5V, ID = -100mA
RDS(ON) Static drain-to-source on-state resistance - Ω
19 25 VGS = -10V, ID = -100mA
∆RDS(ON) Change in RDS(ON) with temperature - - 0.75 %/ C
O
VGS = -10V, ID = -100mA
GFS Forward transconductance 100 175 - mmho VDS = -25V, ID = -100mA
CISS Input capacitance - 60 125 VGS = 0V,
COSS Common source output capacitance - 20 70 pF VDS = -25V,
CRSS Reverse transfer capacitance - 10 25 f = 1.0 MHz
td(ON) Turn-on delay time - - 10
tr Rise time - - 10 VDD = -25V,
ns ID = -0.4A,
td(OFF) Turn-off delay time - - 20 RGEN = 25Ω
tf Fall time - - 13
VSD Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -100mA
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = -100mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.

Switching Waveforms and Test Circuit


0V Pulse
10%
INPUT
Generator

-10V 90% RGEN


t(ON) t(OFF)
D.U.T.
td(ON) tr td(OFF) tf
INPUT
OUTPUT
0V
90% 90% RL
OUTPUT
10% 10%
VDD
VDD

Doc.# DSFP-TP2540
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2 [Link]
TP2540
Typical Performance Curves
BVDSS Variation with Temperature On-Resistance vs. Drain Current
1.1 100

80 VGS = -4.5V
VGS = -10V
BVDSS (normalized)

RDS(ON) (ohms)
60

1.0

40

20

0.9 0
-50 0 50 100 150 0 -0.4 -0.8 -1.2 -1.6 -2.0
Tj (OC) ID (amperes)

Transfer Characteristics V(th) and RDS Variation with Temperature


-2.0 2.5
VDS = -25OC
1.2

-1.6 2.0
RDS(ON) @ -10V, -0.1A

RDS(ON) (normalized)
VGS(th) (normalized)

1.1
TA = -55OC
ID (amperes)

-1.2 1.5

1.0
25OC
-0.8 1.0

0.9
V(th)@ -1mA
-0.4 0.5

125OC
0.8

0 0
0 -2.0 -4.0 -6.0 -8.0 -10 -50 0 50 100 150
VGS (volts) Tj (OC)

Capacitance vs. Drain-to-Source Voltage Gate Drive Dynamic Characteristics


200 -10

f = 1MHz
-8.0 VDS = -10V
150
C (picofarads)

-6.0
VGS (volts)

VDS = -40V
100

-4.0

CISS 190 pF

50
-2.0
60pF

CRSS COSS
0 0
0 -10 -20 -30 -40 0 0.4 0.8 1.2 1.6 2.0

VDS (volts) QG (nanocoulombs)

Doc.# DSFP-TP2540
B081613
Supertex inc.
3 [Link]
TP2540
Typical Performance Curves (cont.)
Output Characteristics Saturation Characteristics
-2.0 -1.0

-1.6 -0.8
VGS = -10V

VGS = -10V -8V

ID (amperes)
ID (amperes)

-1.2 -0.6
-8V -6V

-0.8 -0.4

-6V
-0.4 -0.2
-4V

-4V
0 0
0 -10 -20 -30 -40 -50 0 -2.0 -4.0 -6.0 -8.0 -10

VDS (volts) VDS (volts)

Transconductance vs. Drain Current Power Dissipation vs. Ambient Temperature


0.5 2.0
VDS = -25V

TO-243AA
0.4
GFS (siemens)

0.3
PD (watts)

1.0
TA = -55OC
0.2
25OC
TO-92
125OC
0.1

0 0
0 -0.4 -0.8 -1.2 -1.6 -2.0 0 25 50 75 100 125 150

ID (amperes) TA (OC)

Maximum Rated Safe Operating Area Thermal Response Characteristics


-10 1.0
TA = 25OC
Thermal Resistance (normalized)

0.8
TO-243AA (pulsed) TO-243AA
TA = 25OC
-1.0 PD = 1.6W
TO-92 (pulsed)
ID (amperes)

0.6
TO-243AA (DC)

0.4
-0.1 TO-92 (DC)

0.2 TO-92
TC = 25OC
PD = 1.0W

-0.01 0
-1.0 -10 -100 -1000 0.001 0.01 0.1 1.0 10
VDS (volts)
tp(seconds)

Doc.# DSFP-TP2540
B081613
Supertex inc.
4 [Link]
TP2540
3-Lead TO-92 Package Outline (N3)
D

A
Seating
Plane 1 2 3

b c
e1
e

Front View Side View

E
E1
1 3

Bottom View

Symbol A b c D E E1 e e1 L
MIN .170 .014† .014† .175 .125 .080 .095 .045 .500
Dimensions
NOM - - - - - - - - -
(inches)
MAX .210 .022† .022† .205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.

Doc.# DSFP-TP2540
B081613
Supertex inc.
5 [Link]
TP2540
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1 C

E H E1

1 2 3
L

b b1 A
e
e1

Top View Side View

Symbol A b b1 C D D1 E E1 e e1 H L
MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00† 3.94 0.73†
Dimensions 1.50 3.00
NOM - - - - - - - - - -
(mm) BSC BSC
MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 4.25 1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
Supertex Doc. #: DSPD-3TO243AAN8, Version F111010.

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to [Link]

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//[Link])

©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Doc.# DSFP-TP2540 Tel: 408-222-8888
B081613 6 [Link]

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