APW7057

High Power Step-Down Synchronous DC/DC Controller

Features General Description

• Operates from +5V Input The APW7057 is a 300kHz constant frequency voltage
• 0.8V Internal Reference Voltage mode synchronous switching controller that drives exter-
- ±1.5% Accuracy Over Line, Load and nal N-channel MOSFETs. When the input supply drops
close to output, the upper MOSFET remains on, achiev-
Temperature
ing 100% duty cycle. Internal loop compensation is opti-
• 0.8V to VCC Output Range mized for fast transient response, eliminating external
• Full Duty Cycle Range compensation network. The precision 0.8V reference
makes this part suitable for a wide variety of low voltage
- 0% to 100%
applications. Soft-start is internally set to 2ms, limiting
• Internal Loop Compensation the input in-rush current and preventing the output from
• Internal Soft-Start overshoot during powering up.
The APW 7057 has over current and short circuit
- Typical 2ms
protections. Over current protection is achieved by moni-
• Programmable Over-Current Protection toring the voltage drop across the high side MOSFET,
- Lossless Sensing Using MOSFET RDS (ON) eliminating the need for a current sensing resistor and
short circuit condition is detected through the FB pin. If
• Under-Voltage Protection
either fault conditions occur, the APW7057 would initiate
• Drives External N-Channel MOSFETs the soft-start cycle. After three cycles and if the fault condi-
• Shutdown Control tion persists, the controller will be shut down. To restart
the controller, either recycle the VCC supply or momen-
• Small SOP-8 Package
tarily pull the OSCSET pin below 1.25V.
• Lead Free and Green Devices Avaliable The APW7057 can be shutdown by pulling the OCSET
(RoHS Compliant) pin below 1.25V. In shutdown, both gate drive signals will
be low. The controller is available in a small SOP-8
Applications package.

• Motherboard

• Graphics Cards Pin Configuration

• Cable or DSL Modems, Set Top Boxes

• DSP Supplies BOOT 1 8 PHASE

• Memory Supplies UGATE 2 7 OCSET

• 5V Input DC-DC Regulators GND 3 6 FB

• Distributed Power Supplies LGATE 4 5 VCC

SOP-8 (Top View )

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 [Link]

Rev. A.5 - Jun., 2008
APW7057

Ordering and Marking Information

Package Code
APW7057 K : SOP-8
Operating Junction Temperature Range
C : 0 to 70°C
Assembly Material Handling Code
Handling Code TR : Tape & Reel
Temperature Range Assembly Material
Package Code L : Lead Free Device G : Halogen and Lead Free Device

APW7057
APW7057 K : XXXXX - Date Code
XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Absolute Maximum Ratings

Symbol Parameter Rating Unit

VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V

VBOOT BOOT Supply Voltage (BOOT to GND) -0.3 ~ 15 V

PHASE, OCSET to GND Input Voltage -0.3 ~ 12 V

FB to GND Input Voltage -0.3 ~ VCC+0.3 V

o
Maximum Junction Temperature 125 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 C

Thermal Characteristics
Symbol Parameter Typical Value Unit

Junction-to-Ambient Resistance in Free Air

θJA o
C/W
SOP-8 160

Recommended Operating Conditions

Symbol Parameter Range Unit

VCC VCC Supply Voltage 5 ± 5% V

(Note)
VOUT Output Voltage of the Switching Regulator 0.8 ~ VCC V
(Note)
VIN Input Voltage of the Switching Regulator 3.3 ~ VCC V
o
TA Ambient Temperature 0 ~ 70 C
o
TJ Junction Temperature 0 ~ 125 C

Note : Refer to the typical application circuit

Copyright  ANPEC Electronics Corp. 2 [Link]

Rev. A.5 - Jun., 2008
APW7057

Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are
at T =25oC.
A

APW7057
Symbol Parameter Test Conditions Unit
Min. Typ. Max.

SUPPLY CURRENT

IVCC VCC Nominal Supply Current UGATE and LGATE Open - 2.1 - mA

IBOOT BOOT Nominal Supply Current UGATE Open - 2.1 - mA

UNDER VOLTAGE LOCKOUT (UVLO)

Rising VCC Threshold 4.0 4.2 4.4 V

Falling VCC Threshold 3.8 4.0 4.2 V

OSCILLATOR

FOSC Free Running Frequency 250 300 340 kHz

Ramp Upper Threshold - 2.85 - V

Ramp Lower Threshold - 0.95 - V

∆VOSC Ramp Amplitude - 1.9 - VP-P

REFERENCE VOLTAGE

VREF Reference Voltage - 0.8 - V

Reference Voltage Accuracy -1.5 - +1.5 %

ERROR AMPLIFIER

DC Gain - 75 - dB

FP First Pole Frequency - 10 - Hz

FZ First Zero Frequency - 1 - kHz

UGATE Duty Range 0 - 100 %

FB Input Current - - 0.1 µA

PWM CONTROLLER GATE DRIVERS

UGATE Source VUAGTE=1V - 0.6 - A

UGATE Sink VUGATE=1V - 7.3 - Ω

LGATE Source VLGATE=1V - 0.6 - A

LGATE Sink VLGATE=1V - 1.8 - Ω

TD Dead Time - 50 - nS

PROTECTION

IOCSET OCSET Sink Current VOCSET=4.5V 34 40 46 µA

UVFB FB Under-Voltage Level FB falling - 0.5 - V

FB Under-Voltage Hysteresis - 15 - mV

Copyright  ANPEC Electronics Corp. 3 [Link]

Rev. A.5 - Jun., 2008
APW7057

Electrical Characteristics (Cont.)

Unless otherwise specified, these specifications apply over VCC=5V, VBOOT=12V and TA= 0~70 oC. Typical values are
at T =25oC.
A

APW7057
Unit
Symbol Parameter Test Conditions
Min. Typ. Max.

SOFT-START AND SHUTDOWN

TSS Soft-Start Interval - 2 - mS

Shutdown Threshold VOCSET Falling - 1.25 - V

OCSET Shutdown Hysteresis - 20 - mV

Function Pin Description

BOOT (Pin 1) OCSET (Pin 7)
This pin provides the supply voltage to the high side This pin serves two functions: as a shutdown control and
MOSFET driver. A voltage no greater than 13V can be con- for setting the over current limit threshold. Pulling this pin
nected to this pin as a supply to the driver. For driving below 1.25V shuts the controller down, forcing the UGATE
logic level N-channel MOSEFT, a bootstrap circuit can be and LGATE signals to be at 0V. A soft-start cycle will be
use to create a suitable driver’s supply. initiated upon the release of this pin.
A resistor (Rocset) connected between this pin and the drain
UGATE (Pin 2)
of the high side MOSFET will determine the over current
This pin provides gate drive for the high-side MOSFET. limit. An internally generated 40µA current source will flow
GND (Pin 3) through this resistor, creating a voltage drop. This volt-
age will be compared with the voltage across the high
Signal and power ground for the IC. All voltage levels are
side MOSFET. The threshold of the over current limit is
measured with respect to this pin. Tie this pin to the ground
therefore given by:
plane through the lowest impedance connection available.
40uA x ROCSET
LGATE (Pin 4) IOI =
RDS(ON)
This pin provides the gate drive signal for the low side
An over current condition will cycle the soft-start function.
MOSFET.
After three consecutive cycles and if the fault condition
VCC (Pin 5) persists, the controller will be shut down. To restart the
This is the main bias supply for the controller and its low controller, either recycle the VCC supply or momentarily
side MOSFET driver. Must be closely decoupled to GND pull the OSCSET pin below 1.25V.
(Pin 3). DO NOT apply a voltage greater than 5.5V to this
pin. PHASE (Pin 8)
This pin is connected to the source of the high-side
FB (Pin 6)
MOSFET and is used to monitor the voltage drop across
This pin is the inverting input of the error amplifier and it
the high-side MOSFET for over-current protection.
receives the feedback voltage from an external resistive
divider across the output (VOUT). The output voltage is de-
termined by:
ROUT
VOUT = 0.8V(1+ )
RGND
where ROUT is the resistor connected between VOUT
and FB while RGND is the resistor connected from FB to
GND.
Copyright  ANPEC Electronics Corp. 4 [Link]
Rev. A.5 - Jun., 2008
APW7057

Block Diagram
VCC BOOT

UnderVoltage Shutdown
Lockout OCSET
IOCSET
40µA
UVLO OC
Comparator
Soft-Start OCP
and Fault
Logic PHASE
0.5V UVP
UGATE

Soft-Start Inhibit
Gate
PWM Control
FB -+ COMP
+ VCC
Error -
VREF Amplifier
LGATE
0.8V

Oscillator
FOSC GND
300kHz

Figure 1.

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Rev. A.5 - Jun., 2008
APW7057

Typical Application Circuit

R3

C3 2.2
1uF
VIN
+5V
5
D1 C1 C2
R4 C7 VCC 1uF
1N4148 1000uF x2
8.2k 470pF
1
BOOT
7 OCSET
C4
2 0.1uF
Q3 UGATE Q1
L1
3.3uH
8 VOUT
Shutdown PHASE
U1 +2.5V/10A
APW7057 C5
4
6 LGATE Q2 1000uF x2
FB

GND
3 R1
5.1k

R2
2.4k
C6
0.1uF

Q1: APM2014N UC C2: 1000uF/10V, ESR = 25m Ω

Q2: APM2014N UC C5: 1000uF/6.3V, ESR = 25m Ω
Q3: 2N7002

Figure 2.

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Rev. A.5 - Jun., 2008
APW7057

Typical Operating Characteristics

Reference Voltage vs. Junction Temperature Switching Frequency vs. Junction Temperature

0.812 350

340

Switching Frequency, FOSC (kHz)

0.808 330
Reference Voltage, VREF (V)

320
0.804
310

0.800 300

290
0.796 280

270
0.792
260

0.788 250

-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150

Junction Temperature (oC) Junction Temperature (°C)

OCSET Current vs. Junction Temperature

46
45
44
OCSET Current , IOCSET (µA)

43
42
41
40
39
38
37
36
35
34
-50 -25 0 25 50 75 100 125 150

Junction Temperature (oC)

Copyright  ANPEC Electronics Corp. 7 [Link]

Rev. A.5 - Jun., 2008
APW7057

Operating Waveforms (Refer to the typical application circuit)

1. Load Transient Response : IOUT = 0A -> 10A -> 0A

- IOUT slew rate = ±10A/µS

IOUT = 0A -> 10A IOUT = 0A -> 10A -> 0A IOUT = 10A -> 0A

VOUT VOUT
VOUT

VUGATE VUGATE

10A

IOUT IOUT
IOUT
0A

Ch1 : VOUT, 100mV/Div, DC, Ch1 : VOUT, 100mV/Div, DC, Ch1 : VOUT, 100mV/Div, DC,
Offset = 2.50V Offset = 2.50V Offset = 2.50V
Ch2 : VUGATE, 10V/Div, DC Ax1 : IOUT, 5A/Div Ch2 : VUGATE, 10V/Div, DC
Ax1 : IOUT, 5A/Div Time : 100µS/Div Ax1 : IOUT, 5A/Div
Time : 10µS/Div BW = 20MHz Time : 10µS/Div
BW = 20MHz BW = 20MHz

2. UGATE and LGATE

UGATE Rising UGATE Falling

IOUT=10A IOUT=10A

VUGATE VUGATE

VLGATE VLGATE

Ch1 : VUGATE, 2V/Div, DC Ch2 : VLGATE, 2V/Div, DC Ch1 : VUGATE, 2V/Div, DC Ch2 : VLGATE, 2V/Div, DC
Time : 125nS/Div BW = 500MHz Time : 125nS/Div BW = 500MHz

Copyright  ANPEC Electronics Corp. 8 [Link]

Rev. A.5 - Jun., 2008
APW7057

Operating Waveforms (Cont.)

(Refer to the typical application circuit)

3. Powering ON / OFF

Soft-Start at Powering ON Powering OFF

VIN VIN

VOUT VOUT

Ch1 : VIN, 2V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch1 : VIN, 2V/Div, DC Ch2 : VOUT, 1V/Div, DC
Time : 1mS/Div BW = 20MHz Time : 5mS/Div BW = 20MHz

4. Short-Circuit Protection

UVP Under-Voltage (UVP)

and Over-Current Protection (OCP)

OCP OCP
Ch1 : VOUT, 1V/Div, DC
VOUT
Ax1 : IOUT, 10A/Div
Time : 1mS/Div
BW = 20MHz

IOUT

Copyright  ANPEC Electronics Corp. 9 [Link]

Rev. A.5 - Jun., 2008
APW7057

Application Information
Component Selection Guidelines The maximum ripple current occurs at the maximum in-
Output Capacitor Selection put voltage. A good starting point is to choose the ripple
current to be approximately 30% of the maximum output
The selection of COUT is determined by the required effec-
current.
tive series resistance (ESR) and voltage rating rather than
Once the inductance value has been chosen, select an
the actual capacitance requirement. Therefore, select high
inductor that is capable of carrying the required peak cur-
performance low ESR capacitors that are intended for
rent without going into saturation. In some types of
switching regulator applications. In some applications,
inductors, especially core that is make of ferrite, the ripple
multiple capacitors have to be paralled to achieve the
current will increase abruptly when it saturates. This will
desired ESR value. If tantalum capacitors are used, make
result in a larger output ripple voltage.
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer. MOSFET Selection
Input Capacitor Selection The selection of the N-channel power MOSFETs are de-
The input capacitor is chosen based on the voltage rating termined by the RDS(ON), reverse transfer capacitance (CRSS)
and the RMS current rating. For reliable operation, select and maximum output current [Link] losses in
the capacitor voltage rating to be at least 1.3 times higher the MOSFETs have two components: conduction loss and
than the maximum input voltage. The maximum RMS transition loss. For the upper and lower MOSFET, the
current rating requirement is approximately IOUT/2 , where losses are approximately given by the following equations:
IOUT is the load current. During power up, the input capaci- 2
PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
tors have to handle large amount of surge current. If tanta-
2
lum capacitors are used, make sure they are surge tested PLOWER = Iout (1+ TC)(RDS(ON))(1-D)
by the manufactures. If in doubt, consult the capacitors
manufacturer. where IOUT is the load current
For high frequency decoupling, a ceramic capacitor be- TC is the temperature dependency of RDS(ON)
tween 0.1µF to 1µF can be connected between VCC and FS is the switching frequency
ground pin. tsw is the switching interval
D is the duty cycle
Inductor Selection
The inductance of the inductor is determined by the out- Note that both MOSFETs have conduction losses while
put voltage requirement. The larger the inductance, the the upper MOSFET includes an additional transition loss.
lower the inductor’s current ripple. This will translate into The switching internal, tsw, is the function of the reverse
lower output ripple voltage. The ripple current and ripple transfer capacitance CRSS. Figure 3 illustrates the switch-
voltage can be approximated by: ing waveform internal of the MOSFET.
VIN - VOUT V OUT
IRIPPLE = x Layout Consideration
Fs x L VIN
In high power switching regulator, a correct layout is im-
∆VOUT = IRIPPLE x ESR portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-
where Fs is the switching frequency of the regulator.
mized by using short, wide printed circuit traces. Signal
There is a tradeoff exists between the inductor’s ripple and power grounds are to be kept separate and finally
current and the regulator load transient response time. A combined using ground plane construction or single point
smaller inductor will give the regulator a faster load tran- grounding. Figure 4 illustrates the layout, with bold lines
sient response at the expense of higher ripple current indicating high current paths. Components along the bold
and vice versa. lines should be placed close together.

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Rev. A.5 - Jun., 2008
APW7057

Application Information
Layout Consideration (Cont.)
Below is a checklist for your layout: VIN
C HF
• Keep the switching nodes (UGATE, LGATE, and
PHASE) away from sensitive small signal nodes since CIN
5
these nodes are fast moving signals. Therefore, keep VCC

traces to these nodes as short as possible. +

1
BOOT
• Decoupling capacitor CIN provides the bulk capacitance
and needs to be placed close to the IC since it will 4
LGATE
provide the MOSFET drivers transient current APW7057
requirement. U 2 COUT
1 UGATE Q1 Q2 +
• The ground return of CIN must return to the combine
PHASE 8
COUT (-) terminal. L1 VOUT
• Capacitor CBOOT should be connected as close to the
BOOT and PHASE pins as possible. Figure 4. Recommended Layout Diagram

• Capacitor CHF is to improve noise performance and a

small 1µF ceramic capacitor will be sufficient.

V DS
drain and source of MOSFET
Voltage across

t sw Time

Figure 3. Switching waveform across MOSFET

Copyright  ANPEC Electronics Corp. 11 [Link]

Rev. A.5 - Jun., 2008
APW7057

Package Information
SOP-8
D

SEE VIEW A

E1

°
h X 45

e b c
A2

0.25
A

GAUGE PLANE
SEATING PLANE
A1

L
VIEW A

S SOP-8
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.

A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 5.80 6.20 0.228 0.244
E1 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
0 0° 8° 0° 8°

Note: 1. Follow JEDEC MS-012 AA.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

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Rev. A.5 - Jun., 2008
APW7057

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 A
B OD1 B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
330.0 50 MIN. 12.4+2.00 13.0+0.50 1.5 MIN. 20.2 MIN. 12.0 0.30 1.75 0.10 5.5 0.05
2.00 -0.00 -0.20
SOP-8 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0 0.10 8.0 0.10 2.0 0.05 -0.00 1.5 MIN. -0.40 6.40 0.20 5.20 0.20 2.10 0.20

(mm)

Devices Per Unit

Package Type Unit Quantity

SOP-8 Tape & Reel 2500

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Rev. A.5 - Jun., 2008
APW7057

Reflow Condition (IR/Convection or VPR Reflow)

TP tp
Critical Zone
TL to TP
Ramp-up

TL
Temperature

tL
Tsmax

Tsmin
Ramp-down
ts
Preheat

t 25°C to Peak
25

Time
Reliability Test Program
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C
PCT JESD-22-B, A102 168 Hrs, 100%RH, 121°C
TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms, 1tr > 100mA

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Average ramp-up rate
3°C/second max. 3°C/second max.
(TL to TP)
Preheat
100°C 150°C
- Temperature Min (Tsmin)
- Temperature Max (Tsmax) 150°C 200°C
60-120 seconds 60-180 seconds
- Time (min to max) (ts)
Time maintained above:
183°C 217°C
- Temperature (TL)
60-150 seconds 60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp) See table 1 See table 2
Time within 5°C of actual
10-30 seconds 20-40 seconds
Peak Temperature (tp)
Ramp-down Rate 6°C/second max. 6°C/second max.
Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.
Notes: All temperatures refer to topside of the package. Measured on the body surface.

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Rev. A.5 - Jun., 2008
APW7057

Classification Reflow Profiles (Cont.)

Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
3 3
Package Thickness Volume mm Volume mm
<350 ≥350
<2.5 mm 240 +0/-5°C 225 +0/-5°C
≥2.5 mm 225 +0/-5°C 225 +0/-5°C

Table 2. Pb-free Process – Package Classification Reflow Temperatures

3 3 3
Package Thickness Volume mm Volume mm Volume mm
<350 350-2000 >2000
<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*
1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*
≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the
stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C)
at the rated MSL level.

Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

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