SE COMP SEM I 2025-26

DELD END SEM EXAM QUESTION BANK

UNIT 1
1. Convert the following expression into their standard SOP form.
i) Y=AB+AC+BC
ii) Y=A+BC+ABC

2. Express the function Y = AB+ACD in canonical sum of product form

3. Express the Boolean function F = A + B’C as a sum of minterms.
4. Express the Boolean function F = xy + x’z as a product of maxterms.
5. Reduce the expression f=(A+B)(A+B‘)(A‘+B‘) using mapping.
6. Represent following equation using K-Map
i. Y=(A+B+C)(A+B’+C)(A’+B’+C)
ii. Y=(A+B+C+D’)(A+B+C’+D’)(A+B+C+D)(A+B+C+D)
iii. Y=AB+AC’+BC

7. Subtract 14 from 46 using 8 bit 1‘s compliment arithmetic.

8. Add -75 to +26 using 8 bit 1‘s compliment arithmetic.

9. Subtract 14 from 46 using 8 bit 2‘s compliment arithmetic.

10. Add -75 to +26 using 8 bit 2‘s compliment arithmetic
11. Represent +27, - 62 in
1) Signed magnitude
2) 1’s complement
3) 2’s complement

12. Represent +87, - 43 in

1) Signed magnitude
2) 1’s complement
3) 2’s complement

13. Simplify the expression F(A,B,C,D) = ∑m (3,4,5,7,9,13,14,15) using the K-map

method.
14. Simplify the expression F(A,B,C,D) = π M (0,1,4,5,6,8,9,12,13,14) using the K-map
method.
15. Simplify the expression F(A,B,C,D) = ∑m (1,3,7,11,15)+d(0,2,5) using
the K-map method.
16. Minimize the following expression using the K-map with minimum hardware. Y =
∑m (1,5,6,7,11,12,13,15)

17. Minimize the following boolean functions using K-Map and also draw MSI circuit for
the output.
i. F(A, B, C, D) = Σm(0,2,4,5,6,7,8,10,13,15).
ii. F(A, B, C, D) = Σm(0,2,4,5,6,8,10,15)+d(7,13,14).
 iii. F(W, X, Y, Z) = Σm(4,5,7,12,14,15)+d(3,8,10).
iv. F(A, B, C, D) = Σm(4,5,6,7,8,12)+d(1,2,3,9,11,14).
v. F(A, B, C, D) = Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15).
vi. F(A, B, C, D) = Σm(0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
vii. F(A, B, C, D) = Σm(3, 4, 5, 7, 9, 13, 14, 15)
viii. F(W, X, Y, Z) = Σm(1, 3, 4, 6, 9, 11, 12, 14)
ix. f=∑m(0,1,6,7,8,13,14,15)
x. f=∑m(1, 2, 3, 5, 6,7,8,9,12,13,15)
xi. F(A,B,C,D)=∑m(0,4,5,10,11,13,15)
xii. f=∑m(1, 2, 3, 5, 6,7,8,9,12,13,15)
xiii. F(A, B, C, D) = Σm(1, 3, 4, 6, 8, 9, 11, 13, 15) + Σd(0, 2, 14)
xiv. F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 5)
xv. F(A, B, C) = Σm(1, 2, 5, 7) + Σd(0, 4, 6)
xvi. F(A, B, C) = Σm(0, 1, 6, 7) + Σd(3, 4, 5)
xvii. F(A, B, C, D) = Σm(0, 2, 8, 10, 14) + Σd(5, 15)
xviii. f=∑m(1,5,6,12,13,14)+d(2,4)
xix. Z=f(A,B,C,D) =∑(1,2,7,8,10,12,15,)+d(0,5,6)
xx. Z=f(A,B,C,D) =∑(1,3,4,6,8,11,15)+d(0,5,7)
xxi. Z=f(A,B,C,D) =∑(2,4,6,11,12,14)+d(3,10)
xxii. Z=f(A,B,C,D) =∑(1,3,6,7,12,13)+d(0,2,8,9)

18. Minimize the following boolean functions using K-Map and also draw MSI circuit for
the output.
i. F(A,B,C,D)= πM(0,2,3,8,9,12,13,15)
ii. Y=π M(0,2,3,5,7)
iii. F(A,B,C,D)= πM(1,3,5,6,7,10,11)+d(2,4)

19. Find the expression for the following K-Map in the POS form

20. Simplify the expression

A) (AB’+ABC) + A(B+AB’)
B) A’B’+CB’+ABC+AC
 UNIT 2

1. Design Full-adder circuit using two Half-adders. In diagram use block diagram of half-
adder.
2. Design Full-subtractor circuit using two Half-subtractors. In diagram use block diagram
of half-subtractors.
3. Design single digit BCD adder using 4-bit binary adder IC7483 and explain two
examples of BCD.
4. Explain the rules for BCD addition with suitable example and Design one digit BCD
adder using IC 7483
5. Design 4 bit binary to gray code converter circuit using logic gates
6. Design a 4 bit Gray to Binary code converter? State the application of Gray code.
7. Design a 4 bit BCD to Excess-3 code converter circuit using logic gates
8. Design a 4 bit Excess-3 to BCD code converter circuit using logic gates
9. Design 2-bit comparator with minimum number of gates.
10. What is Multiplexer? Design 8:1 multiplexer with a dual 4:1 multiplexer.
11. What is Multiplexer? Design 16:1 multiplexer with a dual 8:1 multiplexer.
12. What is Multiplexer? Design 16:1 multiplexer with a dual 4:1 multiplexer.
13. Implement the following Boolean function using 8:1 multiplexer
a. F(A,B,C,D) =∑m (2,4,5,7,10,14).
14. Implement following Boolean function using Mux
a. 1.Y(A,B,C)= ∑m (0,1,2,6,7).

b. 2.Y(A,B,C)= πM (0,1,4,5).

15. Implement Full adder and Full substractor using Demultiplexer (DEMUX).
16. Implement Full adder and Full substractor using Multiplexer (MUX).
17. Implement 3 Bit binary to Gray code converter using Demultiplexer.
18. Implement 1:8 Demux using 1:4 Demux.

19. Implement following Boolean function using Demux

1.F1(A,B,C)= ∑m (0,3,7) and F2 (A,B,C)= ∑m (1,2,5)

2.Y(A,B,C)= πM (0,1,4,5).
 UNIT 3
1. Distinguish between combinational and sequential switching circuits also write examples
of both.
2. Explain the effect of Preset and Clear signals on the working of Flip Flop.
3. What is a race-around condition in JK FF and how it is overcome in Master Slave (MS)-
JK FF?
4. Draw truth tables and Excitation tables of following Flip Flops
i) SR ii) JK iii) D and iv) T
5. Convert the following flip flops:
i) SR flip-flop to D flip-flop.
ii) D flip flop to T flip-flop.
iii) JK flip-flop to T flip-flop
iv) JK to D flip flop
v) D to T flip flop
vi) JK to SR flip flop
vii) SR to JK flip flop
viii) SR to T flip flop
6. With neat diagrams explain the working of the following types of shift registers
i) Serial-in, serial-out ii) Parallel-in, serial-out.
7. Draw the circuit and explain the function of 4-bit bidirectional shift register.
8. State different types of shift registers. Give its applications.
9. Compare synchronous and Asynchronous counter.
10. Write short note on Ring Counter.
11. Write short note on BCD Counter.
12. Write short note on Twisted Ring/Johnson/Moebius Counter.
13. Design MOD-83 counter using IC 7490
14. Design Decade(BCD) Ripple(asynchronous) counter using T flip flop. Write truth table
and draw timing diagram.
15. Draw basic internal structure of Decade counter IC 7490 and explain its operation.
16. Draw basic internal architecture of IC [Link] a divide-by-29 counter using IC 7490.
17. Design the following Mod counter using 7490.
i) MOD 67 counter ii) Mod 75 Counter iii) MOD 24 Counter
iv) MOD 45 Counter v) MOD 97 Counter vi) MOD 98 Counter.
 UNIT 4
1. What is ASM chart? State and Explain basic component of ASM chart.
2. State and explain basic components of ASM chart. Draw ASM chart for MOD 3 UP
counter.
3. Draw an ASM chart for 2-bit binary counter having enable line E such that E=1 (counting
enable) E=0 (hold present count).
4. Design an ASM chart for 2-bit UP counter using mode control line.
a. When M = I UP counting
b. When M = 0 remain in same state.
5. What is ASM chart? Draw an ASM chart and state table for 2-bit up down counter having
mode control input M:
a. When M = I UP counting
b. When M = 0 Down counting.
6. Draw and explain various notations used in ASM charts.
7. Compare between FSM and ASM
8. What is logic family ? Give classification of logic family in detail.
9. Explain the characteristics of digital TTL ICs ?
10. Explain the characteristics of digital CMOS ICs ?
11. Explain the following characteristics of digital ICs?
i) Figure of Merit
ii) Propagation delay
iii) VIH and VOH
iv) Noise Margin
v) Fan Out and Fan In
vi) Power Dissipation
12. With the help of a neat diagram, explain the working of two-input TTL NAND gate.
13. Draw and explain working of 2 input standard TTL NAND gate with Totem pole.
Explain operation of transistor (ON/OFF) with suitable input conditions and truth table.
List advantages of Totem Pole.
14. Explain TTL open collector output circuit. Also explain the advantages of open collector
output.
15. Compare TTL and CMOS logic family.
16. Draw and explain the circuit diagram of CMOS Inverter.
17. Explain with a neat diagram CMOS NAND gate.
18. Explain Tristate logic and Tristate TTL Inverter.
19. Explain wired logic in CMOS.

UNIT 5
1. Define PLD. Mention different types of PLD.
2. What is the difference between PAL and PLA?
3. Draw and explain the general structure of PLA.
4. Draw a block diagram of the PAL device and explain.
5. Implement 3 bit binary to gray code converter using PLA.
6. Implement full adder using PLA.
7. Implement full subtractor using PLA.
8. Design BCD to Excess-3 code converter using PLA.
9. Design BCD to Gray code converter and implement using PLA.
10. Implement BCD to Excess-3 code converter using PAL.
11. Implement full adder using PAL
12. Implement full subtractor using PAL.
13. Implement 4:1 multiplexer using PAL.
14. Implement the following function using PAL.
F1(A, B, C,D)=∑m(1,3,4,6,9,12,14)
F2(A, B, C,D)=∑m(1,2,3,7,12,15)
15. Implement the following function using PAL.
a. F1=∑m(0,2,3,4,5,6,7,8,10,11,15)
b. F2=∑m(1,2,8,12,13).
16. Implement following Boolean function using PAL
a. F (A, B, C, D) = Σ m (0, 1, 3, 15)
17. Implement following Boolean function using PAL
a. F1= Σm (0, 2, 4, 6, 8, 12)
b. F2 = Σm (2, 3, 8, 9, 12, 13)
c. F3 = Σm (l, 3, 4, 6, 9, 11, 12, 14, 15)
18. Implement the following Boolean function using PAL.
a. F1 =Σ m (0, 3, 5, 7, 9, 10, 11, 14, 15)
b. F2 =Σ m (2, 3, 12, 14)

19. Implement the following Boolean functions using PAL

a. X1(A, B, C, D)= Σ m (0,2,6,7,8,9,12,13)
b. X2(A, B, C, D)= Σ m (3,6,7,11,14,15)

20. Implementing a Combinational Circuit Using a PAL

a. W(A, B, C, D) = Σ m(2, 12, 13)
b. X(A, B, C, D) = Σ m(7, 8, 9, 10, 11, 12, 13, 14, 15)
c. Y(A, B, C, D) = Σ m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
d. Z(A, B, C, D) = Σ m(1, 2, 8, 12, 13)

21. Implement this circuit using PLA.

a. F1(A, B, C)=∑m(0,2,4,5)
b. F2(A, B, C)=∑m(13,6,7).
22. Implement this circuit using PLA.
a. F1(A,B,C) = ∑m (0,1,3,7)
b. F2(A,B,C) = ∑m (1,2,5,6).

23. Design of Boolean functions using PLA

F0 = A + B' C’
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A