1.
4 – BIT ALU
VERILOG CODE:
module ALU_4_BIT (
input [3:0] A, B, // 4-bit inputs
input [3:0] ALU_Sel, // Operation select
output reg [3:0] ALU_Out, // 4-bit output (normal ops)
output reg CarryOut, // Carry flag
output reg [7:0] Result // General 8-bit result (for multiplication)
);
reg [4:0] tmp; // Temporary register for arithmetic with carry
always @(*) begin
// Default values
ALU_Out = 4'b0000;
CarryOut = 0;
Result = 8'b00000000;
case (ALU_Sel)
4'b0000: begin // Addition
tmp = A + B;
ALU_Out = tmp[3:0];
CarryOut = tmp[4];
Result = {4'b0000, ALU_Out}; // Store in Result too
end
4'b0001: begin // Subtraction
tmp = A - B;
ALU_Out = tmp[3:0];
CarryOut = tmp[4];
Result = {4'b0000, ALU_Out};
end
4'b0010: begin // Increment
tmp = A + 1;
ALU_Out = tmp[3:0];
CarryOut = tmp[4];
Result = {4'b0000, ALU_Out};
end
4'b0011: begin // Decrement
tmp = A - 1;
ALU_Out = tmp[3:0];
CarryOut = tmp[4];
Result = {4'b0000, ALU_Out};
end
4'b0100: begin // AND
ALU_Out = A & B;
Result = {4'b0000, ALU_Out};
end
4'b0101: begin // OR
ALU_Out = A | B;
Result = {4'b0000, ALU_Out};
end
4'b0110: begin // XOR
ALU_Out = A ^ B;
Result = {4'b0000, ALU_Out};
end
4'b0111: begin // NOR
ALU_Out = ~(A | B);
Result = {4'b0000, ALU_Out};
end
4'b1000: begin // Shift Left
ALU_Out = A << 1;
Result = {4'b0000, ALU_Out};
end
4'b1001: begin // Shift Right
ALU_Out = A >> 1;
Result = {4'b0000, ALU_Out};
end
4'b1010: begin // Multiplication
Result = A * B; // Full 8-bit multiplication result
ALU_Out = Result[3:0]; // Lower 4 bits shown in ALU_Out
end
default: begin
ALU_Out = 4'b0000;
Result = 8'b00000000;
end
endcase
end
endmodule
Testbench file:
module ALU_4_BIT_TB;
reg [3:0] A, B; // Inputs
reg [3:0] ALU_Sel; // Operation select
wire [3:0] ALU_Out; // 4-bit output
wire CarryOut; // Carry flag
wire [7:0] Result; // Full 8-bit result (for multiplication)
// Instantiate the ALU
ALU_4_BIT uut (
.A(A),
.B(B),
.ALU_Sel(ALU_Sel),
.ALU_Out(ALU_Out),
.CarryOut(CarryOut),
.Result(Result)
);
initial begin
// Monitor values in console
// $monitor("Time=%0t | A=%b (%0d), B=%b (%0d), Sel=%b | ALU_Out=%b (%0d),
Carry=%b, Result=%b (%0d)",
// $time, A, A, B, B, ALU_Sel, ALU_Out, ALU_Out, CarryOut, Result, Result);
// Test vectors
A = 4'b1010; B = 4'b0101; // A=10, B=5
ALU_Sel = 4'b0000; #10; // Addition
ALU_Sel = 4'b0001; #10; // Subtraction
ALU_Sel = 4'b0010; #10; // Increment
ALU_Sel = 4'b0011; #10; // Decrement
ALU_Sel = 4'b0100; #10; // AND
ALU_Sel = 4'b0101; #10; // OR
ALU_Sel = 4'b0110; #10; // XOR
ALU_Sel = 4'b0111; #10; // NOR
ALU_Sel = 4'b1000; #10; // Shift Left
ALU_Sel = 4'b1001; #10; // Shift Right
// Multiplication special case
A = 4'b1111; B = 4'b1111; // 15 x 15 = 225
ALU_Sel = 4'b1010; #10;
$stop; // End simulation
end
endmodule
SCHEMATIC:
POWER REPORT
AREA REPORT
2. ENCODER AND DECODER
ENCODER:
module ENCODER (
input [7:0] D, // 8 input lines
output reg [2:0] Y // 3-bit encoded output
);
always @(*) begin
case (D)
8'b00000001: Y = 3'b000; // Input 0 active
8'b00000010: Y = 3'b001; // Input 1 active
8'b00000100: Y = 3'b010; // Input 2 active
8'b00001000: Y = 3'b011; // Input 3 active
8'b00010000: Y = 3'b100; // Input 4 active
8'b00100000: Y = 3'b101; // Input 5 active
8'b01000000: Y = 3'b110; // Input 6 active
8'b10000000: Y = 3'b111; // Input 7 active
default: Y = 3'bxxx; // Invalid input (none or multiple 1’s)
endcase
end
endmodule
Testbench file
module ENCODER_TB;
reg [7:0] D; // 8 input lines
wire [2:0] Y; // 3-bit output
// Instantiate the encoder
ENCODER uut (
.D(D),
.Y(Y)
);
initial begin
//$monitor("Time=%0t | D=%b | Y=%b", $time, D, Y);
D = 8'b00000001; #10; // Input 0
D = 8'b00000010; #10; // Input 1
D = 8'b00000100; #10; // Input 2
D = 8'b00001000; #10; // Input 3
D = 8'b00010000; #10; // Input 4
D = 8'b00100000; #10; // Input 5
D = 8'b01000000; #10; // Input 6
D = 8'b10000000; #10; // Input 7
D = 8'b00000000; #10; // Invalid (none)
D = 8'b00000110; #10; // Invalid (multiple 1's)
$stop;
end
endmodule
OUTPUTS:
DECODER
module DECODER(
input [2:0] in,
output reg [7:0] out
);
always @(*) begin
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
default: out = 8'b00000000;
endcase
end
endmodule
Testbench file
module DECODER_TB;
reg [2:0] in;
wire [7:0] out;
// Instantiate the decoder
DECODER uut (
.in(in),
.out(out)
);
initial begin
//$monitor("Time = %0t | Input = %b | Output = %b", $time, in, out);
// Apply test inputs
in = 3'b000; #10;
in = 3'b001; #10;
in = 3'b010; #10;
in = 3'b011; #10;
in = 3'b100; #10;
in = 3'b101; #10;
in = 3'b110; #10;
in = 3'b111; #10;
$finish;
end
endmodule
RESULTS
3. COMPARATOR – 2 BIT
Verilog Code
module COMPARATOR(
input [1:0] A, // First 2-bit input
input [1:0] B, // Second 2-bit input
output reg A_greater,
output reg A_equal,
output reg A_less
);
always @(*) begin
if (A > B) begin
A_greater = 1;
A_equal = 0;
A_less = 0;
end
else if (A == B) begin
A_greater = 0;
A_equal = 1;
A_less = 0;
end
else begin
A_greater = 0;
A_equal = 0;
A_less = 1;
end
end
endmodule
Testbench file
module COMPARATOR_TB;
reg [1:0] A;
reg [1:0] B;
wire A_greater;
wire A_equal;
wire A_less;
// Instantiate the comparator
comparator_2bit uut (
.A(A),
.B(B),
.A_greater(A_greater),
.A_equal(A_equal),
.A_less(A_less)
);
initial begin
//$monitor("Time=%0t | A=%b | B=%b | A>B=%b | A==B=%b | A<B=%b",
// $time, A, B, A_greater, A_equal, A_less);
// Apply test cases
A = 2'b00; B = 2'b00; #10;
A = 2'b01; B = 2'b00; #10;
A = 2'b10; B = 2'b11; #10;
A = 2'b11; B = 2'b10; #10;
A = 2'b01; B = 2'b01; #10;
A = 2'b00; B = 2'b10; #10;
A = 2'b11; B = 2'b11; #10;
$finish;
end
endmodule
4. PRIORITY ENCODER
module PRIENCODER(
input [7:0] D, // Input bits
output reg [2:0] Y, // Encoded output
output reg valid // 1 if any input is high
);
always @(*) begin
valid = 1'b1; // assume at least one input is high
casex (D)
8'b1xxxxxxx: Y = 3'b111; // D7 has highest priority
8'b01xxxxxx: Y = 3'b110; // D6
8'b001xxxxx: Y = 3'b101; // D5
8'b0001xxxx: Y = 3'b100; // D4
8'b00001xxx: Y = 3'b011; // D3
8'b000001xx: Y = 3'b010; // D2
8'b0000001x: Y = 3'b001; // D1
8'b00000001: Y = 3'b000; // D0
default: begin
Y = 3'b000;
valid = 1'b0; // no input active
end
endcase
end
endmodule
Testbench file
module PRIENCODER_TB;
reg [7:0] D;
wire [2:0] Y;
wire valid;
// Instantiate DUT
PRIENCODER uut (
.D(D),
.Y(Y),
.valid(valid)
);
initial begin
// $display("Time\t\tD\t\tY\tvalid");
// $monitor("%0t\t%b\t%b\t%b", $time, D, Y, valid);
// Test cases
D = 8'b00000000; #10;
D = 8'b00000001; #10; // D0 active
D = 8'b00000101; #10; // D2 active (higher than D0)
D = 8'b00010000; #10; // D4 active
D = 8'b10000000; #10; // D7 active (highest)
D = 8'b01111111; #10; // D6 active
D = 8'b00001000; #10; // D3 active
D = 8'b00000010; #10; // D1 active
$stop;
end
endmodule
5. MULTIPLEXER AND DEMULTIPLEXER
a) 8:1 MUX Direct Implementation
Verilog code
module MUXEIGHT (
input [7:0] D, // Data inputs
input [2:0] S, // Select inputs
output reg Y // Output
);
always @(*) begin
case (S)
3'b000: Y = D[0];
3'b001: Y = D[1];
3'b010: Y = D[2];
3'b011: Y = D[3];
3'b100: Y = D[4];
3'b101: Y = D[5];
3'b110: Y = D[6];
3'b111: Y = D[7];
default: Y = 1'b0;
endcase
end
endmodule
Testbench code
module MUXEIGHT_TB;
reg [7:0] D;
reg [2:0] S;
wire Y;
// Instantiate DUT
MUXEIGHT uut (
.D(D),
.S(S),
.Y(Y)
);
initial begin
//$display("Time\tSelect\tInput\tOutput");
//$monitor("%0t\t%b\t%b\t%b", $time, S, D, Y);
// Test
D = 8'b10101010; // Pattern of 1s and 0s
for (S = 0; S < 8; S = S + 1) begin
#10;
end
D = 8'b11001100; // Another pattern
for (S = 0; S < 8; S = S + 1) begin
#10;
end
$stop;
end
endmodule
OUTPUTS
8:1 MUX using 2:1 MUX
Verilog Code
module mux2to1 (
input a, b, sel,
output y
);
assign y = sel ? b : a;
endmodule
// 8:1 MUX built using 2:1 MUX blocks
module MUXTWO (
input [7:0] D,
input [2:0] S,
output Y
);
wire [3:0] w1; // outputs from first stage
wire [1:0] w2; // outputs from second stage
// Stage 1: 4 instances → reduce 8 → 4
mux2to1 m1(D[0], D[1], S[0], w1[0]);
mux2to1 m2(D[2], D[3], S[0], w1[1]);
mux2to1 m3(D[4], D[5], S[0], w1[2]);
mux2to1 m4(D[6], D[7], S[0], w1[3]);
// Stage 2: 2 instances → reduce 4 → 2
mux2to1 m5(w1[0], w1[1], S[1], w2[0]);
mux2to1 m6(w1[2], w1[3], S[1], w2[1]);
// Stage 3: Final 2:1 mux → reduce 2 → 1
mux2to1 m7(w2[0], w2[1], S[2], Y);
endmodule
Testbench file
module MUXTWO_TB;
reg [7:0] D;
reg [2:0] S;
wire Y;
// Instantiate DUT
MUXTWO uut (
.D(D),
.S(S),
.Y(Y)
);
initial begin
//$display("Time\tSelect\tInput\tOutput");
//$monitor("%0t\t%b\t%b\t%b", $time, S, D, Y);
// Test
D = 8'b10101010;
for (S = 0; S < 8; S = S + 1) begin
#10;
end
D = 8'b11001100;
for (S = 0; S < 8; S = S + 1) begin
#10;
end
$stop;
end
endmodule
OUTPUTS
1:8 DEMUX
Verilog Code
module DEMUX (
input Din, // Single input
input [2:0] S, // 3-bit select
output reg [7:0] Y // 8 outputs
);
always @(*) begin
// Default: all outputs off
Y = 8'b00000000;
// Activate the selected output
case (S)
3'b000: Y[0] = Din;
3'b001: Y[1] = Din;
3'b010: Y[2] = Din;
3'b011: Y[3] = Din;
3'b100: Y[4] = Din;
3'b101: Y[5] = Din;
3'b110: Y[6] = Din;
3'b111: Y[7] = Din;
default: Y = 8'b00000000;
endcase
end
endmodule
Testbench file
module DEMUX_TB;
reg Din;
reg [2:0] S;
wire [7:0] Y;
// Instantiate DUT
DEMUX uut (
.Din(Din),
.S(S),
.Y(Y)
);
initial begin
//$display("Time\tDin\tSelect\t\tOutput");
//$monitor("%0t\t%b\t%b\t%b", $time, Din, S, Y);
// Test case 1: Din = 0 → All outputs 0
Din = 0;
for (S = 0; S < 8; S = S + 1)
#10;
// Test case 2: Din = 1 → One output active each time
Din = 1;
for (S = 0; S < 8; S = S + 1)
#10;
$stop;
end
endmodule
OUTPUTS
module demux1to2 (
input Din,
input S,
output Y0,
output Y1
);
assign Y0 = (~S) & Din;
assign Y1 = S & Din;
endmodule
// 1:8 DEMUX using 1:2 DEMUX modules
module DEMUXTWO (
input Din,
input [2:0] S,
output [7:0] Y
);
wire [1:0] w1; // outputs from stage 1
wire [3:0] w2; // outputs from stage 2
// Stage 1: 1 DEMUX → 2 outputs
demux1to2 d1 (.Din(Din), .S(S[2]), .Y0(w1[0]), .Y1(w1[1]));
// Stage 2: 2 DEMUXes → 4 outputs
demux1to2 d2 (.Din(w1[0]), .S(S[1]), .Y0(w2[0]), .Y1(w2[1]));
demux1to2 d3 (.Din(w1[1]), .S(S[1]), .Y0(w2[2]), .Y1(w2[3]));
// Stage 3: 4 DEMUXes → 8 outputs
demux1to2 d4 (.Din(w2[0]), .S(S[0]), .Y0(Y[0]), .Y1(Y[1]));
demux1to2 d5 (.Din(w2[1]), .S(S[0]), .Y0(Y[2]), .Y1(Y[3]));
demux1to2 d6 (.Din(w2[2]), .S(S[0]), .Y0(Y[4]), .Y1(Y[5]));
demux1to2 d7 (.Din(w2[3]), .S(S[0]), .Y0(Y[6]), .Y1(Y[7]));
endmodule
module DEMUXTWO_TB;
reg Din;
reg [2:0] S;
wire [7:0] Y;
// Instantiate DUT
DEMUXTWO uut (
.Din(Din),
.S(S),
.Y(Y)
);
initial begin
//$display("Time\tDin\tSelect\tOutput");
//$monitor("%0t\t%b\t%b\t%b", $time, Din, S, Y);
Din = 0;
for (S = 0; S < 8; S = S + 1)
#10;
Din = 1;
for (S = 0; S < 8; S = S + 1)
#10;
$stop;
end
endmodule
