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4-Bit Combinational Shifter Design

The document details a lab report on designing a 4-bit combinational shifter using multiplexers for logical shifts. It outlines the operations performed during shifting, including truth tables for both right and left shifts, and presents simulation results confirming the circuit's functionality. The conclusion states that the design met theoretical expectations, successfully implementing the desired shifting operations.

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MUHAMMAD TALHA
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60 views7 pages

4-Bit Combinational Shifter Design

The document details a lab report on designing a 4-bit combinational shifter using multiplexers for logical shifts. It outlines the operations performed during shifting, including truth tables for both right and left shifts, and presents simulation results confirming the circuit's functionality. The conclusion states that the design met theoretical expectations, successfully implementing the desired shifting operations.

Uploaded by

MUHAMMAD TALHA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

RAMEEZ RAJA (NUML-

F23-50489)

Subject: Computer Architecture

Name: Rameez
Hassan Raja
Roll #: 3305
Dated: 13thOct,2025
Lab-7
1. Logical Shift Left (SL)

The design uses four 2-to-1 multiplexers controlled by a single select line S, and two external input
bits (IR, IL) used during shifting.

2. Introduction

Shift microoperations are widely used in computer processors for manipulating binary data.
They are essential in:

 Multiplication

 Division

 Bit alignment

 Arithmetic operations

 Logical transformations

A combinational shifter performs these operations immediately without using clocked registers.

In this lab, a 4-bit combinational shifter is created that takes a 4-bit input vector A[3:0] and shifts it
either right or left depending on select line S.

3. Pre-Lab Analysis

Let:

 Input: A = A₃ A₂ A₁ A₀

 Output: F = F₃ F₂ F₁ F₀

 S = 0 → Shift Right

 S = 1 → Shift Left

 IR = Input bit inserted during shift right

 IL = Input bit inserted during shift left

3.1 Truth Table of Shifter

Case 1: Shift Right (S = 0)

Output Bit Value

F₃ IR
Output Bit Value

F₂ A₃

F₁ A₂

F₀ A₁

Case 2: Shift Left (S = 1)

Output Bit Value

F₃ A₂

F₂ A₁

F₁ A₀

F₀ IL

4. Circuit Design

The 4-bit shifter uses four 2-to-1 multiplexers, each selecting between:

 Shift Right path

 Shift Left path

The select line S controls all multiplexers.

Multiplexer Logic

F[i] = (S == 1) ? SL_input : SR_input

Where SL and SR inputs follow the truth table defined earlier.

7. Simulation Results

Shift Right (S = 0)

Input A IR Output F Result

1011 0 0101 Correct

0110 1 1011 Correct

Shift Left (S = 1)

Input A IL Output F Result

1011 0 0110 Correct

0110 1 1101 Correct


Input A IL Output F Result

8. Waveform (Optional Screenshot)

(Insert screenshot of GTKWave output here)

9. Conclusion

In this lab, a 4-bit combinational shifter was successfully designed and tested.
The circuit uses four 2-to-1 multiplexers controlled by a single select line.

The simulation confirmed:

 When S = 0, the circuit performs a Logical Shift Right, inserting IR at MSB.

 When S = 1, the circuit performs a Logical Shift Left, inserting IL at LSB.

The system behaved exactly as expected based on theoretical design.


Logic_Mircooperations.v

Logic_Microoperations_tb.v
Simulation

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