10 MHz to 3 GHz VGA with

60 dB Gain Control Range

Data Sheet ADL5330
FEATURES FUNCTIONAL BLOCK DIAGRAM
Voltage controlled amplifier/attenuator
GAIN ENBL VPS2 VPS2 VPS2 VPS2
Operating frequency 10 MHz to 3 GHz
VPS1 VPS2
Optimized for controlling output power
GAIN
High linearity: OIP3 31 dBm at 900 MHz CONTROL
COM1 COM2
Output noise floor: −150 dBm/Hz at 900 MHz

CONTINUOUSLY

ATTENUATOR
50 Ω input and output impedances

VARIABLE
INHI INPUT O/P OPHI
Single-ended or differential operation GM (TZ) RFOUT
RFIN
Wide gain control range: −34 dB to +22 dB at 900 MHz STAGE STAGE
INLO OPLO BALUN
Linear in dB gain control function, 20 mV/dB
Single-supply 4.75 V to 5.25 V COM1 BIAS COM2
AND
APPLICATIONS VREF
VPS1 VPS2
Transmit and receive power control at RF and IF

05134-001
VREF IPBS OPBS COM1 COM2 COM2

Figure 1.

GENERAL DESCRIPTION
The ADL5330 is a high performance, voltage controlled, variable The output of the high accuracy wideband attenuator is applied
gain amplifier (VGA)/attenuator for use in applications with to a differential transimpedance output stage. The output stage
frequencies up to 3 GHz. The balanced structure of the signal sets the 50 Ω differential output impedances and drives the
path minimizes distortion while it also reduces the risk of OPHI and OPLO pins. The ADL5330 has a power-down
spurious feedforward at low gains and high frequencies caused function. It can be powered down by a Logic LO input on the
by parasitic coupling. While operation between a balanced source ENBL pin. The current consumption in power-down mode is
and load is recommended, a single sided input is internally 250 μA.
converted to differential form. The ADL5330 is fabricated on an Analog Devices, Inc.,
The input impedance is 50 Ω from INHI to INLO. The outputs proprietary high performance, complementary bipolar IC process.
are usually coupled into a 50 Ω grounded load via a 1:1 balun. A The ADL5330 is available in a 24-lead (4 mm × 4 mm), Pb-free
single supply of 4.75 V to 5.25 V is required. LFCSP package and is specified for operation from ambient
The 50 Ω input system converts the applied voltage to a pair of temperatures of −40°C to +85°C. An evaluation board is also
differential currents with high linearity and good common available.
rejection even when driven by a single sided source. The signal
currents are then applied to a proprietary voltage controlled
attenuator providing precise definition of the overall gain under
the control of the linear in dB interface. The GAIN pin accepts a
voltage from 0 V at minimum gain to 1.4 V at full gain with a
20 mV/dB scaling factor.

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2017 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support [Link]
ADL5330 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Basic Connections ...................................................................... 13
Applications ....................................................................................... 1 RF Input/Output Interface ........................................................ 14
Functional Block Diagram .............................................................. 1 Gain Control Input .................................................................... 15
General Description ......................................................................... 1 Automatic Gain Control ............................................................ 15
Revision History ............................................................................... 2 Interfacing to an IQ Modulator ................................................ 17
Specifications..................................................................................... 3 WCDMA Transmit Application ............................................... 18
Absolute Maximum Ratings............................................................ 5 CDMA2000 Transmit Application........................................... 19
ESD Caution .................................................................................. 5 Soldering Information ............................................................... 19
Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ........................................................................ 20
Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 24
Theory of Operation ...................................................................... 12 Ordering Guide .......................................................................... 24
Applications Information .............................................................. 13

REVISION HISTORY
11/2017—Rev. A to Rev. B
Changed LFCSP_VQ to LFCSP ................................... Throughout
Changes to Figure 2 and Table 3 ..................................................... 6
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24

6/2005—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Figure 27 ...................................................................... 11
Changes to Figure 35 ...................................................................... 14
Changes to the Gain Control Input Section................................ 15
Changes to Figure 42 ...................................................................... 17

4/2005—Revision 0: Initial Version

Rev. B | Page 2 of 24
Data Sheet ADL5330

SPECIFICATIONS
VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match.

Table 1.
Parameter Conditions Min Typ Max Unit
GENERAL
Usable Frequency Range 0.01 3 GHz
Nominal Input Impedance Via 1:1 single-sided-to-differential balun 50 Ω
Nominal Output Impedance Via 1:1 differential-to-single-sided balun 50 Ω
100 MHz
Gain Control Span ±3 dB gain law conformance 58 dB
Maximum Gain VGAIN = 1.4 V 23 dB
Minimum Gain VGAIN = 0.1 V −35 dB
Gain Flatness vs. Frequency ±30 MHz around center frequency, 0.09 dB
VGAIN = 1.0 V (differential output)
Gain Control Slope 20.7 mV/dB
Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 0.88 V
Input Compression Point VGAIN = 1.2 V 1.8 dBm
Input Compression Point VGAIN = 1.4 V −0.3 dBm
Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 38 dBm
Output Noise Floor 1 20 MHz carrier offset, VGAIN = 1.4 V −140 dBm/Hz
Noise Figure VGAIN = 1.4 V 7.8 dB
Input Return Loss 2 1 V < VGAIN < 1.4 V −12.8 dB
Output Return Loss2 −15.5 dB
450 MHz
Gain Control Span ±3 dB gain law conformance 57 dB
Maximum Gain VGAIN = 1.4 V 22 dB
Minimum Gain VGAIN = 0.1 V −35 dB
Gain Flatness vs. Frequency ±30 MHz around center frequency, 0.08 dB
VGAIN = 1.0 V, (differential output)
Gain Control Slope 20.4 mV/dB
Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 0.89 V
Input Compression Point VGAIN = 1.2 V 3.3 dBm
Input Compression Point VGAIN = 1.4 V 1.2 dBm
Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 36 dBm
Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −146 dBm/Hz
Noise Figure VGAIN = 1.4 V 8.0 dB
Input Return Loss2 1 V < VGAIN < 1.4 V −19 dB
Output Return Loss2 −13.4 dB
900 MHz
Gain Control Span ±3 dB gain law conformance 53 dB
Maximum Gain VGAIN = 1.4 V 21 dB
Minimum Gain VGAIN = 0.2 V −32 dB
Gain Flatness vs. Frequency ±30 MHz around center frequency, 0.14 dB
VGAIN = 1.0 V (differential output)
Gain Control Slope 19.7 mV/dB
Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 0.92 V
Input Compression Point VGAIN = 1.2 V 2.7 dBm
Input Compression Point VGAIN = 1.4 V 1.3 dBm
Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 31.5 dBm
Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −144 dBm/Hz
Noise Figure VGAIN = 1.4 V 9.0 dB

Rev. B | Page 3 of 24
ADL5330 Data Sheet
Parameter Conditions Min Typ Max Unit
Input Return Loss2 1 V < VGAIN < 1.4 V −18 dB
Output Return Loss2 −18 dB
2200 MHz
Gain Control Span ±3 dB gain law conformance 46 dB
Maximum Gain VGAIN = 1.4 V 16 dB
Minimum Gain VGAIN = 0.6 V −30 dB
Gain Flatness vs. Frequency ±30 MHz around center frequency, 0.23 dB
VGAIN = 1.0 V (differential output)
Gain Control Slope 16.7 mV/dB
Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 1.06 V
Input Compression Point VGAIN = 1.2 V 0.9 dBm
Input Compression Point VGAIN = 1.4 V −2.0 dBm
Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 21.2 dBm
Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −147 dBm/Hz
Noise Figure VGAIN = 1.4 V 12.5 dB
Input Return Loss2 1 V < VGAIN < 1.4 V −11.7 dB
Output Return Loss2 −9.5 dB
2700 MHz
Gain Control Span ±3 dB gain law conformance 42 dB
Maximum Gain VGAIN = 1.4 V 10 dB
Minimum Gain VGAIN = 0.7 V −32 dB
Gain Flatness vs. Frequency ±30 MHz around center frequency, 0.3 dB
VGAIN = 1.0 V (differential output)
Gain Control Slope 16 mV/dB
Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 1.15 V
Input Compression Point VGAIN = 1.2 V 1.2 dBm
Input Compression Point VGAIN = 1.4 V −0.9 dBm
Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 17 dBm
Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −152 dBm/Hz
Noise Figure VGAIN = 1.4 V 14.7 dB
Input Return Loss2 1 V < VGAIN < 1.4 V −9.7 dB
Output Return Loss2 −5 dB
GAIN CONTROL INPUT GAIN pin
Gain Control Voltage Range3 0 1.4 V
Incremental Input Resistance GAIN pin to COM1 pin 1 MΩ
Response Time Full scale: to within 1 dB of final gain 380 ns
3 dB gain step, POUT to within 1 dB of final gain 20 ns
POWER SUPPLIES Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL
Voltage 4.75 5 5.25 V
Current, Nominal Active VGN = 0 V 100 mA
VGN = 1.4 V 215 mA
Current, Disabled ENBL = LO 250 μA
1
Noise floor varies slightly with output power level. See Figure 9 to Figure 13.
2
See Figure 27 and Figure 29 for differential input and output impedances.
3
Minimum gain voltage varies with frequency. See Figure 3 to Figure 7.

Rev. B | Page 4 of 24
Data Sheet ADL5330

ABSOLUTE MAXIMUM RATINGS

Table 2. ESD CAUTION
Parameter Rating
Supply Voltage VPS1, VPS2 5.5 V
RF Input Power at Maximum Gain 5 dBm at 50 Ω
OPHI, OPLO 5.5 V
ENBL VPS1, VPS2
GAIN 2.5 V
Internal Power Dissipation 1.1 W
θJA (with Pad Soldered to Board) 60°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range (Soldering 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. B | Page 5 of 24
ADL5330 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

23 ENBL
22 VPS2
21 VPS2
20 VPS2
19 VPS2
24 GAIN
VPS1 1 18 VPS2
COM1 2 17 COM2
INHI 3 ADL5330 16 OPHI
INLO 4 TOP VIEW 15 OPLO
(Not to Scale)
COM1 5 14 COM2
VPS1 6 13 VPS2

GNLO 11
7
IPBS 8

COM2 12
OPBS 9
COM1 10
VREF
NOTES
1. EXPOSED PAD. THE EXPOSED PAD UNDER

05134-002
THE DEVICE MUST BE CONNECTED TO
GROUND VIA A LOW IMPEDANCE PATH,
THERMALLY AND ELECTRICALLY.

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Descriptions
1, 6, 13, 18 to 22 VPS1, VPS2 Positive Supply. Nominally equal to 5 V.
2, 5, 10 COM1 Common for Input Stage.
3, 4 INHI, INLO Differential Inputs, AC-Coupled.
7 VREF Voltage Reference. Output at 1.5 V; normally ac-coupled to ground.
8 IPBS Input Bias. Normally ac-coupled to ground.
9 OPBS Output Bias. AC-Coupled to ground.
11 GNLO Gain Control Common. Connect to ground.
12, 14, 17 COM2 Common for Output Stage.
15 OPLO Low Side of Differential Output. Bias to VP with RF chokes.
16 OPHI High Side of Differential Output. Bias to VP with RF chokes.
23 ENBL Device Enable. Apply logic high for normal operation.
24 GAIN Gain Control Voltage Input. Nominal range 0 V to 1.4 V.
EPAD Exposed Pad. The exposed pad under the device must be connected to ground via a low
impedance path, thermally and electrically.

Rev. B | Page 6 of 24
Data Sheet ADL5330

TYPICAL PERFORMANCE CHARACTERISTICS

30 4 30 12
–40°C ERROR
–40°C GAIN
20 3 20 9
+25°C ERROR

GAIN LAW CONFORMANCE (dB)

GAIN LAW CONFORMANCE (dB)

10 2 10 6

+85°C ERROR
0 –40°C ERROR 1 0 3
GAIN (dB)

GAIN (dB)
–10 0 –10 0
+25°C ERROR
–20 –1 –20 –3
+85°C GAIN

–30 –2 –30 –6
+85°C ERROR
+25°C GAIN
–40 –3 –40 –9
–40°C GAIN
+25°C GAIN +85°C GAIN
–50 –4 –50 –12

05134-003

05134-006
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V) VGAIN (V)

Figure 3. Gain and Gain Law Conformance vs. VGAIN Figure 6. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 100 MHz over Temperature at 2200 MHz

30 4 20 12
–40°C GAIN
–40°C GAIN
20 3 10 9
–40°C ERROR

GAIN LAW CONFORMANCE (dB)

GAIN LAW CONFORMANCE (dB)

10 2 0 6
+25°C GAIN

0 1 –10 3
–40°C ERROR
GAIN (dB)
GAIN (dB)

–10 0 –20 0
+85°C GAIN
+25°C ERROR
–20 –1 –30 –3
+25°C ERROR
+85°C ERROR
–30 –2 –40 –6
+85°C ERROR

–40 –3 –50 –9
+25°C GAIN +85°C GAIN

–50 –4 –60 –12

05134-007
05134-004

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V) VGAIN (V)

Figure 4. Gain and Gain Law Conformance vs. VGAIN Figure 7. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 450 MHz over Temperature at 2700 MHz

180
30 4
–40°C GAIN
160
20 3
+25°C GAIN 140
GAIN CONTROL SLOPE (dB/V)
GAIN LAW CONFORMANCE (dB)

10 2
120
–40°C ERROR
0 1
100
GAIN (dB)

VGAIN = 1.0V
–10 0
80

–20 –1 60
+25°C ERROR

–30 –2 40

+85°C GAIN +85°C ERROR

–40 –3 20

0
05134-008

–50 –4 10 100 1,000 10,000

05134-005

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

FREQUENCY (kHz)
VGAIN (V)

Figure 5. Gain and Gain Law Conformance vs. VGAIN Figure 8. Frequency Response of Gain Control Input,
over Temperature at 900 MHz Carrier Frequency = 900 MHz

Rev. B | Page 7 of 24
ADL5330 Data Sheet
40 –115 30 –115
OIP3 OIP3
30 –120 20 –120

20 –125 10 –125
INPUT P1dB

NOISE FLOOR (dBm/Hz)

NOISE FLOOR (dBm/Hz)

INPUT P1dB
10 –130 0 –130
POWER (dBm)

POWER (dBm)
0 –135 –10 –135

–10 –140 –20 –140

OUTPUT P1dB OUTPUT P1dB

–20 –145 –30 –145

–30 –150 –40 –150

–40 –155 –50 –155

05134-009

05134-012
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V) VGAIN (V)

Figure 9. Input Compression Point, Output Compression Point, Figure 12. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 100 MHz OIP3, and Noise Floor vs. VGAIN at 2200 MHz

40 –115 30 –120
OIP3
OIP3
30 –120 20 –125
INPUT P1dB
20 –125 10 –130

NOISE FLOOR (dBm/Hz)

NOISE FLOOR (dBm/Hz)

INPUT P1dB
10 –130 0 –135
POWER (dBm)
POWER (dBm)

0 –135 –10 –140

OUTPUT P1dB
–10 –140 –20 –145
OUTPUT P1dB
–20 –145 –30 –150

–30 –150 –40 –155

–40 –155 –50 –160

05134-013
05134-010

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V) VGAIN (V)

Figure 10. Input Compression Point, Output Compression Point, Figure 13. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 450 MHz OIP3, and Noise Floor vs. VGAIN at 2700 MHz

40 –115 T
T
30 –120
OIP3
20 –125
NOISE FLOOR (dBm/Hz)

INPUT P1dB
10 –130
POWER (dBm)

0 –135
2

–10 –140
OUTPUT P1dB
–20 –145

–30 –150

–40 –155
05134-011

1
05134-014

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

CH1 200mV CH2 100mV  M100ns A CH4 2.70V
VGAIN (V)
T 382.000ns

Figure 11. Input Compression Point, Output Compression Point, Figure 14. Step Response of Gain Control Input
OIP3, and Noise Floor vs. VGAIN at 900 MHz

Rev. B | Page 8 of 24
Data Sheet ADL5330
40 30
OIP3 (–40°C)
30 20

20 10

10 OIP3 (–40°C)

OIP3, OP1dB (dBm)

0
OIP3, OP1dB (dBm)

OIP3 (+85°C)
OP1dB (–40°C)
0 OIP3 (+25°C)
–10 OIP3 (+85°C)
–10 OP1dB (+85°C)
–20 OIP3 (+25°C)
–20 OP1dB (+85°C)
–30
–30
–40
–40 OP1dB (+25°C) OP1dB (–40°C) OP1dB (+25°C)

–50 –50

05134-018
05134-015
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V) VGAIN (V)

Figure 15. OP1dB and OIP3 vs. Gain over Temperature at 100 MHz Figure 18. OP1dB and OIP3 vs. Gain over Temperature at 2200 MH
z

40 20
OIP3 (+85°C)
30 10

20
0
OIP3 (+85°C)
OIP3, OP1dB (dBm)

OIP3, OP1dB (dBm)

10 OIP3 (–40°C)
–10
0 OIP3 (+25°C) OIP3 (+25°C) OP1dB (+25°C)
–20
–10 OP1dB (+25°C) OP1dB (–40°C)
OIP3 (–40°C)
–30
–20 OP1dB (+85°C)

–30 –40

OP1dB (–40°C) OP1dB (+85°C)

–40 –50
05134-016

05134-019
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V) VGAIN (V)

Figure 16. OP1dB and OIP3 vs. Gain over Temperature at 450 MHz Figure 19. OP1dB and OIP3 vs. Gain over Temperature at 2700 MHz

40 250
OP1dB (+25°C) OIP3 (–40°C)

30
OIP3 (+85°C)
200
20
OIP3, OP1dB (dBm)

10 TEMP = +85°C
OIP3 (+25°C) 150
ISUPPLY (mA)

TEMP = +25°C
0
TEMP = –40°C
–10 100
OP1dB (+85°C)

–20
50
–30
OP1dB (–40°C)
–40 0
05134-017

05134-020

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V) VGAIN (V)

Figure 17. OP1dB and OIP3 vs. Gain over Temperature at 900 MHz Figure 20. Supply Current vs. VGAIN and Temperature

Rev. B | Page 9 of 24
ADL5330 Data Sheet
70 30

60
25

50
20
PERCENTAGE (%)

PERCENTAGE (%)
40
15
30

10
20

5
10

0 0

05134-021
18.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5 18 18.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24

05134-024
OP1dB (dBm)
OIP3 (dBm)

Figure 21. OP1dB Distribution at 900 MHz at Maximum Gain, VGAIN = 1.4 V Figure 24. OIP3 Distribution at 2200 MHz at Maximum Gain; VGAIN = 1.4 V

30 30
VGAIN = 1.4V
20 VGAIN = 1.2V
25
10 VGAIN = 1.0V
20
PERCENTAGE (%)

0 VGAIN = 0.8V
GAIN (dB)

15 –10 VGAIN = 0.6V

–20 VGAIN = 0.4V

10
VGAIN = 0.2V
–30
5
–40

0 –50
05134-022

05134-025
9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16 10 100 1,000 10,000
OP1dB (dBm) FREQUENCY (MHz)

Figure 22. OP1dB Distribution at 2200 MHz at Maximum Gain, VGAIN = 1.4 V Figure 25. Gain vs. Frequency (Differential)

30 30
VGAIN = 1.4V
20
25 VGAIN = 1.2V

10
VGAIN = 1.0V
20
PERCENTAGE (%)

0 VGAIN = 0.8V
GAIN (dB)

15 –10 VGAIN = 0.6V

–20 VGAIN = 0.4V

10
–30 VGAIN = 0.2V

5
–40

0 –50
05134-026

28 29 30 31 32 33 34 35 10 100 1,000 10,000

05134-023

28.5 29.5 30.5 31.5 32.5 33.5 34.5 33.5

FREQUENCY (MHz)
OIP3 (dBm)

Figure 23. OIP3 Distribution at 900 MHz at Maximum Gain, VGAIN = 1.4 V Figure 26. Gain vs. Frequency (Using ETC1-1-13 Baluns)

Rev. B | Page 10 of 24
Data Sheet ADL5330
90 90

120 60 120 60

150 150 30
30
VGAIN = 0.2V 450MHz

450MHz VGAIN = 0.2V

3GHz VGAIN = 1.2V
180 0
180 0
3GHz
VGAIN = 1.2V
1.9GHz
1.9GHz
210 330
210 330

240 300
240 300

05134-028
05134-027
270
270

Figure 27. Input Impedance (Differential) Figure 29. Output Impedance (Differential)

0 0

–5 –5

–10 –10

–15 –15
S11 (dB)
S11 (dB)

–20 –20

–25 –25

–30 –30

–35 –35

05134-030
05134-029

100 600 1100 1600 2100 2600 100 600 1100 1600 2100 2600
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 28. Input Return Loss with ETC1-1-13 Baluns Figure 30. Output Return Loss with ETC1-1-13 Baluns

Rev. B | Page 11 of 24
ADL5330 Data Sheet

THEORY OF OPERATION
The ADL5330 is a high performance, voltage controlled variable by proprietary means to achieve linear in dB gain control and
gain amplifier/attenuator for use in applications with frequencies low distortion.
up to 3 GHz. This device serves as an output variable gain Linear in dB gain control is accomplished by the application of
amplifier (OVGA) for applications where a reasonably constant a voltage in the range of 0 V dc to 1.4 V dc to the gain control
input level is available and the output level adjusts over a wide pin, with maximum gain occurring at the highest voltage.
range. One aspect of an OVGA is the output metrics, OIP3 and
OP1dB, decrease with decreasing gain. The output of the ladder attenuator is passed into a fixed gain
transimpedance amplifier (TZA) to provide gain and buffer the
The signal path is fully differential throughout the device in ladder terminating impedance from load variations. The TZA
order to provide the usual benefits of differential signaling, uses feedback to improve linearity and to provide controlled
including reduced radiation, reduced parasitic feedthrough, and 50 Ω differential output impedance. The quiescent current of
reduced susceptibility to common-mode interference with other the output amplifier is adaptive; it is slaved to the gain control
circuits. Figure 31 provides a simplified schematic of the voltage to conserve power at times when the gain (and output
ADL5330. power) are low.
The outputs of the ADL5330 require external dc bias to the
TRANSIMPEDANCE positive supply voltage. This bias is typically supplied through
AMPLIFIER
external inductors. The outputs are best taken differentially to
INHI OPHI avoid any common-mode noise that is present, but, if necessary,
INLO OPLO
can be taken single-ended from either output.
Gm STAGE If only a single output is used, it is still necessary to provide bias
to the unused output pin, and it is advisable to arrange a reasonably
05134-031

GAIN equivalent ac load on the unused output. Differential output can

CONTROL
be taken via a 1:1 balun into a 50 Ω environment. In virtually all
Figure 31. Simplified Schematic cases, it is necessary to use dc blocking in the output signal path.
A controlled input impedance of 50 Ω is achieved through a At high gain settings, the noise floor is set by the input stage, in
combination of passive and active (feedback-derived) termination which case the noise figure (NF) of the device is essentially
techniques in an input Gm stage. The input compression point independent of the gain setting. Below a certain gain setting,
of the Gm stage is 1 dBm to 3 dBm, depending on the input however, the input stage noise that reaches the output of the
frequency. attenuator falls below the input equivalent noise of the output
Note that the inputs of the Gm stage are internally biased to a stage. In such a case, the output noise is dominated by the
dc level, and dc blocking capacitors are generally needed on the output stage itself; therefore, the overall NF of the device gets
inputs to avoid upsetting operation of the device. worse on a dB per dB basis, because the gain is reduced below
the critical value. Figure 9 through Figure 13 provide details of
The currents from the Gm stage are then injected into a balanced this behavior.
ladder attenuator at a deliberately diffused location along the
ladder, wherein the location of the centroid of the injection
region is dependent on the applied gain control voltage. The
steering of the current injection into the ladder is accomplished

Rev. B | Page 12 of 24
Data Sheet ADL5330

APPLICATIONS INFORMATION
BASIC CONNECTIONS Since the differential outputs are biased to the positive supply,
ac-coupling capacitors, preferably 100 pF, are needed between
Figure 32 shows the basic connections for operating the ADL5330. the ADL5330 outputs and the next stage in the system. Similarly,
There are two positive supplies, VPS1 and VPS2, which must be the INHI and INLO input pins are at bias voltages of about
connected to the same potential. Both COM1 and COM2 3.3 V above ground.
(common pins) should be connected to a low impedance
ground plane. The nominal input and output impedance looking into each
individual RF input/output pin is 25 Ω. Consequently, the
A power supply voltage between 4.75 V and 5.25 V should be differential impedance is 50 Ω.
applied to VPS1 and VPS2. Connect decoupling capacitors with
100 pF and 0.1 μF power supplies close to each power supply To enable the ADL5330, the ENBL pin must be pulled high.
pin. The VPS2 pins (Pin 18 through Pin 22) can share a pair of Taking ENBL low puts the ADL5330 in sleep mode, reducing
decoupling capacitors because of their proximity to each other. current consumption to 250 μA at ambient. The voltage on
ENBL must be greater than 1.7 V to enable the device. When
The outputs of the ADL5330, OPHI and OPLO, are open collectors enabled, the device draws 100 mA at low gain to 215 mA at
that need to be pulled up to the positive supply with 120 nH RF maximum gain.
chokes. The ac coupling capacitors and the RF chokes are the
principle limitations for operation at low frequencies. For example,
to operate down to 1 MHz, 0.1 μF ac coupling capacitors and
1.5 μH RF chokes should be used. Note that in some circum-
stances, the use of substantially larger inductor values results in
oscillations.

VPOS VPOS

C1 C3
0.1F 0.1F

C2 C4
100pF 100pF

GAIN
L1
120nH
VPOS
GAIN

ENBL

VPS2

VPS2

VPS2

VPS2

C12 C16
L2
0.1F 100pF
VPS1 VPS2 120nH

C13 COM1 COM2 C5

100pF 100pF
INHI OPHI
RF INPUT ADL5330 RF OUTPUT
INLO OPLO
C14 C6
100pF COM1 COM2 100pF
VPOS VPS1 VPS2
GNLO
COM1

COM2
OPBS

C12 C11
VREF

IPBS

0.1F 100pF C7
100pF

C8
C10 C9
0.1F
1nF 1nF
05334-032

VPOS

Figure 32. Basic Connections

Rev. B | Page 13 of 24
ADL5330 Data Sheet
RF INPUT/OUTPUT INTERFACE band baluns can be used for applications requiring lower insertion
The ADL5330 is primarily designed for differential signals; loss over smaller bandwidths.
however, there are several configurations that can be implemented The device can be driven single-ended with similar performance,
to interface the ADL5330 to single-ended applications. Figure 33 as shown in Figure 34. The single-ended input interface can be
to Figure 35 show three options for differential to single-ended implemented by driving one of the input terminals and terminating
interfaces. All three configurations use ac-coupling capacitors at the unused input to ground. To achieve the optimal performance,
the input/output and RF chokes at the output. the output must remain balanced. In the case of Figure 34, a
+5V transformer balun is used at the output.
As an alternative to transformer baluns, lumped element baluns
120nH comprised of passive L and C components can be designed at
120nH
specific frequencies. Figure 35 illustrates differential balance at
the input and output of the ADL5330 using discrete lumped
ADL5330
100pF RF VGA 100pF
element baluns. The lumped element baluns present 180° of
RFIN INHI OPHI RFOUT phase difference while also providing impedance transformation
INLO OPLO from source to load, and vice versa. Table 4 lists recommended
100pF 100pF 05134-033
passive values for various center frequencies with single-ended
ETC1-1-13 ETC1-1-13
impedances of 50 Ω. Agilent’s free AppCADTM program allows
Figure 33. Differential Operation with Balun Transformers for simple calculation of passive components for lumped element
+5V baluns.
The lumped element baluns offer ±0.5 dB flatness across 50 MHz
120nH
for 900 MHz and 2200 MHz. At 2.7 GHz, the frequency band is
120nH
limited by stray capacitances that dominate the passive components
in the lumped element balun at these high frequencies. Therefore,
ADL5330
100pF RF VGA 100pF PCB parasitics must be considered during lumped element
RFIN INHI OPHI RFOUT balun design and board layout.
INLO OPLO
05134-041

100pF 100pF Table 4. Recommended Passive Values for Lumped Element

ETC1-1-13
Balun, 50 Ω Impedance Match
Figure 34. Single-Ended Drive with Balanced Output Center Input Output
Figure 33 illustrates differential balance at the input and output Frequency Ci Li Cip Co Lo Cop
using a transformer balun. Input and output baluns are recom- 100 MHz 27 pF 82 nH 1 pF 33 pF 72 nH 3.3 pF
mended for optimal performance. Much of the characterization 900 MHz 3.3 pF 9 nH 3.9 pF 8.7 nH 0.5 pF
for the ADL5330 was completed using 1:1 baluns at the input 2.2 GHz 1.5 pF 3.3 nH 16 nH 1.5 pF 3.6 nH 27 nH
and output for single-ended 50 Ω match. Operation using 2.7 GHz 1.5 pF 2.4 nH 1.3 pF 2.7 nH 33 nH
M/A-COM ETC1-1-13 transmission line transformer baluns
is recommended for a broadband interface; however, narrow-
+5V

120nH

120nH

Li 100pF 100pF Lo
INHI OPHI
Ci Ci Co Co
ADL5330
RFIN Cip Cop RFOUT
RF VGA
INLO OPLO
Ci Ci 100pF 100pF Co Co
Li Lo
05134-035

Figure 35. Differential Operation with Discrete LC Baluns

Rev. B | Page 14 of 24
Data Sheet ADL5330
GAIN CONTROL INPUT The error amplifier of the detector uses CFLT, a ground referenced
When the VGA is enabled, the voltage applied to the GAIN pin capacitor pin, to integrate the error signal (in the form of a
sets the gain. The input impedance of the GAIN pin is 1 MΩ. current). A capacitor must be connected to CFLT to set the loop
bandwidth and to ensure loop stability.
The gain control voltage range is between 0 V and +1.4 V, which +5V +5V
corresponds to a typical gain range between −38 dB and +22 dB.
The useful lower limit of the gain control voltage increases at
high frequencies to about 0.5 V and 0.6 V for 2.2 GHz and VPOS COMM
2.7 GHz, respectively. The supply current to the ADL5330 can RFIN
INHI OPHI
vary from approximately 100 mA at low gain control voltages to ADL5330 DIRECTIONAL
215 mA at 1.4 V. INLO OPLO COUPLER

The 1 dB input compression point remains constant at 3 dBm GAIN

through the majority of the gain control range, as shown in ATTENUATOR

Figure 9 through Figure 13. The output compression point VOUT

increases dB for dB with increasing gain setting. The noise floor LOG AMP OR
TRUPWR
is constant up to 1 V where it begins to rise. DETECTOR
The bandwidth on the gain control pin is approximately 3 MHz. DAC VSET RFIN
CLPF
Figure 14 shows the response time of a pulse on the GAIN pin.

05134-036
AUTOMATIC GAIN CONTROL
Although the ADL5330 provides accurate gain control, precise Figure 36. ADL5330 in AGC Loop
regulation of output power can be achieved with an automatic
gain control (AGC) loop. Figure 36 shows the ADL5330 in an The basic connections for operating the ADL5330 in an AGC
AGC loop. The addition of the log amp (AD8318/AD8315) or a loop with the AD8318 are shown in Figure 37. The AD8318 is a
TruPwr™ detector (AD8362) allows the AGC to have improved 1 MHz to 8 GHz precision demodulating logarithmic amplifier.
temperature stability over a wide output power control range. It offers a large detection range of 60 dB with ±0.5 dB tempera-
ture stability. This configuration is similar to Figure 36.
To operate the ADL5330 in an AGC loop, a sample of the output
RF must be fed back to the detector (typically using a directional The gain of the ADL5330 is controlled by the output pin of the
coupler and additional attenuation). A setpoint voltage is applied AD8318. This voltage, VOUT, has a range of 0 V to near VPOS.
to the VSET input of the detector while VOUT is connected to To avoid overdrive recovery issues, the AD8318 output voltage
the GAIN pin of the ADL5330. Based on the defined linear in dB can be scaled down using a resistive divider to interface with the
relationship of the detector between VOUT and the RF input 0 V to 1.4 V gain control range of ADL5330.
signal, the detector adjusts the voltage on the GAIN pin (the A coupler/attenuation of 23 dB is used to match the desired
VOUT pin of the detector is an error amplifier output) until the maximum output power from the VGA to the top end of the
level at the RF input corresponds to the applied setpoint voltage. linear operating range of the AD8318 (at approximately −5 dBm
The GAIN setting settles to a value that results in the correct at 900 MHz).
balance between the input signal level at the detector and the
setpoint voltage.

Rev. B | Page 15 of 24
ADL5330 Data Sheet
+5V +5V

RF INPUT RF OUTPUT
SIGNAL 120nH SIGNAL
VPOS COMM 120nH
100pF 100pF
INHI OPHI
ADL5330 100pF DIRECTIONAL
INLO OPLO COUPLER
100pF
GAIN

412 +5V ATTENUATOR

1k

SETPOINT
VOUT VPOS 1nF
VOLTAGE
DAC VSET INHI
AD8318
LOG AMP 1nF
CLPF INLO
220pF COMM

05134-037
Figure 37. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318

Figure 38 shows the transfer function of the output power vs. In order for the AGC loop to remain in equilibrium, the
the VSET voltage over temperature for a 900 MHz sine wave AD8318 must track the envelope of the ADL5330 output signal
with an input power of −1.5 dBm. Note that the power control and provide the necessary voltage levels to the ADL5330’s gain
of the AD8318 has a negative sense. Decreasing VSET, which control input. Figure 39 shows an oscilloscope screenshot of the
corresponds to demanding a higher signal from the ADL5330, AGC loop depicted in Figure 37. A 100 MHz sine wave with
tends to increase GAIN. 50% AM modulation is applied to the ADL5330. The output
The AGC loop is capable of controlling signals just under the signal from the ADL5330 is a constant envelope sine wave with
full 60 dB gain control range of the ADL5330. The performance amplitude corresponding to a setpoint voltage at the AD8318 of
over temperature is most accurate over the highest power range, 1.5 V. Also shown is the gain control response of the AD8318 to
where it is generally most critical. Across the top 40 dB range of the changing input envelope.
output power, the linear conformance error is well within T

±0.5 dB over temperature. AM MODULATED INPUT T

30 4
1

20 3

10 2
AD8318 OUTPUT
OUTPUT POWER (dBm)

0 1
ERROR (dB)

–10 0

–20 –1
3
–30 –2
ADL5330 OUTPUT
05134-039

–40 –3
CH1 250mV  M2.00ms A CH4 1.80V
CH3 250mV  T 0.00000s
–50 –4
05134-038

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
SETPOINT VOLTAGE (V) Figure 39. Oscilloscope Screenshot Showing an AM Modulated Input Signal
Figure 38. ADL5330 Output Power vs. AD8318 Setpoint Voltage,
PIN = −1.5 dBm

The broadband noise added by the logarithmic amplifier is

negligible.

Rev. B | Page 16 of 24
Data Sheet ADL5330
Figure 40 shows the response of the AGC RF output to a pulse can be driven single-ended, as shown in Figure 42. Similar con-
on VSET. As VSET decreases to 1 V, the AGC loop responds figurations are possible with the AD8345 (250 MHz to 1 GHz)
with an RF burst. Response time and the amount of signal and AD8346 (800 MHz to 2.5 GHz) quadrature modulators.
integration are controlled by the capacitance at the AD8318 CFLT Figure 41 shows how output power, EVM, ACPR, and noise
pin—a function analogous to the feedback capacitor around an vary with the gain control voltage. VGAIN is varied from 0 V to
integrating amplifier. An increase in the capacitance results in 1.4 V. Figure 41 shows that the modulation generated by the
slower response time. AD8349 is a 1 GHz 64 QAM waveform with a 1 MHz symbol
T rate. The ACPR values are measured in 1 MHz bandwidths at
T
AD8318 WITH PULSED VSET 1.1 MHz and 2.2 MHz carrier offsets. Noise floor is measured at
a 20 MHz carrier offset.
20 4.5

NOISE (dBm/Hz) (20MHz CARRIER OFFSET)

0 OUTPUT POWER 4.0
1

ACPR (dBm) (1MHz BANDWIDTH)

–20 3.5

OUTPUT POWER (dBm)

–40 3.0
ACPR 1.1MHz OFFSET
–60 2.5

EVM (%)
ADL5330 OUTPUT
2
–80 2.0
ACPR 2.2MHz OFFSET
–100 1.5
EVM
05134-040

–120 1.0
CH1 2.00V CH2 50.0mV M10.0s A CH1 2.60V NOISE FLOOR
T 20.2000s –140 0.5

Figure 40. Oscilloscope Screenshot Showing the –160 0

05134-042
Response Time of the AGC Loop 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGAIN (V)
More information on the use of AD8318 in an AGC application
Figure 41. AD8349 and ADL5330 Output Power, ACPR, EVM, and Noise vs.
can be found in the AD8318 data sheet.
VGAIN for a 1 GHz 64 QAM Waveform with 1 MHz Symbol Rate
INTERFACING TO AN IQ MODULATOR The output of the AD8349 driving the ADL5330 should be
The basic connections for interfacing the AD8349 with the limited to the range that provides the optimal EVM and ACPR
ADL5330 are shown in Figure 42. The AD8349 is an RF performance. The power range is found by sweeping the output
quadrature modulator with an output frequency range of power of the AD8349 to find the best compromise between
700 MHz to 2.7 GHz. It offers excellent phase accuracy and EVM and ACPR of the system. In Figure 41, the AD8349 output
amplitude balance, enabling high performance direct RF power is set to −15 dBm.
modulation for communication systems.
The output of the AD8349 is designed to drive 50 Ω loads and
easily interfaces with the ADL5330. The input to the ADL5330
+5V

120nH
+5V +5V

120nH
VPOS COMM VPOS COMM
IBBP
DAC AD8349 100pF ADL5330 100pF
IBBN VOUT INHI OPHI RF OUTPUT
DIFFERENTIAL I/Q IQ MOD RF VGA
BASEBAND INPUTS INLO OPLO
QBBP
DAC 100pF 100pF
QBBN
ETC1-1-13

100pF
200
LO GAIN CONTROL
05134-034

100pF 200
ETC1-1-13

Figure 42. AD8349 Quadrature Modulator and ADL5330 Interface

Rev. B | Page 17 of 24
ADL5330 Data Sheet
–20 –50
WCDMA TRANSMIT APPLICATION
Figure 43 shows a plot of the output spectrum of the ADL5330 –30 –55

ADJACENT/ALTERNATE CHANNEL
transmitting a single-carrier WCDMA signal (Test Model 1-64

NOISE – dBm @ 50MHz CARRIER

–40 –60
at 2140 MHz). The carrier power output is approximately ACPR +5MHZ OFFSET

POWER RATIO (dBc)

OFFSET (1MHz BW)

−9.6 dBm. The gain control voltage is equal to 1.4 V giving a –50 –65

gain of approximately 14.4 dB. At this power level, an adjacent –60 –70
channel power ratio of −65.61 dBc is achieved. The alternate
ACPR +10MHZ
–70 –75
channel power ratio of −71.37 dBc is dominated by the noise OFFSET
floor of the ADL5330. –80 –80
MARKER 1 [T1] NOISE –50MHz OFFSET
RBW 30kHz RF ATT 0dB
REF LVL –29.78dBm VBW 300kHz –90 –85
–20dBm 2.13996994GHz SWT 100ms UNIT dBm
–20 –100 –90

05134-044
0.4 dB OFFSET 1 [T1] –29.78 dBm
A –40 –35 –30 –25 –20 –15 –10 –5 0 5 10
2.13996994 GHz
–30 CH PWR –9.56 dBm OUTPUT POWER (dBm)
ACP Up –66.30 dB
–40 ACP Low –65.61 dB Figure 44. ACPR and Noise vs. Output Power; Single-Carrier
ALT1 Up –71.37 dB
ALT1 Low –72.79 dB WCDMA Input (Test Model 1-64 at 2140 MHz), VGAIN = 1.4 V (Fixed)
–50
1 AVG 1RM
–60 Figure 45 shows how output power, ACPR, and noise vary with
EXT
–70
the gain control voltage. VGAIN is varied from 0 V to 1.4 V and
input power is held constant at −19 dBm.
–80
10 –20
–90
CL2 C0 C0
CL2 0 –30
–100 CL1

NOISE @ 50MHz OFFSET (1MHz BW)

CL1 CU1 CU2
–110 CU1 –10 OUTPUT POWER –40
CU2
OUTPUT POWER (dBm)

–120 –20 –50

05134-043

CENTER 2.14GHz 2.46848MHz/ SPAN 24.6848MHz

ACPR (dBc)
ACPR 5MHz
–30 –60
Figure 43. Single-Carrier WCDMA Spectrum at 2140 MHz;
VGAIN = 1.4 V, PIN = −23 dBm –40 –70

Figure 44 shows how ACPR and noise vary with different input –50
ACPR 10MHz
–80
power levels (gain control voltage is held at 1.4 V). At high power NOISE –50MHz OFFSET
–60 –90
levels, both adjacent and alternate channel power ratios sharply
increase. As output power drops, adjacent and alternate channel –70 –100

05134-045
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
power ratios both reach minima before the measurement becomes VGAIN (V)
dominated by the noise floor of the ADL5330. At this point,
adjacent and alternate channel power ratios become Figure 45. Output Power, ACPR, and Noise vs. VGAIN;
Single-Carrier WCDMA (Test Model 1-64 at 2140 MHz) Input at −19 dBm
approximately equal.
As the output power drops, the noise floor, measured in dBm/Hz
at 50 MHz carrier offset, initially falls and then levels off.

Rev. B | Page 18 of 24
Data Sheet ADL5330
CDMA2000 TRANSMIT APPLICATION The results show that up to a total output power of +8 dBm,
To test the compliance to the CDMA2000 base station standard, ACPR remains in compliance with the standard (<−45 dBc at
an 880 MHz, three-carrier CDMA2000 test model signal (forward 750 kHz and <−60 dBc at 1.98 MHz). At low output power
pilot, sync, paging, and six traffic, as per 3GPP2 C.S0010-B, levels, ACPR at 1.98 MHz carrier offset degrades as the noise
Table [Link]) was applied to the ADL5330. A cavity-tuned filter floor of the ADL5330 becomes the dominant contributor to
with a 4.6 MHz pass band was used to reduce noise from the measured ACPR. Measured noise at 4 MHz carrier offset begins
signal source being applied to the device. to increase sharply above 0 dBm output power. This increase is
not due to noise but results from increased carrier-induced
Figure 46 shows the spectrum of the output signal under distortion. As output power drops below 0 dBm total, the noise
nominal conditions. Total POUT of the three-carrier signal is floor drops towards −85 dBm.
equal to 0.46 dBm and VGAIN = 1.4 V. Adjacent and alternate
channel power ratio is measured in a 30 kHz bandwidth at With a fixed input power of −23 dBm, the output power was
750 kHz and 1.98 MHz carrier offset, respectively. again swept by exercising the gain control input. VGAIN was
swept from 0 V to 1.4 V. The resulting total output power,
MARKER 1 [T1]
RBW 30kHz RF ATT 10dB
REF LVL –18.55dBm VBW 300kHz MIXER –10dBm
ACPR, and noise floor are shown in Figure 48.
–10dBm 880.00000000MHz SWT 200ms UNIT dBm 10 –30
–10

NOISE – 4MHz CARRIER OFFSET – (1MHz RBW)

0.4 dB OFFSET 1 1 [T1] –18.55dBm A
880MHz
–20 CH PWR 0.46dBm 0 –40
ACP Up –65.13dB
–30

TOTAL OUTPUT POWER (dBm)

ACP Low –64.40dB OUTPUT POWER
ALT1 Up –89.05dB –10 –50
–40 ALT1 Low –83.68dB
ALT2 Up –80.72dB
1 AVG 1RM
ALT2 Low –81.24dB –20 –60

ACPR (dBc)
–50
EXT
–60 ACPR 750kHz OFFSET
–30 –70
ACPR 1.98MHz OFFSET
–70 C0
C0
CL3 –40 –80
CL3 CL2
–80
CL2 CL1
–90 CL1 CU1 –50 –90
CU1 CU2
–100 CU2
NOISE 4MHz OFFSET
CU3
CU3 –60 –100

05134-048
–110 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
05134-046

CENTER 880MHz 1.5MHz/ SPAN 15MHz VGAIN (V)

Figure 46. 880 MHz Output Spectrum, Three-Carrier CDMA2000 Test Model Figure 48. Total Output Power and ACPR vs. VGAIN, 880 MHz Three-Carrier
at −23 dBm Total Input Power, VGAIN = 1.4 V, ACPR Measured at 750 kHz and CDMA2000 Test Model at −23 dBm Total Input Power; ACPR Measured in
1.98 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter 30 kHz Bandwidth at 750 kHz and 1.98 MHz Carrier Offset
(Pass Band = 4.6 MHz)
Above VGAIN = 0.4 V, the ACPR is still in compliance with the
In testing, by holding the gain control voltage steady at 1.4 V, standard. As the gain control input drops below 1.0 V, the noise
input power was swept. Figure 47 shows ACPR and noise floor floor drops below −90 dBm.
vs. total output power. Noise floor is measured at 1 MHz
bandwidth at 4 MHz carrier offset. SOLDERING INFORMATION
–30 –0 On the underside of the chip scale package, there is an exposed
–40 –10
compressed paddle. This paddle is internally connected to the
NOISE – dBm @ 4MHz CARRIER OFFSET

chip’s ground. Solder the paddle to the low impedance ground

–50 –20
plane on the printed circuit board to ensure specified electrical
ACPR – dBc (30kHz RBW)

–60 –30 performance and to provide thermal relief. It is also recommended

ACPR 750kHz OFFSET
that the ground planes on all layers under the paddle be stitched
(1MHz RBW)

–70 –40
together with vias to reduce thermal impedance.
–80 –50

–90 –60
ACPR 1.98MHz OFFSET
–100 –70
NOISE 4MHz OFFSET
–110 –80

–120 –90
05134-047

–30 –25 –20 –15 –10 –5 0 5 10 15

TOTAL OUTPUT POWER (dBm)

Figure 47. ACPR vs. Total Output Power, 880 MHz Three-Carrier CDMA2000
Test Model; VGAIN = 1.4 V (Fixed), ACPR Measured in 30 kHz Bandwidth at
750 kHz and 1.98 MHz Carrier Offset

Rev. B | Page 19 of 24
ADL5330 Data Sheet
EVALUATION BOARD through M9 are used for the input interface, and M10 through
Figure 49 shows the schematic of the ADL5330 evaluation M18 are used for the output interface. DC blocking capacitors
board. The silkscreen and layout of the component and circuit of 100 pF must be installed in C15 and C16 for the input and
sides are shown in Figure 50 through Figure 53. The board is C17 and C18 for the output. The C5, C6, C11, and C12
powered by a single-supply in the 4.75 V to 5.25 V range. The capacitors must be removed. An alternate set of SMA
power supply is decoupled by 100 pF and 0.1 μF capacitors at connectors, INPUT2 and OUT2, are used for this
each power supply pin. Additional decoupling, in the form of a configuration.
series resistor or inductor at the supply pins, can also be added. The ADL5330 can be driven single-ended; use the RF input path
Table 5 details the various configuration options of the on the circuit side of the board. A set of 100 pF dc blocking
evaluation board. capacitors must be installed in C15 and C16. C5 and C6 must
The output pins of the ADL5330 require supply biasing with be removed. Use the INPUT2 SMA to drive one of the differential
120 nH RF chokes. Both the input and output pins have 50 Ω input pins. The unused pin should be terminated to ground, as
differential impedances and must be ac-coupled. These pins are shown in Figure 34.
converted to single-ended with a pair of baluns (M/A-COM The ADL5330 is enabled by applying a logic high voltage to the
part number ETC1-1-13). ENBL pin by placing a jumper across the SW1 header in the
Instead of using balun transformers, lumped-element baluns O position. Remove the jumper for disable. This pulls the
comprising passive L and C components can be designed. ENBL pin to ground through the 10 kΩ resistor.
Alternate input and output RF paths with component pads are
available on the circuit side of the board. Components M1

Rev. B | Page 20 of 24
 Data Sheet

VPOS
VPOS VPOS

SMA SW1
C2 C14
0.1µF 0.1µF
R1
0Ω R2 R12
R3 0Ω 0Ω
0Ω
GAIN R13
10kΩ C1 C13
R5
0Ω 100pF 100pF
VPOS
C8 C7
C5 0.1µF 100pF C11
100pF L1 100pF
T1 120nH T2
INPUT OUT

GAIN
VPS2
VPS2
VPS2
VPS2

ENBL
VPS1 VPS2 L2
C6 C12
120nH
100pF 100pF
COM1 COM2

INHI OPHI
M1 M4 C15 ADL5330 C17 M12 M14
OPEN OPEN OPEN INLO OPLO OPEN OPEN OPEN

R4 COM1 COM2
M3 M5 M11 M13

Rev. B | Page 21 of 24
M6 VPOS 0Ω M10
INPUT2 OPEN OPEN VPS1 VPS2 OPEN OPEN OUT2
OPEN C3 C4 OPEN
0.1µF 100pF C10

VREF
IPBS
OPBS
COM1
GNLO
COM2

100pF

Figure 49. Evaluation Board Schematic

M7 M9 R6 M15 M17
C16 0Ω C18
OPEN OPEN OPEN OPEN OPEN OPEN
M2 M8 R8 M16 M18
OPEN OPEN 0Ω C9 OPEN OPEN
VREF 0.1µF
R14 R15
OPEN OPEN VPOS
R7 R9
0Ω 0Ω
IPBS IPBS
R10 R11
1nF 1nF

05134-049
ADL5330
ADL5330 Data Sheet
Table 5. Evaluation Board Configuration Options
Components Function Default Conditions
C1 to C4, C7 to C10, C13, Power Supply Decoupling. The nominal supply decoupling consists of C1, C4, C7, C10, C13 = 100 pF
C14, R2, R4, R5, R6, R12 100 pF and 0.1 μF capacitors at each power supply pin (the VPS2 pins, Pin 18 (size 0603)
to Pin 22, share a pair of decoupling capacitors because of their proximity). A C2, C3, C8, C9, C14 = 0.1 μF
series inductor or small resistor can be placed between the capacitors for (size 0603)
additional decoupling. R2, R4, R5, R6, R12 = 0 Ω
(size 0402)
T1, C5, C6 Input Interface. The 1:1 balun transformer T1 converts a 50 Ω single-ended T1 = ETC1-1-13 (M/A-COM)
input to the 50 Ω differential input. C5 and C6 are dc blocks. C5, C6 = 100 pF (size 0603)
T2, C11, C12, L1, L2 Output Interface. The 1:1 balun transformer T2 converts the 50 Ω differential T2 = ETC1-1-13 (M/A-COM)
output to 50 Ω single-ended output. C11 and C2 are dc blocks. L3 and L4 C11, C12 = 100 pF (size 0603)
provide dc biases for the output. L1, L2 = 120 nH (size 0805)
SW1, R1, R13 Enable Interface. The ADL5330 is enabled by applying a logic high voltage to SW1 = installed
the ENBL pin by placing a jumper across SW1 to the O position. Remove the R1 = 0 Ω (size 0402)
jumper for disable. To exercise the enable function by applying an external R13 = 10 kΩ (size 0402)
high or low voltage, use the pin labeled O on the SW1 header.
C15 to C18, M1 to M18 Alternate Input/Output Interface. The circuit side of the evaluation board M1 to M18 = not installed
offers an alternate RF input and output interface. A lumped-element balun (size 0603)
can be built using L and C components instead of using the balun transformer C15 to C18 = not installed
(see the Applications Information section). The components, M1 through (size 0603)
M9, are used for the input, and M10 through M18 are used for the output. To
use the alternate RF paths, disconnect the dc blocking capacitors
(Capacitor C5 and Capacitor C6 for the input and Capacitor C11 and Capacitor
C12 for the output). Place 100 pF dc blocking capacitors on C15, C16, C17,
and C18. Use the alternate set of SMA connectors, INPUT2 and OUT2.

Rev. B | Page 22 of 24
Data Sheet ADL5330

05134-053
05134-051

Figure 50. Component Side Silkscreen Figure 52. Component Side Layout

05134-052
05134-050

Figure 51. Circuit Side Silkscreen Figure 53. Circuit Side Layout

Rev. B | Page 23 of 24
ADL5330 Data Sheet

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10 0.30
4.00 SQ 0.25
PIN 1 3.90 0.20
INDICATOR PIN 1
INDIC ATOR AREA OPTIONS
19 24
(SEE DETAIL A)
18 1

0.50
BSC 2.44
EXPOSED
PAD 2.30 SQ
2.16

13 6

0.50 12 7
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30
0.80 FOR PROPER CONNECTION OF
0.75 THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.203 REF

03-09-2017-B
PKG-003994/5111

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8

Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters

ORDERING GUIDE
Package Ordering
Model1,2 Temperature Range Package Description Option Quantity
ADL5330ACPZ-WP −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-14 64
ADL5330ACPZ-REEL7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-14 1,500
ADL5330ACPZ-R2 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-14 250
ADL5330-EVAL Evaluation Board
1
Z = RoHs Compliant Part.
2
WP = waffle pack.

©2005–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05134-0-11/17(B)

Rev. B | Page 24 of 24