software and custom hardware logic.

In systems where both high-level software execution

and custom hardware acceleration are required, SoCs with integrated FPGA fabric allow
designers to harness the strengths of both paradigms within a single device.

Course Block Diagram and Sub-Parts Explanations

Board / System Context

Mezzanine (Top)

A mezzanine connector is a board-to-board expansion interface mounted on the top side of

the main PCB. It exposes selected PS/PL signals, power rails, and clocks to an add-on card.
This allows modular expansion (e.g. ADCs, motor drivers, RF modules) without redesigning
the base board.

Mezzanine (Bottom)

The bottom mezzanine serves the same purpose as the top one but increases pin count,
routing flexibility, and mechanical separation. Using both top and bottom mezzanines
allows higher I/O density and better segregation of noisy or high-power modules from
sensitive logic.

Main Device
AMD/Xilinx Zynq System-on-Chip

Zynq is a heterogeneous SoC that integrates a hard ARM processor system and FPGA fabric
on the same silicon. It enables tight coupling between software (running on ARM cores) and
custom hardware logic (implemented in FPGA), reducing latency and component count
compared to discrete CPU + FPGA designs.

PS (Processing System)

The Processing System is the hardwired ARM subsystem inside Zynq. It includes CPU cores,
DDR controller, boot ROM, and standard peripherals (Ethernet, USB, SD, UART, QSPI). The PS
runs Linux or bare-metal software and handles system control, networking, and high-level
tasks.

PL (Programmable Logic)

The Programmable Logic is the FPGA fabric portion of Zynq. It is used to implement custom
hardware accelerators, real-time processing, and application-specific peripherals. The PL can
communicate with the PS through high-bandwidth internal interfaces and can directly drive
external I/O.

Memories (Left Side)

QSPI Flash (16 MB)

QSPI Flash is a non-volatile serial memory used primarily for booting the system. It stores
the First Stage Bootloader, FPGA bitstream, and optional firmware components. It is simple,
reliable, and commonly used as the primary boot source.

eMMC Memory (4 GB)

eMMC is a managed non-volatile storage device accessed via an SDIO interface. It provides
higher capacity and better reliability than raw NAND flash and is typically used to store the
Linux kernel, root filesystem, and user data.

DDR3L Memory (512 MB)

DDR3L is external volatile system RAM directly connected to the Zynq PS DDR controller. It
is used as main memory for the operating system and applications. DDR3L requires strict
routing, impedance control, and power integrity to function correctly.

DDR3L Memory (512 MB)

A second DDR3L device may be used to increase memory capacity or bandwidth, depending
on bus width and controller configuration. Multiple DDR devices increase layout complexity
but improve system performance for memory-intensive workloads.
Memory / Interface Labels

QSPI

QSPI refers to the quad-SPI interface connecting the Zynq PS to the QSPI Flash. It allows
faster boot times compared to single-SPI by transferring multiple bits per clock cycle.

SDIO

SDIO is the SD-card–style interface used to communicate with eMMC memory. It supports
multiple data lines and higher transfer rates, making it suitable for OS and filesystem
storage.

Debug / Programming / USB (Right Side – Top)

JTAG / UART

JTAG is used for hardware debug, programming, and boundary scan, while UART provides a
serial console for boot logs and low-level software interaction. These interfaces are essential
for development and bring-up.

FTDI USB-UART / JTAG

An FTDI chip converts USB from a host PC into UART and/or JTAG signals. This allows
programming and debugging the board using a standard USB cable without external debug
hardware.

USB Micro-B

USB Micro-B is the physical connector used to connect the board to a PC for debugging,
programming, or serial communication through the FTDI device.

Ethernet

RGMII / MDIO

RGMII is the high-speed digital interface carrying Ethernet data between the Zynq MAC and
the Ethernet PHY. MDIO is a low-speed management interface used to configure and
monitor the PHY registers.

Gigabit Ethernet PHY

The Ethernet PHY is the physical-layer transceiver that converts digital Ethernet data into
analog signals suitable for transmission over twisted-pair cables. It handles auto-negotiation,
line encoding, and signal conditioning.

RJ45
RJ45 is the Ethernet connector that interfaces with standard network cables. It typically
includes or connects to magnetics that provide electrical isolation and improve signal
integrity and EMI performance.

USB High-Speed

ULPI

ULPI (UTMI+ Low Pin Interface) is a digital interface between the Zynq USB controller and an
external USB PHY. It reduces pin count while supporting USB High-Speed operation.

USB HS PHY

The USB High-Speed PHY performs the analog signaling required by USB 2.0 (480 Mb/s). It
converts digital ULPI data into compliant USB electrical waveforms and ensures signal
integrity and protocol timing.

USB Micro-AB

USB Micro-AB is a dual-role connector that supports both USB host and USB device modes.
It allows the system to either connect to peripherals or act as a peripheral itself, depending
on configuration.

Power

DCDC Converters

DC-DC converters generate the various regulated voltage rails required by the Zynq,
memory, and peripherals from the main input voltage. Switching regulators are used for
efficiency, especially for high-current rails.

+1V0

The 1.0 V rail typically powers the Zynq core and FPGA fabric. It is high-current and noise-
sensitive, requiring careful decoupling and layout to ensure stable operation.

+1V35

The 1.35 V rail is used by DDR3L memory. Voltage stability on this rail directly affects
memory reliability and timing margins.

+3V3

The 3.3 V rail powers I/O banks, PHYs, flash memory, USB components, and general
peripherals. It is less sensitive than core rails but still requires proper regulation and filtering.

DC Barrel
The DC barrel jack is the primary external power input to the board. It connects an external
adapter to the power system and must be protected against reverse polarity, surges, and
EMI.

Related Links
AMD/Xilinx, Intel(pre. Altera), Lattice

[Link]

[Link]

[Link]
CMVzQts9uh3-rP925QF0FmB-l9ljvb3eMBoCbp0QAvD_BwE

[Link] RTZ7 board olmalı ref design bak hele

[Link]

[Link]
Configuration-Memory-Devices
Lesson 3: Schematic Fundamentals
Constraint Manager??? Anladığıma göre design rulesa ek bi sistem belki beginnerlar içindir

Variants örneğin kartı PCIe ya da MIPIya falan uygun çizersin böyle ek özelliklerin olur ama bu
varyantta bu temel özelliklerle devam ediyoruz dersin varyant öğren. Varyant araştır vidyo
izle şematik zamanı gelince. İnternetten oku biraz bi de projeye başlarken varyant nedir diye.
Çünkü yukarda planladığın şekilde değil de daha çok örneğin final kartta halihazırda bulunan
komponentin footprinti farklı kullanmak istersen ikisini de ekliyosun gibi bişi oluyo.

Using Queries

Here are some activities for you to try out, which will help reinforce this lesson's content:

 If you already have a schematic in place, update your schematic with the guidelines
given in this lesson.

 Pick out a random, freely-available commercial schematic on the internet. Do their

schematics follow these guidelines?

 Create your own schematic symbol from scratch, using a part's datasheet and the
guidelines given in this lesson.

Note: These activities are not required for the course certificate!
Getting Familiar with the Altium Design Environment
Configuring the Snap Grid
The next step is to select a suitable grid for placing the components. All the objects are
placed in the PCB design space on the current snap grid.

1. If the Properties panel is not already visible, make it visible by clicking the
button at the bottom right of the design space and selecting Properties from the
menu that opens. The panel displays the properties of the selected object, or if no
object is selected, it displays the properties of the PCB document.

2. In the Grid Manager region of the panel's General tab, select the Global Board Snap
Grid entry and click the button. The Cartesian Grid Editor dialog will
open.

3. In the Cartesian Grid Editor dialog:

 Make sure that the Step X field has the value 1mm. Because the X and Y fields are
linked, there is no need to define the Step Y value.
 Click the color swatch for the Fine grid and select a lighter color using the Choose
Color dialog that opens (e.g., select the color in row 34 on the Basic tab – ).
 For the Coarse grid, select Lines from the drop-down and click the Darker control
to automatically set its color to a shade darker than the current fine grid color.
This will make it easier to distinguish between the fine and coarse grids.
 Make sure that the Multiplier is set to 5x Grid Step. This will make the grid visible
at lower zoom levels.
Setting Up the Environment
The Preferences dialog is a central location where you can set up global system settings
across different functional areas of Altium Designer. To access the Preferences dialog, click
the icon at the top-right of the design space.

Design Variants
1) What “Design Variants” mean

Design Variants let you build multiple product versions from one base PCB project without
cloning the whole design. You keep one schematic + one PCB, then define what changes per
version, and Altium uses that when generating outputs (BOM, Pick&Place, assembly
drawings, etc.).

2) Assembly variant vs Fabrication variant

Assembly Variants (most common)

 Same bare PCB for all variants.

 Only the assembly (which parts get placed) changes.

Fabrication Variants (more rare)

 Changes affect PCB overlay info (e.g., silkscreen/comment differences).

 This can require different overlay screens, meaning you may end up with different
bare boards.

3) Logical vs Physical Components (important concept)

Logical component = what you place on the schematic (conceptual).

Physical component = the compiled “real instance” that goes to the PCB / manufacturing
outputs.

Why this matters:

 In multi-channel designs, one schematic symbol can become many physical

instances.

 Variants need to operate on the physical reality (what gets built), not just the logical
symbol.

In Altium:

 The compiler creates the physical model automatically.

  In the schematic editor, you can switch tabs:

o Editor tab = logical schematic (editable)

o Compiled tabs = physical view (read-only), where variant effects are visible

4) What you can change per component (Types of Variations)

For each component in a variant, you can set:

A) Fitted (default)

 Same as base design.

 In managers, this often appears as an empty cell.

B) Fitted with Varied Parameter(s)

 Component is still used, but you change one or more parameters (commonly Value,
Comment, etc.).

 This does not edit the base schematic; it’s variant-only and mainly affects outputs.

C) Not Fitted (DNF)

 Component still exists in design (footprint can remain on PCB),

 But it’s removed/marked in outputs like BOM, assembly docs, etc.

 Display style (cross/mesh/text) can be configured.

D) Alternate Part

 Replace base component with a different component.

 Must be pin-compatible: same number of pins, same pin locations, same electrical
types (to keep connectivity valid).

 PCB behavior depends on footprint:

o Same footprint name → one footprint on PCB (cleanest)

o Different footprint → both footprints can be transferred; you must decide

placement (side-by-side, nested, stacked)

5) “Swapping component type” (Resistor → Capacitor etc.)

Allowed, but watch the consequences:

 Designator stays the same (because it’s tied to the logical component).

 Pin-compatibility rules still apply (same pin count/location/type).

 You may want a designator convention if this is common (example: R_C).

6) Multi-channel designs + variants

Multi-channel = repeating a circuit block automatically (“stamping out”).

Variants can be applied:

 Across all channels, or

 Inside a specific channel only

And you can still do fitted / not-fitted / param changes / alternate parts.

Example idea:

 Variant A fits 2 memory channels,

 Variant B fits 4 memory channels (by not-fitting a channel in A, or enabling in B).

7) Where you manage variants (two UIs)

Altium offers two ways (depends on settings/features):

Variant Management Dialog (classic)

 Access: Project » Variants or project right-click → Variants

 Upper area: component list

 Lower area: parameters of selected component(s)

 Alternate parts stored in: <ProjectName>.PrjPcbVariants

Variant Manager (newer, document-based UI, “Open Beta”)

 Also accessed via project → Variants

 Has features like filtering, properties panel edits, copy/paste, “Changed Only”

 Also supports Groups (explained below)

8) Variant-level options you should know

When creating/editing a variant, you may see options like:

 Allow variation of fabrication outputs

Needed if you want fabrication-type outputs to change with the variant (e.g., overlay
gerbers).

 Allow variation for paste mask

Useful when DNF components should not have paste openings.

 Do not overwrite schematic symbol

Keeps the base symbol graphics on schematic even if you selected an alternate part
(connectivity still uses the alternate part rules, so pin-compatibility still matters).
  Do not overwrite PCB footprint
Prevents adding the alternate footprint to PCB via ECO
(still shows correct parameters in BOM/ActiveBOM).

9) Groups (Variant Manager feature for many variants)

If you have tons of variants, groups help you avoid repeating work.

Concept:

 You define a Group (from a schematic sheet / sheet symbol / component class)

 Inside that group you define Options (like “WiFi module installed”, “High-current
MOSFET option”, etc.)

 Then, in each variant, you just select which group option applies.

 Changing the group option updates all variants that use it.

Rule of thumb:

 Groups are great for “feature modules” that repeat across variants.

10) Seeing variants in schematic and PCB

Schematic

 Pick a variant in the Projects panel

 Switch to a compiled tab to see what that variant really becomes

 Active Bar shows variant tools (toggle fitted state, choose alternate part, etc.)

PCB

 All footprints are generally visible because the bare board must support all assembly
variants.

 Fitted/not-fitted can be visually clearer in 3D mode (3D body may appear/disappear).

11) Outputs affected by variants

Assembly variants affect things that depend on “what gets placed”:

 BOM (ActiveBOM or reports)

 Pick & Place

 Assembly drawings

 Schematic/PCB prints (depending on settings)

 Test point reports, etc.

Fabrication variants additionally affect:

 Gerber/ODB++ overlay layers (and similar fabrication outputs)

Selecting variant for output

 If you generate from schematic/PCB editor menus → uses the currently selected
variant in Projects panel.

 In Report Manager / OutputJob → you can choose variant per output or per job.

12) One practical workflow (quick)

1. Finish base design (schematic + PCB).

2. Open Variants UI (Dialog or Variant Manager).

3. Add Variant(s) → name them clearly (e.g., BGA, TSOP, Lite, Pro).

4. Apply changes:

o DNF parts, change values, choose alternates

5. Verify in schematic compiled tabs for each variant.

6. Generate outputs with the correct variant selected (ActiveBOM + OutputJob is the
clean setup).

Design Insight
1) What Design Insight is

Design Insight is a visual navigation system in Altium Designer that allows previewing and
navigating project content without opening documents. It provides hover-based previews
for projects, documents, and connectivity, focusing on speed, orientation, and overview
rather than design modification.

2) Why it exists

As projects grow in size and complexity (many schematic sheets, multiple PCB documents,
hierarchical designs), navigating by filenames becomes inefficient. Design Insight enables
faster document discovery, quicker understanding of project structure, and easier tracing of
connectivity.

3) Enabling Design Insight

All Design Insight features are configured under:

Preferences → System → Design Insight
Each feature can be enabled or disabled independently.

4) Project Insight
  Displays visual previews of all documents in a project

 Activated by hovering over the project icon in the Projects panel

 Useful for quickly identifying schematics, PCBs, and documents

 Navigation arrows appear for large projects

 Document order reflects the order files were added to the project

5) Document Insight

 Displays a preview of an individual document when hovering over its icon

 The document must be opened at least once to generate a preview

 Helps avoid opening incorrect or irrelevant sheets

6) Connectivity Insight

 Provides previews of connectivity inside schematics

 Hover actions:

o Component → preview sub-parts

o Sheet symbol → preview child sheets

o Net → preview connections across the project

 Shortcut: Hover over a net + Ctrl + Alt opens a selectable connectivity tree

 Especially valuable for hierarchical and multi-sheet designs

7) Net Name Identification (Logical vs Physical)

When hovering over a wire, Altium shows:

 Logical Net Name (local schematic name)

 Physical Net Name (actual netlist name used on PCB)

This is critical in hierarchical designs where nets are renamed through ports and sheet
entries. The same information is also visible in the Properties panel.

Practical takeaway

 Design Insight = navigation and understanding

 It does not modify design data

 Most useful for large projects, hierarchical schematics, and connectivity debugging
Capturing Your Design Idea as a Schematic
1) What schematic capture is

Schematic capture is the process of creating a logical representation of an electronic circuit

by connecting component symbols. In Altium Designer, the schematic defines electrical
connectivity, feeds simulation and annotation, drives PCB layout, and serves as the source of
truth for the entire design flow.

2) Schematic editor setup

The Schematic editor behavior is configured via:

Preferences → Schematic
Configurable options include cursor style, selection colors, auto-pan behavior, and grid
behavior. These settings affect usability and speed, not design data.

3) Creating and configuring a schematic document

A new schematic is added by right-clicking the project and selecting Add New to Project →
Schematic.
Sheet-level options are configured in the Properties panel when no objects are selected. Key
settings include:

 Grid and snap behavior (multiple grid presets can be cycled using G)

 Page size, margins, zones, and templates

These settings affect readability and consistency, not electrical connectivity.

4) Placing components

Components are placed using the Components panel, which provides:

 Access to Workspace libraries and categories

 Parameter-based searching and filtering

 Detailed component inspection and comparison (Ctrl+Click)

Placing a component inserts its schematic symbol already linked to footprints, simulation
models (if available), and parameters.

5) Component designators

Newly placed components receive temporary designators (e.g., R?, C?).

Unique designators are assigned either manually or through annotation, which is the
recommended approach for consistency.

6) Wiring and connectivity

Electrical connectivity is created using wires, not drawing lines. Wires must start and end on
pin hotspots to form valid electrical connections. The Line object is graphical only and does
not create connectivity.

7) Net labels

Net labels assign names to nets, improve readability, and allow logical connections without
long wires. Nets with the same name on the same sheet are electrically connected even
without a drawn wire between pins.

8) Multi-sheet designs

A design becomes multi-sheet once more than one schematic sheet exists. Two structures
are supported:

Flat design

 All sheets exist on the same logical level

 Nets connect directly across sheets

 Optional top sheet (no wiring allowed)

Hierarchical design

 Tree-structured organization

 Uses sheet symbols, sheet entries, and ports

 Connectivity flows through sheet symbols, not directly between sheets

 Preferred for complex designs

9) Net Identifier Scope

Connectivity across sheets is governed by:

Project Options → Net Identifier Scope
This setting defines how Altium interprets net names across hierarchy levels.

10) Hierarchy automation

Altium provides tools to quickly build hierarchy:

 Create Sheet Symbol From Sheet

 Create Sheet From Sheet Symbol

These commands ensure matching ports and sheet entries, preventing manual errors.

11) Annotation

Annotation assigns unique, ordered designators across selected sheets. It prevents

duplicates, enforces consistency, and is essential before PCB transfer.
12) Design validation

Validation checks for logical, electrical, and drafting errors based on Project Options settings.
It is run via Validate PCB Project, with results reported in the Messages panel. A clean
design reports:
“Compile successful, no error found.”

Practical mental model

 Schematic = logic and intent

 Wires and net labels = electrical truth

 Hierarchy = scalability

 Annotation = identity

 Validation = correctness before layout

Working with Directives on a Schematic

1) What “Design Directives” are

Design Directives are schematic objects used to carry instructions to other parts of Altium.
They are used in two main ways:

 Compilation/validation control (reduce ERC/compile noise during capture)

 PCB-intent definition (pass constraints/classes/diff pairs from schematic → PCB)

A) Compilation-related Directives (noise control)

2) Why you use them during capture

While a design is incomplete, compiling/validating often creates “noise” (errors from

unfinished sections). Directives let you suppress those warnings so you can verify the parts
that are complete.

3) No ERC Directive

 Placed on a node (pins/ports/sheet entries/nets)

 Suppresses reported ERC warnings/errors during project validation

 Best when you need to suppress a small number of specific violations

4) Compile Mask Directive (hide incomplete areas)

Use when you want to exclude an entire unfinished region (including components) from
compiler checking during manual validation.
Key behavior:
  Compiler ignores objects that fall completely inside the mask bounds

 Truly masked objects appear greyed-out

 Helpful when you want a clean validation result from the finished sections

Important detail (conceptual):

 Compile Mask is not about Altium’s continuous “dynamic compilation” after edits

 It matters when you manually run project validation (Validate PCB Project / Validate
Project)

5) Compile Mask states + editing behavior

 Expanded (full frame) = enabled

 Collapsed (triangle) = disabled

 Toggle by clicking the top-left corner icon

 Rotation/mirroring is allowed but doesn’t change the circuitry logic

Placement basics (all equivalent):

 Place » Directives » Compile Mask

 Active Bar → Compile Mask

 Right-click → Place → Directives → Compile Mask

Edit basics:

 Drag handles to resize/reposition

 Drag outline to move; Space/Shift+Space rotate; X/Y mirror while dragging

 Collapsed masks can be moved but not resized

 Locked objects may require unlocking (and “Protect Locked Objects” can block edits)

B) PCB-related Directives (drive PCB rules from schematic)

6) Why PCB-related directives exist

Altium supports defining PCB requirements before layout so the schematic stays the master
record. Some objects (components, ports, sheet symbols, etc.) can hold parameters directly,
but wires/buses/harnesses cannot, so directives are used to attach rule/constraint
metadata to nets.

7) What you can define via directives (and transfer to PCB)

Typical transferred intent includes:

 PCB layout constraints (rules)

 Differential pairs

 Net classes

This is especially valuable for multi-person or distributed teams because constraints are
embedded in the design, not communicated externally.

8) Parameter Set directive (the core container)

A Parameter Set is a directive that acts as a container for parameters targeting the net
object it is attached to.

 Place it on a wire/bus/signal harness to apply constraints to that net(s)

 It can be empty initially; parameters/classes/rules can be added later

 “Pre-defined” directives (like Differential Pair) are essentially parameter sets that
already include a specific parameter

Scope principle:

 A Parameter Set applies only to the net(s) it is connected to

 Multiple parameters can be stacked into one directive for schematic cleanliness

9) Differential Pair directive (pre-defined parameter set)

This is a pre-defined directive used to identify two nets as a differential pair. Functionally it is
a Parameter Set that already includes the parameter(s) Altium uses to recognize a diff pair
definition.

10) Moving from Directives to Constraint Manager (modern flow)

Altium now supports a unified approach using the Constraint Manager.

 If the project uses Constraint Manager, directives-defined net classes/diff pairs/rules

are not automatically detected/transferred during Update PCB

 Instead, Constraint Manager definitions are what transfer

 However, you can Import from Directives inside Constraint Manager

(Physical/Electrical view right-click)

One-way transition behavior:

 After importing and saving, imported directives become blue and read-only in the
schematic
  This indicates the project has transitioned from directive-driven rules to Constraint
Manager ownership

Quick check:

 If you see Constraint Manager in the Design menu → new approach

 If you only see PCB Design Rules in PCB editor menus → older rules approach

C) Net Classes, Blankets, and scaling intent

11) Net Class via directives (schematic-driven grouping)

Net classes can be created in schematics by defining a net class (via a Parameter Set / Net
Class directive concept) and then transferring to PCB during synchronization.
Key idea: schematic is clearer for logical grouping, so driving from schematic often makes
more sense.

Project options needed for propagation:

 Enable Generate Net Classes (Class Generation tab, User-Defined Classes region)

 Comparator tab: set Extra Net Classes checking mode to Find Differences

Rule scoping note:

 If a net class is defined, rules generated from that directive can scope to Net Class
rather than individual nets

12) Blanket directive (expand scope beyond one net)

Parameter Sets normally target only the net they touch. A Blanket lets you apply a directive
across many nets/components.

 Blanket is a rectangular or polygonal grouping region

 A directive placed on the Blanket perimeter applies to all nets/components

registered by that Blanket

How a net gets “captured” by a Blanket (important practical detail):

A net is included if it is under the Blanket by being:

 fully within the Blanket area, or

 having at least one connected end/vertex under the Blanket, or

 having a net identifier (net label etc.) whose hotspot falls within the Blanket
If you don’t see expected nets transferring, adjust Blanket area.

Verification trick:
  Use Net Colors to highlight what nets the Blanket is actually targeting

Blanket controls:

 Can be collapsed/disabled via the triangle toggle or “Collapsed and Disabled” option

 Useful keywords for queries: IsBlanket, Collapsed

D) Indirect (parameter-based) directives (rules on objects that support parameters)

13) What “parameter-based directives” mean

If an object can store parameters directly, you can define PCB constraints by adding rule
parameters to that object, instead of using a Parameter Set directive. When synchronized,
those rule-parameters become PCB design rules, with scope determined by the object type.

14) Parameter-to-rule scope mapping (concept)

Adding a rule parameter to different schematic objects results in different PCB scope targets,
such as:

 Pin → Pad scope

 Port → Net scope

 Component → Component scope

 Sheet symbol variants (local/device/managed) → Component Class scope

 Sheet/document options → All Objects scope

Also: each rule parameter is assigned a unique ID, and the PCB-side rule created inherits
that same ID, allowing edits on either side to push through on synchronization.

15) Component Classes from schematic

Component classes can be defined by adding a ClassName parameter to components.

To propagate them:

 Enable Generate Component Classes (Class Generation tab, User-Defined Classes)

 Comparator tab: set Extra Component Classes Mode to Find Differences

PCB note: a component can belong to multiple classes; on schematic the class names
can be comma-separated.

E) Output/printing behavior

16) Printing directives

By default, directives print on schematics. This can be controlled via:

 Schematic Print Properties (direct printing / OutputJob output)

 Smart PDF Wizard → Additional PDF Settings → Schematics include settings

No ERC symbol styles can be selectively printed/excluded depending on configuration

Working with Placed Components

1) Working between the schematic component and the PCB component (why this exists)

Altium gives you “bridge” tools so you can identify/select the same component in both
editors without manually hunting for it. The core tools are:

 Cross Probe (jump + zoom/center)

 Cross Select Mode (select only, no zoom)

 Select PCB Components from schematic (select a set on SCH, then place/reposition
them on PCB in the same order)

A) Cross Probing / Cross Selection / Reposition workflow

2) Cross Probe (jump to the same part)

What it does:

 Click a component in one editor → it is centered + zoomed in the other editor.

How to use:

 Tools menu → Cross Probe

 Click the component in Schematic → it centers/zooms to it in PCB (and vice versa)

Important behaviors:

 Zoom level is controlled by Preferences → System → Navigation

 Default behavior stays in your current editor so you can keep cross-probing

 Hold Ctrl while cross probing to switch to the other editor as you jump

3) Cross Select Mode (select the same part in the other editor)

What it does:

 Selecting a component in one editor will select the same component in the other
editor

 No zoom/centering
How to use:

 Tools → Cross Select Mode (toggle On/Off)

 Select multiple with Shift + click

4) Selecting PCB Components from the schematic (ordered selection → ordered

placement)

Use case:

 You want to select parts in a specific order on the schematic and then
place/reposition those same parts on the PCB in the same order.

Steps:

1. On schematic: click components one by one (use Shift to multi-select)

2. Switch to PCB editor

3. Press I, C to run Reposition Selected Components

(also available via right-click menu after pressing I)

B) Part Properties (Schematic component properties you’ll see when selecting a

component)

5) General tab (identity + component behavior)

Key fields:

 Reuse Block: shows parent reuse block name if part of one; link opens its properties

 Designator: editable; eye toggles visibility; lock toggles editing

 Comment: editable; eye/lock controls; can display value of a parameter

(system/user)

 Part x of Parts (multipart components): shows current part and total; lock/unlock
then pick part

o Note: you can’t select a sub-part if it has no primitives in the current alternate
display mode

 Description: part description

 Type (big deal): determines sync + BOM behavior

o Standard: electrical, always synchronized SCH↔PCB, in BOM

o Mechanical: no electrical, not synchronized (place manually in both), in BOM

 o Graphical: no electrical, not synchronized, not in BOM (e.g., logo)

o Net Tie (In BOM): shorts multiple nets; sync required; in BOM; copper
shorting not checked like Standard

o Net Tie (No BOM): same as above but excluded from BOM

o Standard (No BOM): normal electrical but excluded from BOM (e.g.,
testpoints)

o Jumper: wire-link style component

 Footprint + pins synchronize, but net assignments do not

 Included in BOM

 Pads must share same non-zero JumperID

 Doesn’t need wiring on schematic (only include if needed for BOM);

otherwise can be PCB-only with manual pad net assignment

 Design Item ID (source identity): shows the component identifier depending on

where it comes from

o Workspace component name, or DbLib key field, or parameter-defined ID for

file-based libs

o Replace/inspect via the Replace Component dialog (details, models, part

choices, suppliers, compare, etc.)

 Source: shows library source; lets you pick another library

 Revision state / revision status (Workspace-managed): lifecycle state + whether it’s

up-to-date

o Can update to latest revision (with prompts for multipart selections)

 Component issues (Workspace health): icons indicate errors/fatal issues and count

 Supply chain data (Workspace): median price, stock totals, lifecycle bar
(new/NRND/EOL style indicator)

o Note: lifecycle indicators are helpful but may lag; verify with manufacturer if
critical

6) Parameters (Name/Value table + visibility/locking)

What you can do:

 View/edit Name/Value parameters on the component

  Lock/unlock parameters to prevent updates

 Control parameter visibility (eye icons)

Dynamic parameters support (Workspace/DB/PLM sync concept):

 Dynamic parameters can update from source systems without making a new
component revision

 Visibility/performance is controlled by advanced settings:

o [Link] (enables Show More/Show Less

behavior)

o [Link] (forces loading all dynamic

parameters)

Favorites + performance:

 You can mark parameters as Favorites and only show those by default

 Show More / Show Less toggles visibility (if enabled)

 Showing everything can reduce performance (Altium warns about this)

Per-parameter formatting/placement options:

 Font control

 “Other” options like:

o show parameter name

o allow sync with database

o X/Y position, rotation, autoposition behavior

Parameter actions:

 Add/edit/delete parameters (including things like model/footprint/rule parameters)

7) Graphical (how the symbol is rendered)

Options:

 Mode: choose an alternate display mode if available (else grayed out)

o Note: you can’t pick a mode that has no primitives for the selected sub-part

 Mirrored: mirror the symbol

  Local Colors: override library colors with local Fill/Line/Pin colors (or disable to use
library defaults)

8) Part Choices (sourcing links)

 Shows part choices and supplier links tied to the component (if any)

 If none exist, you’ll get access to the supplier links editor to add them

9) Pins tab (pin list, naming, visibility, editing lock)

What you get:

 Pins grid listing Pin identifiers + Names

 Eye icon: show/hide pins

 Lock icon: lock/unlock pins

Multi-functional pins:

 If a pin has defined functions, you can choose which function name displays from a
dropdown

 You can also type a custom pin name; if it doesn’t match library-defined
naming/functions it’s treated as temporary and highlighted

 A popup lets you select which function names are shown on the symbol

Pin name display:

 Show Full / Show Short toggles extended vs short pin naming

Pin editing controls:

 There’s a pin-edit lock (when enabled, pins can’t be edited in schematic editor; they
can be edited in schematic library editor)

 Show hidden pins option exists (can reveal pins whose Show property is disabled—
library editor may require View » Show Hidden Pins too)

 Add pin / delete pin controls

 Component Pin Editor dialog provides a consolidated way to view/edit pins (library
editor, or selected component/part in schematic)

Updating Components from Database and File-based Libraries

1) Why this workflow exists
After you’ve already placed and wired parts (and maybe transferred to PCB), you often need
to apply changes made at the component source back onto the placed instances:

 new/edited parameters

 changed model links (footprint, sim models, etc.)

 changed graphics (symbol/footprint visuals)

Rule of thumb: edit at the source → then push updates into the design.

A) Where the “source of truth” is (depends on how the part was placed)

2) Integrated Library (*.IntLib)

 Source libs are extracted

 Edit symbol/footprint/params in the source

 Recompile the IntLib to generate the revised library

 Then update the design from libraries

3) Database Library (*.DBLib / .SVNDBLib) or DBLink (.DBLink)

Two kinds of data can change:

 Parameters + symbol/model references: change in the external database record

 Graphical symbol/footprint: change in the referenced source libraries

Then update the design using the update tools.

4) File-based libraries (*.SchLib / *.PcbLib)

 Edit the component/footprint in that library

 Then update placed instances from libraries

B) Updating parameters from an external database (DB-driven)

5) Requirement: the placed components must be linked to DB records

Linking is done via one of:

 DBLink (*.DBLink): links existing placed parts (or library parts) to a database

 DBLib (*.DBLib): place parts directly from a database

 SVNDBLib (*.SVNDBLib): DBLib concept but symbol/model libs are under VCS

6) Command (Schematic editor)

  Tools → Update Parameters From Database

 Opens Update Parameters From Database dialog

What you choose there:

 Schematic Sheets: which sheets participate (single free doc or all project sheets)

 Component Types list updates based on selected sheets:

o Physical component name

o Logical symbol

o Source library

o Count (instances)

Optional:

 Create Log: generates a *.log under Generated

7) Review step: Select Parameter Changes dialog

If database values differ, Altium shows a grid of proposed parameter updates.

What you can do:

 Update/Reject selected cells

 Update/Reject all

 Show all parts

 Add/remove/edit/rename parameters (columns)

 Generate reports / save table

 Cross Probe from a row to the object in the schematic

Important notes:

 Only mapped DB fields/parameters appear (mapping is in the link file’s Field

Mappings)

 Parameters can be blocked from updating via:

o component parameter lock / “Allow Synchronization With Database”

o link-file field mapping options (Update Values / Add to Design / Remove from
Design)

8) Apply: ECO

To actually apply changes:

  Accept Changes (Create ECO) → validate/execute in the Engineering Change Order
dialog

 You can disable individual ECO entries if you change your mind

9) “Dual synchronization” pitfall (easy to mess up)

If you have a mix of:

 parts linked via DBLink, and

 parts placed via DBLib/SVNDBLib

…and they point to different databases, an update can accidentally match the wrong
record (depending on match field usage and search order). In mixed setups, be extra
cautious reviewing the matching rows before ECO.

C) Updating schematic components from libraries (file-based + IntLib + DBLib/SVNDBLib)

10) Main commands

From a schematic document:

 Tools → Update From Libraries (updates all parts in scope)

 Tools → Update Selected From Libraries (updates only selected parts)

This updates:

 parameters

 symbol graphics

 model links
For DBLib/SVNDBLib, remember: those files aren’t “true libraries”; they provide
connection + mapping, and the real data comes from:

 external DB records (parameters, references)

 referenced symbol/model libraries (graphics)

11) Update From Library dialog — Page 1 (Scope + default actions)

Scope

 Pick schematic sheets (single doc or whole project)

 Component Types list shows:

o physical component, logical symbol, source library, instance count

Filter

 Show:

o All Components (default)

o Standard Components (from SchLib/IntLib)

o Database Components (from DBLib/SVNDBLib)

Selection-based mode

 If you preselect parts on the schematic and enable Selected Parts Only, only those
appear.

Variant/Workspace options (if available in your setup):

 Include Variants

 Update to Latest Revision (Workspace components)

Default action level

 Fully replace symbols on sheet with those from library (most aggressive)

o can also choose:

 update designator lock field

 update part ID lock field

 preserve parameter locations

 preserve parameter visibility

 Or choose Replace selected attributes for finer control:

o graphical attributes

o parameters

o models

Persistence:

 Page 1 settings are stored in the project file (they persist)

12) Advanced control: Library Update Settings dialog

(Opened via Advanced)

Gives global rules for what happens to parameters/models:

Parameter settings

 Library params not in sheet → Add / Do not add / Add if not blank
  Sheet params not in library → Remove / Do not remove / Remove if not blank

 Parameters to update → tick which parameters are allowed to update

Model settings

 Add models found in library but not in sheet

 Remove models found in sheet but not in library

 Update which models are “current”

 Models to update → enable which model types/entries get updated

D) Fine-tuning by component instance (Update From Library dialog — Page 2)

13) Instance grid (per-part control)

This page lists every affected instance and splits into:

 Schematic Parts: designator/comment/physical/logical

 Library Components: what Altium thinks is the matching library part (or <Not
Found>)

 Actions per instance:

o Full Replace

o Graphical

o Parameters (with Parameter Changes… button)

o Models

Key behaviors:

 The initially chosen library component comes from the placed component’s Library
Link info.

 You can override and choose an alternate library component:

o edit Physical Component field, or

o use Choose Component (Replace Component dialog)

 You can revert back with Return Selected to Default

Database component search limitation:

 It can only search across currently loaded DBLib/SVNDBLib files (available file-based
libraries), not arbitrary paths.
E) Parameter Changes dialog differences (important nuance)

14) From “Update Parameters From Database”

 shows only mapped DB parameters for linked components (DB is the reference)

15) From “Update From Libraries” → “Parameter Changes…”

 shows mapped DB parameters plus all parameters found in the placed instances
involved
(broader listing than the pure DB update tool)

The proposed changes are driven by:

 Library Update Settings rules (SchLib/IntLib source), or

 DBLink/DBLib/SVNDBLib mapping rules (DB source)

F) Applying updates directly from the Schematic Library Editor (danger zone)

16) Direct library-to-schematics update

From SCH Library Editor:

 Tools → Update Schematics (or right-click in SCH Library panel)

Behavior:

 Updates all matching placed instances in all open schematic documents, regardless
of project

 Full replacement based on matching Physical Component field

Critical warning:

 If the instance originally came from IntLib or DBLib/SVNDBLib, this method can
replace the original link with a link to the source library you updated from.

 For database parts, this can sever the DB record link. Safer default is usually Update
From Libraries from the schematic.

G) Verifying the update worked (quick checks)

17) Parameters

 Tools → Parameter Manager (Parameter Table Editor), or

 Select component → check Properties panel → Parameters

18) Model links

 Select component → check Models region in Properties

19) Graphics

 Compare placed symbol/footprint vs library version (Components panel helps for

side-by-side)

Creating Circuit Connectivity

1. What “Connectivity” Means in Altium

Connectivity defines which pins belong to the same electrical net.

This is expressed logically in schematics and physically on the PCB.

Connectivity is not final until compilation. Altium continuously compiles the design into a
Unified Data Model (UDM).

2. Two Ways to Create Connectivity

A. Physical Connectivity

 Created by wires directly between pins.

 Easy to follow visually.

 Can clutter large designs.

B. Logical Connectivity

 Created using net identifiers (names).

 Reduces wiring density.

 Requires correct structure and naming discipline.

You can mix both methods freely.

3. Objects That Create Connectivity (Net Identifiers)

Object Purpose

Wire Physical electrical connection

Net Label Names a net (local by default)

Port Sheet-to-sheet connectivity (flat or hierarchical)

Sheet Entry Parent ↔ child connection in hierarchy

Object Purpose

Power Port Global power/ground nets by name

Off-Sheet Connector Legacy horizontal connectivity (flat only)

Bus / Bus Entry Groups multiple sequential nets

Signal Harness Groups arbitrary nets/buses

Pin Endpoint of connectivity

Critical rule:

Different net identifier types do NOT auto-connect just because names match.
Example: AGND Net Label ≠ AGND Power Port unless wired.

4. Net Identifier Scope (MOST IMPORTANT SETTING)

Configured in Project Options → Options → Net Identifier Scope

Modes

 Global
Same names connect everywhere (high risk of accidental merges).

 Flat
Sheet-to-sheet via Ports / Off-Sheet Connectors.

 Hierarchical
Sheet Entry ↔ Port only (parent ↔ child).

 Strict Hierarchical
Same as Hierarchical, but all power nets become local.

 Automatic (recommended)
Altium decides:

1. Sheet Entries exist → Hierarchical

2. Ports exist → Flat

3. Neither → Global

5. Flat vs Hierarchical Design

Flat Design

 All sheets are peers.

 Connectivity is horizontal.

 Use:

o Net Labels inside sheets

o Ports between sheets (recommended)

 Off-Sheet Connectors are supported but limited.

 Top sheet is optional.

Hierarchical Design

 One top sheet only.

 Connectivity is vertical:

o Sheet Entry (parent) ↔ Port (child)

 Easier signal tracing.

 Required for multi-channel designs.

 Sheet Entries and Ports should be synchronized.

6. Net Naming Rules

How nets get names

 Unnamed wire → system name (e.g. NetR7_1)

 Net Label → always names the net

 Ports / Sheet Entries / Power Ports → name nets only if enabled in Project Options

Naming precedence (if multiple allowed)

 If Power Port Names Take Priority = OFF

Net Labels > Power Ports > Ports > Pins

 If ON
Power Ports > Net Labels > Ports > Pins

Recommended setup

 Enable:

o Allow Ports to Name Nets

 o Higher Level Names Take Priority

7. Multiple Net Names (Advanced but Legal)

 Same net may have different names on different sheets.

 Used to:

o Rename signals at hierarchy boundaries

o Reuse child sheets

 Controlled via:

o Error Reporting settings

o No ERC markers

⚠ One PCB net can have only one final name.

8. Duplicate Net Names (Common Failure)

If two different nets share the same name on different sheets → fatal error.

Fix

 Enable Append Sheet Numbers to Local Nets

 Ensure every sheet has a unique SheetNumber

9. Power Nets

Default

 Power Ports with same name are global.

Localizing power nets

 Strict Hierarchical → all power nets local

 Or selectively:

o Wire Power Port → Port → Sheet Entry

Used for:

 Isolated rails

 Per-channel supplies
  Controlled ground connections

10. Intentionally Shorting Nets (Net Ties)

Used when two nets must connect physically but not logically (e.g. AGND ↔ DGND).

 Implemented with Net Tie component

 Nets remain distinct in schematic and PCB

 Short exists only in footprint copper

 No DRC error is generated

11. Compilation Model (Why Things Update Automatically)

 Altium uses Dynamic Compilation

 Builds a Unified Data Model (UDM) continuously

 No manual compile needed

 Used by:

o PCB update (ECO)

o Cross-probing

o Navigator

o ActiveBOM

o Rule checking

12. Inspecting and Tracing Connectivity

Tools

 Navigator Panel – full compiled view

 Alt+Click on a net – global highlight

 Connectivity Insight – hover / tree view

 Cross-Probe / Cross-Select – schematic ↔ PCB

13. Practical Best-Practice Summary

For serious projects

 Use Hierarchical

 Net Identifier Scope: Automatic

 Net Labels inside sheets

 Sheet Entry ↔ Port between sheets

 Enable:

o Allow Ports to Name Nets

o Higher Level Names Take Priority

o Append Sheet Numbers to Local Nets

Avoid

 Mixing Global + Flat + Hierarchical casually

 Relying on name matching between different net identifier types

 Hidden power pins

Bundling Signals
1) When to use Bus vs Signal Harness

Use a Bus when

 Your nets are a numbered family: DATA0..DATA15, ADDR0..ADDR31, etc.

 You want the schematic to show “this is a vector” and keep wiring clean.

Buses are basically syntax sugar for sequential nets. They’re great for address/data lines
and LEDs.

Use a Signal Harness when

 You want to bundle any mix of:

o unrelated nets (EN, RD, FAULT)

o buses (DATA[7..0])

o or even other harnesses (nested harnesses)

 You care about readability across sheets and “logical cable” style connectivity (JTAG,
SWD, SPI bundle, power-sense bundle, etc.)

Harness = arbitrary named container. Much more flexible than buses.

2) Bus: the minimum required pieces (or it won’t behave like you expect)

To form a “real” bus connectivity conceptually:

1. Net label on every individual wire: DATA0, DATA1, …

2. Net label on the bus line: DATA[0..7] (or [7..0])

3. If it leaves the sheet: a Port named the same as the bus.

If any of these are missing, you often end up with a pretty drawing but not the connectivity
you intended.

Bus entries

Use Bus Entry when you need to “rip nets out” from both sides of the bus at the same
physical point without shorting two ripped nets together.
If you don’t need that, a normal wire connection is fine.

Common bus gotchas

 Mixed ordering ([7..0] in one place, [0..7] elsewhere) can trigger Mismatched bus
label ordering warnings.

 Avoid bus base names that contain digits like D2[0..7] → Altium may expand it like
D20..D27, which can collide with other names.

PCB reality

A bus itself does not exist on the PCB. What you can do is auto-generate net classes from
buses (and from bus “sections”) via Project Options → Class Generation.

3) Signal Harness: what it is (and what it is NOT)

A signal harness is two things:

1. The bus-like line you draw (Signal Harness primitive)

2. The connectivity system defined by:

o Harness Connector

o Harness Entries

o Harness Type

o Ports / Sheet Entries carrying that harness type between sheets

The mental model

  Harness Type = the name of the container (e.g., JTAG, ROCKET_IO_LINES,
SENSOR_BUNDLE)

 Harness Entries = the named slots inside that container (e.g., TCK, TMS, TDI, TDO,
TRST)

 The actual net names still come from normal net labels, unless you override naming
(next section).

4) Naming nets inside a harness (super important)

Default behavior (most common)

Harness elements help the compiler understand “these nets belong to this bundle across
sheets”, but they don’t rename nets. Your nets keep their normal net names.

Harness-level naming override

If you place a Net Label on the Signal Harness line, Altium can name nets like:

[Link]

Example:

 Harness net label: HARD

 Harness entry: TCK

 Net becomes: [Link]

This is powerful for multi-instance reuse (e.g., SOFT vs HARD JTAG bundles) because you can
reuse the same harness definition but get distinct final net names per instance.

Also: net classes can be auto-generated for named harnesses (again in Class Generation
options).

5) Connector-free harnesses (clean schematics, but has a rule)

You can use harness naming (Net Label on harness line) without drawing a harness
connector + entries on that sheet, but:

 The harness definition must exist somewhere, and

 It must be protected from auto-update either by:

o having at least one real Harness Connector of that type somewhere in the
design, or

o locking the definition in the .Harness definition file using LOCKED.

If you lock it and then later add entries graphically that don’t match, you’ll get Conflicting
Harness Definition violations.

6) Practical best-practice patterns

“Classic” patterns

 Bus: DDR address/data, LED arrays, GPIO banks

 Harness: JTAG/SWD, SPI bundle, I²C bundle (SCL/SDA/INT/ALERT), power-monitor

bundle (VIN_SENSE, I_SENSE, PG, FAULT), SERDES lane bundle (even if each lane is a
diff pair, you can harness the lane groups)

Sheet-to-sheet sanity

 Prefer Harness when crossing sheets with multiple unrelated signals: it makes the
hierarchy much easier to read and reduces port clutter.

 Prefer Bus when the reader expects vector semantics.

Defining Differential Pairs

1. What “defines a differential pair” in the schematic

A differential pair is created in the design transfer when both nets are:

1. Named as a matched pair using the same base name with _P and _N suffixes (or
your custom suffixes), and

2. Each net has a Differential Pair directive applied (one directive on the P net, one on
the N net).

Result: one PCB differential pair object per P/N directive set.

2. Naming rules and custom suffixes

Default naming convention

 USB_D_P and USB_D_N → base name: USB_D

 V_RX1_P and V_RX1_N → base name: V_RX1

Custom suffix support

If your organization uses different suffixes (e.g., +/-, P/N, H/L), set them in:

 Project Options → Options tab → Diff Pairs section

3. How to place the directive (single pair method)

Placement

 Place → Directives → Differential Pair

This places a Parameter Set object preconfigured as a differential pair directive:

 Label = DIFFPAIR

Critical detail: how it attaches

To apply it to a net, the Parameter Set must touch the target net object (wire/net label
connection area). If it doesn’t touch, it won’t be compiled into the intended output.

4. What you get on the PCB side

 Each P/N directive pair becomes a Differential Pair in PCB.

 It is automatically added to the default differential pair class:

o <All Differential Pairs>

 Differential pair objects can be renamed on the PCB side only.

5. Blanket method (bulk definition for many pairs)

Use this when you have many lanes (SERDES, DDR, PCIe, etc.).

How it works

 Place a Blanket to cover the area containing the target nets.

 Place one Differential Pair directive touching the blanket edge.

 Altium detects nets whose net label hotspot lies within the blanket boundary.

What else you can assign in the same directive

Inside the same directive (Parameter Set), you can also specify:

 A Net Class for the member nets

 A Differential Pair Class for the resulting diff pairs

 A Differential Pair Routing rule (auto-created on PCB transfer)

This is the cleanest way to produce consistent classes/rules across many lanes.
6. Rule/class auto-creation limitations (important)

When using the blanket approach:

 Automatic PCB rule creation does not automatically scope a Differential Pair Routing
rule to the Differential Pair Class you create.

 It does support scoping to a Net Class if you include one.

Practical consequence:

 If you include a Net Class in the directive → Altium creates one routing rule targeting
that Net Class (good).

 If you do not include a Net Class → Altium may create individual routing rules per
pair (usually unwanted clutter).

Best practice:

 Always include a Net Class in the directive when using blankets, then (if desired) edit
the rule in PCB to target the Differential Pair Class.

7. Constraint Manager interaction (modern workflow note)

If you are using Constraint Manager:

 Differential pairs / classes / rules defined via schematic directives are not
automatically detected and transferred during Update PCB.

 Only constraints defined inside Constraint Manager transfer automatically.

To bring directive-defined constraints into Constraint Manager:

 Use Constraint Manager → (Physical or Electrical view) → right-click → Import from

Directives (when accessed from schematics).

8. Recommended workflow (fast and clean)

 Set diff pair suffixes in Project Options first (if not default).

 For small count: place directives on each _P and _N net.

 For large count: use Blanket + one directive, and include:

o Net Class (mandatory for clean rule scoping)

o Diff Pair Class (optional but recommended)

o Routing rule (optional; often defined later in PCB/Constraint Manager)

  If using Constraint Manager: Import from Directives or define everything directly in
Constraint Manager to avoid missing transfers.

Multi-Sheet & Hierarchical Designs

1. Why multi-sheet schematics exist (1 sentence)

You split schematics into multiple sheets to improve readability, teamwork, reuse, and
printing, not because the circuit is electrically different.

2. The ONLY two structural choices you must make

A) Flat design

 All sheets are on the same level

 Connectivity is horizontal

 Ports with the same name connect everywhere

B) Hierarchical design

 One top sheet

 Other sheets are children

 Connectivity is vertical only (parent ↔ child)

These are mutually exclusive concepts controlled by Net Identifier Scope.

3. Net Identifier Scope (this decides EVERYTHING)

Set in: Project → Project Options

Scope What connects

Flat / Global All ports with same name connect everywhere

Hierarchical Ports connect only to matching Sheet Entries

Strict Hierarchical Same as hierarchical, but stricter (no ambiguity)

Rule of thumb:
👉 If you use Sheet Symbols, use Hierarchical (or Strict).

4. Core objects (only 4 matter)

1️⃣ Sheet Symbol (parent sheet)

  Represents a child schematic

 Has:

o Designator (name)

o File Name → links to the child .SchDoc

o Sheet Entries (connection points)

2️⃣ Sheet Entry (on Sheet Symbol)

 Lives inside a Sheet Symbol

 Represents a signal going down to the child sheet

 Must match a Port on the child sheet

3️⃣ Port (on child sheet)

 Signal leaving the child sheet

 Connects upward to a Sheet Entry (hierarchical)

 Or connects everywhere (flat)

4️⃣ Wire

 Only exists inside one sheet

 Never crosses sheets

5. How connectivity REALLY works (important)

Hierarchical design signal path:

Child Sheet:

Wire → Port

Parent Sheet:

Sheet Entry → Wire → Sheet Entry

Other Child Sheet:

Port → Wire

🔴 Ports NEVER connect directly to other ports in hierarchical mode.

6. Flat vs Hierarchical in one table

Feature Flat Hierarchical

Top sheet required ❌ ✅ (exactly one)

Port-to-port connection ✅ ❌

Sheet Entry required ❌ ✅

Signal traceability Medium Excellent

Design reuse Poor Excellent

Large projects ❌ ✅

7. Creating hierarchy (2 workflows only)

🔹 Top-down (recommended for clean design)

1. Place Sheet Symbol

2. Add Sheet Entries

3. Create Sheet From Sheet Symbol

4. Child sheet auto-gets Ports

🔹 Bottom-up (when refactoring)

1. Draw child sheet with Ports

2. Create Sheet Symbol From Sheet

3. Sheet Entries auto-created

8. Synchronization (why this exists)

Whenever you:

 Rename ports

 Add/remove signals

 Move circuitry between sheets

👉 Run Synchronize Sheet Entries and Ports

This keeps:

 Names

 I/O direction

 Harness type
consistent between parent and child

9. Multi-channel designs (advanced but important)

Using:

Repeat(SHEET, 1, 4)

 One schematic sheet

 Instantiated multiple times logically

 Used for:

o Audio channels

o Power stages

o Sensor arrays

👉 Sheet is not duplicated, compiler instantiates it.

10. Critical rules (memorize these)

 ❌ A project can have only one top sheet (hierarchical)

 ❌ A sheet symbol cannot reference itself

 ❌ No circular hierarchy

 ✅ Sheet Entry ↔ Port names must match

 ✅ Use Synchronize instead of manual fixing

11. When YOU should use hierarchical (practical advice)

Use hierarchical design when:

 Board > ~2 schematic sheets

 You care about long-term maintainability

  You plan variants, reuse, or multi-channel blocks

 Someone else might read your design

Design Refactoring in Altium

1. What “refactoring” means (1 sentence)

Refactoring = restructuring a schematic without breaking schematic↔PCB linkage (UIDs

stay intact).

This is the only reason refactoring exists.

2. Why refactoring matters (critical)

 Every schematic component has a Unique ID (UID)

 UID links schematic ↔ PCB

 Cut / Copy / Paste breaks UIDs

 Refactoring tools preserve UIDs

👉 If PCB already exists, never reorganize with copy–paste.

3. Refactoring tools (there are only 5)

1️⃣ Convert Part → Sheet Symbol

Use when:
A single component should become a sub-circuit

What happens:

 Component → Sheet Symbol

 Pins → Sheet Entries

 Pin names & I/O types preserved

 Connectivity preserved

Typical use:

 Replacing an IC with a discrete equivalent

 Turning “black box” IC into real circuitry

2️⃣ Push Part → New Sub-Sheet (fastest)

Use when:
You want to immediately expand a part into its own sheet

What happens automatically:

1. Part copied

2. Original becomes Sheet Symbol

3. New sheet created

4. Copied part placed on new sheet

5. Ports + wiring auto-created

Typical use:

 Power IC → power sub-sheet

 USB IC → USB block

👉 This is the most practical refactoring command.

3️⃣ Convert Part → Ports

Use when:
A whole schematic represents an external module or subsystem

What happens:

 Component → set of Ports

 Pins → Ports

 Used to “plug” a sub-sheet into a higher level

Typical use:

 Daughterboard

 External PSU

 Satellite module

Then:

 Create Sheet Symbol from that sheet

 Insert it into parent hierarchy

4️⃣ Convert Schematic Sheet ↔ Device Sheet

This is reuse abstraction.

a) Schematic → Device Sheet

Use when:
You want reusable functional blocks

Examples:

 USB interface

 Buck regulator

 CAN transceiver

Benefits:

 Versioning

 Lifecycle management

 Team reuse

 No copy–paste errors

Professional teams always end up here.

b) Device Sheet → Local Schematic

Use when:
You need to customize a reusable block

What happens:

 Device Sheet copied locally

 Original remains untouched

 Safe customization

5️⃣ Move Selected Sub-Circuit → Another Sheet

Use when:
Sheet is getting crowded or logically wrong

What happens:

 Selected circuitry moved intact

 UIDs preserved

 Hierarchy updated if needed

⚠️After moving:

 You may need Synchronize Sheet Entries & Ports

4. Golden rule (memorize this)

If PCB exists → use refactoring tools only

Cut / Copy / Paste = UID reset = broken PCB link

5. Typical real-world workflows

🔹 Turning a flat schematic into a clean hierarchy

1. Select power circuitry

2. Push Part To Sheet or Move Sub-Circuit

3. Create hierarchy gradually

4. Synchronize ports

🔹 Replacing a single IC with real circuitry

1. Convert Part → Sheet Symbol

2. Create child sheet

3. Implement replacement circuit

4. PCB stays valid

🔹 Creating reusable company blocks

1. Clean schematic

2. Convert to Device Sheet

3. Store in Workspace

4. Reuse forever

6. Why Altium refactoring is special

Unlike manual editing:

  ✔ Preserves UIDs

 ✔ Preserves PCB placement

 ✔ Preserves design intent

 ✔ Supports hierarchy evolution

This is not cosmetic — it’s structural integrity.

Multi-Channel Design
You draw one channel once, then Altium instantiates it N times in the compiled model, and
pushes the expanded physical components/nets to PCB. Your source schematic stays
“logical”; the “physical” channels exist as compiled views/tabs.

1) Two ways to create channels (pick one)

A) Multiple Sheet Symbols → same child sheet

You place CH1, CH2, CH3… each as its own Sheet Symbol, all pointing to the same .SchDoc.

Pros

 You can wire different signals to each channel explicitly.

 Best when each channel has some unique wiring or per-channel parameterization.

Cons

 More manual work on the top sheet.

B) Repeat keyword on ONE Sheet Symbol (fast & clean)

One Sheet Symbol, repeated automatically.

Syntax
Repeat(<ChannelIdentifier>, <FirstIndex>, <LastIndex>)

Pros

 Fastest way to create many identical channels.

 Clean top sheet (stacked sheet symbol visual).

Cons (important)

 You cannot easily feed a totally unique one-off net into only one channel.

 Some advanced connectivity patterns are restricted (and harness passing is limited in
Repeat-based designs).
2) The compiled model is the truth (UDM)

Altium is continuously compiling into an internal model (UDM). That compiled model is
what:

 resolves designators/nets per channel,

 creates “physical tabs” per channel in schematics,

 generates PCB components + nets for each channel.

So when something “weird” happens, it’s usually naming scope / net naming priority /
channel naming scheme — not “random”.

3) Naming: you must decide how repeated stuff gets unique names

Multi-channel only works if every repeated component and net ends up unique.

Where to set it

Project Options → Multi-Channel tab

You choose:

 Room naming (channel containers on PCB)

 Component naming scheme (and nets follow the same scheme)

Practical recommendation

 If you don’t have channels-inside-channels: use flat naming at room level (simpler).

 For components: choose something short and readable like

C30_CIN1 or C30_1 style (exact token depends on scheme).

4) Connectivity rules (this is where people get confused)

Net Identifier Scope

For multi-channel designs you generally want:

 Automatic / Hierarchical / Strict Hierarchical

Because multi-channel requires hierarchy to instantiate channels safely.

If you used Multiple Sheet Symbols

Connectivity is straightforward:

 You wire whatever goes into each sheet symbol.

 Each channel can get different nets because you explicitly routed them.

If you used Repeat keyword

There are only two “legal” connectivity patterns:

A) “Common-to-all channels” nets

If a net is wired to a sheet entry on the repeated sheet symbol, that net is available to all
channels.

Example: +12V, I2C_SCL, ENABLE, etc.

B) “Per-channel unique net from a bus”

If you need a different signal per channel, you do it from a bus using a repeated sheet entry
name like:

 Repeat(Headphone) on the sheet entry

Then Altium maps:

 Headphone1 → Channel1

 Headphone2 → Channel2

 etc.

Hard limitation: with Repeat-based channelization, you generally can’t route a random
unique net to only one channel unless you restructure into multiple sheet symbols.

5) Net naming priority: avoid “multiple net names” chaos

A single PCB net can’t have two final names, so you must choose how Altium resolves
competing names.

Where to set it

Project Options → Options tab → Netlist Options

Practical strategy that keeps life sane

 Enable “Higher Level Names Take Priority”

 Put net labels on the top-level nets that enter/leave channels

This avoids the situation where internal child-sheet labels override your top-level intent.
If you intentionally have multiple names (common in channels), don’t globally disable the
rule. Use:

 Specific No ERC markers on the exact nets you expect.

6) PCB side: Rooms are the superpower

When you transfer to PCB, Altium can create a Room per channel (Project Options → Class
Generation).

Rooms let you:

 move an entire channel as a block,

 scope rules by room,

 copy placement + routing from one channel to all other channels

(the “this is why multi-channel is worth it” feature)

Key commands live under:

 Design → Rooms → Copy Room Formats

 Design → Rooms → Move Room

7) UID linking (why this still works with repeated parts)

A schematic component UID alone can’t be used (it repeats), so Altium composes the PCB
UID from:

 Sheet Symbol UID + Component UID

 and for Repeat designs, also the ChannelIndex

That’s how cross-probe stays correct.

8) Parametric multi-channel hierarchy (pro move)

If channels are structurally identical but values differ (filters/EQ stages, sense scaling, etc.):

 Put parameters on each channel’s Sheet Symbol (e.g., C2_Value=0.056uF)

 On the child sheet, set component parameters like:

o Value = =C2_Value (or map into Comment)

Result: one schematic, many channels, each with unique values.

Rule of thumb: parametric per-channel values are easiest when you have separate sheet
symbols per channel (because the parameter storage lives on the symbol instance).

The decision cheat-sheet

Use Repeat keyword when:

 many identical channels

 mostly shared inputs (power/clock/control)

 per-channel uniqueness comes from a bus

Use multiple sheet symbols when:

 each channel needs slightly different wiring

 you want per-channel parameter/value overrides cleanly

 you’ll do lots of “special-case” channel handling

Reusing Blocks
1) Refactoring = restructure this design without changing function

Use refactoring when the goal is re-organizing your hierarchy/sheets (not “reusing” across
projects yet): replace an obsolete part with a subcircuit, push circuitry into a new child
sheet, convert between schematic sheets and device sheets, or move a selected subcircuit
to another sheet—while keeping linkage intact (UIDs stay consistent so PCB linkage doesn’t
break). Altium

Typical uses

 “This IC is obsolete; I want to swap it for an equivalent module on a sheet symbol.”

Altium

 “This sheet is overloaded; move this block to another sheet without breaking
connectivity/links.” Altium

 “Turn this sub-sheet into a reusable device sheet (or localize a device sheet into a
normal sheet for edits).” Altium

2) Multi-Channel = repeat circuitry inside the same project

Use multi-channel when you have N copies of the same channel on the same PCB: stereo
paths, 8 sensor channels, 64 front-ends, etc. You capture once, then Altium instantiates
channels during compilation; the “logical” schematic is not flattened, but the PCB gets
repeated physical components/nets per your naming scheme. Altium

Two ways to create channels

  Multiple sheet symbols pointing to the same child sheet, or

 One sheet symbol using the Repeat(...) keyword in the Designator. Altium

Practical win: In PCB you can replicate placement/routing from one channel to the others
(room-based workflows). Altium

3) Reuse Blocks & Snippets = reuse circuitry across designs (and optionally bring PCB
layout too)

This is for “I’ll need this block again in future projects.”

Snippets

 Schematic snippet: selection from one schematic sheet

 PCB snippet: selection from PCB including components + routing Altium

Snippets are fast and lightweight: select → create snippet → place later. Altium

Reuse Blocks (Workspace-based)

A Reuse Block is the “big” reuse object: it can contain both:

 the schematic circuitry and

 its PCB physical representation

When you place the reuse block on the schematic, its PCB implementation can be brought in
through the ECO process, and it lands as a union you can manage in the PCB editor. Altium

Key workflow

1. Create reuse block → capture schematic

2. Design » Update PCB Document → ECO to generate/update PCB for that reuse block

3. Place reuse block/snippet from Design Reuse panel into a design

4. Run ECO to bring the PCB union in Altium

So… which one should you pick? (fast decision rules)

Use Multi-Channel if:

 You need repeated circuitry within one design and want Altium to manage naming +
repeated instantiation. Altium

Use Reuse Blocks/Snippets if:

 You want a “known-good block” reusable across many projects

 You care about reusing PCB placement/routing too → prefer Reuse Blocks
(Workspace) over plain schematic snippets. Altium
Use Refactoring if:

 You’re reorganizing a design’s structure/hierarchy (move blocks, replace a part with a

sub-sheet, convert sheet↔device sheet) without changing functionality and without
breaking schematic↔PCB linkage. Altium

A very practical combined workflow (common in real projects)

 Start with a messy single-sheet prototype

 Refactor into hierarchical sheets (“power”, “MCU”, “interfaces”) Altium

 If you have 4–16 identical interfaces → convert that interface sheet into Multi-
Channel Altium

 If the interface becomes your “standard company block” → package it as a Reuse

Block for future boards Altium

Device Sheet
What a Device Sheet is (vs normal sheet)

 A Device Sheet is just a normal .SchDoc stored inside a folder that you declare as a
Device Sheets folder in Preferences.

 When you place it, you place a Device Sheet Symbol (rounded corners / recycle
icon), and Altium pulls it into the hierarchy without explicitly adding the sheet as a
project document.

 Usually it’s read-only in projects, so the team can’t accidentally change it (and
designators / sheet number on the sheet itself stay locked).

Device Sheets vs Managed Sheets vs Reuse Blocks

Device Sheets (local/shared drive)

 Reuse across projects, but you manage them yourself (folders, versions, access).

Managed Schematic Sheets (Workspace)

 Same reuse idea, but with revision control, lifecycle, access control, where-used,
etc. (better for teams/orgs).

Reuse Blocks (Workspace) & Snippets

 Reuse blocks can carry schematic + PCB physical implementation

(placement/routing via ECO).

 Device sheets are schematic reuse only (unless you combine with other workflows).

How you enable & use Device Sheets (workflow)

 1. Create a Windows folder structure (e.g. Device Sheets/Power, Device
Sheets/Interfaces).

2. In Preferences → Data Management → Device Sheets, add that folder (optionally

include subfolders).

3. In a project: Place → Device Sheet Symbol → pick the device sheet → place the
symbol → wire it like any sheet symbol.

Editing device sheets: the “right” way

Recommended

 Close projects that reference it

 Open the device sheet from the folder as a source file (File → Open)

 Edit/save/close

 All projects that reference it will reflect updates

Not recommended (but possible)

 Disable “Make Device Sheets in Projects Read-Only”

 Now you can edit inside projects — but this is an environment-wide setting and can
cause accidental edits across designs.

Hierarchy & multi-channel compatibility

 A device sheet can contain other device sheet symbols (deep hierarchy is fine).

 A device sheet cannot be the top sheet.

 You can use device sheets inside multi-channel designs (e.g., the repeated channel is
a device sheet block).

The big reason device sheets exist: annotation + sheet numbering without touching the
source

Because device sheets are meant to be “frozen,” Altium avoids modifying their content
during finalization.

What you do instead

1. Number sheets

o Number normal project sheets as usual (Number Schematic Sheets).

o Then run Annotate Compiled Sheets to number including device sheets.

2. Annotate components
 o First make sure everything has designators (Annotate Schematics).

o Then use Board Level Annotate to assign unique physical designators across
the compiled design.

All of this mapping is stored in a <ProjectName>.annotation file, so the device sheet source
files remain unchanged.

How device sheets connect to Refactoring (super important)

If your design has already been pushed to PCB, don’t cut/copy/paste circuitry between
sheets—because UIDs can get regenerated and you can break schematic↔PCB linkage.

Instead:

 Use Edit → Refactor → Move Selected Subcircuit to Different Sheet

 And refactor commands for converting schematic ↔ device sheet

That’s the “safe” restructuring path.

Practical recommendation for how you should use them

For your kind of work (repeatable “known-good” interface blocks, power stages, comms
blocks):

 Device Sheets for stable, schematic-only building blocks you want everywhere.

 Multi-channel for repeating blocks inside one project (8x channels).

 Reuse Blocks when you want schematic + PCB placement/routing reuse as a

packaged module.

Schematic Template
What a Schematic Template Is

A schematic template defines:

 Sheet size & orientation

 Title block graphics

 Sheet-level parameters (metadata like DrawnBy, Date, Revision)

It ensures consistent-looking schematics across projects or teams.

Once applied:

 Graphics/text from the template are locked (cannot be edited)

 Only parameter values change

Where Templates Live

You can have two kinds:

1) Workspace templates (recommended for teams)

 Stored in Altium Workspace

 Revision-controlled

 Can be enforced via Environment Configurations

2) Local templates

 Stored as .SchDot files on disk

 No revision control

 Personal or legacy use

Creating a Workspace Schematic Template (Correct Way)

1. Preferences → Data Management → Templates → Add → Schematic

2. Temporary schematic editor opens

3. Configure Document Options:

o Units, grid

o Page size, orientation

o Title block ON/OFF

⚠️Do NOT apply another template to a template

4. Define sheet-level parameters

o These become available when the template is applied

5. Draw graphics:

o Lines, borders, title block

6. Add Special Strings (placeholders):

o Use text like =DrawnBy, =Revision, =ProjectName

o Values come from sheet / project / variant parameters

⚠️Avoid spaces in parameter names

7. File → Save to Server

 o Creates a revisioned Workspace template

Special Strings (Key Concept)

 Text objects with =<ParameterName>

 Auto-filled when template is applied

 Sources:

o Sheet parameters

o Project parameters

o Variant parameters

Example:

=DrawnBy

=ProjectName

=Revision

Applying a Template

 Apply to any schematic sheet

 Result:

o Graphics become non-selectable

o Special strings show actual values

 Only editable part afterward:

o Parameter values, not the graphics

Editing a Workspace Template

 Preferences → Templates → right-click → Edit

 Opens in temporary editor

 Saving creates a new revision

Migrating Existing Templates to Workspace

You can:

 Open .SchDot → Save to Server

 Or use Load from File

 Or right-click local template → Migrate to Server

Result:

 Local file archived

 Workspace template created with revision history

Creating a Local Template

1. New schematic

2. Design it like a template

3. *Save As → .SchDot in local templates folder

Local templates appear in Preferences if visibility is enabled.

When to Use What

Workspace template

 Team standards

 Audited / locked formats

 Company title blocks

Local template

 Personal experiments

 Legacy designs

 No enforcement needed

Analyzing Your Design Using Circuit Simulation

Verifying and Preparing a Project for Simulation in Altium Designer
1. Overview and Feature Availability

Before running a circuit simulation, the design must be verified and properly prepared to
ensure accurate and reliable results. Simulation features depend on the Altium product in
use (Altium Designer, Altium Develop, or Altium Agile editions). If a required feature is
unavailable, the relevant license level should be confirmed.

Simulation is managed primarily through the Simulation Dashboard, which guides

verification, preparation, and execution of analyses. Note that legacy Altium documentation
is unversioned; older versions are accessible through the Legacy Documentation resources.

2. Controlling the Scope of Simulation

The scope of a simulation is defined using the Affect setting in the Simulation Dashboard.
This determines which schematic sheets are included:

 Document: Simulates only the currently open schematic sheet.

 Project: Simulates all schematic sheets in the active project.

This flexibility allows efficient debugging by isolating issues to a single sheet or expanding
analysis to the full design. The Affect setting can be combined with Compile Mask directives
and manual source inclusion to further control simulation visibility. If design variants are
present, simulations are performed on the active variant only.

3. Using Compile Masks for Simulation-Specific Elements

Compile Mask directives exclude covered elements from compilation. This is particularly
useful for simulation-only components such as voltage and current sources, which are
required for simulation but not for the final PCB.

A recommended approach is to group all simulation-specific components into a dedicated

schematic section and apply a Compile Mask to it.

 During simulation: Disable the Compile Mask to include these components.

 After verification: Re-enable the Compile Mask to exclude them from the final
design.

This method enables repeated simulation without permanently altering the production
schematic.

4. Verifying the Design for Simulation

Simulation is only available for schematics that are part of a PCB project (*.PrjPcb). Free
schematic documents cannot be simulated.

Verification is initiated using Start Verification in the Simulation Dashboard. This process
includes:
  Generation of the SPICE netlist.

 Simulation-specific electrical rule checks (ERC).

 Validation of simulation models and pin mappings.

If no issues are detected, verification is marked as successful. Minor schematic changes

trigger automatic re-verification, while major changes require manual updates.

Common verification issues include:

 Empty circuit: No components with simulation models present.

 No reference node: Missing ground or reference net (default is GND).

 Duplicate designators: Non-unique component identifiers.

 Voltage source or inductor loops: Shorted pins on sources or inductors.

 Net name errors: Use of SPICE-incompatible characters.

 Global parameter errors: Invalid parameter definitions.

5. Simulation Model Validation

All components must have valid simulation models. Violations are grouped under Simulation
Model checks:

 Components without models: Models can be assigned manually or automatically

from local libraries, installed libraries, connected workspaces, or cloud sources.

 Partially assigned models: Pin mappings must be corrected manually.

 Model syntax errors: Errors within the model file must be resolved.

Supported model formats include PSpice and LTspice (.mdl, .ckt, .lib, .cir). Only ANSI-
encoded files are supported.

6. Preparing the Design for Simulation

6.1 Adding and Configuring Simulation Sources

At least one voltage or current source is required for meaningful simulation. Sources can be
added directly from the Simulation Dashboard or schematic menus.

Each source is defined by:

 Stimulus Name: Allows reuse or isolation of signal definitions.

  Stimulus Type: DC, Pulse, Sinusoidal, Exponential, Piecewise Linear (PWL), Frequency
Modulated, or File-based (CSV).

 Parameters: Source-specific values such as amplitude, frequency, or timing.

Sources can be enabled or disabled without deletion, simplifying iterative analysis.

6.2 Piecewise Linear and File-Based Sources

Complex waveforms can be defined using:

 Time–Value pairs for interpolated PWL sources.

 CSV files containing waveform definitions for voltage or current sources.

These methods support accurate reproduction of measured or custom signals.

7. Adding and Managing Probes

Probes are used to observe simulation results at specific circuit points. Supported probe
types include:

 Voltage

 Current

 Power

 Voltage Difference (between two nodes)

Probes must be placed on valid nets or component pins. Incorrect placement results in
inactive or undefined probes. All probes can be managed, enabled, disabled, or color-coded
from the Simulation Dashboard. Probe results are displayed directly on the schematic and in
the Properties panel.

An optional Interactive Probe Mode allows real-time updates to simulation results when
probes are modified, at the cost of increased file size and simulation overhead.

8. Adding Simulation Models to the Design

Simulation-ready components require linked models. Models can be sourced from:

 Component manufacturers

 Altium’s Simulation Generic Components library

 The SPICE Model Wizard

 Third-party modeling tools or vendors

  Custom, manually written models

Models may be attached to library components or placed directly into the schematic. When
placing a model directly, Altium automatically assigns an appropriate generic symbol based
on the model type.

9. Digital Devices and Advanced Features

Altium supports PSpice digital primitives, including digital gates and stimuli, with inertial
delay handling and global digital nodes. Variable passive components are also supported,
allowing resistance, capacitance, or inductance to depend on parameters such as voltage,
current, time, or temperature.

10. Net Naming Best Practices

While not mandatory, assigning net names is strongly recommended. Clear net labeling
simplifies probe placement, result interpretation, and output expression configuration,
particularly in complex designs.

11. Summary

Effective circuit simulation in Altium Designer requires:

 Correct project structure.

 Clear control of simulation scope.

 Proper use of Compile Masks.

 Complete and valid simulation models.

 Thoughtful configuration of sources and probes.

Following these practices ensures accurate simulation results and a smooth transition from
verification to final PCB design.

Configuring and Running Simulations in Altium Designer

1. Overview and Feature Availability

Simulation configuration and execution in Altium Designer are performed through the
Analysis Setup & Run region of the Simulation Dashboard. The availability of specific
simulation features depends on the Altium product edition in use. If required options are
missing, the license level should be verified.
Simulation documentation is no longer versioned; older references are available through
Altium’s Legacy Documentation resources.

Once a circuit has been verified and prepared, the Analysis Setup & Run region is used to
select, configure, and execute one or more simulation analyses.

2. Numerical Entry Formats

All numeric fields in simulation setup support three formats:

 Normal: Explicit numeric values (e.g., 1000000).

 Engineering: Mantissa with SI prefixes (e.g., 1meg, 10u, 5k).

 Scientific: Mantissa and exponent using e notation (e.g., 1e6).

Using engineering notation is recommended for clarity and consistency with electrical units.

3. DC and Small-Signal Analyses

3.1 Operating Point Analysis

Operating Point analysis determines the steady-state DC behavior of the circuit. Inductors
are treated as shorts and capacitors as opens. This analysis computes node voltages, branch
currents, and power dissipation, and establishes the bias point required for other analyses.

Results can be displayed directly on the schematic for voltages, currents, and power. Values
are calculated for all nodes automatically, with additional data selectable from the
simulation results.

A Node Set (.NS) device may be used to assist convergence by specifying an initial node
voltage, though this is typically only required for bistable or difficult circuits.

3.2 Transfer Function Analysis

Transfer Function analysis calculates DC input resistance, output resistance, and gain for
each node. It is enabled from the Operating Point region and requires selection of an input
source and reference node. Results are numerical and added to the simulation data table
rather than plotted by default.

3.3 Pole-Zero Analysis

Pole-Zero analysis evaluates system stability by determining the poles and zeros of the
linearized small-signal transfer function. The user defines input and output nodes, reference
nodes, and the transfer function type. This analysis is computationally intensive and may
require refinement (poles only or zeros only) for large circuits.
4. Sweep and Time-Domain Analyses

4.1 DC Sweep

DC Sweep performs repeated Operating Point analyses while stepping one or two
parameters, such as source values, component values, or temperature. The result is a DC
transfer characteristic similar to a curve tracer.

4.2 Transient Analysis

Transient analysis computes circuit behavior as a function of time, equivalent to oscilloscope

observation. Time can be defined explicitly or in terms of waveform periods. By default, an
Operating Point analysis is performed first unless Use Initial Conditions is enabled.

Initial conditions may be specified per component or using .IC devices. Component-level
initial conditions override net-level .IC definitions.

4.3 Fourier Analysis

Fourier analysis is derived from the final cycle of a Transient analysis and decomposes a
waveform into its harmonic components. The user specifies the fundamental frequency and
number of harmonics. This analysis is commonly used to assess distortion.

5. Frequency-Domain Analyses

5.1 AC Sweep

AC Sweep analysis computes the small-signal frequency response of the circuit. It requires at
least one source with a defined AC Magnitude. Frequency stepping can be linear, per
decade, or per octave.

Complex output functions such as magnitude, phase, and group delay can be plotted. AC
Sweep is typically used for gain, impedance, and bandwidth analysis.

5.2 Noise Analysis

Noise analysis evaluates the noise spectral density contributed by resistors and
semiconductor devices. The total output noise and equivalent input noise can be plotted,
with optional breakdown by component.

5.3 S-Parameters Analysis

S-Parameters analysis characterizes multi-port networks using scattering parameters. Ports

are defined as sources with specified impedances (default 50 Ω). The simulator also
computes Y-parameters and Z-parameters. This analysis is applicable to RF and general
multi-port systems.
6. Reliability and Variation Analyses

6.1 Stress Analysis

Stress analysis evaluates voltages, currents, and power dissipation against component stress
limits. Stress models are defined per component and may include derating. Results are
displayed in a dedicated Stress chart.

6.2 Temperature Sweep

Temperature Sweep repeats an analysis across a defined temperature range, producing one
curve per temperature. This is configured through the Advanced Analysis Settings dialog.

6.3 Parameter Sweep

Parameter Sweep varies selected component or source parameters over defined ranges
using linear, logarithmic, or list-based distributions.

6.4 Monte Carlo Analysis

Monte Carlo analysis performs multiple runs with randomized component values based on
specified tolerances and distributions (uniform, Gaussian, or worst case). This analysis is
used to evaluate manufacturing variability.

6.5 Sensitivity Analysis

Sensitivity analysis identifies which components most strongly affect a selected

measurement. It requires predefined measurements and is mutually exclusive with sweep
and Monte Carlo analyses.

7. Output Expressions and Measurements

In addition to probes, custom Output Expressions can be defined to generate calculated

waveforms. Expressions may combine voltages, currents, powers, constants, and
mathematical functions.

Measurements such as bandwidth, gain, rise time, frequency, RMS value, and extrema can
be attached to output expressions. Results are presented numerically in the simulation data
tables, enabling quantitative design evaluation.

8. Global Parameters

Global parameters define parametric dependencies used throughout the circuit. They are
evaluated before internal constants and can be referenced directly in component values.
Care must be taken to avoid naming conflicts with built-in constants.
9. Advanced Simulation Options

Advanced options provide direct access to SPICE parameters controlling convergence,

accuracy, temperature, integration method, and reference net. These settings should
generally remain at default values unless convergence or stability issues arise.

Key considerations:

 Higher accuracy increases simulation time.

 Trapezoidal integration is fast but may oscillate; Gear methods are more stable but
slower.

 Raising iteration limits or minimum conductance can improve convergence at the

cost of precision.

10. Running and Managing Simulations

Individual analyses can be run independently, or all configured analyses can be executed
together using Run Simulation (F9). Results are stored in a single simulation data file, with
each analysis displayed on its own chart.

Simulations can be aborted at any time, displaying partial results if available. Mixed-signal
simulations may use multi-threading to improve responsiveness.

If a simulation fails, the issue may lie in the circuit definition or in the analysis configuration.
Systematic troubleshooting is recommended before modifying advanced SPICE parameters.

11. Summary

Configuring and running simulations in Altium Designer involves selecting appropriate

analysis types, defining accurate ranges and parameters, and balancing numerical accuracy
with performance. Proper use of output expressions, measurements, and variation analyses
enables thorough validation of circuit behavior prior to hardware implementation.

Working with Simulation Results in Altium Designer

1. Overview of Simulation Results

After running one or more analyses, Altium Designer stores the results in a Simulation Data
File (SDF) named <ProjectName>.sdf. This file appears under Generated → Simulation
Documents in the Projects panel and opens automatically in the SimData editor. The SDF is
initially unsaved and serves as the central workspace for inspecting, comparing, and
documenting simulation results.
The SimData editor is designed to support efficient analysis, debugging, and validation of
circuit behavior through graphical, numerical, and textual representations.

2. Managing Simulation Runs

All completed simulation runs are listed in the Results region of the Simulation Dashboard.
For each result, you can:

 Reopen the results

 Reload the analysis configuration used for that run

 Edit the result title or description

 Delete the result

Results can also be locked to preserve them. When locked, subsequent runs of the same
analysis type are stored separately, allowing comparison across multiple iterations.

3. Structure of Simulation Data

Simulation results are organized hierarchically into three elements:

 Charts: Logical containers corresponding to analysis types (e.g., Transient, AC

Sweep).

 Plots: Graphical regions within a chart that display data.

 Waveforms: Individual data traces representing voltages, currents, or calculated

expressions.

Each analysis type generates its own chart. Some analyses, such as Operating Point or
Transfer Function, present textual data rather than waveforms.

4. Navigating Charts, Plots, and Waveforms

Charts are accessed via tabs at the bottom of the design space. Within charts:

 Waveforms can be moved between plots using drag-and-drop.

 New plots can be created, and existing ones rearranged.

 Zooming, panning, and fitting operations allow detailed inspection of data.

 Plot and axis properties (titles, grids, scaling) are configurable.

The number of visible plots can be adjusted to balance overview and detailed analysis.
5. Selecting and Filtering Waveforms

Selecting a waveform highlights it and dims unrelated waveforms for clarity. Multiple
waveforms can be selected for comparison. The mask level controls how strongly non-
selected waveforms are faded, and filtering can be cleared at any time.

For analyses involving multiple passes (Temperature Sweep, Parameter Sweep, Monte
Carlo), waveforms are labeled by pass index. Selecting a waveform reveals the parameter
values used for that pass and can optionally highlight related waveforms.

6. Scaling, Axes, and Data Accuracy

Waveforms are auto-scaled initially, but axes can be manually configured:

 Linear or logarithmic scaling

 Custom minimum and maximum limits

 Multiple Y-axes within a single plot for signals with different magnitudes

Displaying data points helps assess numerical resolution and verify that simulation accuracy
is sufficient.

7. Frequency-Domain and FFT Analysis

A Fast Fourier Transform (FFT) can be generated from any waveform using the Create FFT
Chart command. FFT results are placed in a new chart and support spectral analysis such as
harmonic content and noise inspection. FFT resolution is controlled through document
options.

8. Creating, Editing, and Managing Waveforms

Beyond analysis-generated waveforms, you can:

 Edit waveforms using mathematical expressions

 Create custom waveforms (user-defined, sinusoidal, pulse-based)

 Store and recall waveform data using ASCII .wdf files

Stored waveforms can be reused for comparison or documentation, though recalled

waveforms are read-only.
Waveforms can be copied, moved, or deleted from plots without deleting their underlying
data. Permanent deletion is performed from the Source Data list.

9. Exporting and Importing Data

Simulation data can be exported to CSV format at the chart, plot, or waveform level. Export
options allow control over real or complex data and delimiter format.

CSV files can also be imported, enabling integration with external tools or reuse of
previously exported data. Name conflicts are resolved during import through renaming.

10. Printing and Documentation

Simulation results can be printed directly from the SimData editor. Page setup, plot
selection, waveform inclusion, and measurement data are configurable. For monochrome
output, designation symbols can be enabled to distinguish waveforms without color.

11. Working with Textual and Digital Data

Some analyses produce textual results rather than plots. These values can be added to
charts, copied to the clipboard, or exported.

Digital simulations display logic levels (0, 1, undefined, high-impedance) using specialized
digital plots. Digital and analog waveforms are kept separate, and Boolean operations
preserve digital representation.

12. Measurement Results and Direct Measurements

Measurement results are shown in the Measurements tab of the Sim Data panel. Features
include:

 Viewing statistics across multiple runs

 Generating plots or histograms of measurement values

 Expanding measurement tables for export or reporting

Direct measurements can be taken in two ways:

 Automatic waveform measurements (min, max, rise time, fall time, etc.)

 Cursor-based measurements, using interactive cursors for precise timing and

amplitude evaluation
13. Cross-Probing to the Schematic

Waveforms derived directly from circuit analysis support cross-probing back to the
schematic. Selecting this option highlights the originating node, enabling rapid correlation
between simulation results and circuit topology. Derived or user-created waveforms do not
support cross-probing.

14. Summary

The SimData editor provides a comprehensive environment for analyzing simulation results
in Altium Designer. Through structured charts, flexible waveform handling, advanced
measurement tools, and export capabilities, it enables thorough validation, comparison, and
documentation of circuit behavior before hardware implementation.

SimData Editor Shortcuts

Reach here.

Simulation Troubleshooting in Altium Designer

1. Overview

When a circuit fails to simulate, the root cause lies either in the circuit definition or in the
simulation setup. Effective troubleshooting requires isolating the problem systematically
and addressing one factor at a time. Altium Designer reports simulation issues through
warning and error messages in the Messages panel:

 Warnings are non-fatal and indicate adjustments made by the simulator to complete
the analysis.

 Errors are fatal and prevent result generation; these must be resolved before analysis
can proceed.

2. Understanding Convergence

Most simulation failures are caused by non-convergence. Altium Designer’s SPICE engine
solves circuit equations iteratively to determine node voltages and branch currents. For
nonlinear circuits, multiple iterations are required at each simulation step. Convergence is
achieved when voltages and currents fall within defined tolerances.

Common convergence-related failures include:

 Singular matrix

 GMIN stepping failed

  Source stepping failed

 Iteration limit reached

 Timestep too small (Transient analysis)

If convergence cannot be achieved within iteration or timestep limits, the simulation is

aborted.

3. General Convergence Troubleshooting Procedure

When a simulation fails, apply the following steps in order:

1. Disable all analyses except Operating Point.

2. Review the Messages panel for errors or warnings.

3. Verify correct circuit wiring; dangling or floating nodes are not allowed.

4. Ensure a valid ground reference exists and every node has a DC path to ground.

5. Check for typographical errors (e.g., O vs 0).

6. Verify correct SPICE multipliers (MEG for 1e6, not M) and remove spaces between
values and units.

7. Confirm all component and source values are realistic and correctly defined.

8. Validate gains of dependent sources.

9. Temporarily remove series capacitors or current sources and retry.

10. Temporarily remove parallel inductors or voltage sources and retry.

If issues persist, adjust advanced settings:

 Increase ITL1 (e.g., to 300) to allow more Operating Point iterations.

 Set RSHUNT to a high value (e.g., 1e12 Ω) to avoid singular matrix errors.

 Add .NS (Nodeset) devices to provide initial voltage guesses.

 Use .IC (Initial Condition) devices to force starting voltages.

 Enable Use Initial Conditions for Transient analysis to bypass Operating Point.

 Increase GMIN and define series resistances in models.

 Set semiconductor starting conditions (e.g., diodes initially OFF).

4. DC Sweep Analysis Troubleshooting

If DC Sweep analysis fails:

 Apply the general convergence steps first.

 Adjust the Step size:

o Larger steps can bypass model discontinuities.

o Smaller steps resolve sharp transitions.

 Avoid DC Sweep for circuits with hysteresis or strong nonlinearity; use Transient
analysis with ramped sources instead.

5. Transient Analysis Troubleshooting

For Transient analysis failures, in addition to general steps:

 Increase RELTOL (e.g., to 0.01) to relax accuracy requirements.

 Increase ITL4 (e.g., to 100) to allow more iterations per timestep.

 Increase ABSTOL and VNTOL if very small current or voltage resolution is

unnecessary.

 Switch the Integration Method from Trapezoidal to Gear for improved numerical
stability, especially in oscillatory or feedback circuits.

Additional best practices:

 Use realistic device models and include parasitics.

 Add snubbers across diodes where appropriate.

 Replace ideal models with subcircuits for power and RF components.

 Increase rise and fall times of pulse sources; avoid ideal step transitions.

6. Summary

Simulation troubleshooting in Altium Designer is primarily about managing convergence.

Begin with circuit correctness, proceed through structured convergence techniques, and
only adjust advanced SPICE parameters when necessary. A methodical approach—combined
with realistic modeling—will resolve most simulation failures and lead to stable, meaningful
results.

Working with a SPICE Netlist in Altium Designer

1. What a SPICE netlist is (and why you should care)
A SPICE netlist is the actual text input the simulator runs. Your schematic is a friendly front-
end; Altium converts it into a netlist that contains:

 Components (R, C, L, sources, semiconductors, etc.)

 Node connections (net names)

 Models / subcircuits (e.g., .model, .subckt)

 Analysis directives (e.g., .op, .tran, .ac, .dc)

 Output directives (e.g., .print, probes → waveform requests)

If a simulation fails, the netlist is often the fastest way to see what SPICE is really trying to
solve.

2. Generating and running a netlist in Altium

 Generate netlist from schematic: Simulate → Generate Netlist

 Create a new empty netlist: File → New → Mixed-Signal Simulation → AdvancedSim

Netlist

 Run simulation from an open netlist: Simulate → Run (F9)

Use this when:

 You want to verify what Altium exported (values, units, node names, model calls).

 You suspect a model or directive mismatch.

 You’re debugging convergence or “singular matrix” style issues.

3. How to read netlist lines (pattern recognition)

Think of a netlist as a list of statements. The key ones:

a) Comments

Lines starting with * are comments:

 Useful for separating blocks, listing selected analyses, etc.

 Not executed by SPICE.

b) Passive components (R/C/L)

Typical pattern:

C<name> <node1> <node2> <value>

R<name> <node1> <node2> <value>

L<name> <node1> <node2> <value>

Example you posted:

CC11 0 NetC11_2 100nF

Means capacitor CC11 between GND (node 0) and NetC11_2, value 100 nF.

Important: In SPICE, node 0 is ground. If your schematic has “GND”, Altium typically maps it
to node 0 in the netlist.

c) Independent sources (voltage/current sources)

Typical voltage source format:

V<name> <plus_node> <minus_node> DC <value> AC <mag> <phase> <time_function>

Example:

VV6 NetC14_2 0 DC 0 PULSE(0 5 100n 10n 10n 400n 1u) AC 1mV 0

Interpreting it:

 Voltage source VV6 between NetC14_2 and ground

 DC value = 0 V

 Transient waveform = PULSE(...)

 AC small-signal magnitude = 1 mV, phase = 0° (used for AC sweep)

d) Analysis directives

These define what simulation is run:

 .OP Operating point (DC bias)

 .TRAN Transient

 .AC AC sweep

 .DC DC sweep

 Etc.

Example:

.TRAN 1 10u 0 1

That’s a transient setup (the exact meaning of each parameter depends on the SPICE flavor,
but conceptually: simulate in time with a defined step/stop time, optional start time / max
step).
e) Output directives

These control what gets recorded:

 In your snippet:

 .PRINT =1 NetC13_1 NetC14_2

It requests plotting/printing certain node quantities.

In Altium, probes and Output Expressions end up generating these kinds of output requests.

f) Models and subcircuits

 .model <name> <type> (params...)

 .subckt ... blocks

 .include "[Link]"

Example:

.model PMOSFET_Level1 pmos (Level=1)

Defines a MOSFET model. Then device instances reference it.

4. The #1 reason netlists “don’t match your intention”

It’s usually one of these:

1. Wrong multipliers / units

 SPICE shorthand is unforgiving (e.g., MEG vs M).

 Also: no spaces in values like 1.0uF (not 1.0 uF).

2. Missing models

 Parts from database libraries/imported designs only simulate if a simulation model is

assigned.

 Otherwise the device might be omitted or replaced with something meaningless.

3. Floating nodes / no DC path to ground

 A netlist makes this visible: you can literally see nodes that never touch 0 through a
DC path.

4. Ideal elements that create singularities

 Loops of ideal voltage sources/inductors, or cutsets of ideal current

sources/capacitors, etc.
  Netlist inspection makes these patterns easier to spot.

5. “Areas of SPICE User Code” (.nsx) — how to use it correctly

This is Altium’s way to inject raw SPICE into the generated netlist.

How to add:

1. Place a Text Frame on schematic

2. First line:

3. .nsx

4. Below it: write SPICE directives / models / params

What it’s good for

 Adding or overriding .model definitions

 Adding .include files (library models)

 Adding .param parameters

 Adding special SPICE commands you can’t easily express via UI

Key behavior

 If you define a parameter in both Global Parameters and in .nsx, the .nsx version
wins (higher priority).

Limit

 You still can’t define an entire circuit purely as .nsx; Altium expects schematic objects
for connectivity/components.

6. Practical workflow: netlist-first debugging

When a sim fails or behaves weirdly, do this:

1. Generate netlist and open it

2. Search for:

o The suspect component designator (e.g., R12, U3, VV6)

o .tran, .ac, .op, .dc

o .model, .subckt, .include

3. Validate:
 o Are node connections correct?

o Are values what you expect?

o Is the right model being called?

o Do you see ground node 0 used everywhere it should?

4. If convergence fails:

o Look for floating nodes / purely capacitive coupling / transformers without

reference

o Add RSHUNT / nodesets / initial conditions (either via UI or .nsx) as needed

Creating and Managing Simulation Models in Altium Designer

1. Purpose of Simulation Models

To simulate a circuit using Altium Designer’s Mixed-Signal Circuit Simulator, every

component must be simulation-ready, meaning it must have an associated SPICE simulation
model. These models define the electrical behavior of components and are ultimately
translated into the SPICE netlist processed by the simulator.

Simulation models may be:

 Provided by manufacturers as downloadable SPICE files

 Extracted from datasheets or measurements

 Created manually using SPICE syntax (e.g., subcircuits)

 Generated or managed within a Workspace for reuse and lifecycle control

2. Creating New Simulation Model Files

Manufacturer models are typically supplied as text-based files (*.mdl, *.ckt). If a model is
provided as plain text (for example, on a web page), a new model file can be created in
Altium Designer and populated by copying the content.

Key points:

 Create model files via File → New → Mixed Simulation

 Determine the correct file type (.mdl, .ckt) by inspecting the model syntax

 Models may include directives such as .MODEL, .SUBCKT, .IC, and source definitions

 Advanced features include support for initial conditions, functional sources, burst
transient definitions, and model inheritance using the AKO keyword
  Altium performs error checking for invalid AKO usage (e.g., missing base models or
recursive definitions)

3. Workspace Simulation Models

When working with a connected Workspace, simulation models can be centrally stored,
versioned, and reused.

Workspace Simulation Models:

 Are created automatically when saving a component with an attached simulation

model to the Workspace

 Can also be created directly in the Workspace via the Components panel

 Are stored as .SimModel items, referencing underlying .mdl or .ckt files

 Are linked (not embedded) into Workspace Components, alongside symbols,

footprints, and parameters

This approach enables consistent simulation behavior across projects and controlled revision
management.

4. Defining a Simulation Model (SimModel File)

A .SimModel file defines how a simulation model is referenced and configured. Required
information includes:

 Model Name
Must exactly match the name defined in the .MODEL or .SUBCKT statement of the
referenced file.

 Model File
The linked .mdl or .ckt file containing the SPICE definition.

 Description
Used for documentation and Workspace revision metadata.

 Parameters
Model-level parameters that define default behavior.

 Model Preview
Read-only view of the referenced SPICE file content.

Model-level parameters can be overridden at the component level. During netlist

generation, component-level values take priority.
5. Editing and Updating Simulation Models

Workspace Simulation Models can be edited at any time. Editing creates a new revision,
preserving traceability.

Important behaviors:

 Lifecycle state can be preserved (if permitted)

 Related Workspace Components can be automatically updated to reference the new

model revision

 This ensures simulation consistency without manual re-linking

6. Generating SimModel Files from Libraries

SimModel files can be generated automatically from schematic or database libraries using
the Generate SimModel Files tool.

Key rules:

 Supported for standard Database Libraries (not SVNDbLibs)

 Only enabled tables/components are processed

 Generated SimModel files reference existing simulation links

 Referenced .mdl, .ckt, or .scb files are copied alongside

Generated SimModel files can then be saved into the Workspace as managed Simulation
Model items.

7. SPICE Model Wizard

The SPICE Model Wizard provides a guided method to create SPICE models for supported
analog devices without manual coding.

Supported device types include:

 Diodes

 BJTs

 Semiconductor resistors and capacitors

 Controlled switches

 Transmission lines
The Wizard:

 Generates .mdl files automatically

 Supports parameter entry or parameter extraction from measured or datasheet data

 Links the generated model to a new or existing schematic component

 Allows preview and manual refinement before saving

Pin mapping and parameter values should always be verified after model generation.

8. Model Creation Methods

Two primary approaches are supported:

Direct Parameter Entry

Used when parameters are known explicitly. Unspecified parameters default to internal
SPICE values.

Parameter Extraction from Data

Used for diodes and BJTs. Parameters are derived from:

 Measured device data

 Manufacturer datasheets

 Graphical curve data (imported manually or via CSV)

The Wizard provides comparison plots to validate extracted parameters and allows fine-
tuning.

9. Device Modeling Scope and Limitations

Not all SPICE parameters can be reliably extracted from data. Parameters such as noise
coefficients, temperature exponents, and secondary effects use SPICE default values unless
explicitly defined.

Advanced users may manually extend generated models by editing the .mdl file to include
these parameters where higher accuracy is required.

10. Summary

Simulation models are a foundational requirement for circuit simulation in Altium Designer.
Whether sourced from manufacturers, generated via the SPICE Model Wizard, or managed
as Workspace Simulation Models, correct model definition, naming, parameter control, and
revision management are critical. A structured modeling workflow ensures reliable
simulation results, reuse across projects, and traceability throughout the design lifecycle.

Managing Design Changes between the Schematic & PCB

Working with Classes on Schematic and PCB in Altium Designer
1. What a Class Is and Why It Matters

A Class is a named group of design objects (such as nets, components, differential pairs,
polygons). Classes serve two primary purposes:

1. Navigation and selection: quickly locate and isolate related objects while browsing a
design.

2. Constraint application: apply consistent requirements (routing width, clearance,

impedance intent, etc.) across all objects in the class.

Classes are especially useful when requirements are defined for functional groups (for
example, Power, LEDS, DDR, CAN, Sensitive Analog), rather than for individual nets or
components.

2. Where Classes Come From

Altium supports two broad sources of classes:

2.1 Automatically Generated (Software-Created) Classes

These are derived from design structure during schematic-to-PCB transfer, such as:

 Nets grouped by a bus or signal harness

 Nets connected to a component (e.g., <U1>_Nets)

 Components grouped by schematic sheet

 Hierarchical groupings using Structure Classes (project hierarchy mapped into PCB)

These are configured in Project Options → Class Generation.

2.2 User-Defined Classes

User-defined classes can be created in two main ways:

 Schematic parameters/directives (classic, design-rules centric workflow)

 Constraint Manager classes (constraint-centric workflow)

An object can belong to multiple classes.

3. Constraint Strategy: Constraint Manager vs Design Rules

When a project is created, you choose how constraints will be managed:

 Constraint Manager approach: classes and constraints are handled as project-level

constraints, edited in a structured environment and synchronized via ECO.

 Design Rules approach: classes are mainly defined through schematic

directives/parameters and edited in PCB via the rules system and Object Class
Explorer.

Key interaction rule:

 If both parametric net-class directives and Constraint Manager net classes exist, the
Constraint Manager takes precedence, and parametric net classes are not applied.

Important limitation:

 Component classes cannot be defined in the Constraint Manager; they must be

created parametrically (e.g., using ClassName on components).

4. Defining Classes on the Schematic

4.1 User-Defined Component Classes (Parameter-Based)

To place components into a component class:

 Add a component parameter named ClassName

 Set its value to the class name (e.g., PowerStage, Analog, Sensors)

This can be applied efficiently by:

 Selecting multiple components and editing in the Properties panel

 Using a Blanket plus a Parameter Set to apply to a grouped region

4.2 User-Defined Net Classes (Directive-Based)

To place nets into a net class (or bus/harness nets into a net class):

 Place a Parameter Set directive touching the wire/bus/harness

 Add a parameter named Net Class Name with the desired class value

For large groups:

 Use a Blanket to cover multiple nets

 Place the Parameter Set so it touches the blanket boundary, not the wire
Note: the parameter value defines the class name; the displayed directive name is only a
visual aid.

5. Defining Classes in the Constraint Manager

In Constraint Manager, classes are managed directly (add/edit/delete) and are designed to
make constraint assignment across grouped nets fast and consistent.

Practical behavior:

 Classes defined in Constraint Manager are transferred during synchronization

regardless of Class Generation settings.

 If you migrate from directives, Altium can convert directive-based net class
definitions into Constraint Manager classes during ECO refresh, after which the on-
sheet directives become non-editable and represent managed constraints.

6. Class Generation During Schematic-to-PCB Transfer

The Class Generation tab in Project Options controls:

6.1 Automatically Generated Classes

Examples:

 Net classes per named bus or harness

 Net classes per component (nets connected to that component)

 Component classes per schematic sheet

 Optional PCB Rooms tied to generated component classes

 Optional sheet-level net-class scope (local-only vs all nets)

6.2 User-Defined Classes (from parameters/directives)

 Component classes from ClassName can be generated in both workflows.

 Net classes from Net Class Name directives are generated only if the project is not
using Constraint Manager.

7. Creating and Editing Classes in the PCB Editor

7.1 PCB Object Class Explorer

The PCB editor provides the most complete view of class types via:
  Design → Classes (Object Class Explorer)

This allows:

 Creating, renaming, deleting classes

 Managing membership using Members / Non-Members lists

 Using selection-based add/remove actions

 Generating component classes via the Component Class Generator

Some system classes are default and cannot be edited (e.g., <All Nets>).

7.2 Creating a Class from Selected Objects

You can create classes directly from selected objects:

 Net class: select nets → create NetClass from selected

 Component class: select components → add class

 Polygon class: create via Polygon Pour Manager

7.3 Cross-Selection Across Editors

Cross Select Mode lets selection propagate between schematic and PCB:

 Enable via Tools menu or Shift+Ctrl+X

 In schematic, hold Alt while selecting a net to select the entire logical net across
sheets (labels/ports/harness behavior included)

This is valuable for verifying that class membership and routing intent align with schematic
connectivity.

8. Structure Classes for Hierarchical Navigation and Rule Scoping

A Structure Class represents a schematic-sheet-level hierarchy inside the PCB domain. It can
contain other class types as members, including:

 net classes, component classes, diff pairs, xSignals, polygons, and even other
structure classes

Structure classes enable:

 Project hierarchy navigation in PCB

 Sheet-level grouping for inspection and design review

 Powerful scoping in rules and filters using query language

Example query capability:

 InStructureClass('SheetA_Block') to target all objects belonging to that hierarchy

branch.

9. Practical Guidance

Use classes when:

 You want consistent constraints across a functional group

 You need fast selection and verification workflows

 You want reusable structure for complex boards (interfaces, power domains,
subsystems)

Choose one dominant strategy early:

 Constraint Manager for centralized, structured constraints and modern constraint

workflows

 Rules + directives/parameters for classic schematic-driven class definition and rules

scoping

Avoid mixing approaches unless you understand precedence and migration behavior,
especially for net classes.

Cross-Probing and Cross-Selecting Between Schematic and PCB

1. Purpose and Core Concepts

Altium Designer provides cross-domain navigation tools that link objects between the
schematic and PCB editors. These features are primarily used to locate, verify, and
manipulate corresponding design objects across domains.

 Cross-Probing: “Point to an object here, jump to and highlight its counterpart there.”
Used to locate an item in the other editor.

 Cross-Selecting: “Select objects here, automatically select the same objects there.”
Used to build a working selection set for placement, class creation, and other actions.

Supported cross-domain object types between schematic and PCB include documents,
components, buses, nets, and pins/pads.

2. Unified Data Model and Project Compilation

Cross-probing and cross-selecting rely on Altium’s Unified Data Model (UDM), an in-
memory representation of the entire project. The UDM captures design entities and
relationships such as:

 component instances and connectivity

 footprint links

 cross-domain relationships (including PCB–FPGA links where applicable)

Because cross features depend on an up-to-date model, Altium uses auto-compilation to

keep the UDM current. Manual validation can be performed via:

 Project → Validate PCB Project

This checks logical, electrical, and drafting consistency based on compiler settings.

3. Recommended Document Setup

These features are easiest to use when schematic and PCB are visible at the same time:

 Right-click a document tab → Split Vertical / Split Horizontal

 To return to a single view: right-click a tab → Merge All

 With multiple monitors: drag a document tab to another screen

4. Cross-Probing (Locate and Highlight)

4.1 Access

Cross-Probing can be launched from either editor:

 Tools → Cross Probe

 Toolbar Cross Probe button (Standard toolbar)

Highlight behavior on the target document is controlled by:

 Preferences → System → Navigation → Highlight Methods

Note: Highlighting is applied to the target document, not the originating one.

4.2 Modes of Operation

Altium provides two operating modes:

Continuous Mode

 Stay in the source editor and probe multiple objects in sequence.

  Best used with schematic and PCB open side-by-side.

 Behavior notes:

o Only the most recently probed object is highlighted (not cumulative).

o If documents are not side-by-side, you must activate the target document to
view results.

Jump-To Mode

 Probe a single object and switch focus to the target editor.

 Triggered by Ctrl+Click (or Ctrl+Enter) after starting Cross Probe.

4.3 Cross-Probing From Other Locations

Cross-probing is also available in several workflows beyond Tools → Cross Probe, enabling
fast navigation while debugging, synchronizing, or reviewing:

 Engineering Change Order (ECO) dialog: right-click to cross probe reference/target

items

 Differences Between dialog: double-click an entry to cross probe

 Differences panel: double-click an item to probe

 Variant Manager / Variant Management: probe selected components

 BomDoc: right-click → Cross Probe

 Projects panel: right-click in Components/Nets → cross probe to schematic/PCB

 Messages panel: double-click an error after validation to jump to the issue

 Constraint Manager: right-click an entry → Cross Probe (or from a custom rule
menu)

5. Cross-Selecting (Build a Matched Selection Set)

5.1 What It Does

With Cross Select Mode enabled, selecting objects in one editor automatically selects the
corresponding objects in the other editor. This is particularly useful for preparing selections
for downstream actions such as:

 creating PCB classes from schematic selections

 arranging placement clusters

 placing components in a controlled sequence

5.2 Enabling Cross Select Mode

Cross-selecting can be toggled by:

 Tools → Cross Select Mode (toggle on/off; icon indicates state)

 Shift+Ctrl+X

 Preferences → System → Navigation → Cross Selection

Enabling it in either schematic or PCB enables it for both.

Selection display behavior (zoom, focus switching, dimming, etc.) is configured in:

 Preferences → System → Navigation → Cross Select Mode settings

6. Selecting PCB Components From the Schematic (Command-Based)

In addition to live cross-select mode, Altium supports a command that transfers a schematic
selection directly to PCB:

Workflow

1. Ensure the target PCB document is open.

2. Select the required component(s) on the schematic.

3. Run Tools → Select PCB Components

o Alternatively: right-click a selected part → Part Actions → Select PCB

Components

Result

 The PCB document becomes active.

 Corresponding footprints are selected and zoomed (not masked).

Operational notes:

 If the project has multiple PCB documents, open only the PCB document you want to
operate on; otherwise the command searches across open PCB documents for
matches.

7. Common Practical Uses

Cross-selecting and cross-probing are most valuable when used as “navigation + intent
verification” tools:
  Layout targeting: select a functional group in the schematic, immediately locate and
place it on the PCB

 Class creation: cross-select parts, then capture them into a PCB component class
efficiently

 Debugging and ECO review: probe from Messages/Differences/ECO to find and

resolve mismatches quickly

 Constraint verification: probe from Constraint Manager entries to confirm the exact
objects being constrained

Using Color to Highlight Nets

1. Purpose of Net Color Highlighting

As schematic and PCB designs grow in complexity, visual clarity becomes critical. Net Color
Override allows designers to apply color to schematic wiring, PCB connection lines, and
routed nets to improve readability and quickly identify critical signal groups such as high-
speed interfaces, power domains, or sensitive analog paths.

Net colors can be applied:

 on the schematic, then transferred to the PCB, or

 directly on the PCB, independent of the schematic.

Net Color Override can be toggled on or off in both editors using F5.

2. Applying Color to Nets in the Schematic

2.1 How to Apply Net Colors

In the schematic editor, net colors are applied via:

 View → Set Net Colors

You may select a predefined color or use Custom to choose a specific color. Click on any of
the following to apply the color:

 wire segment

 pin-connected wire

 net label

 bus

 port, sheet entry, power port, or off-sheet connector

The command remains active, allowing multiple nets to be colored sequentially.

2.2 Important Behavioral Notes

 Net Color Override must be enabled to see the color. If disabled, Altium prompts to
enable it.

 Coloring a bus applies the color to all nets within that bus.

 Color is applied to the entire net, across all schematic sheets.

 Nets between sheet symbols require a net label to carry color across sheets.

 Color is not applied directly to pins or power ports; a wire segment must exist.

 Blanket directives can be used to color all nets covered by the blanket.

 Net colors override previous colors and cannot be undone. Use:

o Clear Net Color or

o Clear All Net Colors

to remove them.

2.3 Where Schematic Net Colors Are Stored

Net colors are not stored on individual schematic objects. Instead, they are saved as net-
level data in the project file and reapplied automatically when sheets are compiled and
opened.

3. Transferring Net Colors Between Schematic and PCB

Net colors can be synchronized between schematic and PCB using:

 Design → Update

If colors do not transfer, verify that the following options are enabled:

 Comparator tab: Differences Associated with Nets → Changed Net Colors

 ECO Generation tab: Modifications Associated with Nets → Change Net Colors

4. Applying and Managing Net Colors in the PCB

4.1 Net Representation on the PCB

On the PCB, a net appears as:

 connection lines (unrouted), and

 routed tracks (physical copper).

Net colors always apply to connection lines. Routed tracks can display either:

 the layer color, or

 the net override color.

4.2 Changing Net Colors in the PCB Editor

Net colors can be defined directly in the PCB editor using the PCB panel (Nets mode):

 Select one or more nets → right-click → Change Net Color, or

 Double-click a net name to open the Edit Net dialog and set the color.

Each net’s color is shown in the PCB panel, along with a checkbox that controls whether the
color override is applied to routed tracks.

5. Displaying Net Colors on Routed Tracks

5.1 Enabling Net Color Override for Routing

To display net colors on routed tracks, all of the following must be enabled:

1. A color is assigned to the net.

2. The Color Override checkbox is enabled for that net in the PCB panel.

3. Net Color Override is globally enabled (F5).

4. Color override behavior is configured in Preferences.

5.2 Configuring Display Behavior

Color override appearance is controlled in:

 Preferences → PCB Editor → Board Insight Color Overrides

Key options include:

 Base Pattern: How net color and layer color are combined when zoomed in.

 Zoom Out Behavior:

o Base Pattern Scales

o Layer Color Dominates

o Override Color Dominates

These options allow designers to retain layer awareness while still emphasizing critical nets,
especially when zooming out in dense designs.
6. Practical Use Cases

Net Color Override is particularly effective for:

 identifying high-speed or length-matched buses

 separating power, analog, and digital domains

 reviewing routing continuity across layers

 visually debugging complex connectivity

When used consistently, net coloring significantly improves navigation, review efficiency, and
design confidence in both schematic and PCB domains.

Swapping Pins, Differential Pairs, and Sub-Parts in Altium Designer

1. Why Swapping Matters

Pin, differential-pair, and sub-part swapping can significantly improve PCB routability, reduce
congestion, and lower layer count (and cost). Because swapping affects functional intent, the
ideal workflow is collaborative: the schematic designer defines what is logically safe to swap,
and the layout engineer uses swapping tools to optimize routing without violating that
intent.

Altium’s swapping system is tightly integrated with the design database. When a swap is
performed, Altium dynamically reassigns nets on pins/pads and updates any connected
copper, enabling swaps even on partially routed nets and BGA escape patterns.

2. Types of Swapping

Altium supports three swap categories:

 Pin Swapping: swap equivalent pins within a component.

 Differential Pair Swapping: swap equivalent differential pairs within a component.

 Sub-Part (Part) Swapping: swap functionally identical sub-parts inside a multi-part

component (e.g., dual gates).

Each category is governed by swap groups, which explicitly define what is allowed to swap.

3. Swap Groups: The Core Concept

Swapping is only permitted when objects share the appropriate group attribute:

 Pin Group → governs pin swapping

 Pair Group → governs differential pair swapping

  Part Group + Sequence ID → governs sub-part swapping

Leaving a group value blank means the pin/pair/sub-part is not swappable.

4. Configuring Swap Groups (Configure Pin Swapping Dialog)

Swap group configuration is performed per component in the Configure Pin Swapping
dialog. It can be opened from either editor:

 PCB: Component Actions → Configure Pin/Part Swapping

 Schematic: Part Actions → Configure Pin Swapping

 Or through the global configuration dialogs (Tools menus) that list all components.

4.1 Pin Swapping Tab

Pins are swappable only within the same Pin Group.

Key capabilities:

 View pin status (designator, pin name, net, type, part number, etc.).

 Assign groups manually or via right-click automation (by pin name, designator, net,
bus, type, etc.).

 Add/remove multiple pins to/from groups in bulk.

4.2 Differential Pair Swapping Tab

Differential pairs are swappable only within the same Pair Group.

Key capabilities:

 View pins/pairs and assign pair groups.

 Populate pairs using schematic directives (when configured).

 Bulk add/remove pairs to groups.

4.3 Part Swapping Tab (Sub-Parts)

Part swapping is governed by:

 Part Group: which sub-parts are equivalent and allowed to swap.

 Sequence ID: which pins are equivalent between those sub-parts (prevents
input/output mix-ups).

This is essential for multi-gate logic, multi-op-amp packages, and similar “repeated function”
devices.
5. Practical Example: Dual 5-Input NOR Gate

A dual NOR gate has two equivalent sub-parts (A and B). Within each sub-part, the input
pins are interchangeable, but inputs must not swap with outputs, and sub-part A pins must
only swap with the equivalent sub-part B pins.

A correct configuration typically looks like this:

 Pin swapping

o INAx pins share one pin group (e.g., group “1”)

o INBx pins share another pin group (e.g., group “2”)

o OUT pins usually are not placed in the same group as inputs confirms
functional safety.

 Part swapping

o Sub-parts A and B share the same Part Group value (e.g., “1”)

o Sequence ID maps OUTA ↔ OUTB and INA0 ↔ INB0, INA1 ↔ INB1, etc.

6. How Swaps Are Reflected Back Into the Schematic

Swaps are executed at PCB level by swapping nets on pads and copper. When changes are
pushed back to the schematic, Altium can update the schematic in two main ways:

1. Swap pins on the symbol (pin names effectively change position)

o Always works, but may diverge from the library symbol definition.

o Can complicate future library updates and consistency across repeated

instances.

2. Swap net labels on attached wires

o Preserves the symbol as-is; better for complex ICs such as FPGAs.

o Requires that connectivity is label-based (not hard-wired pin-to-pin).

This behavior is controlled in Project Options under the “Allow pin swapping using these
methods” settings.

7. Enabling Swapping in the PCB Environment

Swapping is not “always on” during routing:

  During Interactive Routing, the Pin Swapping option must be enabled (accessed
while routing via Tab and the Properties panel).

 Per-component swapping permissions are configured in the PCB component

Properties under Swapping Options.

 For bulk management, use Tools → Pin/Part Swapping → Configure, which provides:

o per-component enable/disable for pin swap and part swap

o quick copying of settings across multiple components

o filtering to show only components that have swap data

8. Performing Swaps

8.1 Interactive Swapping (Manual, One-at-a-Time)

Commands are available under Tools → Pin/Part Swapping:

 Interactive Pin/Net Swapping

 Interactive Differential-Pair Swapping

 Interactive Part Swapping

When active, Altium masks the PCB so only swappable entities remain highlighted. The
typical workflow is:

1. Select a source pin (or a representative pin of a pair/sub-part).

2. Select a target pin (or target pair/sub-part).

Common reasons a swappable entity may not highlight include:

 it already has a routed connection (including plane/polygon connectivity), and/or

 swapping is disabled in interactive routing settings.

8.2 Automatic Pin/Net Optimizer (Batch Optimization)

The Automatic Pin/Net Optimizer runs in two stages:

 a fast single-pass optimization, then

 an optional iterative optimizer that runs multiple passes to reduce crossovers and
routing distance.

This tool is particularly effective when used repeatedly as routing progresses.

9. FPGA-Oriented Workflow: Iterative Optimization with Escape Routing

For large BGAs (FPGAs, processors), swapping is most powerful when used iteratively:

1. Initial I/O assignment (schematic-friendly labeling; often bus-ordered)

2. Initial optimization (reduce obvious crossovers)

3. Escape routing / fanout

4. Re-optimize (now the optimizer can leverage escaped routes and layer alignment)

5. Manual routing toward escape endpoints

6. Final optimization (align routed sub-nets to the closest compatible escaped pins)

7. Manual fine swaps as needed

8. Propagate changes back to schematic (often prefer net-label swapping for FPGA
bank integrity)

9. Repeat as required

For FPGA symbols split by banks into multiple schematic parts, it is usually safer to prevent
symbol pin changes and instead use net label reassignment when pushing swaps back.

10. Key Takeaways

 Swapping is only as safe as the swap group definitions that constrain it.

 Interactive swapping supports partially routed nets and BGA escapes because Altium
reassigns nets dynamically.

 The automatic optimizer enables a practical, staged routing strategy—especially for

dense FPGA designs.

 For complex multi-part symbols (notably FPGAs), prefer schematic updates by net
label swapping to preserve bank organization and library consistency.

FPGA Pin Mapper in Altium

What it is

FPGA Pin Mapper (beta, per the doc you pasted) is Altium’s bridge between:

 an external pin assignment file (usually a CSV exported from your FPGA/MC tool),
and

 the schematic component representing that device in Altium.

It lets you compare pin signal names between the two domains and then push changes
either direction:

 Pin file → schematic (update net labels / signal names on the schematic)

 Schematic → pin file (rewrite the CSV using your schematic net names)

The practical value is: you stop manually copying pin tables between Vivado/Quartus and
Altium, and you reduce the risk of mismatched assignments.

Where it fits in the workflow (especially with pin swapping)

Pin swapping in Altium needs good pin metadata and intent. For FPGAs you typically already
decide pin functions in Vivado/Quartus, then you want Altium to reflect it cleanly.

Pin Mapper helps you keep:

 FPGA tool I/O assignments

 Altium schematic net labels

synchronized.

It also supports Altium’s broader swapping flow because the point is to import pin-related
information from external tools and then use it in Altium’s swap configuration workflows
(even though advanced swap-group import is “planned” in what you pasted).

Supported sources (per your excerpt)

Direct support is described for:

 Intel/Altera Quartus (example: export CSV from Pin Planner)

 Xilinx Vivado (example: export I/O Ports as CSV)

 plus Altium Pin Info file format for broader/other devices

(Your text mentions specific tool versions as examples; in practice, the key is “CSV export of
pin assignments.”)

How you actually use it in Altium (step-by-step)

1) Export a pin file from the FPGA tool

 Quartus: Assignments → Pin Planner → Export → CSV

 Vivado: File → Export → Export I/O Ports → choose CSV

2) Open Pin Mapper from the schematic component

Right-click the schematic component part → Pin Mapping.

3) Link the external pin file

Use the browse button to select the CSV.

4) Review the mapping table and status icons

Each row/pin gets a status/action choice:

 Synced: matches already.

 Update Pin File: write schematic net names into the CSV.

 Update Schematic: change schematic net labels to match the CSV signal names.

 Ignore: don’t change anything for that pin.

 Warning: non-critical mismatch (you choose what to do).

 Fatal Error: critical mismatch; must be fixed before applying updates.

5) Apply

Choose actions (per-row or via bulk right-click actions), then Apply.

UI features that actually help you

Footprint preview

There’s a footprint preview pane that highlights selected pins and can group display by:

 Bank number

 I/O pins

 Differential pair pins

This is useful for sanity checks: “Did these bank pins get the expected signals?”

Part filtering

For multi-part symbols (FPGA banks split into parts), the “Part Selection” helps you:

 filter the table by part,

 see if a part exists on the schematic,

 see if a part is out-of-sync (red indicator in your text).

Bulk operations (important when you have hundreds of pins)

Right-click menu in the table supports bulk actions like:

 Update all pins in schematic

 Update all pins in pin file

 Ignore all

 Apply to selected pins only

 Reset to default behaviors

This matters because per-pin clicking is painful on large BGAs.

Important limitations / gotchas from your excerpt

1) It’s beta

Expect edge cases. Treat it as a “sync helper,” not an authority. You still want discipline:
recompile, check ECOs, validate.

2) Advanced swap-group import isn’t fully there yet

Your text says only general pin parameters can be copied currently; “Swap group etc is
planned.” So you may still manually set swap groups in Altium.

3) Pin Info model affects swapping editability

When a component has a Pin Info model attached:

 the Pin Group column becomes read-only in the Configure Pin Swapping dialog (to
prevent you from drifting out of sync with Pin Mapping).

If you need to manually edit pin groups inside Altium, the doc says you must:

 remove the Pin Info model from the component properties, or

 unlink/remove the external pin file from the Pin Mapper dialog.

This is a big workflow choice: “external file is the source of truth” vs “Altium is the source of
truth.”

Recommended “clean” workflow for FPGA projects

 Use Vivado/Quartus as source-of-truth for pin assignments.

 Use Pin Mapper to bring signal names into the schematic (Update Schematic).
  After big changes, rerun Pin Mapper sync before layout sign-off.

 If you plan to use Altium pin swapping heavily, decide early whether you want Pin
Info locked (external-authoritative) or you want freedom to edit swap groups inside
Altium.

Building & Maintaining Your Components and Libraries

In Altium, the real thing is the physical part you buy and solder. To use it in design, Altium
needs a component definition that collects:

 Parameters (BOM fields, ratings, manufacturer/MPN links, etc.)

 Links to domain models:

o Symbol (schematic)

o Footprint (PCB)

o 3D model (STEP/body)

o Optional: SPICE, IBIS (SI), harness models

So a component is basically a container that points to the right models + carries the right
metadata.

The 3 library “worlds” and when to use each

1) Workspace Library (Altium 365 / Enterprise Server)

Best for: teams, long-term reuse, standardized parts, traceability.

What you gain:

 Single source of truth for parts (everyone places the same vetted component)

 Where-used tracking (what designs use this part)

 Lifecycle state warnings (obsolete/EOL)

 Templates to enforce required parameters + naming/revision rules

 Model reuse (one footprint used by many components, update propagates cleanly)

 Supply chain data integration (availability/cost/alternates), BOM friendliness

Tradeoff:

 More “process”: revisions, lifecycle, approvals, roles/permissions

Use it if you care about: reliability, collaboration, repeat projects, manufacturing readiness.
2) Database Library (DbLib / SVNDbLib / DbLink)

Best for: organizations that already have a company database/ERP and want Altium tied to
it.

What you gain:

 Each database record becomes a “component record”

 Can sync parameters from the DB into placed parts / BOM

 Central control if your company already runs procurement/part masters in DB

Tradeoff:

 Setup complexity + IT ownership

 Quality depends on database discipline and mapping rules

Use it if your environment already lives in a database and you must integrate.

3) File-based libraries (SchLib / PcbLib / IntLib)

Best for: solo, small teams, quick work, offline or simple projects.

 SchLib: symbols (can be pure models or “component-like” if you add params/model

links)

 PcbLib: footprints (+ optional 3D bodies)

 IntLib: “compiled package” of your libs/models for portability/locking

Tradeoff:

 No built-in lifecycle/where-used dashboard the way Workspace does

 Easy to drift into duplicates/inconsistent parameters

 Collaboration is harder unless you enforce version control yourself

Use it if you want speed and simplicity, and you can maintain discipline.

Practical recommendation (what most people end up doing)

 If you’re serious about building a reusable library (even as one person): go

Workspace.
  If you’re doing short projects / learning / prototypes: file-based is fine, but adopt a
simple internal standard so it doesn’t become chaos.

 Database libraries are mainly for corporate ecosystems.

What “good component hygiene” looks like (regardless of library type)

Mandatory fields (minimum viable BOM correctness)

 Internal Part Number (your ID)

 Manufacturer + MPN

 Description

 Package / footprint name

 Value / rating fields (as appropriate)

 Datasheet link or file reference

 Lifecycle state (even if you do it manually)

Mandatory model checks (footprint/symbol)

Footprint:

 Correct pad sizes, solder mask expansion assumptions

 Courtyard + assembly outline

 Pin-1 marker

 Refdes placement

 3D body alignment (optional but nice)

Symbol:

 Pin numbering matches datasheet

 Pin electrical types not insane (helps ERC)

 Multi-part device correctness (banks/units)

A clean workflow you can follow

1. Start from a manufacturer part (or datasheet)

2. Create/verify footprint first (it’s the most failure-prone)

 3. Create symbol and verify pinout

4. Attach parameters (BOM-critical set)

5. Attach models (symbol/footprint/3D; optional SPICE/IBIS)

6. Run a quick validation checklist (pin-1, pad map, 3D, courtyard)

7. Publish to your chosen library system (Workspace preferred if long-term)

Creating a Schematic Symbol

1. Purpose of a Schematic Symbol

A schematic symbol is the graphical representation of a real component in the schematic

domain.
It consists of:

 Body graphics (rectangle/IEEE shape, labels)

 Pins (the electrical connection points)

In modern workflows, the component (Workspace/Component Editor) links the symbol to

footprints, parameters, and supply-chain data; the symbol itself is just the schematic
graphic + pins.

2. The 10 Rules That Prevent Most Mistakes

2.1 Pin-to-Pad Mapping Is Everything

1. Pin Designator must match the footprint pad number.

Altium maps Pin Designator → Pad number. Pin Name is human-readable;
Designator is the key.

2. Never “fix” a mismatch by renaming nets. Fix the pin designators or footprint pads.

2.2 Place Pins Correctly

3. The electrical end (hotspot) must face outward.

Wiring connects at the hotspot. If it’s inside the body, connections get messy.

4. Use consistent pin length (typically 20–30 mil equivalents) so wiring looks uniform.

5. Set Electrical Type correctly (Input/Output/I/O/Passive/Power/HiZ/Open Collector,

etc.) to avoid ERC noise or missed errors.

2.3 Keep It Placeable and Clean

 6. Draw close to the sheet origin.
Placement “holds” the symbol relative to origin; far-away drawings cause awkward
cursor offset.

7. Stay on an imperial grid unless you have a strict reason to switch. Mixed-grid
libraries cause alignment/wiring pain.

8. Do not rely on Undo to remove net color / net-level properties (some net-level
settings aren’t undoable). Use explicit clear commands if relevant.

9. Use consistent naming conventions (pin names, power pins, bank labels, etc.).
Consistency beats cleverness.

10. For multi-part components: lock or manage part packing intentionally to prevent
annotation swapping parts you didn’t want swapped.

3. Recommended Workflow (Fast, Reliable)

3.1 Pre-Setup (2 minutes)

 Jump origin to center if needed (J, O).

 Confirm grid (commonly 100 mil or 50 mil for pins/body; 10 mil for text positioning).

 Set pin defaults once (Place Pin → press Tab → set common defaults).

3.2 Create the Body

 Place a simple consistent body shape (rectangle is fine).

 Add minimal text:

o Designator placeholder (e.g., U?)

o Comment/value placeholder (e.g., component name/part number)

3.3 Add Pins

 Place pins (P, P), rotate with Space, flip as needed.

 Set:

o Designator (pad number mapping)

o Name (signal name)

o Electrical Type

 Verify hotspot direction.

3.4 High-Pin-Count Parts (Best Practice)

Use the Symbol Wizard or Smart Grid Insert:

 Prepare a spreadsheet with columns like:

Designator | Display Name | Electrical Type | Side | (optional) Description |
(optional) X | (optional) Y

 Import/paste into the pin table

 Generate clean pin blocks quickly

 Split into multi-part symbols if needed (banks/groups)

4. Multi-Part Components

4.1 When to Use Multi-Part

Use multi-part when the device has logical sections:

 Multi-gate logic (quad AND, dual op-amp)

 Big FPGAs split by banks/interfaces

 Connectors you want “distributed” across the schematic

4.2 Key Practices

 Keep parts homogeneous only if they truly are.

 Consider a dedicated power pins part and mark it so it can’t be swapped during
annotation (if applicable).

 If annotation keeps swapping parts, lock the part or control packing with a
parameter strategy.

5. Quick Validation Checklist

Before you save/release a symbol:

 Pin Designators match footprint pads

 Hotspot direction correct on all pins

 Electrical Types make sense (Power pins are Power, etc.)

 Symbol is near origin and aligns on grid

 Multi-part structure is intentional and stable

 Names/labels follow your library standard

Creating a PCB Footprint
1. What a PCB Footprint Is

A PCB footprint is the physical landing pattern for a component on the board. It defines:

 Pads (electrical connection points)

 Mechanical/overlay outlines (silk + assembly + courtyard intent)

 Optional: 3D body / STEP

 Optional: special strings and mechanical features (glue dots, keepouts, route paths,
etc.)

Critical concept: the schematic symbol pin Designator must match the footprint pad
Designator (pin→pad mapping).

2. The Core Workflow (Manual, Reliable)

Step 1 — Prepare the design space

 Jump to footprint reference point (J, R) and build around it.

 Set units and grids:

o Use Ctrl+G (grid editor), Q toggles imperial/metric.

o Use a custom grid matched to the package pitch.

 Enable Heads-Up display if useful (Shift+H) to see coordinates/deltas.

Best practice: decide where “pick-up point” is:

 Pin 1 (common for ICs/connectors), or

 Center (often better for symmetric packages)

If you already drew everything, you can set it later:

 Edit → Set Reference → Pin 1 / Center / Location

(This redefines 0,0 and updates primitives accordingly.)

Step 2 — Place pads (the most important step)

 Place → Pad

 Before placing the first pad, press Tab to set defaults:

o Pad designator (auto-increments)

 o Size/shape

o Layer:

 SMD: Top Layer

 Through-hole: Multi-Layer (+ hole size)

o (Usually) don’t hardcode mask expansions unless you must.

Accuracy tactics

 Use arrow keys to nudge by grid step (Shift = 10× step).

 For exact placement, edit pad X/Y in Properties.

 Measure distances: Ctrl+M (Reports → Measure Distance)

Irregular pads / exposed pads

 Use custom pad shapes or Regions if required.

 For thermal pads: consider paste patterning (often split paste).

Multiple pads tied to one schematic pin

 Allowed: give multiple pads the same designator (example: SOT-223 pin 2 has two
pads marked “2”). This makes them share the same net after ECO.

Step 3 — Add outline & mechanical layers (clean DFM)

Use layers intentionally:

 Top Overlay (silk): minimal, readable, avoid pads/holes.

 Mechanical layers: assembly outline, courtyard, cutouts, special features.

 If the part overhangs a cutout: put the true outline on a mechanical layer (common).

Silkscreen cleanup

 Tools → Silkscreen Preparation

o Clip to exposed copper / solder mask openings

o Enforce clearance

o Move text if needed

This prevents common fab/assembly complaints.

Step 4 — Add 3D (optional but recommended)

  Place a 3D Body and link/import a STEP/Parasolid model.

 Alternatively, set a simple Height value, but 3D is better for collisions.

Step 5 — Footprint properties

 Set footprint Name/Description

 Optionally add footprint parameters (if your setup uses them)

 Remember: when placed on PCB, Designator/Comment strings are auto-added, but

you can add extra .Designator / .Comment special strings on mechanical layers for
assembly drawings.

3. Mask Expansion: The Safe Default

Default approach:

 Let design rules control solder/paste mask expansions on the target PCB.

 Only override at pad level when:

o special paste aperture is needed,

o unusual solder mask definition is required,

o rule targeting is impossible.

To visually verify masks in the footprint editor:

 View Configuration → enable mask layers display.

4. Special Case You Must Understand: Layer Pairs

Some mechanical features must “follow the side” when the component flips (top ↔
bottom):

 glue dots

 peelable mask

 special assembly markings

Altium handles this via Layer Pairs (set in PCB editor, not footprint editor):

 If you flip a component without layer pairs, mechanical objects may not transfer as
intended.
  If you define layer pairs after flipping, behavior can be confusing; updating from
library can refresh.

5. Wizards: When to Use Which

IPC Compliant Footprint Wizard

Use when:

 you want IPC-7351B compliant land patterns quickly

 you want density variants (_L, _N, _M)

 you want consistent pad sizing/fillets from package dimensions

Footprint Wizard

Use when:

 you want fast “good enough” generation based on footprint-level dims

 simpler packages, less IPC-driven control

Professional habit: still verify wizard output against the datasheet.

6. Final Checklist (What Pros Always Verify)

 Pad count and numbering order

 Pin 1 marker + orientation is unambiguous

 Pad pitch and body outline match datasheet

 Courtyard/assembly outlines are reasonable

 Silk doesn’t violate solder mask openings (run silkscreen prep)

 Exposed pad paste strategy makes sense

 3D alignment and height are correct

 Reference point choice is consistent with your library standard

Database Libraries in Altium Designer (DbLink, DbLib, SVNDbLib)

1) Purpose and When to Use

Database Libraries let you browse, place, and maintain components from a company
database (Access/SQL/etc.) inside Altium Designer. They are mainly used when your
organization wants:
  A single source of truth for component parameters (MPN, value, tolerance, voltage,
lifecycle, etc.)

 Controlled synchronization of those parameters into schematics/PCB and BOM

output

 A workflow that can range from “link only” to “generate components dynamically at
placement time”

Altium’s modern alternative is Workspace Library components (Altium 365 / Enterprise

Server), which adds lifecycle/revisions and deeper supply-chain integration. Database
Libraries are still valid when a company’s component management is database-centered
and/or tied to legacy processes.

2) The Three Database-Based Approaches (What’s the Difference?)

A) DbLink (*.DbLink) — Link an existing Altium component to a database record

Concept: You already have a normal Altium component (symbol + models + parameters),
and you use DbLink to link it to a record in your database.

Key traits

 Symbol + footprint + other models are defined in the Altium library component

 Database is primarily used for parameter synchronization

 Match is done via a key field (e.g., PartNumber) or a Where clause

 Common pattern: one database record ↔ one Altium component, though it can be
designed otherwise

Use DbLink when

 You want database-driven parameters but still want Altium libraries to “own” the
models

 You want minimal disruption to established .SchLib/.PcbLib/.IntLib style libraries

B) DbLib (*.DbLib) — Place components directly from database (dynamic component

creation)

Concept: DbLib turns the database into a placeable library. When you place a part, Altium
creates the component on-the-fly using mapped fields.

Key traits

 The underlying schematic library symbol (*.SchLib) is typically symbol-only

  The database record contains the mapping to:

o symbol reference

o footprint reference(s)

o parameters

 Placement happens through the Components panel as a database browser

 Very suitable for many database records → one symbol, because the symbol is
generic and the record defines specifics

Use DbLib when

 Your organization wants the database record to “own” the mapping to

models/parameters

 You want direct placement of a company-controlled catalog without maintaining

separate unique Altium components for each MPN

C) SVNDbLib (*.SVNDbLib) — DbLib plus version-controlled model sources (SVN)

Concept: Same database-driven placement model as DbLib, but the referenced

symbol/footprint model source files are stored under Subversion (SVN).

Key traits

 Database provides the param/model mapping

 SVN repository stores symbol and footprint libraries (often one symbol/model per
file)

 Supports “Librarian vs Designer” workflows:

o Librarian maintains repo structure, mapping, and the SVNDbLib definition

o Designer installs/uses the SVNDbLib for browsing/placing parts

 Practical for organizations that require version control and traceability of library
source artifacts

Use SVNDbLib when

 You need DbLib behavior and you need the library sources under formal VCS control

 Your company already has SVN infrastructure and governance

3) Placement and Updates: What Actually Gets Synchronized?

After placing database-based components, you typically manage updates via:

 Tools » Update Parameters From Database

Updates the placed component’s parameter values from the database record.

 Tools » Update From Libraries

Performs broader updates, potentially including symbol/footprint references and
parameters, depending on how the library and linking are set up.

Database values can also flow into:

 BOM output, enabling procurement-ready data

 Design parameter synchronization across schematic/PCB, depending on workflow

 Dimensions are entered/processed in metric units (mm).

5) Reusing Footprints from Other Sources

Footprints can be copied into a library from:

 A PCB document (copy in PCB → paste into open *.PcbLib)

 Another PCB library (copy/paste via PCB Library editor)

 Multi-select copy/paste from the PCB Library panel list

Altium marks pasted duplicates with suffixes like DUPLICATE, DUPLICATE1, etc. This is useful
as a warning but should be cleaned up by renaming and validating.

Workspace link note

If a footprint originated from a connected Workspace (or Manufacturer Part Search), library
items can retain server links. The library editor includes Tools → Clear Server Links to
remove those references when appropriate.

6) Validating Footprints and Producing Reports

Library List

 Reports → Library List

Generates a *.REP summary listing all footprints in the library and total counts.

Library Report

 Reports → Library Report

Generates a Word (*.doc) or HTML (*.html) report. Can include footprint previews.
Component Rule Checker (PCB Library)

 Reports → Component Rule Check (R, R)

Runs checks for issues such as:

 duplicate primitives

 missing pad designators

 floating copper

 inappropriate component reference

Outputs an .ERR report listing violations per footprint.

This is the fastest way to catch structural issues before the footprint spreads across multiple
boards.

7) Updating Footprints Used on Boards: Push vs Pull

Footprint updates can be applied to placed instances in two different strategies:

A) Push updates from the PCB Library (replace from source)

From the PCB Library editor:

 Tools → Update PCB with Current Footprint

 Tools → Update PCB with All Footprints

(or via PCB Library panel right-click)

This updates all open PCB documents containing those footprints, using selectable update
options for primitives/attributes.

Best when:

 You want a straightforward replacement

 You trust the library as the source of truth

B) Pull updates from the PCB Editor (review differences)

From the PCB editor:

 Tools → Update From PCB Libraries

This path is preferable when:

 You need to review what changed

 You want selective updates (object-by-object or attribute-level control)

8) PCB Library Panel (Core Workflow Tool)

The PCB Library panel is the primary browser/editor interface for footprints and their
primitives.

It provides three scopes:

1. Footprints list: shows footprints plus counts of pads and primitives

2. Footprint Primitives: lists the objects in the selected footprint with key properties
(type, sizes, layer, designators)

3. Mini-viewer (Other): a simplified navigation view with current viewport indicated

Filtering and navigation

 Indirect filtering: Mask field at top (supports wildcards *)

 Direct filtering: type-ahead while the list is focused

 You can combine both for fast targeting in large libraries

Visual focus controls (important for editing)

Panel highlight modes:

 Mask: hides/unselects all non-filtered objects (strong isolation)

 Dim: keeps context visible but visually de-emphasized

 Normal: no special contrast

Additional toggles:

 Select / Zoom / Clear Existing filter behavior

 Clear button is required to remove persistent filtering (clicking in editor does not
clear it)

9) Operational Constraints to Know

 Footprints cannot be edited inside an Integrated Library (*.IntLib) directly.

 To edit an IntLib footprint:

1. Decompile/extract source libraries

2. Edit the footprint in the source *.PcbLib

3. Recompile to produce an updated IntLib

This matters in team environments where IntLib is used as a distribution artifact.

10) Recommended Practice (File-based Workflow)

 Rename placeholder footprints immediately and enforce a naming convention.

 Run Component Rule Check before using a footprint in a real board.

 Prefer pull + review when updating footprints on an already-routed PCB, unless you
explicitly want full replacement.

 Keep IPC generator inputs (Excel/CSV) version-controlled if footprints are generated

from templates.

Integrated Libraries (*.IntLib) in Altium Designer

1) What an Integrated Library Is

An Integrated Library (*.IntLib) is a single, portable file that packages complete Altium
components using Altium’s Integrated Component model:

 The component “definition” is centered in the schematic library (*.SchLib) as a

symbol plus:

o links to domain models (footprints, simulation, SI, etc.)

o component parameters (BOM and identification data)

 All required source libraries and models are gathered through an Integrated Library
Package project (*.LibPkg)

 The *.LibPkg is compiled into a single deliverable: the *.IntLib

In practice, an IntLib is a distribution artifact: you place from it, but you do not edit it
directly.

2) Why Teams Use IntLibs (Key Benefits)

Integrated Libraries exist mainly to solve reliability and portability problems that occur with
separate file-based models.

Portability

 All component information is contained in one file, so moving a project between

folders, PCs, or workstations is simpler.

Model link robustness

 Components placed from an IntLib can reliably retrieve their linked models from the
same IntLib, avoiding “broken links” caused by renamed folders, moved model files,
or missing search paths.
Integrity and validation

 During compilation, Altium checks availability and correctness, including pin

mapping consistency between symbol pins and footprint pads (and other model
mapping rules where applicable).

Security and change control

 Once generated, an IntLib is effectively immutable: updating it means modifying the

sources and recompiling a new IntLib (replacing the old file).

Practical takeaway: even if you still prefer placing directly from *.SchLib / *.PcbLib, compiling
an IntLib is a strong validation step to catch mapping issues early.

3) The IntLib Build Artifact: *.LibPkg (Integrated Library Package)

A Library Package (*.LibPkg) is the project container used to assemble sources and define
how models are found at compile time.

What must be in the LibPkg

 At minimum: one or more schematic libraries (*.SchLib) that contain the

components.

What may also be included

 PCB libraries (*.PcbLib) for footprints (2D + 3D bodies)

 Simulation model files (*.mdl, *.ckt)

 Signal integrity models, etc.

Important limitation noted

 SPICE models from *.LIB libraries are not currently added to compiled integrated
libraries.

4) Standard Workflow: Creating an IntLib Using a LibPkg

Step 1 — Create the Library Package

 File → New → Library → Integrated Library

This creates a new *.LibPkg shell project.

Step 2 — Create and Add Source Schematic Libraries (*.SchLib)

Build or collect components in a schematic library:

 Create from scratch (new SchLib and build symbols)

  Add new SchLib directly under the LibPkg

 Generate from an existing design using Design → Make Schematic Library (archives
placed parts)

Then add the SchLib(s) to the LibPkg (Add Existing to Project).

Step 3 — Create and Provide Domain Models (Footprints, Simulation, etc.)

Create or gather model files referenced by the schematic components:

 Footprints in *.PcbLib (and 3D bodies inside footprints)

 Simulation models/subcircuits in *.mdl and *.ckt

You can generate a footprint library from an existing PCB via Design → Make PCB Library.

Step 4 — Ensure Models Can Be Found (Model Availability Strategy)

Altium uses a consistent model resolution strategy. You typically choose one (or combine
them) based on your workflow:

1. Add libraries/models to the LibPkg project

Best when you want everything visible and tightly controlled in the project.

2. Install libraries/models in the Installed Libraries list

Best when a common model set should be available to many projects.

3. Define Search Paths

Best when models live in standardized folders (e.g., simulation model directories)
and you do not want them cluttering the project.

Search paths are evaluated in order; use refresh/verification to confirm models are detected.

Note: Access to some search path UI options may require enabling an advanced preference
option and restarting Altium (as described in the excerpt).

Step 5 — Compile and Validate

 Project → Compile Integrated Library

Compilation produces:

 (<LibraryPackageName>.IntLib) in the configured output folder (default under a

Project Outputs folder)

During compile, check the Messages panel for:

 Missing models

 Pin mapping mismatches (e.g., mapping to pads 1/2 when footprint pads are A/K)

 Any warnings/errors driven by your Error Reporting settings

Fix problems in source libraries and recompile.

5) Creating an IntLib Directly From a Project (Design Archive Path)

You can also generate an IntLib from an existing design project via Make Integrated Library
(from schematic or PCB editor). The process effectively automates:

 Make a schematic library from all schematics

 Make a PCB library from the PCB document

 Compile into <ProjectName>.IntLib

If components share the same library reference but differ internally, Altium prompts how to
handle duplicates (ignore others, rename all uniquely, or abort).

This approach is ideal for:

 Freezing a “working library” snapshot of a completed design

 Sharing a project with a self-contained component set

6) Creating an Offline IntLib From Database Libraries (DbLib / SVNDbLib)

If your organization uses Database Libraries (DbLib/SVNDbLib) but designers need an offline
deliverable, Altium supports conversion using the Offline Integrated Library Maker.

Key characteristics:

 Conversion is performed per database table

 A separate IntLib is generated for each included table

 The wizard creates a temporary LibPkg, generates SchLib and PcbLib content from
table records, then compiles to IntLib

 Output is organized into subfolders named after each table

This approach allows librarians to maintain database-driven truth, while designers place
from regenerated “offline” IntLibs.

7) Creating an IntLib From Workspace Components (Content Cart Acquisition)

You can also acquire components from a connected Workspace into an IntLib using the
Content Cart workflow:

 Set the cart target to an IntLib file

  Choose output location/name

 The system generates a temporary LibPkg (with generated SchLib and PcbLib) and
compiles an IntLib

 The produced IntLib is added to Installed Libraries

Notably, when placing from such an IntLib, the design may still maintain links back to the
Workspace components (offline usage with a retained connection concept).

8) Placing Components From an IntLib

Placement is done via the Components panel:

 Select the *.IntLib in the panel

 Place via right-click “Place …” (multi-place placement mode until Esc/right-click)

 Or drag-and-drop (single-shot feel)

Important behavioral difference:

 Components placed from an IntLib will seek their models from that IntLib.

 Components placed from raw SchLib do not automatically gain access to models
stored only inside an IntLib.

9) Modifying and De-compiling IntLibs

Modifying (the normal way)

You cannot edit an IntLib directly. The correct workflow is:

1. Open the source *.LibPkg

2. Edit source SchLib / PcbLib / model files

3. Recompile to generate a replacement IntLib

De-compiling (when you don’t have the sources)

If the original LibPkg is missing, you can extract sources from an IntLib:

 Open the IntLib → Extract

Result:

 A new folder is created (named after the IntLib) containing extracted SchLib/PcbLib
sources
  A LibPkg is created and populated with extracted symbol and PCB libraries

 Simulation .mdl / .ckt files are not automatically added, but a search path to the
extracted folder is added so models can be found

The extracted LibPkg is not automatically saved; you decide where and under what name to
save it.

10) Recommended Use Patterns

 Use IntLibs when you need portable, shareable, robust component delivery.

 Compile frequently as a validation gate (model availability + pin mapping

correctness), even if you ultimately place from discrete libraries.

 Treat the LibPkg as the editable “source of truth” and the IntLib as a versioned
deliverable.

Laying Out Your PCB

PCB Environment Setup
This page is basically: “Before you start placing parts and routing, set the PCB document’s
coordinate system, units, grids/snaps, and viewing filters so you don’t fight the tool for the
next 50 hours.”

1) What “PCB Environment Setup” really means

When you create a new PCB (File → New → PCB), you’re not designing yet—you’re
configuring the editing physics of the PCB editor:

 What can be selected (selection filter)

 Where the cursor snaps (grid, guides, hotspots, axis alignment)

 How the board is measured / reported (units, origin, board info)

 How you manage placement grids & guides (Grid Manager, Guide Manager)

 How objects and layers are shown (visibility and view config)

Most of this is done in the Properties panel in Board mode (i.e., nothing selected).

2) Selection Filter (stop “why can’t I click this?” problems)

This is a hard gate: it decides which object types are selectable.

  All – On: removes filtering (everything selectable)

 Individual object toggles: make object types non-selectable when you want to avoid
accidental edits (common when routing around text/regions/rooms)

Practical use:

 While routing: disable selecting components / rooms / regions so you only grab
tracks/vias.

 While moving placement: disable selecting tracks/vias to avoid dragging routing by

mistake.

3) Snap Options (the “cursor behavior engine”)

A) Snap to Grid

 Grids toggle: snaps to the active snap grid.

 If you place parts slightly off-grid, you can get misalignment cascades later.

B) Snap to Guides and Points

 Guides toggle: snaps to manually placed snap guides/points (overrides grid).

 Use this for mechanical constraints, connector alignment, edge-to-edge spacing.

C) Axis snap (X/Y alignment “magnet”)

 Axes toggle + Axis Snap Range

 Lets you align objects horizontally/vertically to other objects even if off-grid

 Shows a dynamic guide line when alignment triggers

D) Snapping to object hotspots (Unified Cursor-Snap idea)

 Snapping mode:

o All Layers: snap to hotspots on any visible layer

o Current Layer: only snap to the currently active layer

o Off: no hotspot snapping

 For each object type: enable snapping + set Snap Distance

Practical settings (typical):

 Placement phase: All Layers can be useful

 Dense routing: often safer to use Current Layer to reduce “snap surprises”
4) Board Information (sanity metrics + reports)

Board mode shows:

 Board Size (X/Y), Area

 Components Area and Density

o Density uses the “courtyard-derived” selection area logic (courtyard → else

silk/3D/copper shapes; excludes strings).

Also includes Board Report generation with a lot of manufacturing-style breakdowns:

 primitives per layer, via layer pairs, copper area by layer, hole size distributions,
annular rings, mask expansions, track widths, routing completion, etc.

When it matters:

 You’re preparing for DFM review

 You want quick stats before fab (e.g., “what hole sizes exist?”, “how many unique
track widths?”)

 You’re trying to spot accidental “odd” values (like one random 3.1416 mil track)

5) Grid Manager (multiple local grids with priorities)

This is bigger than “one grid size”:

 You can define multiple grids (Cartesian / Polar) and assign priority.

 You can apply grids to:

o Comp (components only)

o Non Comp (everything else)

Why it’s powerful:

 You can place components on a clean grid (e.g., 0.25 mm) while routing uses a tighter
grid (e.g., 0.05 mm), without constantly changing settings.

6) Guide Manager (snap guides & snap points)

 Lets you define and manage:

o horizontal/vertical guides
 o ±45° guides

o snap points (manual hotspots)

Two ways:

 Add (numerically / via fields)

 Place (interactive placement)

Visibility note:

 Guides are visible only if Show Grid is enabled in View configuration.

Use cases:

 Align connector rows, mounting holes, keepouts

 Enforce consistent margins from board edge

 Create repeatable mechanical alignment structure

7) “Other” board-level settings that bite later

Units

 Sets default measurement units for display/reporting.

 Shortcuts:

o Q toggles mm/mil in the design space

o Ctrl+Q toggles units inside dialogs/panels

Best habit:

 Always type explicit units when critical (e.g., 0.2mm, 8mil) to avoid accidental
assumptions.

Polygon Naming Scheme

Controls auto polygon names based on net/layer/index.

Important because:

 Rule targeting and debugging polygons becomes easier when names are predictable.

 Renaming nets or moving layer order can auto-change polygon names (and rules
update with it).

Designator Display (Physical vs Logical)

For multi-channel designs:

  Physical: unique, e.g., R1_CH1

 Logical: schematic-style R1 (not unique)

This affects how readable the PCB is, but can require extra channel annotation on the board
if you go logical.

Sheet Settings

The PCB “sheet” is like a drawing area for notes/title blocks/dimensions.

 Not the board shape itself.

 Useful when you want documentation elements tied to sheet visibility.

8) Properties panel behavior when an object is selected

Once you click an object, the Properties panel switches from Board mode to that object’s
properties (Track, Via, Pad, Polygon, etc.).
This is why “Board setup” feels hidden: you must click empty space to return to board mode.

9) A practical 2-minute setup checklist (what I’d do every new PCB)

1. Click empty space → Board mode confirmed

2. Set Units (mm or mil) and stick with it

3. Set Snapping:

o Grid ON

o Guides ON (if you plan mechanical alignment)

o Hotspot snapping = Current Layer (often safer during routing)

4. Create two grids:

o Component grid (coarser) → Comp only

o Routing grid (finer) → Non Comp only

5. Add key Guides:

o Board edge offsets

o Connector alignment axes

o Mounting hole axis lines

6. Set Selection Filter based on phase:

 o placement: avoid selecting tracks

o routing: avoid selecting components/text/regions

7. Generate Board Information report once mid-design to catch weird outliers (track
widths, drill sizes, mask expansions)

Board Insight System

The Board Insight System is Altium Designer’s unified set of tools for understanding,
navigating, and controlling visibility in dense, multi-layer PCB designs. Its purpose is not
editing, but clarity—helping you see the right information at the right time without hiding
critical context.

1) What Board Insight Solves

Modern PCBs contain thousands of overlapping objects across many layers. Even
experienced designers struggle with:

 Identifying objects under the cursor

 Understanding routing and net connectivity

 Inspecting rule violations in dense areas

 Navigating layers without losing context

Board Insight addresses this through interactive inspection, live feedback, and controlled
highlighting, all integrated into the PCB editor.

2) Board Insight Pop-up Mode (Object & Violation Inspection)

Browse Objects – Shift + X

Displays a hierarchical pop-up of:

 Components

 Nets

 Primitives (pads, tracks, vias, etc.)

located under the cursor.

You can:

 Open properties

 Select the object

  Zoom directly to it

This is cursor-based and works best via shortcut (not menu).

Browse Violations – Shift + V

Shows design rule violations under the cursor:

 Violations are grouped hierarchically

 You can drill down to affected primitives

 Direct access to violation details, selection, and zoom

This is one of the fastest ways to debug DRC issues locally.

3) Visual Pick List (Precise Selection in Crowded Areas)

When multiple objects overlap:

 Double-click to open the Visual Pick List

 Objects are listed by layer

 Hovering highlights the object visually

Locked primitives inside components are marked, making it clear why something cannot be
selected or edited.

This eliminates guesswork when clicking in dense routing regions.

4) Heads Up Display (HUD)

The Heads Up Display provides real-time, on-screen information about the cursor and
nearby objects.

Typical information shown:

 Cursor coordinates

 Delta distances (dx, dy)

 Active layer

 Active snap grid

 Net, component, and primitive details

 Rule violations (in hover mode)

Key controls:
  Toggle HUD: Shift + H

 Toggle tracking (fixed vs follows cursor): Shift + G

 Reset delta origin: Insert

 Toggle delta display: Shift + D

The HUD can be:

 Fixed in place

 Cursor-relative

 Configured in content, font, and color

All configuration is done via

Preferences → PCB Editor → Board Insight Modes

5) Live Highlighting (Net Visibility)

Live Highlighting helps you visually isolate routing.

Static highlighting

 Ctrl + Click on a net

 Everything else dims

 Multiple nets can be highlighted using Shift + Ctrl + Click

 Clear by Ctrl+Clicking empty space

Dynamic highlighting

 Nets highlight automatically as the cursor passes over them

 Uses outline-style highlighting

 Does not dim the rest of the board

This is essential for:

 Tracing signal paths

 Verifying continuity across layers

 Debugging dense routing

Configured via
Preferences → PCB Editor → Board Insight Display
6) Active Layer Control

Only one layer is active at a time in 2D mode.

Ways to change it:

 Layer tabs at the bottom

 Active Layer dropdown (View Configuration panel)

 Keyboard shortcuts:

o Ctrl + Shift + Mouse Wheel

o + / - (numeric keypad)

o * (next signal layer)

Active layer control directly affects:

 Routing

 Snapping

 Object interaction

7) Net Names on Tracks

You can display net names directly on routed tracks:

 Enabled via View Configuration → Additional Options

 Net names repeat along the routing

This allows instant visual confirmation of signal identity without cross-probing or

highlighting.

8) Pad and Via Detail Display

Board Insight allows detailed control over:

 Pad and via text

 Font, color, and background

 Automatic right-reading orientation

 Smart contrast for readability

Configured via
Preferences → PCB Editor → Board Insight Display
This is especially useful during:

 DFM checks

 Drill and via audits

 Manual inspection of power structures

9) Locked Object Visualization

Locked objects can be visually marked using textures:

 Always visible

 Or visible only during live highlighting

This prevents confusion when objects appear selectable but cannot be edited.

10) 3D Board Insight

In 3D mode, Board Insight extends to projection control:

 Orthographic: exact geometry, no perspective distortion

 Perspective: realistic depth and visual context

Projection mode is selected via the View Configuration panel while in 3D view.

11) Scope and Persistence

Board Insight settings:

 Apply globally to all PCB and PCB library documents

 Affect viewing and interaction, not design data

 Are critical for long-term productivity on complex boards

Key Takeaway

The Board Insight System is not optional polish—it is a core navigation and comprehension
layer for professional PCB design. Mastery of:

 Pop-up inspection

 HUD usage
  Live highlighting

 Layer control

directly translates to faster debugging, fewer mistakes, and less visual fatigue on complex
boards.

Shortcuts
Wherever you are in the environment, over a menu command, a dialog, a panel, or a design
object, press F1 to display comprehensive information about whatever was under the cursor.

While you are running a command, for example, during Interactive Routing, press Shift+F1 to
display a list of in-command shortcuts.

You can also re-position a selected schematic object or a group of objects using the arrow
keys on the keyboard. Select the objects then press an arrow key while holding down
the Ctrl key. Hold Shift as well to move objects by 10 times the current snap grid.

Right-Click – drop the current connection and remain in interactive routing mode. Right-
Click again to exit interactive routing mode.

Among other standard methods of accessing a panel, the Properties panel can be accessed
by double-clicking on an object in the design space or using the F11 keyboard shortcut.

Using the commands of the Edit » Jump sub-menu from the main menus of the schematic,
schematic symbol, PCB or PCB footprint editor, you can jump to a specific point in the active
document. The Jump pop-up menu also can be accessed by pressing the J key in the design
space.

Alt + Double Click to see the tree and preview. Hover over a net + press Ctrl + Alt. Opens a
selectable connectivity tree. Click any entry to jump directly to that sheet

Use the F4 shortcut to toggle the display of all panels that are currently in 'floating' mode.
Upon pressing F4, all currently floating panels will either disappear or reappear, depending
on whether they are currently visible or not.

The fastest way to add or edit the shortcut(s) assigned to a command is to Ctrl+click on the
entry for that command on the relevant menu or toolbar. This will open the Edit
Command dialog, from where you can add a shortcut or edit the currently assigned one.

Ctrl+Click on a main menu or sub-menu entry, to access the Edit Drop Down
Menu dialog. Ctrl+Click on a command entry to access the Edit Command dialog. Add
the & character at the required position before that letter within the defined Caption for an
accelerator key. Within any given menu or sub-menu, a particular letter can be used only
once as an accelerator key.
Strictly speaking, access to a root main menu through its accelerator key requires holding
down the Alt key. This is because the same key may also be assigned to a pop-up menu. So
for example, access to the Simulate menu in the Schematic Editor (with the Mixed
Simulation system extension installed) would, at first sight, look to be a case of clicking
the S key. However, while this is the menu's defined accelerator key, doing so will pop-up
the Select sub-menu (from the main Edit menu). By using Alt+S, the
intended Simulate menu is accessed.

In many cases, a main menu will also have a pop-up key assigned (and typically the same key
as its accelerator). Where this is the case, using that key will access the menu in pop-up
form. For example, the Design menu in the PCB Editor can strictly be accessed using Alt+D,
but also in pop-up form using D. This functionality is defined for a menu in the Edit Drop
Down Menu dialog, by using the Popup Key field.

Ctrl + Shift + Mouse Wheel to change layer in PCB editor.

Press the Alt key while moving, to constrain the direction of movement to the horizontal or
vertical axis, depending on the initial direction of movement.

Not unlike the Link parameter, the HelpURL parameter allows the definition of a link from a
component to an external document, such as a PDF, or web page URL. When added as a
component parameter, this link is activated when the F1 key is pressed over the component
on the schematic sheet or when that component is selected in the Libraries panel. Note that
this action will override the normal F1 key feature, which links to the relevant page in the
Altium online documentation.

The net connectivity throughout a design can also be highlighted in all schematics by holding
the Alt key when selecting a net by clicking on a wire (Alt+Click).

You can quickly convert a 4-way junction (created with wire or bus objects), into two
adjacent 3-way junctions. To do this, select the Tools » Convert » Convert Cross
Junctions command from the main menus. After launching the command, the Junctions
Conversion dialog will appear. Use this dialog to determine the scope of the conversion
(current document, project documents, or all open schematic documents), and whether all
potential 4-way junctions are considered, or only those associated to selected wires/busses
in the target documents. Once conversion options are configured as desired, clicking OK in
the dialog will effect conversion.

If you hover over a netLabel and press Insert, when you are placing another netlabel. Its
name becomes the name of hovered over netlabel.

General schematics editing -> Ctrl+R: Copy selected object(s) and paste repeatedly where
needed in the design space (rubber stamping).

General schematics editing -> Shift+Ctrl+V: Access the Smart Paste dialog.
Ctrl+Y: Redo

Shift+F: Access the Find Similar Objects feature (click on an object to use as the base
template).

Shift+Ctrl+X: Toggle Cross Select Mode On or Off.

Shift+Ctrl+Y:Toggle the Cross Select Mode's Reposition selected component in PCB option
On or Off.

Aligning

Shift+Ctrl+L Align selected objects by their left edges.

Shift+Ctrl+R Align selected objects by their right edges.

Shift+Ctrl+H Make the horizontal spacing of selected objects equal.

Shift+Ctrl+T Align selected objects by their top edges.

Shift+Ctrl+B Align selected objects by their bottom edges.

Shift+Ctrl+V Make the vertical spacing of selected objects equal. ???SMART PASTE
ILE AYNI

Shift+Ctrl+D Move selected objects to the nearest point on the current snap grid.

Spacebar Rotate selection counterclockwise by 90°.

Shift+Spaceba Rotate selection clockwise by 90°.
r

Miscellaneous

Ctrl+Double-  On a Sheet Entry to jump to the corresponding port on the sub-

Click sheet referenced by that entry's parent Sheet Symbol.

 On a Port to jump to the corresponding sheet entry in the parent

sheet symbol that references the sub-sheet on which the port
resides.

 On a port to jump to another port with the same name, on the

indicated target schematic document (only available when
the Net Identifier Scope - set on the Options tab of
the Project Options dialog - is set to Flat, or Global).

 On a sheet symbol to descend the design hierarchy to open the

child sheet referenced by that symbol.

Ctrl+L Perform Board Level Annotation through use of the Board Level
Annotate dialog.

Shi When auto-panning while placing/moving an object, use to pan at higher speed.
ft
 S Relocate the currently selected Sheet Entry (or entries) that are being moved, to the
directly opposite side of the parent Sheet Symbol.

V Reverse order while moving two or more selected Sheet Entries.

T  Toggle IO Type while moving one or more selected Sheet Entries.

 Toggle IO Type for all Sheet Entries while graphically resizing the parent Sheet
Symbol.

Pop-up Menu Shortcuts

The following shortcuts give access to specific pop-up menus of commands, directly from
within the design space itself. Some of these will be familiar as they are sub-menus found
within the main menus for the editor. Each of the main menus also have a defined pop-up
key for quick access from within the design space, see Accelerator Keys for more
information.

A The Align sub-menu (from the main Edit menu).

B The Toolbars sub-menu (from the main View menu).

J The Jump sub-menu (from the main Edit menu).

K The Panels sub-menu (from the main View menu).

M The Move sub-menu (from the main Edit menu).

 O A pop-up menu offering quick access to options and preferences.

S The Select sub-menu (from the main Edit menu).

X The DeSelect sub-menu (from the main Edit menu).

Y A pop-up menu with filtering commands.

Z A pop-up menu with zoom commands.

Show/Hide Ratsnest Connections and Jumpers ("N" in PCB Editor)

Keyboard shortcut Function Accessed in

Ctrl + Alt + O Access the Open Project Layout or schematic

Documents dialog for the current
project

2 or 3 Toggles between 2D view and 3D Layout

view

0 and 9 Rotates the view of the board by 3D mode only

90 degrees clockwise or counter-
clockwise

TAB while routing, Displays the appropriate Layout

length tuning, or interactive editing dialog
placement

C Brings up the right-click menu Layout or schematic

 from the Projects Panel

Shift + R Cycles through three the ignore, Layout

avoid, or push obstacle routing
modes

Shift + E Toggles the electrical grid on/off Layout

G or Ctrl + G Toggle grid snap options Layout

L while dragging a Flips component to the other side Layout

component of the board

Ctrl + F Flips the board to the other side Layout and 3D mode

Spacebar while Rotates the component by 90 Layout or schematic

dragging a degrees
component

J followed by C Opens the Component Designator Layout or schematic

dialog. Enter a component
designator, and the editor will
move the view to that
component.

 Choose the Tools » Select PCB Components command.

Clear the Press Shift+C to clear the current highlighting across all affected sheets.
results Note that selection is not cleared using this shortcut, use the X, D shortcut
key sequence to clear selections across all sheets.

During Interactive Navigation, hold the Alt key as you click on an object on the schematic
to simultaneously navigate to that object on the PCB. ON NAVIGATOR SCREEN, USING
INTERACTIVE ROUTING.
Parameters are a key element of each component, and it is common for many of the
parameters to be used across multiple components. As well as adding them individually to
each component, you can also use the Parameter Manager command (Tools » Parameter
Manager) to add them to multiple components. As well as adding and removing parameters,
the values of parameters can also be edited across multiple components.

BUNLAR HARBİ KIYAK

Press Shift+Spacebar to cycle through the five available corner modes: 45 degree, 45
degree with arc, 90 degree, 90 degree with arc, and Any Angle.

Press Spacebar to toggle between the two corner direction sub-modes.

When in either of the arc corner modes, hold the "," or "." keys to shrink or grow the arc.
Hold the Shift key as you press to accelerate arc resizing.

When moving a vertex, use Shift+Spacebar to change modes.

Ctrl+Click anywhere along an edge away from editing handles to insert a new end vertex.

Sometimes, the feature pulls the cursor when you do not want it to. In this situation, press
the Ctrl key to temporarily inhibit snapping. Alternatively, use the Shift+E shortcut to cycle
the Hotspot Snap mode through the three possible states – Hotspot Snap (All
Layers) / Hotspot Snap (only snaps on the current layer) / Off. The current mode is displayed
on the Status Bar (nothing is displayed there when the feature is off).

ROUTING
 During interactive routing, you can use the following shortcuts:

o Tab to pause routing and open the Properties panel to configure interactive
routing options. When done, click the button in the design space to
return to interactive routing mode.

o Shift+Spacebar to cycle through the corner styles: Track 45, Line 45/90 With
Arc, Any Angle, etc.

o Spacebar to toggle the corner direction.

o Shift+R to cycle through the available routing conflict resolution modes:

Walkaround Obstacles, Push Obstacles, Ignore Obstacles, etc.

o Ctrl+Shift+Wheel Scroll to switch to the next available signal layer and insert
a via.

o Shift+F1 to display the list of interactive routing shortcuts.

Use the Ctrl+W shortcut to toggle the clearance boundaries off and on. When the feature is
enabled and a net is being routed, all other net objects display a clearance boundary defined
by the applicable electrical clearance constraint. It is not possible to cross this boundary
during routing.

Aligning the Editing Cursor with a Placed Object (Bu da örneğin simetrik bir yerleştirme
yaparken işe yarar)

A common design task is to align a new object with an existing object. This can be achieved
by enabling the Axes feature. When this feature is enabled, a dynamic alignment guide line
is displayed from the current cursor location to the X or Y aligned object's hotspot whenever
the editing cursor is within the Axis Snap Range. This allows an object hotspot that is close
to the mouse cursor on one axis but distant on the other axis to drive the cursor position.

Heads Up display (Shift+H to toggle on/off).

Snap Options shortcuts:

 Ctrl+E - display a palette of snap options

 Shift+E - cycle to the next Snapping mode (Off, Current Layer, All Layers)

 Ctrl - hold to inhibit object snapping

Besides the standard ways of accessing a panel (from the Panels button at the bottom right
of the design space or the View » Panels menu), the View Configuration panel can also be
accessed by using the L or Ctrl+D shortcut keys (to open the panel with the Layers &
Colors or View Options tab displayed, respectively) or by clicking the color swatch on the
Layer Sets control at the bottom left of the design space

Controlling Layer Visibility from the Keyboard

In a busy PCB design, layers are often toggled on and off during the design process. To help
with this, layer visibility can be changed using keystrokes in the following way:

 Press the L shortcut key to display/make the Layers & Colors tab of the View
Configuration panel active. The panel's title bar will become colored, indicating that
it is the active element in the software.

 Note that there are characters and numbers in curved brackets to the right of some
of the layers and sets of layers, for example, Component Layer Pairs (C), and [1] Top
(T). The character/number in curved brackets is a keyboard shortcut key. As an
example, press the L shortcut to make the panel active, then press the T shortcut to
toggle the visibility of the Top signal layer.
  If you have accessed a set of layers, press Spacebar to toggle the visibility of all layers
in that set.

 If you have accessed a layer, its visibility will toggle immediately and
the Spacebar can then be used to toggle it again.

 Press the Up or Down arrow keys to move up or down through the list, for example,
to access a specific mechanical layer or a pair of component layers. You can then use
the Spacebar to toggle the visibility of that layer/layer pair.

 The number within the square brackets indicates which physical copper layer that
signal or plane layer is, in the layer stack. Consider the string, [6] Bottom (B),
the [6] indicates that this is the 6th copper layer in the layer stack, Bottom is the
user-defined name assigned to this layer in the Layer Stack Manager, and the (B) is
the shortcut key to toggle the visibility of that layer.

 Shortcut keys for signal and plane layers stop at (9), the last available numeric key on
the keyboard.

To include a layer in the Single Layer Mode display, perform a Ctrl+Click on the eye icon
associated with the desired layer on the Layers & Colors tab of the View
Configuration panel to add that layer into Single Layer Mode display; a square will appear
behind the eye icon ( ) to denote that layer will be permanently displayed in Single Layer
Mode.

When you press the 2 and 3 shortcuts to switch between 2D and 3D view modes, the default
behavior is for each view to retain its last-used view state. That means, if you had the entire
board shown in 2D mode, then switched to 3D mode and zoomed in, when you switch back
to 2D mode, the entire board will be shown again. This behavior can be overridden if
required, by holding the Ctrl+Alt shortcuts as you press 2 or 3.

Available 3D Outputs

Output Type From Notes

Screen capture PCB editor When the editor is in 3D Layout Mode,

press Ctrl+C to take a screenshot of the
current view. The 3D Snapshot
Resolution dialog will appear, select the
 required Render Resolution and click OK to
copy the image onto the Windows
clipboard. From there, paste it into your
preferred bitmap editor.

Export as an image PCB editor Select the File » Export » PCB 3D

Print command. After selecting the location
to save the image file, the PCB 3D Print
Settings dialog will open, where you can set
the Render Resolution, how you would like
the board to be viewed, and the image
format.

PCB 3D Print OutputJob Configured in the PCB 3D Print Settings

dialog. In the OutputJob, map the output
a New PDF container or directly to a printer.
Position the board as required before
generating output, then click the Take
Current Camera Position and Take Current
View Configuration buttons to generate a
printout of what you can see on the screen.
You can also create an image file, by
mapping the Output Job to a Folder
Structure Output Container.

PCB 3D Video OutputJob Configured in the PCB 3D Video dialog. In

the OutputJob, map the output to a New
Video container. Output can be in a variety
of video formats. To generate this output
you need to first define a PCB 3D movie in
the PCB 3D Movie Editor panel. Refer to
the Preparing a 3D PCB Video page to learn
more.
 PDF 3D notes/PCB Configured in the PDF3D dialog. In the
editor OutputJob, map the output to a New Folder
Structure. Requires Adobe Acrobat v9 or
newer to support the 3D motion. Output
can also include key frames from a PCB 3D
Movie, if one has been defined. Refer to
the Preparing a PDF3D File page to learn
more.

Mechanical data PCB editor The completed board can also be exported
in a number of different mechanical data
formats (in its folded state for a rigid-flex
board if required), ready to load into your
MCAD design tool. Learn more
about mechanical format import/export.

Board Insight Pop-up Mode

The Board Insight pop-up mode is an excellent tool for viewing objects under the cursor.
Press Shift+X (Tools » Browse Objects) to view detailed information about any components
and nets located under the cursor, as well as objects that belong to them, for example, pads
and tracks. Use Shift+V (Tools » Browse Violations) to view information about violations (of
defined Design Rules) currently under the cursor.

Headsup Display
The following commands of the View » Board Insight menu (can also be accessed
by pressing F2 in the design space) can be used to configure the Heads Up Display:

 Toggle Heads Up Display (Shift+H) - toggles the Heads Up Display on or off.

  Toggle Heads Up Tracking (Shift+G) - toggles the location of the Heads Up Display to
be at a fixed position on the board or allows it to be moved with the cursor. The HUD
will not jump to the cursor but rather move in relation to where the cursor was when
tracking was enabled. It is advised to position the cursor in relation to the current
HUD position before using this command.

 Resets Heads Up Delta Origin (Ins) - resets the Delta Origin to the current mouse
coordinates. The distance horizontally and vertically the mouse is moved from the
Delta Origin can be displayed in the Heads Up Display. The Delta Origin can also be
reset by using the left-click mouse button. This setting can be configured in the PCB
Editor - Board Insight Modes page of the Preferences dialog.

The ability and controls that are used to set the Delta Origin point follow the Insert Key
Resets Heads Up Delta Origin and Mouse Click Resets Heads Up Delta Origin options on
the PCB Editor - Board Insight Modes page of the Preferences dialog. If both of these options
are disabled, the Delta Origin feature is effectively disabled and the delta coordinates will
remain at 0,0 as you move the mouse.

 Toggle Heads Up Delta Origin (Shift+D) - toggles the display of the Delta Origin
coordinates. The delta coordinates display the distance horizontally (dx) and
vertically (dy) from the Delta Origin coordinates - a point that can be user-defined
within the design space. Use the Delta coordinates to gauge distance relative to a
position on your board.

Changes made to the Board Insight system affect the PCB domain design space, and
therefore, affect all PCB and PCB footprint documents on which you work.

Live Highlighting
Use Ctrl+Click to highlight any net on the board. Everything in the design that is not part of
that net is dimmed, making the routing stand out on all signal layers, as shown in the image
below. To highlight multiple nets, hold the Shift key as you Ctrl+Click on each
net. Ctrl+Click in any free space to restore the display.
Lesson 4: PCB Design Fundamentals
BGA (BALL GRID ARRAY)
Phase 0 — What a BGA really is
1) What “BGA” means physically

BGA (Ball Grid Array) is a package where the electrical connections are an array of solder
balls on the underside of the chip package.

 Each ball is a pad-to-pad solder joint:

o Package side: a pad on the BGA substrate

o Board side: a pad on your PCB footprint

o After reflow, the ball becomes a short, squashed solder column (a joint), not
a “wire.”

Key consequence:

 Unlike QFP/QFN, there are no exposed pins around the edges you can touch with a
probe or soldering iron.

So the “pins” are:

 hidden,

 underneath,

 and only accessible through PCB copper/vias you design.

(That’s the core reality.)

2) Why BGAs exist (why industry uses them)

BGAs solve problems that leaded packages can’t when pin counts and speeds rise:

1. High pin count without huge perimeter

 QFP: pins live on perimeter → pin count scales with perimeter length.

 BGA: pins live on area → pin count scales with area.

So you can pack hundreds/thousands of connections in a reasonable size.

2. Better electrical performance

The current path is often:
  shorter,

 lower inductance,

 lower impedance discontinuity

than long leads on a QFP.

At high speeds, long leads behave like little inductors/antennas. BGA reduces that.

3. Better power delivery

FPGAs/SoCs need many power/ground pins and low-inductance return paths.
BGA lets vendors distribute GND + power balls across the array, not just at edges.

4. Thermal
Many BGAs can conduct heat through the package and board more effectively than
leaded packages.

3) What makes BGAs “hard” (the real reasons)

BGAs are hard for system reasons, not because “routing is tricky.”

A) You must route under the part (3D constraint)

With a QFP:

 you can escape from the outer pins sideways.

With a BGA:

 inner balls are buried.

 you can only escape by using vias (holes) and internal layers.

So the package forces you into:

 multilayer boards,

 via strategies,

 stackup decisions.

B) The PCB stackup becomes part of the component

With BGAs (especially FPGA BGAs), your choices like:

 number of layers,

 where ground planes sit,

 how many signal layers exist,

  via types (through, blind, microvia),
directly determine whether it’s routable and reliable.

For fine pitch BGAs, you can’t “skill” your way out of bad stackup.

C) Assembly and inspection are hidden

A BGA joint is under the package.

You can’t visually inspect solder quality.

So manufacturing becomes essential:

 stencil design matters,

 reflow profile matters,

 X-ray inspection is often used for verification.

This is why BGA design is tightly coupled with DFM/DFA.

D) Rework is harder / riskier

If something goes wrong:

 removing/reballing a BGA requires specialized tools.

That pushes you to design for higher first-pass success.

4) How BGAs “connect” electrically on the PCB (mental picture)

Think of each ball as a node that must transition into your board’s copper network.

There are only a few ways a ball becomes a usable connection:

1. Direct trace on the top layer

 possible for some outer balls (depends on pitch and trace/space capability)

2. Dogbone fanout

 ball pad → short trace → via → inner layer routing

Classic for ~0.8–1.0 mm pitch.

3. Via-in-pad

 the via is placed directly in the BGA pad.

Used when pitch gets tight (often ≤0.65 mm, commonly ≤0.5 mm).
But it usually requires:

 via fill,
  cap/planarization,
otherwise solder wicks into the via and assembly fails.

This is the big “fork in the road” later.

5) A BGA is basically a “via and plane problem”

This is the mindset shift:

For big BGAs (FPGAs especially), you’ll have:

 tons of power balls

 tons of ground balls

 many high-speed signals

So the challenge is:

 Can you deliver clean power (low inductance paths)?

 Can you escape enough signals without violating fab limits?

 Can you preserve return paths (reference planes)?

 Can your fab/assembler actually build it?

That’s why BGA work quickly becomes:

 stackup,

 plane strategy,

 via strategy,

 DFM + assembly capabilities,

more than “drawing traces.”

Phase 1 — Absolute-Minimum BGA Knowledge

1) BGA package basics (what actually matters)

Ball pitch

 The single most important number.

 It decides routing method, vias, layers, and cost.

Rule of thumb:

 1.0 / 0.8 mm → dogbone + through-vias usually work

 0.65 mm → borderline, HDI often needed

  0.5 mm → HDI + via-in-pad almost mandatory

If pitch ≤ 0.65 mm, assume HDI unless proven otherwise.

Ball diameter

 Smaller pitch → smaller balls → less assembly margin.

 You don’t optimize this, just respect it.

Ball map orientation (A1)

 Must match datasheet exactly.

 Wrong orientation = dead board.

 Always mark A1 in footprint and silkscreen.

Package type

 Wire-bond BGA: simpler, lower performance.

 FCBGA: typical FPGA package, many power/ground balls, higher demands on stackup
and decoupling.

2) PCB manufacturing constraints (why boards fail)

You must know these before routing:

 Minimum trace/space
Determines if traces fit between pads.

 Via drill + pad size

Determines if dogbone fanout physically fits.

 Via-in-pad
Required for fine pitch. Must be filled and capped. Higher cost.

 Microvia vs through-via
Through-via = cheap, large.
Microvia = small, HDI, expensive.

 Aspect ratio
Limits how small drills can be in thick boards.

If your fab cannot meet these, the design is impossible.

3) Stackup literacy (non-negotiable)

  Signals require a nearby reference plane, usually ground.

 Layer 2 is ground because it provides:

o return path,

o impedance control,

o low noise.

BGAs, especially FPGAs, need:

 solid ground plane under the package,

 power planes close by,

 6–10 layers typical.

If you cannot explain why L2 is ground, stop.

Phase 3 — Footprint & Land Pattern (Fast)

One rule

Never invent a BGA footprint.

Always start from the manufacturer’s recommended land pattern.

If the footprint is wrong, nothing else matters.

What you must always verify

Manufacturer land pattern

 Use the exact pad size, spacing, and tolerances from the datasheet or package
drawing.

 Do not “optimize” pad sizes.

 Do not reuse a similar-looking footprint.

Solder mask defined (SMD) vs non-solder mask defined (NSMD)

You must know which one the vendor expects.

 NSMD (most common for BGAs)

o Copper pad defines size.

o Better solder joint reliability.

 SMD
 o Solder mask defines pad.

o Sometimes used for very fine pitch or specific reliability goals.

Rule:
If the datasheet specifies NSMD or SMD, follow it exactly.

Via-in-pad requirements

If vias are placed in BGA pads:

 They must be filled and capped.

 Unfilled via-in-pad causes solder loss and failures.

Before committing:

 Confirm your fab supports filled and capped vias.

 Confirm allowed via sizes and fill type.

If the fab cannot do this, via-in-pad is not an option.

Key decisions you must make before routing

Dogbone fanout vs via-in-pad

This is dictated by pitch and fab capability, not preference.

 Dogbone

o Through-vias

o Lower cost

o Works for ≥0.8 mm pitch in most cases

 Via-in-pad

o HDI process

o Required for ≤0.65 mm pitch in most cases

o Higher cost

If dogbone works, use dogbone.

Filled & capped vias

Only needed when:

 using via-in-pad,

 or routing critical power/ground connections under the BGA.

This affects:

 cost,

 lead time,

 yield.

Decide this before layout.

Escape direction strategy

Before routing, decide:

 which rows escape on top layer,

 which rows drop to inner layers,

 how power and ground balls drop into planes.

You should have a clear breakout plan before placing a single trace.

Phase 3 success condition

You are ready to place and route when:

 Footprint exactly matches vendor land pattern

 SMD vs NSMD is confirmed

 Via-in-pad rules are agreed with fab

 Fanout method is chosen

 Escape direction is planned

At this point, placement and routing become mechanical.

Phase 4 — Escape Routing (Core Skill)

Goal: get signals out of the BGA without thinking about SI yet.

Only patterns you learn

  Outer row → direct trace
If a pad can escape sideways on the top layer, do it.

 Inner rows → dogbone

Pad → short trace → via → inner layer.
Works for moderate pitch.

 Fine pitch → via-in-pad (microvia)

When there is no room for a trace + via beside the pad.

 Bank-oriented breakout
Escape signals in groups based on I/O banks.
Do not mix banks randomly.

What you are NOT doing yet

 Length matching

 Impedance tuning

 DDR rules

 SI optimization

This phase is pure geometry: fit, escape, continue.

Success condition:
All BGA signals escape cleanly without violating fab rules.

Phase 5 — Power Integrity Basics (Enough for Now)

Goal: avoid obvious PI mistakes.

What you must understand

 Planes > pours

Solid planes have much lower inductance than polygon pours.

 Short via loops matter

Power current path is: plane → via → pin → via → plane.
Shorter loop = lower inductance = better PI.

 Decoupling caps go under or near the BGA

Distance matters more than exact value at this stage.

 Stitching vias exist

They keep return paths short and continuous when signals change layers.

If you understand current loops, you understand enough PI for now.

Phase 6 — Assembly & DFM Reality Check
Goal: don’t design something that cannot be built or debugged.

Non-negotiable facts

 BGAs are reflow-only

No hand soldering.

 Inspection is X-ray
You cannot visually inspect joints.

 PCB house capability limits design

Trace/space, via size, HDI, via fill.

 Assembly cost rises fast

HDI, via-in-pad, fine pitch all increase cost and lead time.

These constraints should influence:

 pitch choice,

 layer count,

 via strategy,

 budget decisions.

Delay Tuning and Length Matching (Practical Notes)

1. Purpose

Delay tuning (often called length tuning) is used to control timing skew so multiple signals
arrive within an allowed timing window. The target is not “equal length,” but acceptable
time alignment at the receiver. Altium+1

2. Delay tuning vs length tuning

Most PCB tools enforce constraints in length, but the real specification is usually time
(skew). If the interface defines an allowed timing mismatch, convert it to an allowed length
mismatch using the propagation velocity of the trace. Altium+1

Practical note:

 If you change stackup/material (dielectric constant), the same time skew corresponds
to a different length mismatch. Altium+1
3. Where matching is actually required

A) Differential pairs

Main requirement: intra-pair matching (P vs N) so the differential receiver sees the

transitions aligned, preserving common-mode cancellation. Northwest Engineering
Solutions+1

Two related ideas:

 Intra-pair skew: mismatch between P and N inside one pair.

 Inter-pair skew: matching between multiple pairs only when the protocol requires
lane-to-lane timing alignment (many serial links do not require tight inter-pair
matching unless specified). Northwest Engineering Solutions+1

B) Parallel / source-synchronous buses (example: DDR families)

These interfaces care about relative timing between groups (data/strobe/clock) and specify
skew constraints in documentation. Example guideline: Intel’s DDR layout guidance includes
clock pair matching guidance on the order of ±5 ps (for the clock pair) and additional skew
constraints involving CLK and DQS. Intel+1

4. Timing mismatch concept (the only formula you need)

Allowed length mismatch is derived from allowed timing mismatch:

 ΔL = Δt × v

Where:

 ΔL is allowed length mismatch

 Δt is allowed timing mismatch

 v is propagation velocity on that layer/stackup

Use this because standards often state time limits, while tools often constrain length.
Altium+1

5. How delay is added (tuning structures)

When one route is short, you add delay by adding length to that route using controlled
meanders:

 accordion / serpentine

 trombone
  sawtooth

Use tuning as a correction step after clean routing, not as a routing style.
Altium+2Northwest Engineering Solutions+2

Placement rule (practical):

 Add tuning where mismatch is created (often near breakouts, bends, or layer
transitions), and keep tuning sections as short as necessary. Northwest Engineering
Solutions+1

6. Risks of over-tuning (why “perfect matching” can backfire)

Length tuning structures are not free:

 they can create impedance discontinuities (reflections),

 they can increase coupling/crosstalk in tight serpentine regions,

 for differential pairs, asymmetry can contribute to mode conversion.

Therefore:

 route direct first,

 tune minimally,

 avoid long, dense meanders unless required by the timing budget. Altium+1

7. Phase mismatch in differential pairs (local vs global matching)

A common real problem is local uncoupling around vias/breakouts: even if total lengths
match, short uncoupled regions can introduce small skew. “Phase matching” refers to adding
small compensation close to the mismatch source to keep the pair aligned through that
region. Altium+1

8. Non-etched delay (package and vias)

In strict timing budgets, total delay is not just copper trace length.

Pin-package delay

Signals also traverse package structures (pads/bond wires/internal paths). Manufacturers

may provide pin-package delay data (often tens to hundreds of ps). This can matter when
rise times are very fast or when bus timing is tight. Altium

Via delay
Vias add delay and discontinuities; in many differential cases, both traces experience similar
via structures so the differential skew impact is reduced. Via delay becomes more relevant
when routing wide parallel buses across different layers with different via counts/paths.
Altium

9. Minimal workflow (what to do in real layouts)

1. Identify nets that truly require matching (protocol/vendor rules). Northwest

Engineering Solutions+1

2. Route cleanly first (short, direct, consistent layer/reference).

3. Apply constraints as timing where possible, otherwise convert to length using your
stackup velocity. Altium+1

4. Tune only the short routes; keep tuning sections compact and not overly dense.
Altium+1

5. Re-check skew after any routing changes (tuning is easy to break accidentally).
Lesson 5: Build-Up, Stack-Up, and Controlled
Impedance
Chapter: Build-Up, Stack-Up, Controlled Impedance, and Critical Length

1. Purpose

High-speed PCB behavior is governed by four linked ideas:

 Build-up → what can be manufactured

 Stack-up → where signals and return currents flow

 Controlled impedance → how signals propagate

 Critical length → when impedance control actually matters

If you miss any one of these, design decisions become arbitrary.

2. Build-Up (HDI / Sequential Lamination)

Build-up defines how the PCB is fabricated in stages.

 Start with a core (2–4 layers).

 Add outer layers in separate lamination cycles.

 Use microvias (blind, laser-drilled) to connect layers.

Why build-up exists

 Fine-pitch BGAs do not allow large through-vias.

 Microvias are shorter and smaller → better routing density and cleaner electrical
behavior.

Practical impact

 More build-up layers = higher cost and tighter fab constraints.

 Via types and lamination count must be decided before layout.

 Build-up choices constrain stack-up and impedance options.

Build-up is a manufacturing constraint first, electrical second.

3. Stack-Up (Electrical Layer Structure)

Stack-up is the vertical arrangement of:

 signal layers,

 reference planes (ground, power),

 dielectric layers between them.

Core principle

Every signal is a current loop:

 forward current in the trace,

 return current in the reference plane.

Stack-up determines:

 how close that return path is,

 how predictable it is,

 how much loop inductance exists.

Good stack-up behavior

 Signal layers adjacent to solid reference planes.

 Ground preferred over power as a reference.

 Power planes tightly coupled to ground planes.

 Minimal, well-planned layer transitions.

Stack-up is not “number of layers”; it is reference integrity.

4. Controlled Impedance (What Sets It)

Controlled impedance means a trace behaves as a predictable transmission line.

Impedance is set by geometry and materials, not by routing intent.

Primary factors that set impedance

1. Trace width
Wider → lower impedance
Narrower → higher impedance

2. Distance to reference plane (dielectric thickness)

Smaller distance → lower impedance
Larger distance → higher impedance
Often more influential than trace width.
 3. Dielectric constant (Dk)
Higher Dk → lower impedance, slower signal
Lower Dk → higher impedance, faster signal

4. Copper thickness and roughness

Thicker copper slightly lowers impedance.
Roughness matters at multi-GHz speeds.

5. Trace geometry

o Microstrip (outer layer): less stable, fields partly in air

o Stripline (inner layer): more stable, fields fully in dielectric

6. Differential pair spacing

Closer spacing → lower differential impedance
Wider spacing → higher differential impedance

Impedance is defined after stack-up is fixed, not before.

5. Critical Length (When Impedance Matters)

Critical length defines when a trace must be treated as a transmission line.

Definition

A trace becomes “high-speed” when its electrical length is long enough that reflections
affect signal integrity.

Rule of thumb:

 If trace length ≥ (rise time × propagation velocity) / 6,

the trace is electrically long.

On FR-4:

 Propagation ≈ 150–180 ps/in

 Fast edges (sub-ns) → critical length can be only a few centimeters.

Why this matters

 Below critical length: lumped behavior, impedance less critical.

 Above critical length: reflections dominate, impedance control is mandatory.

This explains why:

 Low-speed GPIO ignores impedance.

 DDR, USB, PCIe, LVDS cannot.

Critical length tells you whether you must care about impedance at all.

6. How the Concepts Connect

 Critical length tells you if impedance matters.

 Controlled impedance tells you what geometry is required.

 Stack-up enables that geometry and return path.

 Build-up determines whether the stack-up can be fabricated.

You cannot:

 decide impedance without stack-up,

 decide stack-up without build-up,

 ignore impedance once traces exceed critical length.

7. Correct Design Order

1. Identify interfaces and estimate critical length.

2. Decide whether HDI / build-up is required.

3. Define stack-up with clear reference planes.

4. Calculate controlled impedance geometries.

5. Lock stack-up and impedance rules.

6. Route.

7. Apply length/delay tuning only if timing requires it.

Any other order causes rework.

Lesson 6: Power
Power Distribution in an FPGA system

PDN VIA PLACEMENT WITH CAPS

DECOUPLING VIA PLACEMENTS DA BAK İNT ARTI FERANECTE VARDI BİŞİLER

EMC CONSIDERATIONS FOR DC POWER DESIGN TZONG-LIN WU

Principles of Power Integrity Eric Bogatin

High Speed Design Concepts
What “High-Speed Design” Really Means

High-speed design does not mean high data rate alone.

It means:

Signal edge rise time is comparable to the electrical length of the interconnect

When that happens, wires stop behaving like simple connections and start behaving like
distributed transmission lines.

1. When a Trace Becomes a Transmission Line

Rule of thumb

A trace is “high-speed” if:

1
trace delay ≥ ×signal rise time
6

Typical PCB propagation:

 ~150–180 ps/inch (FR-4)

Example:

 1 ns rise time → ~1 inch already matters

Consequence

 Voltage is not the same everywhere at once

 Reflections, ringing, overshoot appear

 You must treat the trace as a controlled impedance system

2. Characteristic Impedance (Z₀)

What it is

Characteristic impedance is the natural V/I ratio of a propagating wave on a trace.

It depends on:

 Trace width

 Dielectric height

 Dielectric constant (εr)

 Reference plane geometry

Typical values:
  Single-ended: 50 Ω

 Differential: 90 Ω / 100 Ω

Critical idea

Impedance is not resistance

It exists even in a perfect conductor.

3. Reflections & Termination

Why reflections happen

A reflection occurs when:

Z source ≠ Z 0 ≠ Z load

What reflections cause

 Overshoot / undershoot

 Ringing

 False logic transitions

 EMI

Fixes

 Series termination (source)

 Parallel termination (load)

 Differential termination (receivers)

 Proper driver impedance selection

4. Reference Planes & Return Current
One of the MOST misunderstood topics

High-frequency return current:

 Flows directly under the signal trace

 Takes the path of minimum inductance, not resistance

If the reference plane is broken:

 Return current detours

 Loop area increases

 EMI explodes

 Signal integrity collapses

Rule

Every high-speed signal must have an unbroken reference plane

5. Differential Signaling
Why it’s used

 Noise immunity

 Reduced EMI

 Higher data rates

What actually matters

 Differential impedance

 Intra-pair skew

 Pair-to-pair skew

 Tight coupling

Common myth

“As long as they’re the same length it’s fine”

False.
Spacing, reference plane continuity, and symmetry matter just as much.

6. Crosstalk (NEXT & FEXT)

Why it happens

 Capacitive coupling (electric field)

 Inductive coupling (magnetic field)

Factors that increase crosstalk

 Long parallel runs

 Tight spacing

 Poor reference planes

  Fast edges

Mitigation

 Increase spacing

 Shorten parallelism

 Ground stitching vias

 Slower edge rates

 Differential routing

7. Timing, Skew & Length Matching

Why timing matters

Digital systems fail when:

data arrives outside setup/hold window

Length matching is about:

 Arrival time, not physical length

 Different layers ≠ same delay

 Vias add delay

Key idea

Serpentines are delay tuning, not decoration.

8. Losses: Why Signals Degrade
Loss mechanisms

 Skin effect (conductor loss)

 Dielectric loss

 Via stubs

 Connector loss

Symptoms

 Closed eye diagrams

 Reduced noise margin

 Data errors at high speed

9. EMI & Signal Integrity Are the Same Problem

Key truth:

A board with good signal integrity automatically has low EMI

Radiation increases when:

 Loop areas increase

 Impedance discontinuities exist

 Reference planes are broken

 Edges are unnecessarily fast

10. Mental Model Summary (This Is the Core)

High-speed design is about controlling:

1. Where the signal goes

2. Where the return current goes

3. How fast edges transition

4. Impedance continuity

5. Timing alignment

If you control those five, everything else follows.

1. Setup Time & Hold Time (Why timing even matters)

What they are

They describe how stable data must be around a clock edge for a flip-flop to sample
correctly.

 Setup time (tSU)

Data must be stable before the active clock edge

 Hold time (tH)

Data must remain stable after the clock edge

Why this exists (physical reason)

Inside a flip-flop:

 Transistors need finite time to charge/discharge

 Internal nodes must settle before regeneration

If violated → metastability (undefined logic level for some time)

Core inequality (simplified)

t clk +t data +t skew <T clk −t setup
¿ path

Key insight

 Setup is a max-delay problem

 Hold is a min-delay problem

 Faster clocks → setup becomes harder

 Faster edges → hold becomes harder

2. Clock Skew (Why “same clock” isn’t actually same)

What clock skew is

Difference in arrival time of the same clock edge at different flip-flops.

Caused by:

 Different trace lengths

 Different buffer delays

 Different loading

 Different routing layers

Types

 Positive skew: clock arrives later at receiver

 Negative skew: clock arrives earlier at receiver

Why skew is dangerous

Skew directly eats timing margin:

 Too much skew → setup violation

 Wrong direction skew → hold violation

Important realization

You can have perfect data routing and still fail because of clock skew.

This is why clocks are:

 Short

 Shielded

 Buffered

 Matched

 Often routed on dedicated layers

3. Source-Synchronous vs Embedded Clock

(How the receiver knows when to sample)

Embedded Clock (traditional)

Clock and data are separate.

Examples:

 Simple MCU buses

 Old parallel interfaces

Problem:

 Clock and data experience different delays

 Skew grows with frequency

At high speed → breaks.

Source-Synchronous Clocking

The data source sends the clock together with data.

Examples:

 DDR (DQS)
  LVDS interfaces

 Some ADC/DAC links

Why it works

 Clock and data see same channel conditions

 Skew largely cancels out

 Much higher data rates possible

Embedded Clock in Data (Clock Recovery)

Clock is encoded inside the data stream.

Examples:

 PCIe

 USB

 SATA

 Ethernet

Receiver uses a CDR (Clock & Data Recovery) loop.

Why it’s used

 No separate clock line

 Fewer pins

 Better scalability at very high speeds

Comparison summary

Scheme Clock Location Skew Sensitivity Speed

Embedded (separate) Independent High Low

Source-synchronous Sent with data Low High

Embedded in data Recovered Very low Very high

4. Deterministic vs Elastic Timing

(Does latency matter, or only correctness?)

Deterministic Timing

Latency is fixed and predictable.

Used when:

 Cycle-accurate behavior is required

 Tight real-time constraints exist

Examples:

 DDR memory access

 Synchronous MCU buses

 Control systems

If timing shifts → system breaks

Elastic Timing
Latency can vary, as long as data arrives correctly.

Achieved using:

 FIFOs

 Elastic buffers

 Clock domain crossing logic

Examples:

 PCIe

 USB

 Ethernet

 Network links

Receiver says:

“I don’t care when it arrives, just don’t corrupt it.”

Why elastic timing enables high speed

 Allows phase drift

 Allows clock tolerance mismatch

 Allows long channels

 Allows retiming and buffering

This is why PCIe can run at tens of GHz while DDR cannot tolerate random latency.

The Big Picture (connect all four)

All four concepts answer one question:

How does the receiver know what value to sample, and when, reliably?

 Setup/hold → local sampling correctness

 Clock skew → global timing alignment

 Clocking scheme → how timing info is delivered

 Deterministic vs elastic → whether latency is sacred or flexible

DDR
1. Memory Basics — DRAM

1.1 What “Memory” Means in Digital Systems

In digital hardware, memory is a subsystem that stores state across clock cycles and power
domains (volatile vs non-volatile). For high-performance systems, the dominant requirement
is bandwidth at low cost, not persistence. This requirement leads directly to Dynamic
Random-Access Memory (DRAM).

DRAM is optimized for:

 High bit density

 Low cost per bit

 High sustained bandwidth

It is not optimized for simplicity, determinism at the circuit level, or ease of use. Those
responsibilities are delegated to the memory controller.

1.2 Why DRAM Exists (and SRAM Is Not Enough)

Static RAM (SRAM) stores data using bistable circuits (flip-flops). While fast and simple,
SRAM:

 Consumes large silicon area

 Has high static power

 Does not scale economically to large capacities

DRAM replaces each flip-flop with a single capacitor and an access transistor, trading
simplicity for density.

Key trade-off:

 SRAM: fast, simple, expensive

 DRAM: dense, complex, inexpensive

This trade-off is the foundation of all DDR systems.

1.3 The DRAM Cell (Physical Reality)

A DRAM cell consists of:

 One capacitor (stores charge = data)

  One access transistor (connects the cell to a bitline)

A charged capacitor represents one logic state; a discharged capacitor represents the other.

Important physical consequences:

 Charge leaks over time → refresh is mandatory

 Read operations are destructive (the act of sensing disturbs the charge)

 Data must be restored after each read

These physical constraints shape the entire DRAM protocol.

1.4 Organization: Rows, Columns, and Banks

DRAM is not accessed as a flat array. It is hierarchically organized:

 Rows: large groups of cells sharing a wordline

 Columns: individual cells accessed via bitlines

 Banks: independent arrays allowing limited parallelism

Accessing data requires:

1. Activating a row (connecting all its cells to sense amplifiers)

2. Selecting a column (choosing which data to transfer)

3. Precharging (closing the row and restoring bitlines)

This multi-step access is why DRAM has inherent latency.

1.5 Sense Amplifiers and the Row Buffer

When a row is activated:

 All cells in the row share their charge with sense amplifiers

 The sense amplifiers latch the data and restore the cell contents

 The entire row becomes temporarily available in the row buffer

Implications:

 Accessing data in an open row is fast

 Accessing a different row requires closing the current one first

 Memory access time depends on row locality

This behavior explains why DRAM timing parameters exist and why access is not
instantaneous.

1.6 Volatility and Refresh

Because DRAM stores data as charge:

 Charge decays due to leakage

 Data must be periodically refreshed

 Refresh occurs even when the system is idle

Refresh is:

 Invisible at the software level

 Managed by the memory controller

 A fundamental bandwidth and latency cost

Refresh overhead increases with:

 Temperature

 Memory density

 Process scaling

1.7 DRAM as a Timed Device (Key Concept)

DRAM is not event-driven and not elastic. It is a timed analog system controlled digitally.

Core idea:

DRAM correctness depends on when signals occur, not just what their values are.

Because of this:

 Commands must be issued in strict sequences

 Minimum and maximum delays must be respected

 Timing violations cause data corruption, not retries

This property directly leads to:

 Synchronous DRAM (SDRAM)

 Double Data Rate DRAM (DDR)

  Source-synchronous interfaces

 Training and calibration mechanisms

1.8 What This Means for the Designer

At the DRAM level:

 The memory does not “understand” transactions

 There is no concept of packets or retries

 There is no tolerance for variable latency

All complexity is pushed upward into:

 The memory controller

 The PHY

 The PCB interconnect

Understanding DRAM at this level is essential before discussing SDRAM, DDR signaling,
timing, or layout.

1.9 Summary

 DRAM trades simplicity for density

 Data is stored as charge, not logic states

 Reads are destructive; refresh is mandatory

 Memory access is inherently multi-step and timed

 DRAM is the physical foundation on which all DDR systems are built

2. SDR vs DDR

2.1 Single Data Rate (SDR)

Single Data Rate memories transfer data once per clock cycle, typically on one clock edge.

Key characteristics:

 One data transfer per clock period

 Simpler timing and wider margins

 Lower bandwidth for a given clock frequency

  No data strobe (data is referenced directly to the clock)

SDR memories are useful as a conceptual baseline because they expose the command →
wait → data relationship clearly, without additional timing layers.

2.2 Double Data Rate (DDR)

Double Data Rate memories transfer data on both the rising and falling edges of the clock,
effectively doubling bandwidth without doubling clock frequency.

Key changes compared to SDR:

 Two data transfers per clock period

 Tighter timing margins

 Introduction of data strobe (DQS) for reliable sampling

 Stronger dependence on signal integrity and layout quality

The critical insight is that DDR does not change what memory does; it changes how tightly
time must be controlled.
2.3 Why DDR Requires a Strobe

As data rates increase:

 Clock-to-data skew becomes comparable to valid data windows

 A global clock reference is no longer sufficient

DDR solves this by introducing source-synchronous timing:

 Data is sampled relative to DQS, not the global clock

 Clock is used for command/address timing

 DQS is used for data timing

This separation is fundamental and persists across all DDR generations.

3. DDR Types (Including LPDDR)

3.1 Mainstream DDR Generations

Each DDR generation primarily improves bandwidth per pin and power efficiency, while
increasing integration complexity.

Type Typical Use Key Characteristics

DDR Early PCs First double-edge data transfer

DDR2 PCs, servers Higher clock, lower voltage

DDR3 PCs, embedded Higher density, fly-by topology

Type Typical Use Key Characteristics

DDR4 PCs, servers Bank groups, tighter SI requirements

DDR5 High-end systems On-die ECC, higher speeds, more complexity

Progression trends:

 Higher data rates

 Lower I/O voltage

 More aggressive timing

 Increased reliance on training and calibration

3.2 Low-Power DDR (LPDDR)

LPDDR memories are optimized for mobile and power-constrained systems.

Key differences from standard DDR:

 Lower operating voltage

 Aggressive power-down modes

 Reduced termination power

 Different command and timing models

Common LPDDR types:

 LPDDR2 / LPDDR3: early mobile platforms

 LPDDR4 / LPDDR4X: smartphones, embedded SoCs

 LPDDR5: high-performance mobile and edge devices

Important distinction:

LPDDR is not a drop-in replacement for DDR.

Controllers, pinouts, timing, and power architecture are different.

3.3 Choosing Between DDR and LPDDR

Design choice depends on:

 Power budget

 Required bandwidth

 Available controller support

 PCB complexity tolerance

In practice:

 PCs and FPGAs → DDR3/DDR4

 Mobile SoCs → LPDDR4/LPDDR5

 Embedded Linux platforms → either, depending on vendor support

4. DDR Pins and Timing Parameters

4.1 DDR Signal Groups

DDR interfaces are organized into functional signal groups:

Clock

 CK / CK#: differential clock for command and address timing

Command and Address

 CS#, RAS#, CAS#, WE#

 ADDR[x], BA[x] (or BG for newer DDR)

These signals define what operation happens and when.

Data

 DQ[x]: bidirectional data bus

 DQS / DQS#: data strobe (per byte lane)

 DM / DBI: data mask or data bus inversion

4.2 Byte Lanes

Data is grouped into byte lanes, each with:

 8 DQ signals

 One DQS/DQS# pair

 Optional DM/DBI

Each byte lane is timed and trained independently, which directly impacts routing and
length-matching rules.

4.3 Core Timing Parameters (Conceptual)

DDR timing parameters define minimum safe delays between operations.

Focus on relationships, not values:

 tCK: clock period

 tCL (CAS latency): READ command to data

 tRCD: ACTIVATE to READ/WRITE

 tRP: PRECHARGE time

 tWR: write recovery time

These parameters exist because:

 Charge sharing takes time

 Sense amplifiers need settling time

 Data must be restored reliably

Violating these constraints causes silent data corruption.

4.4 Setup and Hold Around DQS

For data transfers:

 DQ must meet setup and hold requirements relative to DQS

 DQS defines the valid sampling window

 Skew between DQS and DQ directly reduces margin

This is why:

 DQS-to-DQ matching is critical

 Byte lanes are routed as tightly coupled groups

 Training is mandatory at high speeds

5. Summary

 SDR transfers data once per clock; DDR transfers on both edges

 DDR introduces DQS to survive tight timing margins

 DDR generations scale bandwidth but increase complexity

 LPDDR prioritizes power efficiency with different constraints

 DDR pin groups reflect strict separation of timing roles

 Timing parameters describe physical limits, not abstract rules

5. DDR System Architecture

5.1 High-Level View

A DDR interface is not a simple bus between a processor and a memory device. It is a tightly
coupled system consisting of three main elements:

1. Memory Controller

2. PHY (Physical Interface)

3. External DRAM Device(s)

The correctness of the system depends on all three behaving coherently in time.
5.2 Memory Controller

The memory controller is responsible for logical correctness and timing orchestration.

Its functions include:

 Translating read/write requests into DRAM command sequences

 Enforcing DRAM timing constraints (tRCD, tRP, tCL, etc.)

 Scheduling accesses to maximize row locality

 Managing refresh operations

 Initiating and supervising training and calibration

The controller operates in a cycle-accurate, deterministic manner. It assumes that the

physical interface and PCB interconnect meet the required electrical constraints.

5.3 PHY (Physical Interface)

The PHY is responsible for electrical correctness.

Its functions include:

 Driving and sampling high-speed DDR signals

 Managing DQS-based source-synchronous sampling

 Implementing programmable delays and phase alignment

 Executing write leveling, read leveling, and gate training

 Compensating for process, voltage, and temperature variation

Conceptually:

 The controller decides what happens and when

 The PHY ensures signals arrive cleanly and aligned

This separation is critical: timing closure at the controller level is meaningless if the PHY
cannot achieve electrical alignment.

5.4 Clock Domains and Timing Ownership

DDR systems use multiple clock domains:

 Controller clock (internal logic)

 PHY clock(s)

 External DDR clock (CK/CK#)

Although these clocks are related, they are not identical. The PHY bridges these domains
using calibrated delay elements.

Key principle:

The memory controller owns logical time, but the PHY owns sampling time.

This division is why training exists and why DDR bring-up is sensitive to both firmware
configuration and board layout.

5.5 Data Path vs Command Path

DDR intentionally separates timing responsibilities:

 Command / Address Path

o Referenced to CK/CK#

o Lower bandwidth

o Routed using fly-by topology

o Timing is globally aligned

 Data Path

o Referenced to DQS

o Highest bandwidth

o Organized into byte lanes

 o Individually trained and aligned

This asymmetry explains many DDR routing rules and is fundamental to understanding
board-level constraints.

5.6 Why DDR Is Not Bit-Banged

DDR signaling requires:

 Sub-nanosecond timing resolution

 Per-bit and per-byte delay tuning

 Continuous calibration

These requirements exceed what general-purpose logic or software can provide. As a result:

 DDR controllers and PHYs are hardened or highly specialized

 Integration is configuration-driven, not implementation-driven

For the designer, this means correct integration, not protocol invention, is the goal.

6. Board-Level DDR Design Rules

6.1 Design Philosophy

DDR board design is governed by a single principle:

Preserve timing relationships by preserving electrical symmetry.

Board-level rules are not arbitrary; they exist to ensure that the PHY can successfully train
and maintain alignment across all operating conditions.

6.2 Stackup and Reference Planes

A DDR layout must provide:

 Continuous reference planes for all high-speed signals

 Controlled impedance for data, strobe, and clock lines

 Minimal impedance discontinuities

Key guidelines:

 Route DDR signals adjacent to solid ground planes

 Avoid reference plane splits under DDR routing

  Keep layer transitions consistent across byte lanes

Violating reference continuity directly increases jitter and skew.

6.3 Data Byte Lanes

Each byte lane forms an independent timing domain.

Rules:

 DQ signals must be tightly matched to their associated DQS

 Length matching is done within a byte lane, not across the entire bus

 Intra-lane skew matters more than inter-lane skew

Implication:

It is acceptable for different byte lanes to have different absolute delays, as long as each lane
is internally consistent.
6.4 DQS-Centric Routing

DQS is the timing reference for data sampling.

Therefore:

 DQS-to-DQ matching has the tightest constraints

 DQS should be routed cleanly, with minimal vias

 DQS polarity and pairing must be preserved

Any skew between DQS and its DQ signals directly reduces the valid data window.

6.5 Clock Routing (CK/CK#)

The clock pair:

 Defines command/address timing

 Does not directly sample data

Guidelines:

 Route CK/CK# as a tightly coupled differential pair

 Match clock lengths to each other

 Keep clock routing symmetrical relative to the memory devices

Clock skew primarily affects command timing margins, not data eye width.

6.6 Fly-By Topology

Modern DDR systems use fly-by routing for command, address, and clock signals.

Characteristics:

 Signals pass through memory devices sequentially

 Each device sees a slightly delayed version of the clock

 Training compensates for this intentional skew

Benefits:

 Improved signal integrity at high speeds

 Reduced simultaneous switching noise

 Scalable to multiple memory devices

6.7 Termination and Impedance Control

DDR relies on controlled impedance and termination to suppress reflections.

Common concepts:

 On-die termination (ODT)

 Series termination at the driver

 Differential impedance control for CK and DQS

Termination choices are controller- and memory-specific and must follow validated
guidelines.

6.8 Vias, Stubs, and Layer Transitions

At DDR speeds:

 Vias introduce inductance and capacitance

 Stubs create reflections

 Layer changes add discontinuities

Guidelines:

 Minimize via count on DQ and DQS

 Keep via structures consistent across byte lanes

 Avoid unused stubs, especially on data lines

6.9 What Board Design Can and Cannot Fix

Board design can:

 Minimize skew

 Reduce jitter

 Preserve eye opening

Board design cannot:

 Compensate for incorrect controller configuration

 Fix unsupported memory/controller combinations

  Overcome fundamentally broken topology

Training can correct small mismatches, not structural errors.

6.10 Summary

 DDR architecture separates logical control and physical signaling

 The PHY is the bridge between digital intent and analog reality

 Board-level rules exist to preserve timing symmetry

 Byte lanes are the fundamental unit of routing and timing

 Fly-by topology and DQS-centric routing are essential at high speeds

SDIO

1. What is SDIO?

What problem does SDIO solve?

SDIO solves this problem:

“I need to connect a reasonably fast peripheral to my MCU/SoC without using many pins
or a very complex interface.”

Before SDIO, designers often had to choose between:

 SPI → simple, but slow

 USB → fast, but complex and heavy

 Parallel buses → fast, but many pins

SDIO sits in between.

What does SDIO do (in simple words)?

SDIO is a way for a processor to talk to an external device using a small group of shared
signals and a clock.

In practice:

 The processor sends a request

 The device responds

  Data moves back and forth in chunks

 Errors can be detected and retried

You can think of SDIO as:

“SPI, but wider, faster, and standardized.”

What kind of devices use SDIO?

SDIO is commonly used for:

 Wi-Fi modules

 Bluetooth modules

 GPS modules

 Camera modules (some designs)

 SD cards (storage)

 Combo cards (SD memory + SDIO I/O)

Very common real-world example:

An MCU talking to a Wi-Fi chip over SDIO

2. What does SDIO look like physically?

This is the most important beginner question.

What pins / signals exist?

An SDIO interface uses very few signals:

 CLK → Clock (generated by the MCU/SoC)

 CMD → Command line (bidirectional)

 DAT0–DAT3 → Data lines (1 or 4 used)

 VDD / GND → Power

That’s it.

No differential pairs.
No strobes.
No dozens of pins.
How does an SDIO device connect to a microcontroller or SoC?

At hardware level, it looks like this:

 MCU has an SDIO (or SDMMC) peripheral

 SDIO device or SD card connects directly

 Signals are point-to-point

 MCU is always the host (master)

Schematic-level example (what you actually draw)

What you typically see in schematics:

 CLK from MCU → device

 CMD bidirectional with pull-up

 DAT lines with pull-ups

 Power rail (often 3.3 V or 1.8 V)

 Optional card-detect pin (for SD cards)

Board-level context (what you route on PCB)

On the PCB:

 Short, clean traces

 All signals referenced to ground

 No special high-speed stackup needed

 Usually routed on one layer if possible

This already tells you something important:

SDIO is NOT physically scary like DDR.

3. When should I choose SDIO?

What is SDIO good at?

Choose SDIO when:

 You need more speed than SPI

 You want few pins

 You want a well-supported interface

 You are connecting modules, not raw memory

Typical sweet spot:

 10–50 MB/s range

 Embedded systems

 Battery-powered devices

When should I NOT choose SDIO?

Do NOT choose SDIO when:

 You need extremely high bandwidth → use PCIe or USB

 You need very long cables → use USB or Ethernet

 You want extreme simplicity → SPI or UART

 You need main system memory → DDR

Very high-level comparison

Interface Speed Pins Complexity Typical Use

UART Very low 2 Very low Debug, text

SPI Low–medium 4–6 Low Sensors, flash

SDIO Medium 6–8 Medium Wi-Fi, SD

USB High Few High External devices

DDR Very high Many Very high Main memory

4. How hard is SDIO for a hardware designer?

Is it sensitive like DDR?

No. Not even close.

DDR:

 Sub-nanosecond timing

 Tight skew budgets

 Training and calibration

 Complex stackups

SDIO:

 Single clock

 Wide timing margins

 No training

 Forgiving routing

Is SDIO forgiving?

Yes.

SDIO tolerates:

 Small skew

 Some trace length differences

 Normal vias

 Ordinary PCB materials

If SDIO fails, it usually:

 Fails visibly

 Reports errors

 Can be debugged logically

Common beginner mistakes

 Forgetting pull-up resistors on CMD/DAT

 Wrong voltage (1.8 V vs 3.3 V)

 Poor power sequencing

 Using wrong MCU pins (pin-mux issue)

 Mixing up SDIO and SPI modes

5. Hardware design guidelines (beginner level)

Do I need controlled impedance?

Usually no.

At normal SDIO speeds:

 Standard PCB traces are fine

 You do not calculate impedance

 You do not need differential pairs

Treat it like a moderate-speed digital bus.

Do I need length matching?

 No strict matching

 Just keep traces reasonably short and similar

 Avoid extreme differences

Nothing like DDR byte-lane matching.

Typical clock speeds

Very roughly:

 Low speed: a few MHz

 Normal speed: ~25 MHz

 High speed: ~50 MHz

 Some systems go higher, but that’s advanced

Pull-ups, power, voltage

Important basics:

 CMD and DAT lines need pull-ups

 Common voltages: 3.3 V or 1.8 V

 Power must be stable before communication

 Some devices support voltage switching

What usually breaks SDIO on real boards?

Most failures are not signal integrity issues.

Common real problems:

 Wrong voltage level

 Missing pull-ups

 Incorrect pin multiplexing

 Bad power sequencing

 Noisy power rail to the module

6. Electrical limits and timing modes (high level)

What “speed modes” exist?

Think of modes as:

 Slow and safe

 Normal

 Faster
As speed increases:

 Clock frequency increases

 Timing margins shrink

 Signal quality matters more

But still far from DDR-level sensitivity.

What changes electrically when speed increases?

 Edges get sharper

 Crosstalk becomes more relevant

 Ground reference becomes more important

Still:

 No differential signaling

 No strobe signals

 No per-bit tuning

Where do these limits come from?

From:

 SD Association specifications

 MCU/SoC SDIO controller datasheets

 Reference designs

7. Where do I find REAL design rules and numbers?

This is critical.

Documents that matter MOST

1. MCU / SoC datasheet and reference manual

o Pin usage

o Voltage levels

o Max clock
 2. MCU application notes

o SDIO hardware design guide

o Known-good examples

3. Reference schematics

o Evaluation boards

o Development kits

Documents that are reference-only

 SD Association full specs

(Good for definitions, not first-time design)

What should you copy from reference designs?

Copy:

 Pull-up resistor values

 Power rail structure

 Pin assignments

 Basic routing style

This is good engineering, not cheating.

eMMC

1. What is eMMC?

What problem does eMMC solve?

eMMC solves this problem:

“I need non-volatile storage that is fast, reliable, cheap, and easy to integrate on my PCB.”

Before eMMC, designers used:

 NOR flash → simple but small and expensive

 NAND flash → cheap and large but very hard to manage

 SD cards → removable, unreliable for embedded systems

eMMC was created to hide NAND flash complexity and give designers a simple, memory-
like storage device.

What does eMMC do (in simple words)?

eMMC is a flash storage chip that already contains its own controller.

That internal controller:

 Manages bad blocks

 Handles wear leveling

 Corrects errors

 Presents a clean interface to the SoC

So to the processor:

eMMC looks like “a smart flash chip” instead of raw NAND.

You do not manage flash pages or erase blocks manually.

The eMMC chip does that for you.

What kind of devices use eMMC?

eMMC is used in:

 Smartphones (older generations)

 Tablets

 Embedded Linux boards

 Industrial controllers

 Automotive ECUs

 IoT gateways

If a system needs:

 Bootloader

 Linux filesystem

 Application storage

…and does not need removability → eMMC is a very common choice.

2. What does eMMC look like physically?

This is where eMMC becomes very clear.

What pins / signals exist?

eMMC uses a dedicated parallel interface:

 CLK → Clock from SoC

 CMD → Command line (bidirectional)

 DAT0–DAT7 → Data lines (1, 4, or 8 used)

 VCC → Flash core power

 VCCQ → I/O power

 GND

That’s it.

No differential pairs.
No high-speed serial lanes.
No USB-style PHY.

How does an eMMC device connect to a microcontroller or SoC?

eMMC is:

 Soldered permanently to the PCB

 Connected directly to the SoC’s eMMC / MMC controller

 Point-to-point (no sharing)

Unlike SD cards:

 No socket

 No hot-plug

 No card detect

Schematic-level example (what you actually draw)

Typical schematic features:

 CLK, CMD, DAT lines directly between SoC and eMMC

 Decoupling capacitors near the eMMC

  Separate VCC and VCCQ rails

 Sometimes series resistors (optional, vendor-dependent)

Board-level context (what you route on PCB)

On the PCB:

 eMMC placed very close to the SoC

 Short, clean parallel traces

 Solid ground reference

 Usually routed on inner layers or top layer

This already tells you something important:

eMMC is much more sensitive than SDIO, but far less extreme than DDR.

3. When should I choose eMMC?

What is eMMC good at?

Choose eMMC when:

 You need embedded, non-removable storage

  You are running Linux or an OS

 You want simple flash management

 You want low BOM complexity

Typical use:

 Boot storage

 Root filesystem

 Application data

When should I NOT choose eMMC?

Do NOT choose eMMC when:

 You need removable storage → SD card

 You need very high performance → UFS or NVMe

 You need very small code storage → NOR flash

 You need extreme simplicity → SPI flash

Conceptual positioning

Think of eMMC as:

“An internal SD card, soldered down, optimized for embedded systems.”

4. How hard is eMMC for a hardware designer?

Difficulty level

eMMC is:

 Harder than SDIO

 Much easier than DDR

 Very manageable with reference designs

There is:

 No training like DDR

 No source-synchronous strobes
  No protocol debugging at signal level

But:

 Signal quality matters

 Placement matters

 Power sequencing matters

Common beginner mistakes

 Placing eMMC too far from SoC

 Mixing up VCC and VCCQ voltages

 Ignoring power-up sequence

 Using unsupported eMMC speed mode

 Poor decoupling near the chip

5. Hardware design guidelines (beginner level)

Do I need controlled impedance?

Usually no strict impedance control, but:

 Traces should be consistent

 Avoid wildly different widths

 Keep reference plane continuous

Treat it like a moderate-speed parallel bus.

Do I need length matching?

 Yes, but loosely

 Match DAT lines reasonably

 CLK is the most critical

 This is not DDR-level matching

Think: “keep things neat and symmetric.”

Typical clock speeds

Very roughly:

 Legacy modes → tens of MHz

 High-speed modes → ~100–200 MHz (effective)

 Advanced modes → faster, but more sensitive

You don’t need exact numbers at the beginning.

Pull-ups, power sequencing, voltage

Important basics:

 CMD and DAT lines often need pull-ups (internal or external)

 VCC and VCCQ may be different voltages

 Power must be stable before communication

 Some modes require voltage switching (1.8 V)

What usually breaks eMMC on real boards?

Most failures come from:

 Power instability

 Incorrect voltage rails

 Bad placement

 Over-aggressive speed mode selection

 Ignoring SoC vendor guidelines

6. Electrical limits and timing modes (high level)

What “speed modes” exist?

Think of eMMC modes as:

 Slow and safe

 Faster

 Much faster (more sensitive)

Each mode increases:

 Clock rate

 Edge speed

 Sensitivity to layout quality

What changes electrically when speed increases?

As speed increases:

 Timing margins shrink

 Crosstalk matters more

 Trace length differences matter more

 Power integrity becomes critical

Still:

 No differential signaling

 No DDR-style strobes

 No per-bit training

Where do these limits come from?

From:

 eMMC standard definitions

 SoC eMMC controller documentation

 eMMC vendor datasheets

 Reference designs

7. Where do I find REAL design rules and numbers?

This is critical for safe design.

Documents that matter MOST

1. SoC datasheet and reference manual

 o eMMC controller capabilities

o Supported modes

o Voltage requirements

2. SoC hardware design guide

o Layout rules

o Length matching guidance

o Placement recommendations

3. Reference schematics and layouts

o Evaluation boards

o Development kits

Documents that are reference-only

 eMMC standard documents (JEDEC)

o Good for definitions

o Not beginner-friendly

o Not layout guides

What should you copy from reference designs?

Copy:

 Placement strategy

 Decoupling scheme

 Pull-ups / series resistors

 Routing style

 Power rail structure

This is exactly how professionals do it.

Final mental summary (lock this in)

eMMC is an embedded, soldered-down flash storage device with an internal controller.
It replaces raw NAND, simplifies storage design, and provides reliable non-volatile memory
for embedded systems.

If you understand:

 What it is

 How it connects physically

 When to choose it

 That it is not DDR-level sensitive

Then you are at the correct beginner level.

PATA, SATA, and NVMe

1) PATA (Parallel ATA / IDE)
What is it?

PATA (Parallel ATA, often called IDE) is the oldest mainstream PC storage interface.
What problem did it solve?

It standardized how hard drives connect to PCs, replacing many vendor-specific interfaces in
the 1990s.

What does it do (simple)?

It sends data bits in parallel (many bits at once) over a wide ribbon cable between the drive
and the controller.

What devices used it?

 Early HDDs

 Early CD/DVD drives

 Old desktop and laptop PCs (≈1995–2005)

What does it look like physically?

 40-pin connector (later 80-wire cable for signal integrity)

 Wide ribbon cable

 Two devices per cable (Master / Slave configuration)

Hardware reality (why it died)

 Parallel signals must arrive at the same time → skew problems

 Very poor signal integrity at high speed

 Thick cables block airflow

 Manual jumpers (master/slave) = error-prone

Typical speed: up to ~133 MB/s (theoretical)

2) SATA (Serial ATA)

What is it?

SATA (Serial ATA) is the serial replacement for PATA.

What problem did it solve?

 Eliminated parallel timing/skew problems

 Reduced cable size

 Increased speed and reliability

What does it do (simple)?

It sends data serially (bit-by-bit) over high-speed differential pairs.

What devices use it?

 HDDs

 2.5" SATA SSDs

 Optical drives

 Consumer PCs and embedded systems

What does it look like physically?

 7-pin data connector

 15-pin power connector

 One device per cable (no master/slave)

Hardware / PCB perspective

 Differential pairs (TX±, RX±)

 Requires controlled impedance

 Point-to-point link (much cleaner topology)

Performance evolution

SATA Version Raw Rate Real Throughput

SATA I 1.5 Gb/s ~150 MB/s

SATA II 3.0 Gb/s ~300 MB/s

SATA III 6.0 Gb/s ~550 MB/s

Architectural limitation

SATA still talks to storage using AHCI, which was designed for slow spinning disks → high
latency, shallow queues.

3) NVMe (Non-Volatile Memory Express)

4

What is it?

NVMe is not a cable standard—it is a storage protocol designed specifically for solid-state
memory, running on PCI Express.

What problem did it solve?

SATA + AHCI became the bottleneck once storage turned into very fast memory chips.

NVMe solves:

 High latency

 Low command parallelism

 CPU overhead

What does it do (simple)?

It lets an SSD talk to the CPU almost like RAM, using PCIe lanes instead of a slow storage
bus.

What devices use it?

 M.2 NVMe SSDs

 U.2 enterprise SSDs

 Data centers, laptops, desktops, consoles

What does it look like physically?

Most common:

 M.2 2280 card

 Key-M connector

 Uses PCIe x4 lanes

Hardware / PCB perspective

 Same signaling as PCIe:

o High-speed differential pairs

o AC-coupling capacitors

o Strict impedance and length control

 Direct connection to CPU or chipset

Performance (typical)

PCIe Gen Lanes Throughput

PCIe 3.0 x4 ~3.5 GB/s

PCIe 4.0 x4 ~7 GB/s

PCIe 5.0 x4 ~14 GB/s

Architectural leap

 64K queues × 64K commands

 Extremely low latency

 Designed for parallel access from day one

Big-Picture Comparison (Hardware-Relevant)

Feature PATA SATA NVMe

Era 1990s 2000s 2010s+

Signaling Parallel Serial differential PCIe differential

Max Speed ~133 MB/s ~550 MB/s 3–14 GB/s

Protocol ATA AHCI NVMe

Feature PATA SATA NVMe

Cable Wide ribbon Thin cable PCB traces

Devices per link 2 1 1

Latency Very high Medium Very low

Storage type HDD HDD + SSD SSD only

Scales with PCIe ❌ ❌ ✅

How to Think About Them as a Hardware Designer

Mental model

 PATA → “Parallel bus era (like old memory buses)”

 SATA → “Serial link but HDD-era software”

 NVMe → “Memory-speed storage over PCIe”

When you’d choose each

 PATA: You wouldn’t (legacy repair only)

 SATA: Cheap mass storage, compatibility, embedded Linux boards

 NVMe: Performance-critical systems, modern PCs, data logging at high rates

Why NVMe dominates modern designs

Because storage is no longer mechanical—it’s semiconductor memory, and NVMe finally

treats it that way.

PCIe and CXL

1️⃣ PCIe (Peripheral Component Interconnect Express)
4

1. What is PCIe?

What problem does it solve?

Old buses (PCI, PCI-X, parallel buses) were:

 Shared → slow

 Clocked in parallel → noisy

 Hard to scale

PCIe solves this by using high-speed serial point-to-point links.

What does it do (simple words)?

PCIe is:

A very fast data highway that connects chips and cards directly using pairs of wires, not
wide parallel buses.

Each device gets its own private link.

What kind of devices use PCIe?

 GPUs
  NVMe SSDs

 Ethernet cards (10G / 25G / 100G)

 AI accelerators

 FPGA cards

 Wi-Fi cards

 Thunderbolt controllers

 SoCs talking to external devices

If it needs high bandwidth + low latency, it’s probably PCIe.

2. What does PCIe look like physically?

PCIe is NOT “one signal”

It’s a bundle of differential pairs + a few sideband signals.

PCIe lane (the basic unit)

One lane =

 TX+ / TX- (from transmitter)

 RX+ / RX- (to receiver)

That’s it.

Bandwidth scales by adding lanes:

 x1 = 1 lane

 x4 = 4 lanes

 x8, x16, x32 …

Key PCIe signals (schematic view)

Signal Meaning

TX+ / TX- High-speed data out

RX+ / RX- High-speed data in

REFCLK+ / REFCLK- Reference clock (100 MHz)

Signal Meaning

PERST# Reset

WAKE# Power management

SMBus / I2C Sideband control (optional)

Power 12 V / 3.3 V rails

Schematic-level example (simplified)

SoC / CPU

├── PCIe_TX_P/N ─────────────┐

├── PCIe_RX_P/N ─────────────┤ Differential pairs

├── PCIe_REFCLK_P/N ────────┤

├── PERST# ─────────────────┤

└── 3.3V / GND ─────────────┘

PCIe Device

(SSD / NIC / FPGA)

No address bus.
No data bus.
Just fast serial links.

Board-level reality (what you actually route)

You route:

 Matched differential pairs

 Controlled impedance (~85 Ω diff)

 Length-matched TX/RX pairs

 Clean reference planes

Typical routing:
  Inner layers preferred

 No stubs

 Minimal vias

 AC coupling capacitors (important!)

AC coupling capacitors (critical)

PCIe requires series capacitors on TX lines:

TX_P ──||──────────> RX_P

TX_N ──||──────────> RX_N

Usually:

 75–220 nF

 Placed close to transmitter

Missing these = link won’t train.

3. When should I choose PCIe?

Choose PCIe when:

✅ You need >500 MB/s

✅ You want industry-standard expansion
✅ You connect SoC ↔ high-performance peripheral
✅ Latency matters
✅ You want scalability (x1 → x16)

Do NOT choose PCIe when:

❌ MCU-level systems (SPI/I2C/UART are enough)

❌ Low power battery devices
❌ You don’t control impedance
❌ Short development time
❌ No PCIe PHY available

PCIe is not beginner-cheap, even if conceptually clean.

4. How hard is PCIe for a hardware designer?

Conceptually: ⭐⭐☆☆☆

(Simple idea: serial lanes)

Physically: ⭐⭐⭐⭐☆

(Signal integrity matters)

System-level: ⭐⭐⭐⭐⭐

(Reset, clocking, power sequencing)

Common beginner mistakes

 ❌ No controlled impedance

 ❌ Wrong reference plane

 ❌ Forgetting AC coupling caps

 ❌ Bad REFCLK routing

 ❌ Lane polarity mismatch

 ❌ Not following reset timing

 ❌ Too many vias

 ❌ Using MCU without PCIe PHY

5. PCIe hardware design rules (beginner-safe)

Controlled impedance?

✅ YES (mandatory)

 ~85 Ω differential

 ~42–50 Ω single-ended

Length matching?

✅ YES

 Within a lane: tight (±5 mil typical)

 Lane-to-lane: looser (±100 mil)

Clock speeds?

 REFCLK: 100 MHz

 Data rate:

o Gen1: 2.5 GT/s

o Gen2: 5 GT/s

o Gen3: 8 GT/s

o Gen4: 16 GT/s

o Gen5: 32 GT/s

(You don’t “see” the clock — it’s embedded in data.)

Power & voltage

 3.3 V (logic)

 12 V (slots/cards)

 Tight sequencing relative to PERST#

What breaks PCIe boards in real life?

 Bad return path

 Poor stackup

 Missing ground stitching vias

 Reflections from stubs

 Wrong capacitor placement

 Cheap connectors

2️⃣ CXL (Compute Express Link)

4

1. What is CXL?

What problem does it solve?

PCIe is fast, but:

  Memory is stuck behind CPUs

 Accelerators can’t share memory easily

 Copying data wastes time and power

CXL fixes this by extending memory semantics across PCIe.

What does it do (simple words)?

CXL lets devices:

Share memory like it’s local RAM, even if it’s on another card.

Think:

 CPU ↔ accelerator ↔ memory

 All talking the same memory language

Devices using CXL

 Memory expanders

 AI accelerators

 SmartNICs

 Coherent FPGA cards

 Data-center CPUs (Intel, AMD, ARM)

2. What does CXL look like physically?

Important insight

⚠️CXL uses PCIe PHY and connectors

Same:

 Lanes

 Differential pairs

 Routing rules

 Slots

 Cables
Different:

 Protocol layer

 Memory coherency

Physical signals?

Exactly the same as PCIe:

 TX/RX differential pairs

 REFCLK

 Reset

 Power rails

If you can route PCIe, you can route CXL.

Schematic reality

There is no “CXL pin”.

Your schematic still says:

PCIe_TX_P/N

PCIe_RX_P/N

REFCLK

PERST#

CXL lives above the PHY.

3. When should I choose CXL?

Choose CXL when:

✅ You design data-center hardware

✅ You need memory pooling
✅ CPU ↔ accelerator coherence matters
✅ NUMA systems
✅ AI / ML systems
✅ You control both endpoints
Do NOT choose CXL when:

❌ Embedded systems
❌ MCUs
❌ Consumer electronics
❌ Cost-sensitive designs
❌ You don’t own the CPU architecture

CXL is not for hobbyist boards.

4. How hard is CXL?

Hardware difficulty

Same as PCIe ⭐⭐⭐⭐☆

System difficulty

🔥🔥🔥🔥🔥

Why?

 Cache coherency

 Memory ordering

 CPU support required

 Firmware + BIOS + OS support

Beginner mistake with CXL

Thinking:

“It’s just faster PCIe”

No.
It’s shared memory across devices.

5. CXL hardware design rules

Controlled impedance?

✅ Mandatory (same as PCIe)

Length matching?

✅ Mandatory
Clocking?

Same as PCIe

Power?

Much stricter due to memory semantics

What breaks CXL?

 Slight signal integrity issues

 Firmware mismatch

 CPU not supporting it

 BIOS configuration

 Training failures

Final mental model (important)

PCIe:

Fast point-to-point data pipe

CXL:

Shared memory fabric built on PCIe

Physically:

 Same wires

 Same routing

 Same connectors

Logically:

 Completely different worlds

USB

1) What is USB?

What is it?

USB (Universal Serial Bus) is a standardized way to connect devices so they can:
  Exchange data

 Receive power

 Identify themselves automatically

All with one cable and one connector family.

What problem does it solve?

Before USB:

 Different connectors for each device (serial, parallel, PS/2, etc.)

 Manual configuration (IRQs, drivers, jumpers)

 No standardized power delivery

USB solved:

 Plug-and-play

 One connector for many devices

 Data + power together

 Automatic device detection

What does it do (in simple words)?

USB lets a host (PC, phone, SoC) talk to devices (keyboard, flash drive, camera) over two
data wires, while also supplying power.

What kind of devices use USB?

Almost everything:

 Keyboards, mice

 Flash drives

 Cameras

 Phones

 Microcontroller boards (Arduino, STM32, ESP32)

 Debuggers (ST-Link, J-Link)

  Audio interfaces

 Storage devices

2) What does USB look like physically?

We’ll start with USB 2.0, because everything builds on it.

USB 2.0 — The Core You Must Understand First

4

Physical signals (USB 2.0)

USB 2.0 has only 4 main signals:

Signal Meaning

VBUS +5 V power from host

GND Ground

D+ Data (positive)

D− Data (negative)

👉 D+ and D− form a differential pair

(meaning data is sent as a voltage difference between them, not referenced to ground)
Speed levels (USB 2.0)

Mode Speed Typical use

Low-Speed 1.5 Mb/s Mouse, keyboard

Full-Speed 12 Mb/s MCU devices

High-Speed 480 Mb/s Flash drives, cameras

How does a device connect to a microcontroller / SoC?

There are three common hardware cases.

Case 1 — MCU with built-in USB Full-Speed PHY (most common)

What you route on PCB:

 D+ and D− from MCU directly to connector

 Series resistors (≈22–33 Ω)

 ESD protection

 5 V sensing (VBUS)

Key schematic blocks:

USB Connector

ESD Diodes

22Ω 22Ω

│ │

D+ ---- MCU USB DP

D- ---- MCU USB DM

Why this is easy

 No external PHY

 No high-speed routing complexity

 Ideal for learning

Case 2 — USB High-Speed via ULPI PHY (advanced)

What is ULPI?
ULPI (UTMI+ Low Pin Interface) is a digital bus between:

 SoC ↔ External USB PHY

Instead of routing fast analog USB signals directly from the SoC, you:

 Route digital signals (8-bit + clock) to a PHY

 PHY handles D+/D− signaling

Why it exists

 High-speed USB (480 Mb/s) is hard to route inside big SoCs

 PHY placement near connector improves signal integrity

PCB reality
  ULPI bus: ~60 MHz parallel signals

 USB D+/D− only exist after the PHY

Case 3 — USB 3.x (SuperSpeed)

USB 3 adds extra high-speed lanes.

USB 3.0+ (SuperSpeed) — Conceptually

New signals added

In addition to USB 2.0 pins:

 TX+ / TX−

 RX+ / RX−

These are separate high-speed differential pairs.

USB Version Data Method

USB 2.0 Half-duplex over D+/D−

USB 3.x Full-duplex over TX/RX pairs

Think of USB 3 as:

USB 2.0 + PCIe-like serial lanes

What is USB OTG?

Problem it solves

Classic USB has:

 Host (PC)

 Device (mouse)
OTG allows role switching:

 Phone can be host (USB drive)

 Or device (connected to PC)

How OTG works (hardware view)

 Extra pin: ID

 ID grounded → device becomes host

 ID floating → device becomes peripheral

Important:
OTG mostly affects power control and role logic, not routing.

3) When should I choose USB?

Choose USB when:

 You need PC connectivity

 You want plug-and-play

 You want power + data

 You want driver support everywhere

 You’re designing:

o Dev boards

o Debug ports

o Data logging devices

o Firmware update ports

Do NOT choose USB when:

 You need deterministic real-time latency

 You need very long cables

 You need simple point-to-point internal communication

 You need multi-drop bus (use CAN, RS-485)

4) How hard is USB for a hardware designer?

Difficulty level

USB Type Difficulty

USB 2.0 Full-Speed ⭐⭐ (easy)

USB 2.0 High-Speed ⭐⭐⭐⭐

USB 3.x ⭐⭐⭐⭐⭐

Common beginner mistakes

 Forgetting ESD protection

 Incorrect VBUS sensing

 No series resistors

 Bad grounding near connector

 Routing D+/D− over split planes

 Treating USB like UART (it is not)

5) Hardware design guidelines (beginner-level)

Do I need controlled impedance?

USB Type Controlled impedance?

Full-Speed (12 Mb/s) Not strict

High-Speed (480 Mb/s) Yes (90 Ω diff)

USB 3.x Mandatory

Do I need length matching?

 USB 2.0 FS: No

 USB 2.0 HS: Keep D+/D− close

 USB 3.x: Yes (tight)

Typical clock speeds

Interface Clock

USB FS 12 MHz signaling

USB HS 480 Mb/s NRZI

ULPI 60 MHz

USB 3.x 5–20 Gb/s

Pull-ups, voltage levels, power

 USB devices advertise speed using pull-ups on D+ or D−

 Usually internal to MCU

 VBUS = 5 V

 Data signaling ≈ 3.3 V logic

What usually breaks USB on real boards?

 Poor grounding near connector

 Long stubs on D+/D−

 Missing ESD diodes

 Power noise on VBUS

 Wrong connector footprint

 Routing under switching regulators

Mental Model to Keep Forever

 USB is NOT “just serial”

 USB 2.0 = differential signaling + timing

 USB 3.x = high-speed SerDes

 ULPI = digital escape hatch for hard analog

 OTG = power + role logic, not routing magic

Ethernet
4

1. What is Ethernet?

What problem does it solve?

Devices need to:

 Communicate over long distances

 Be interoperable (any vendor ↔ any vendor)

 Be robust against noise

 Support many devices on a network

Ethernet solves reliable digital communication over cables, at building-to-campus scale.

What does it do (simple words)?

Ethernet is:

A standardized way for devices to send digital data as electrical signals over twisted-pair
cables, so they can talk on a network.

It lets:

 Your device talk to other devices

 Your device connect to the internet

  Many devices share the same network infrastructure

What kind of devices use Ethernet?

 Microcontroller boards

 Industrial controllers (PLCs)

 Routers and switches

 PCs and servers

 Cameras (IP cameras)

 Printers

 Embedded Linux systems

 Automotive and industrial equipment

If a device needs stable wired networking, it uses Ethernet.

2️⃣ What does Ethernet look like physically?

This is where Ethernet becomes very concrete for a hardware designer.

Ethernet is split into layers (important)

You will hear these terms often:

 MAC (Media Access Controller)

Digital logic inside MCU/SoC
Talks in bytes and frames

 PHY (Physical Layer Transceiver)

Analog + mixed-signal IC
Converts digital data ↔ analog signals on the cable

 Magnetics (Isolation Transformers)

Provide electrical isolation and impedance matching

 Connector (RJ45)
The physical Ethernet jack

As a hardware designer, you design PHY + magnetics + routing.

Typical Ethernet signal chain

MCU / SoC

│ (digital interface: RMII / RGMII / MII)

Ethernet PHY

│ (analog differential pairs)

Magnetics (transformers)

│ (twisted-pair cable)

RJ45 Connector

What pins and signals exist?

Between MCU/SoC and PHY (digital side)

Common interfaces:

 MII – older, wide, slow

 RMII – reduced pin count (very common)

 RGMII – faster, used for Gigabit Ethernet

Example (RMII):

Signal Meaning

TXD[1:0] Transmit data

RXD[1:0] Receive data

TX_EN Transmit enable

CRS_DV Carrier sense / data valid

REF_CLK 50 MHz clock

Signal Meaning

MDC / MDIO PHY configuration

These are normal CMOS digital signals.

Between PHY and magnetics (analog side)

This is where beginners usually get confused.

Signals:

 TX+ / TX-

 RX+ / RX-

These are:

 Differential

 Analog

 AC-coupled

 Carefully impedance-controlled

You do not treat these like GPIOs.

Schematic-level example (simplified)

MCU / SoC

├── RMII_TXD[1:0]

├── RMII_RXD[1:0]

├── RMII_REF_CLK (50 MHz)

├── MDIO / MDC

└── RESET

▼
Ethernet PHY

├── TX_P ──||──┐

├── TX_N ──||──┤

├── RX_P ──────┤── Magnetics ── RJ45

├── RX_N ──────┘

├── AVDD / DVDD

└── Bias resistors

Notes:

 Capacitors on TX lines are mandatory

 RX lines usually connect directly

 Magnetics provide isolation and common-mode noise rejection

Board-level context (what you actually route)

You will route:

 One or two differential pairs

 100 Ω differential impedance

 Short, symmetric routes

 Solid reference plane underneath

Typical layout flow:

1. PHY close to magnetics

2. Magnetics close to RJ45

3. No stubs

4. Few vias

5. Ground stitching near magnetics

3️⃣ When should I choose Ethernet?

Choose Ethernet when:

 You need wired networking

  Cable length > a few meters

 Noise immunity matters

 Interoperability matters

 You want TCP/IP, UDP, HTTP, etc.

 Industrial or professional product

Ethernet is the default wired network choice.

Do NOT choose Ethernet when:

 Ultra-low power battery devices

 Very short distance (SPI/UART/I2C sufficient)

 Cost and PCB area are extremely tight

 No PHY available

 Wireless is mandatory

Ethernet is powerful, but not lightweight.

4️⃣ How hard is Ethernet for a hardware designer?

Conceptually

Easy
Clear block separation (MAC ↔ PHY ↔ cable)

Physically

Medium
Analog rules matter

System-level

Medium
Clocking, reset, strap pins, configuration

Common beginner mistakes

 Forgetting magnetics

 Treating PHY signals as digital

  Wrong impedance on differential pairs

 Long routes between PHY and magnetics

 Poor grounding near RJ45

 Missing termination resistors

 Wrong reference clock frequency

 Ignoring ESD protection

5️⃣ Hardware design guidelines (beginner level)

Controlled impedance?

Yes, mandatory

 Differential impedance: 100 Ω

 Especially PHY ↔ magnetics

Length matching?

 Match TX+ to TX-

 Match RX+ to RX-

 TX vs RX does not need matching

Typical clock speeds

 RMII reference clock: 50 MHz

 MII: 25 MHz

 RGMII: 125 MHz

Cable signaling:

 10BASE-T: 10 Mbps

 100BASE-TX: 100 Mbps

 1000BASE-T: 1 Gbps

Pull-ups, power, voltage levels

  PHY usually uses:

o 3.3 V analog

o 1.2–1.8 V core

 Strap resistors configure PHY mode at reset

 Reset timing is critical

 Decoupling near PHY is very important

What usually breaks Ethernet boards in real life?

 Bad magnetics footprint

 Incorrect RJ45 pinout

 Poor ground reference under PHY

 No ESD protection on cable side

 Long stubs on differential pairs

 Wrong clock source or jitter

 Missing common-mode chokes

Final mental model (important)

Ethernet is:

A carefully controlled analog interface wrapped around a digital network protocol

As a hardware designer:

 You don’t implement Ethernet logic

 You enable it electrically

 If the PHY sees clean signals, Ethernet “just works”

LVDS Display, MIPI-DSI, HDMI, DisplayPort

Big Picture First (Mental Map)

Before details, lock this in:

Interface Primary Use Typical Context

LVDS Display Internal panels Laptops, industrial HMIs

MIPI-DSI Internal mobile displays Phones, tablets, SBCs

HDMI External consumer displays TVs, monitors

DisplayPort High-performance displays PCs, docks, laptops

Key idea:
Some display interfaces are meant for inside the device, others for between devices.

1) LVDS Display (Panel LVDS)

4

1. What is LVDS Display?

What is it?
LVDS (Low-Voltage Differential Signaling) display is a simple, point-to-point video interface
used to connect a processor to an internal LCD panel.

What problem does it solve?

 Transmitting pixel data reliably inside a device

 Low EMI

 Simple electronics

 Long flat-flex cables

What does it do in simple words?

It sends pixel bits over multiple low-voltage differential pairs, synchronized by a clock,
directly into the LCD panel.

No packets. No negotiation. No hot-plug.

What kind of devices use it?

 Laptop internal displays

 Industrial HMIs

 Older SBCs

 Automotive displays (legacy)

2. What does it look like physically?

Signals you route

Typical single-channel LVDS:

 3–4 data differential pairs

 1 clock differential pair

 Power rails (panel logic, backlight)

 Control pins (enable, reset)

Example:

TX0+ TX0-

TX1+ TX1-

TX2+ TX2-

CLK+ CLK-
Each pair carries 7 bits serialized.

How it connects to a SoC

SoC LVDS TX

│ (5–10 differential pairs)

LCD Panel Connector

Often:

 SoC has built-in LVDS serializer

 No external IC required

Board-level reality

You route:

 Multiple 90–100 Ω differential pairs

 Medium speed (hundreds of MHz)

 Flat cable or FFC connector

3. When should I choose LVDS?

Choose LVDS when:

 Internal display

 Fixed resolution

 No hot-plug needed

 Simple hardware

 Long internal cable

Do NOT choose LVDS when:

 External monitor

 High resolution (>1080p)

  Hot-plug required

 EMI compliance is strict

4. How hard is LVDS?

Difficulty: LOW to MEDIUM

Common beginner mistakes

 Forgetting panel power sequencing

 Wrong pin mapping (panels are not standardized)

 Poor ground reference

 Treating LVDS like slow GPIO

5. Hardware design guidelines (LVDS)

Topic Rule

Controlled impedance Yes (≈100 Ω diff)

Length matching Within pair only

Clock speed ~65–150 MHz

Voltage ~350 mV swing

Power sequencing Critical

Common failure Panel stays white/black

2) MIPI-DSI (Display Serial Interface)

4

1. What is MIPI-DSI?

What is it?

MIPI-DSI is a high-speed serial display interface optimized for mobile and embedded
devices.

What problem does it solve?

 LVDS uses many wires

 Mobile devices need:

o Fewer pins

o Lower power

o Higher resolution

What does it do in simple words?

It sends pixel data as packets over 1 clock lane + 1–4 data lanes, using very high speed serial
signaling.

Devices using it

 Smartphones

 Tablets

 Raspberry Pi displays

 Embedded Linux boards

2. What does it look like physically?

Signals

 CLK+ / CLK−

 DATA0± … DATA3±

 Power and control pins

Each lane can run >1 Gbps.

How it connects to a SoC

SoC DSI Controller

│ High-speed differential lanes

DSI Display Connector

Usually:

 PHY integrated inside SoC

 Display panel contains DSI receiver

Board-level reality

You route:

 Few differential pairs

 Very high speed

 Short distances

 Tight impedance control

3. When should I choose DSI?

Choose DSI when:

 Mobile or embedded system

 Small, high-resolution display

 Low pin count

  Low power

Do NOT choose DSI when:

 External display

 Long cables

 Simple microcontrollers

 Beginner-only designs

4. How hard is DSI?

Difficulty: HIGH

Common beginner mistakes

 Underestimating signal speed

 Ignoring termination rules

 Bad connector choice

 No reference ground stitching

5. Hardware design guidelines (DSI)

Topic Rule

Controlled impedance Mandatory

Length matching Mandatory

Lane speed 500 Mbps–2 Gbps

Voltage ~200 mV

Power sequencing Very strict

Common failure No display init

3) HDMI
4

1. What is HDMI?

What is it?

HDMI (High-Definition Multimedia Interface) is a consumer external display interface for

video + audio.
What problem does it solve?

 One cable for:

o Video

o Audio

o Control

 Plug-and-play TVs and monitors

What does it do in simple words?

It sends video pixels over TMDS differential pairs at very high speed to an external display.

Devices using HDMI

 TVs

 Monitors

 SBCs

 GPUs

 Media players

2. What does it look like physically?

Signals

 3 × TMDS data pairs

 1 × TMDS clock pair

 DDC (I²C)

 Hot-plug detect

 5 V power

SoC connection

SoC HDMI PHY

│
ESD Protection

HDMI Connector

Often requires:

 External HDMI PHY or level shifter

 ESD diodes

 Common-mode chokes

Board-level reality

 Long cables

 EMI compliance critical

 Connector placement critical

3. When should I choose HDMI?

Choose HDMI when:

 External consumer display

 TV or monitor compatibility

 Audio + video needed

Do NOT choose HDMI when:

 Internal display

 Low power system

 Tight EMI constraints

4. How hard is HDMI?

Difficulty: HIGH

Common beginner mistakes

 No ESD protection

 Wrong impedance
  Poor connector grounding

 Ignoring EMI requirements

5. Hardware design guidelines (HDMI)

Topic Rule

Controlled impedance Mandatory (100 Ω diff)

Length matching Required

Clock speed Up to GHz

Voltage ~800 mV TMDS

Power 5 V from source

Common failure Unstable image

4) DisplayPort (DP)
4

1. What is DisplayPort?

What is it?

DisplayPort is a high-performance packet-based display interface, similar architecturally to

PCIe.

What problem does it solve?

 HDMI bandwidth limits

 Daisy-chaining

 High refresh rates

 Professional displays

What does it do in simple words?

It sends video as packets over multiple high-speed lanes, not raw pixel streams.

Devices using DP

 PCs

 Laptops

 Docking stations
  High-end monitors

2. What does it look like physically?

Signals

 1–4 high-speed lanes

 AUX channel (bidirectional)

 Hot-plug detect

 Power

SoC connection

Similar to HDMI but:

 Packet-based

 Link training required

Board-level reality

 PCIe-like routing discipline

 Very high data rates

 Strict compliance testing

3. When should I choose DisplayPort?

Choose DP when:

 High resolution / refresh

 PC-class system

 Docking support

Do NOT choose DP when:

 Simple embedded system

 Beginner board

 Low power budget

4. How hard is DisplayPort?

Difficulty: VERY HIGH

5. Hardware design guidelines (DP)

Topic Rule

Controlled impedance Mandatory

Length matching Mandatory

Lane speed Up to 8+ Gbps

Voltage Low swing

Common failure Link training fails

Final Comparison (Design Perspective)

Interface Internal / External Complexity

LVDS Internal Low

MIPI-DSI Internal High

HDMI External High

DisplayPort External Very High

Core Takeaway (This Is the Rule)

 Internal display? → LVDS or MIPI-DSI

 External TV/monitor? → HDMI or DisplayPort

 Beginner embedded board? → LVDS

 Mobile-class SoC? → MIPI-DSI

 PC-class system? → DisplayPort

Parallel CMOS, MIPI CSI-2, GMSL, HD-SDI
1️⃣ Parallel CMOS (a.k.a. DVP – Digital Video Port)
4

1. What is it?

What problem does it solve?

Early image sensors needed a simple way to output pixel data without high-speed serial
links.

Parallel CMOS solves:

 Low-cost

 Low-complexity

 Short-distance image transfer

What does it do (simple words)?

It sends pixel data one byte at a time, using many wires in parallel, synchronized by a clock.

Think:

“Every clock tick, put the next pixel on the bus.”

What kind of devices use it?

 Low-resolution cameras
  MCUs with camera interface

 Older SoCs

 Educational / hobbyist systems

 Simple vision systems

2. What does it look like physically?

Signals (typical)

Signal Meaning

D[7:0] or D[9:0] Pixel data

PCLK Pixel clock

HSYNC Line valid

VSYNC Frame valid

I2C (SDA/SCL) Sensor configuration

Power rails Analog + digital

This is pure digital CMOS signaling.

Schematic-level view

CMOS Sensor

├── D[7:0] ────────────────┐

├── PCLK ─────────────────┤

├── HSYNC ────────────────┤

├── VSYNC ────────────────┤

├── I2C SDA/SCL ──────────┤

└── AVDD / DVDD ──────────┘

MCU / SoC
No PHY.
No serializers.
No magnetics.

Board-level reality

You route:

 8–12 single-ended traces

 One clock trace

 All traces length-matched

 Very short distances

This does not scale well.

3. When should I choose it?

Choose Parallel CMOS when:

 Resolution is low

 Frame rate is low

 Distance < a few centimeters

 MCU directly supports it

 Simplicity > performance

Do NOT choose it when:

 High resolution (HD, 4K)

 Long cable

 EMI matters

 Pin count is limited

 You want scalability

4. How hard is it?

Conceptually: Easy
Physically: Medium
System-level: Easy

Common beginner mistakes

 No length matching

 Treating clock like GPIO

 Too long traces

 Crosstalk between data lines

 No solid ground reference

5. Hardware design guidelines

 Controlled impedance: Not strictly, but recommended

 Length matching: Yes (clock ↔ data)

 Clock speeds: 6–48 MHz typical

 Voltage levels: 1.8 V / 2.8 V / 3.3 V

 What breaks it:

o Skew

o Noise

o Long routing

2️⃣ MIPI CSI-2

4

1. What is it?

What problem does it solve?

Parallel CMOS:
  Uses too many pins

 Is slow

 Is noisy

MIPI CSI-2 solves:

 High resolution

 High frame rate

 Low pin count

 Low power

What does it do (simple words)?

It sends camera data serially over differential pairs, very fast, with very few wires.

Think:

“Instead of many slow wires, use a few very fast ones.”

Devices using it

 Smartphones

 Tablets

 SBCs (Raspberry Pi, Jetson)

 Automotive cameras

 Embedded vision SoCs

2. What does it look like physically?

Signals

Signal Meaning

D0+ / D0- Data lane

D1+ / D1- Data lane

CLK+ / CLK- Differential clock

I2C Sensor configuration

Signal Meaning

Power rails Multiple domains

Typically:

 1–4 data lanes

 1 clock lane

Schematic-level view

Image Sensor

├── D0_P/N ───────────┐

├── D1_P/N ───────────┤

├── CLK_P/N ──────────┤

├── I2C SDA/SCL ──────┤

└── Power rails ──────┘

SoC CSI-2 RX

Board-level context

You route:

 Differential pairs

 100 Ω impedance

 Very tight length matching

 Short, direct paths

 No stubs

This is high-speed design, even if cables are short.

3. When should I choose it?

Choose CSI-2 when:

  You need HD or higher

 Power efficiency matters

 SoC supports CSI-2

 Camera is close to processor

Do NOT choose it when:

 Long cables (>30 cm)

 Harsh EMI environment

 No CSI-2 receiver

 Simple MCU system

4. How hard is it?

Conceptually: Medium
Physically: Hard
System-level: Medium

Common beginner mistakes

 No controlled impedance

 Bad connector footprint

 Lane length mismatch

 Wrong lane polarity

 Ignoring power sequencing

5. Hardware design guidelines

 Controlled impedance: Mandatory (100 Ω diff)

 Length matching: Mandatory (within lane, lane-to-lane)

 Clock speeds: 80 Mbps → several Gbps per lane

 Voltage levels: 1.2 V / 1.8 V

 What breaks it:

 o Skew

o Bad reference plane

o Connector discontinuities

3️⃣ GMSL (Gigabit Multimedia Serial Link)

1. What is it?
What problem does it solve?

MIPI CSI-2:

 Short distance only

 Not cable-friendly

GMSL solves:

 Long cable camera links

 Automotive EMI

 Power + data over one cable

What does it do (simple words)?

It serializes camera data, sends it over a single coax or twisted pair, then deserializes it back
to CSI-2 or parallel.

Think:

“Camera over a long cable, reliably.”

Devices using it

 Automotive cameras

 ADAS systems

 Industrial vision

 Robotics

2. What does it look like physically?

Signal chain

Camera

→ Serializer

→ Coax / STP cable

→ Deserializer

→ SoC (CSI-2 or parallel)

Schematic-level view

Sensor → Serializer ── Coax ── Deserializer → SoC

Signals:

 High-speed serial differential or coax

 Power over cable (often)

 I2C tunneled over link

Board-level context

You route:

 One high-speed differential pair OR coax

 Controlled impedance

 ESD protection

 Robust grounding

3. When should I choose it?

Choose GMSL when:

 Camera is far away (meters)

 Automotive or industrial

 EMI is harsh

 You want few cables

Do NOT choose it when:

 Camera is on same PCB

 Cost sensitive

 Simple consumer design

4. How hard is it?

Conceptually: Medium
Physically: Hard
System-level: Hard

Common beginner mistakes

 Treating cable like PCB trace

 Bad coax impedance

 Ignoring grounding

 No ESD protection

5. Hardware design guidelines

 Controlled impedance: Mandatory

 Length matching: Inside serializer/deserializer only

 Speeds: 1–6 Gbps

 Voltage levels: Device-specific

 What breaks it:

o Cable mismatch

o Poor connector choice

o EMI coupling

4️⃣ HD-SDI (High-Definition Serial Digital Interface)

4
1. What is it?

What problem does it solve?

Broadcast video needs:

 Zero compression

 Long cables

 Deterministic timing

HD-SDI solves professional video transport.

What does it do (simple words)?

It sends raw video data over a single coax cable, very fast, very reliably.

Devices using it

 Broadcast cameras

 Video mixers

 Medical imaging

 Surveillance

2. What does it look like physically?

Signals:

 Single high-speed serial signal

 75 Ω coax

 BNC connectors

Schematic-level view

Video Source → SDI Driver → Coax → SDI Receiver

Board-level context

You route:
  One controlled-impedance trace

 75 Ω

 Short PCB path to connector

3. When should I choose it?

Choose HD-SDI when:

 Professional video

 Long cable runs

 No compression allowed

Do NOT choose it when:

 Embedded vision

 Consumer products

 Cost sensitive

 Small form factor

4. How hard is it?

Conceptually: Medium
Physically: Hard
System-level: Medium

Common beginner mistakes

 Wrong impedance (50 Ω instead of 75 Ω)

 Bad connector choice

 Poor return path

5. Hardware design guidelines

 Controlled impedance: Mandatory (75 Ω)

 Length matching: Not needed (single line)

  Speeds: 1.5 / 3 / 6 / 12 Gbps

 Voltage levels: Standardized

 What breaks it:

o Reflections

o Connector mismatch

o Poor grounding

Final comparison (important)

Interface Distance Speed Complexity Typical Use

Parallel CMOS cm Low Low Simple cameras

MIPI CSI-2 cm Very high High Mobile / embedded

GMSL meters Very high Very high Automotive

HD-SDI 10–100 m Very high High Broadcast

SERDES (Serializer / Deserializer)

4

1. What is SERDES?

SERDES is a hardware block that converts parallel data → high-speed serial data (serializer)
and then serial → parallel again (deserializer).

Problem it solves

 Parallel buses need many pins, many traces, and suffer from skew (signals arriving at
different times).

 At high speed, parallel routing becomes impractical.

In simple words

 Instead of sending 16 or 32 bits at once on many wires, SERDES sends them one bit
at a time, very fast, over one or a few differential pairs.
Where it is used

 PCIe, USB 3.x, SATA, Ethernet, DisplayPort, HDMI, MIPI, CXL

 FPGAs, SoCs, CPUs, GPUs, network switches

 Camera, display, storage, and inter-board links

2. What does it look like physically?

Signals you will see

At the PCB level, SERDES is simple:

 TX+ / TX− → differential transmit pair

 RX+ / RX− → differential receive pair

 Power rails (often multiple: analog, digital, PLL)

 Reference clock (sometimes external)

That’s it. No data bus, no clock bus.

Inside the SERDES block (conceptual)

 Serializer / Deserializer

 PLL / CDR (Clock Data Recovery)

 Line coding (e.g., 8b/10b, 64b/66b)

 Equalization (TX pre-emphasis, RX CTLE/DFE)

You do not design these blocks — they are inside the chip.

3. How data actually works (key intuition)

1. Parallel data exists inside the chip (e.g., 16 or 32 bits wide).

2. Serializer converts it into a bitstream.

3. Bitstream is sent over a differential pair at multi-GHz speed.

4. Receiver recovers the clock from data (no separate clock wire).

5. Deserializer reconstructs the original parallel data.

Important consequence

 Timing is no longer controlled by PCB trace length of a clock.

  Timing is recovered inside silicon, which is why SERDES scales to very high speeds.

4. Why differential signaling is mandatory

SERDES always uses differential pairs because:

 Better noise immunity

 Lower EMI

 Defined impedance (typically 100 Ω differential)

 Enables multi-GHz operation on PCB traces

Single-ended signaling cannot support SERDES speeds reliably.

5. When should you choose SERDES?

Choose SERDES when

 Data rate > ~500 Mbps

 Long distances (connectors, cables, backplanes)

 Pin count must be minimized

 You need standardized interfaces (PCIe, Ethernet, etc.)

Do NOT choose SERDES when

 Low speed control or sensor data

 Simple microcontroller projects

 Short, slow, wide buses are acceptable (SPI, parallel RGB, FSMC)

6. How hard is SERDES for a hardware designer?

Reality

 You do not design SERDES circuits

 You design the environment around them

Difficulty level

 Logic design: low (handled by IP / protocol)

 PCB design: high

  Power integrity & layout discipline: critical

SERDES is a PCB + SI problem, not a schematic creativity problem.

7. Core hardware design rules (beginner level)

Controlled impedance

 Mandatory

 100 Ω differential (most standards)

 Stack-up must be defined before routing

Length matching

 Match within a differential pair

 Lane-to-lane matching depends on protocol (PCIe stricter than Ethernet)

Routing rules

 Continuous reference plane (no splits)

 Avoid stubs

 Minimize vias (or use back-drilling)

 Smooth geometry, no sharp corners

Power & clocks

 SERDES PLLs are noise-sensitive

 Separate analog/digital rails if required

 Follow reference design decoupling exactly

8. Common beginner mistakes

 Treating SERDES like SPI or GPIO

 Ignoring impedance and stack-up

 Routing across plane splits

 Excessive vias and stubs

 Not following vendor reference layouts

 Assuming “short trace = safe” at multi-GHz

9. Mental model to remember

SERDES trades wires for speed.

Fewer pins, higher frequency, stricter PCB discipline.

If you respect impedance, return paths, and power integrity, SERDES works extremely
reliably.
If you don’t, it fails silently and brutally.

LVDS, TMDS, CML, SLVS

1. LVDS (Low-Voltage Differential Signaling)

What it is

LVDS is a low-power, low-noise differential signaling standard designed for high-speed data
over PCB traces or cables.

What problem it solves

 CMOS/TTL is too noisy and power-hungry at high speed

 Parallel buses suffer from skew and EMI

LVDS allows fast data with low voltage swing and excellent noise immunity.

How it works (physically)

 Differential pair

 ~350 mV swing

 Constant current source

 100 Ω differential termination at the receiver

Typical speeds

 ~100 Mbps up to ~1–2 Gbps (practical PCB range)

Where it is used

 FPGA I/O banks

 LCD panels (older)

 High-speed ADC/DAC outputs

 Industrial & automotive data links

Hardware difficulty

Medium

 Controlled impedance required

 Length matching recommended

 Very forgiving compared to SERDES

When to choose LVDS

Choose LVDS if:

 You need clean, fast, short-to-medium distance links

 Data rate is below multi-GHz

 You want simplicity without full SERDES

Do NOT choose if:

 You need long cables at multi-Gbps

 You want standardized protocols (PCIe, USB, etc.)

2. TMDS (Transition-Minimized Differential Signaling)

What it is

TMDS is a high-speed differential signaling method specifically designed for video data.

What problem it solves

 Video data has lots of transitions → EMI & DC imbalance

 Needs reliable transmission over cables

TMDS reduces transitions and maintains DC balance.

How it works (physically)

 Differential pairs

 Higher voltage swing than LVDS

 Uses 8b/10b-like encoding (transition minimization)

 Typically AC-coupled

Typical speeds

 Several Gbps per lane

  HDMI / DVI use multiple TMDS lanes

Where it is used

 HDMI

 DVI

 Some display links

Hardware difficulty

Medium–High

 Controlled impedance mandatory

 Length matching between lanes important

 Connector and cable quality matters

When to choose TMDS

You don’t “choose” TMDS freely — it comes with HDMI/DVI.

If you design HDMI hardware, you must respect TMDS rules.

3. CML (Current-Mode Logic)

What it is

CML is a very high-speed differential signaling style, optimized for multi-GHz operation.

What problem it solves

 CMOS logic is too slow and noisy at extreme speeds

 Voltage swing must be minimized to reduce edge distortion

CML trades power for speed.

How it works (physically)

 Differential pair

 Constant current

 Small voltage swing

 Termination usually at the receiver (50 Ω to VTT)

Typical speeds

 10–30+ Gbps
Where it is used

 SERDES transceivers

 PCIe PHYs

 Ethernet PHYs

 High-end ASICs and FPGAs

Hardware difficulty

High

 Power integrity is critical

 Tight impedance control

 Very sensitive to layout errors

When to choose CML

You typically don’t choose CML manually — it is inside SERDES PHYs.

Your job is to route it correctly.

4. SLVS (Scalable Low-Voltage Signaling)

What it is

SLVS is a very low-swing differential signaling standard, designed mainly for image sensors.

What problem it solves

 Cameras need high bandwidth

 Power consumption must be extremely low

 EMI must be minimal

How it works (physically)

 Differential pair

 ~200 mV or less swing

 Very low power per bit

 Point-to-point links

Typical speeds

 Up to several Gbps per lane (with multiple lanes)

Where it is used

 CMOS image sensors

 Mobile and embedded vision systems

 Camera-to-SoC links

Hardware difficulty

Medium

 Controlled impedance required

 Clean power important

 Short distances

When to choose SLVS

Choose SLVS if:

 You are interfacing modern image sensors

 Power and EMI are critical

 You don’t need long cables

5. Quick comparison (hardware view)

Signaling Speed Range Power Complexity Typical Use

LVDS 100 Mbps – ~1 Gbps Low Medium FPGA I/O, ADC

TMDS ~1–6+ Gbps Medium Medium-High HDMI, DVI

CML 10–30+ Gbps High High SERDES, PCIe

SLVS ~1–5+ Gbps Very Low Medium Image sensors

6. Key takeaway (important)

These are not protocols.

They are electrical signaling styles.

 Protocol = what the bits mean

 Signaling = how bits move on copper

As a hardware designer:
  You route LVDS / TMDS / CML / SLVS

 You do not invent them

 Success depends on impedance, return paths, and power integrity

High-Speed PCB Connectors

A hardware-designer’s practical guide

4

1. What makes a connector “high-speed”?

A high-speed PCB connector is one that can carry fast edge rates / multi-Gbps signals
without destroying signal integrity.

At high speed, a connector is not a mechanical part anymore.

Electrically, it is a short transmission line + discontinuity + coupling structure.

If the connector is bad:

 Reflections close the eye

 Crosstalk injects jitter

 Loss kills margin

 EMI explodes

So “high-speed” means:

 Controlled impedance through the connector

 Controlled return paths

 Low insertion loss

 Low crosstalk
2. Why connectors are dangerous at high speed

On a PCB trace, you control geometry.

Inside a connector, the manufacturer controls geometry.

A connector introduces:

 Impedance discontinuities (pad → pin → contact → pin → pad)

 Stub length

 Mode conversion (differential → common mode)

 Crosstalk between adjacent pins

At multi-GHz, even 1–2 mm of uncontrolled metal matters.

3. The most important connector parameters (you must understand these)

3.1 Differential impedance

 Most high-speed links expect 100 Ω differential

 The connector must maintain this through the mating interface

 Poor connectors dip to 70–80 Ω → reflections

Always check:

“Differential impedance profile” in the datasheet

3.2 Insertion loss (IL)

 How much signal amplitude is lost

 Increases with frequency

 Measured in dB

Rule of thumb:

 < −1 dB is excellent

 −3 dB is usually the limit per connector

Two connectors back-to-back add losses.

3.3 Return loss (RL)

 How much signal reflects back

 Indicates impedance mismatch

Bad return loss = eye closure.

3.4 Crosstalk (NEXT / FEXT)

 NEXT: near-end crosstalk

 FEXT: far-end crosstalk

High-speed connectors use:

 Ground pins between signal pins

 Shielded pin geometry

 Pair-to-pair isolation

3.5 Bandwidth rating (do not misread this)

Connector bandwidth is not data rate.

Example:

 10 GHz connector ≠ 10 Gbps safe

 Depends on encoding, eye margin, channel loss

Always assume:

Required connector bandwidth ≈ 5× fundamental frequency

4. Common high-speed connector types (and what they are good at)

4.1 Board-to-board (mezzanine) connectors

Used when:

 Two PCBs stack (SoM + carrier)

 Short distances

 Many lanes

Pros:
  Excellent SI

 Controlled pin geometry

Cons:

 Expensive

 Tight mechanical tolerances

Used for:

 PCIe

 SERDES links

 High-speed memory extensions

4.2 Edge connectors (card-edge)

Used when:

 Plug-in cards

 Backplanes

Pros:

 Robust

 Standardized

Cons:

 Large impedance discontinuity at edge

 Requires careful pad design

Used for:

 PCIe cards

 Backplane systems

4.3 Cable connectors (coax / twinax)

Used when:

 Distance > PCB length

 EMI control is critical

Pros:

 Excellent SI

 Shielded environment

Cons:

 Cost

 Assembly complexity

Used for:

 External PCIe

 High-speed video

 RF-like links

5. Differential pair handling inside connectors

Pair integrity

Good connectors:

 Keep pair spacing constant

 Maintain symmetry

 Avoid splitting the pair

Bad connectors:

 Route + and − on different pin fields

 Introduce skew

Always check:

 “Pair mapping” drawings

 Pin-to-pin symmetry

Grounding strategy

High-speed connectors need ground pins:

 Between differential pairs

 Around high-speed groups

Rule of thumb:

 At least 1 ground per differential pair

 More grounds = less crosstalk

6. Connector + PCB is ONE channel

Never evaluate a connector alone.

Your channel is:

TX → PCB trace → via → connector → via → PCB trace → RX

That means:

 Pad size

 Anti-pad size

 Via stub length

 Back-drilling

 Reference plane continuity

All matter as much as the connector itself.

7. Common beginner mistakes

1. Choosing connectors by pin count only

2. Ignoring insertion loss graphs

3. Treating connectors as “short wires”

4. Forgetting return path continuity

5. Using generic headers for >1 Gbps

6. Mixing high-speed and slow signals randomly

7. Not simulating the full channel

8. Practical selection checklist (use this)

Before choosing a connector, answer:

1. Target data rate per lane?

 2. Required bandwidth?

3. Differential impedance requirement?

4. How many connectors in series?

5. Max allowed insertion loss?

6. Required ground pin density?

7. Mechanical tolerance and mating cycles?

8. Vendor SI models available? (S-parameters)

If S-parameters are not available → red flag.

9. Mental model (very important)

A high-speed connector is a short, ugly transmission line

Your job is to make it as boring as possible electrically

Flat impedance
Minimal stubs
Strong return paths
Predictable loss

If the connector disappears electrically, you did your job.

SoC kütüphanesini oluşturmaya başla ve Zynq FPGA pinoutunu öğren dosyaları nasıl
kullancağını kavra. Sonra zaten FPGA Config I/O videosu ile devam edersin.
Burada hocam oluşturduğun high speed steps bak. Burdan sonra belki ref design +
datasheetlere göre Schematics tamamlarsın. ++ Constraintleri buna göre peripheralları
ayarla

Sonra Lesson 8 ile devam edersin böylece. Şematik bitmiş olur o kısımları tekrar edersin +
PCB kısmı hakkında bilgileri alıp kartı çizmeye başlarsın ne bilim DDR, GiE, USB, Emmc diye
ne varsa.

Start creating your own board constraints. Maybe you start from the Lesson 0. Then youd
have related reference designs for yourself. Start Lesson 7. In this lesson youd have chosen
your FPGA so you learn about the lesson also start doing the schematics of the FPGA.
Continue with other lessons and also do schematics of DDR3, GiE, USB, Emmc and if there is
anything else you added. Burada VRM seçerken PDN analizi yaparken sana yardımcı olacak
mı bak. Hatta layouta geçmeden Signal Analysis yapabilcen mi ona da bak. Ona göre layouta
geçmeden düzelt. Atp you might start routing your system or maybe to test yourself youd do
other board as you wrote down below. I dunno you decide. Then the project ends. Create
the project file add it to your CV also share with Philipp. Do your simulations and analysis.
Create a final document. Share it on linkedin. Fix your CV and linkedin page with the new
certificate.

Outcomes:

High Speed Design, PDN Analysis, Signal Analysis

Next up: Power Electronics, Spice Simulation, Osciloscope

EN SON HIGH SPEED PCB YA DA ROUTING TARZI BİR BÖLÜM KOY TASARIMA BAŞLAMADAN
BURADA DA GENEL HARDWARE DOSYALARININ İÇİNE BAK HEM ÖNCEKİ BÖLÜMLERLE İLGİLİ
BİR ŞEY OOLURSA TEKRAR ETMİŞ OLURSUN HEM DE HIGH SPEED KURALLARI YAZARSIN BU
SENİN BERİDEN BERİ SAHİP OLDUĞUN DOSYAN

MAYBE DOWNLOAD OPEN SOURCE PROJECTS FROM INTERNET CHECK THEIR SCHEMATICS
AND DO THEIR PCB DESIGN SO THAT YOU GET A FEELING OF WHAT THEY ARE. DOWNLOAD
THEM IN SCHEMATICS PHASE CHECK HOW DID THEY DO THE SCHEMATICS AND WHEN YOU
ARE ABOUT TO DO PCB DESIGN, DO THEIR LAYOUT DESIGN.

İndirdiğin dokümanlara bak şimdi işine yarayacakları seç geri kalanını sil. ÖRNEĞİN PDN için
kullanacağın da kalsın ama orda değil.

Library oluşturma ve kendi footprinlerini çizmeyi de öğren. Package delay ekle.