ECE 465
Lecture Notes # 1
Introduction to Digital Design
Shantanu Dutt
ECE Dept.
UIC
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Copyright: Shantanu Dutt
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—the analog BW is proportional to n, the
the # of distinct values or levels, while the corresponding digital BW
is proportional to log n (or more exactly to Vdd(log n))
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i.e., 2’s complement number system, floating-point number system, etc.
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Proof:
Can
always
construct . This represents a complete set of logic ops.
a table of Is this set minimal (taking out any operations renders it incomplete)? Are there other such sets?
i/ps and
o/ps for
any logic
function
as
shown
below
[Not(A1) AND Not(A2) AND Not(A3)] OR
[Not(A1) AND A2 AND A3] OR other 1 o/p rows
Representation of table w/ OR of ANDs of
variable value combos for each 1 o/p row
Is there any other set of logic ops fewer than 3 in number that is
complete (can be used to represent any logic function): {NAND},
{NOR}: NOT(x) = NAND(x, x), AND(x, y) = NOT(NAND(x,y));
OR(x,y) = NAND(NOT(x), NOT(y)) = (x’ * y’)’ = x+y
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Binary Digital
System:
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Role of Logic for Implementation of Discrete Functions
Input and output binary encoding (can represent numbers/colors/on-off signals/etc.)
based purely on required functionality; nothing to do with logic yet. In this example, the inputs are
encodings of the VIBGYOR colors in sequence (violet = 000, Indigo = 001, … Red = 110), and the
output is supposed to give a simplified 2-tone color interpretation of bluish (f=0) or reddish (f=1)
Color f (o/p) x1 x2 x3 f
0 0 0 0
violet bluish
0 0 1 0
indigo bluish
0 1 0 0
blue bluish
Binary
0 1 1 0 Note: Encoding directly from a light source will
green bluish encoding 1 0 0 1 include:
yellow reddish 1 0 1 1 • A light color sensor that converts the light
orange reddish 1 1 0 1 color to current or voltage
1 1 1 X • An A/D converter that converts above voltage
red reddish
TT with input & output encoding into digital/binary values/numbers
Original functionality for the required simplified color-tone
table functionality
• Logic plays a central role in digital circuit design as follows. Can interpret input digital signals 1
(high voltage) and 0 (low voltage) as T and F, and determine digital outputs (1/0 = T/F) based on
functionality required . Then each o/p can be seen as a logic function of inputs that can be
composed with AND/OR/NOT operators (e.g., f = x1 AND x2 OR x2 AND NOT(x3) for above
TT). Further, if we have electronic components that implement AND/OR/NOT, we can get a
circuit to implement the function producing o/p f.
• Thus, any discrete function (or a continuous one that can be converted to a discrete one w/ the
required resolution, as this one) whether logic-based or not, can be interpreted as a logic function
and implemented using a logic/digital circuit! Copyright: Shantanu Dutt
Another Design Problem
• Sometimes the TT generation may not be as straightforward as it was in the color
scheme problem. Some analysis and ingenuity may be required.
• There are two switches S1 and S2 to control a light bulb (e.g., one switch near each door
of a room w/ 2 doors). Design a logic circuit so that the bulb can be controlled
(essentially, toggled) by either switch (i.e., by flicking/pushing either switch).
Assume an
initial condition
S1 S2 Z S1 S2 Z
Off/0 np/0 np/0 On/1
np/0 np/0
On/1 np/0 p/1 Off/0
np/0 p/1
On/1 p/1 np/0 Off/0
p/1 np/0
Off/0 p/1 p/1 On/1
1-switch flick
p/1 p/1
transition arrows
(verifying consistency Legend: np: not pushed (or, say, “up” posn)
of corresponding
o/p transitions) p: pushed (or, say, “down” posn)
Design Steps (for small-size designs w/ up to around 6 vars; we will later learn
about hierarchical or divide-and-conquer strategies for larger designs)
1a. If TT can be obtained directly (due to the nature of the problem statement), then get a
“symbolic” TT/function table, encode inputs and outputs, get the logic/Boolean (0/1) TT, and go
straight to the minimization step (Step 4). Copyright: Shantanu Dutt
Otherwise go to Step 1b.
Another Design Problem (cont’d)
Alternate Statement
Design Steps (for small-size designs w/ up to around 6 vars; we will later learn
about hierarchical or divide-and-conquer strategies for larger designs)
1b.
(symbolic)
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(Canonical SOP)
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FPGAs—will do later)
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Derived from direct logic inputs
Connection between Programming Statements and or encoded from sensor inputs
Logic/Digital Circuits
Encodings provide direct logic
i/ps to actuators or decoded
to provide actuator i/ps
Pure if-then-else type constructs can be implemented using combinational
circuits since TTs that represent of comb. circuits, are big if-then-else’s.
Derived from logic inputs (direct or
encoded) and from current loop state.
Loops need to be implemented using sequential circuits, since the circuit/system needs to at
least “remember” whether currently “in the loop or out of it” and also “where in the loop” in
order to either perform the function(s) in the loop or some other function(s). There are also other
function types besides loops that a seq. circuit performs.
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Pure if-then-else type constructs can be implemented using
combinational circuits
if-then-else or
unconditional
Loops b, c using sequentialacircuits, since the
codeneed to be implemented x
circuit/system
for f (e.g., a = b*c); needs to at least “remember” f what it needs to re-dog in each iteration
of the
if-then-else loop in order to perform the combinational
(comb.) function(s)(comb.)
in the loop. There are
also code
otheror
function types besides loops that a seq. circuit performs.
unconditional code d
for g (e.g., x = a + d);
A purely combinational circuit
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Using a seq. circuit to control a loop w/ Mux or wired OR w/ initial i/p zeroing
combinational ckts (also called functional
units) processing statements in the loop:
r
repeat mapping
a e delay = 5 cc’s
a,b f (comb g
do f ; (if-then-else or uncond. code like i g
/seq) + C0 s
a = a + b) generator
t
e (comb.)
until cond C0 (e.g., a > 100) use-ip-op r
do g; (if-then-else or uncond. code for g like x = a + d) C0 ld_reg cntinp
reset 4 Counter
• In the above loop, the system, besides remembering use i/p
C0 = 1 ld_reg = 1 1 Ghz
ld_cnt
C0 = 1 cntinp = 5 clock
whether it is in or out of the loop, also needs to a in a+b
C0 use o/p
ld_cnt = 1 cntdn
remember which “a” to use; the primary input or =0
a in a+b
Assuming cnt != 0 cnt
4
just-computed feedback “a”. C0 = 0 f takes 1
• In the above loop the concept of “enabling” cc cnt =
wait state
compl
combinational function(s) o/p arises. E.g., f’s o/p is compl 0 cntdn=1 (until g done)
enabled to go to the next function g, only after the =1
loop has finished, i.e., when C0 is true
• AFTER this, f’s operation and o/p enabling has to Loading 4 (n) in the counter, and
stop. then counting down in order to
• AFTER this, the system needs to activate a wait for 5 (n+1) ccs for g to finish.
completion signal for the next function/ module g if
it is sequential since it f; g takes a varied # of cc’s A sequential circuit/system to implement a repeat loop
dependent on the i/p data (combinational is always followed by a combinational function
“ready”, so no signal to start is needed), else for the
external world when g finishes. Note: Besides implementing loops, there are other
• In general, the system needs to remember which situations in which a circuit will need to remember
stage of data processing it is in to process the data information from the past, and if so, it has to be a
of that stage, and hence a sequential circuit is
needed to control the system—do the right data sequential circuit.
processing at the right time.
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AB
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Drain
Source
Drain
Source
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nMOS Transistor – Logic ‘1’
Transfer
• VT,MP (or Vth) is the threshold
voltage of the nMOS
transistor.
• The gate-source voltage Vgs
needs to be >= Vth for an
nMOS transistor to conduct
Ack: From [Link] Copyright: Shantanu Dutt
nMOS Transistor – Logic
‘0’ Transfer
• Thus, an nMOS transistor conducts a weak 1 and a strong 0
• For a pMOS transistor to conduct, the gate-source voltage Vgs <= -Vth, and an
analogous analysis shows that with the transistor conducting (Vg = 0): (a) the
lowest output voltage can be Vth (any lower and the trans. switches off), and
(b) the highest voltage can be Vdd.
• Thus, a pMOS transistor conducts a weak 0 and a strong 1
Ack: From [Link] Copyright: Shantanu Dutt
GATES IN SERIES
Vdd – 2Vth
VA=Vdd
Vy; max Vy = min{ VA- Vth, Volt-source} = min{Vdd-Vth, Vdd} = Vdd-Vth
VB=Vdd Vx; max Vx = min{ VB- Vth, Volt-source} = min{Vdd-Vth, Vdd-Vth}
= Vdd-Vth
weak 1
Vdd
Vdd -Vt
Vdd -2Vt very weak 1
Vdd -3Vt
Vdd Vdd -4Vt
Vdd
The output can thus be a very weak 1
Ack: From [Link] Copyright: Shantanu Dutt
CMOS TRANSMISSION & LOGIC GATES
Thus an nMOS transistor passes a strong 0 and a weak 1.
A similar analysis (for pMOS, gate to source voltage has to be < the (negative) threhold
voltage VT for transistor to conduct) shows that a pMOS transistor passes a strong 1 and a
weak 0.
This is the basis of CMOS logic gates, where pMOS transistors are used in the “top” n/w
connected to Vdd to conduct a strong or good 1, and nMOS transistors are used in the
“bottom” or complementary n/w to conduct a strong 0.
Also, can Combine the two to make a CMOS pass gate, called a transmission gate, which will
pass a strong 0 and a strong 1.
VA=0 VB=0
Vx; max Vx = Vdd
Ack: Partly from [Link] Copyright: Shantanu Dutt
Problem w/ Large Switching Networks
• Even though pMOS conducts a good 1, a long series of pMOS transistors for a many-
input gate can lead to excessive resistance R and thus a large output delay RC, where C
is the load capacitance driven by the gate.
•Example: Consider an 8-variable NOR function f = (x7+x6+x5+x4+x3+x2+x1+x0)’.
Its implementation using a single n/w is given below; we assume that a pMOS
transistor has an on-resistance of Rp. Note that f = x7’x6’ ….. x1’x0’
Vdd=3v x7 x6 x5 x4 x3 x2 x1 x0
R = 8Rp f
Output delay = 8RpC
Corresponding compl. n/w (f’=x7+x6+….+x1+x0)
GND Copyright: Shantanu Dutt
Problem with Large Switching Networks (contd)
• The solution for avoiding such excessive delay is using a number of smaller switching
n/ws over “parallel” paths [otherwise, if all the smaller n/ws are on one sequential path,
there will be no or little delay improvement].
• Thus we need to break down a large function (function w/ many variables—generally >
6) into smaller ones that can each be implemented using smaller n/ws. This happens to
a large extent when a function is represented as an SOP or POS expression (it is
already broken down into ANDs and ORs) but not always (e.g., an AND or OR term
may have a large # of vars).
• E.g., the 8-i/p NOR function f can be decomposed as (and then impl as below):
– f = [(x7+x6+x5+x4) + (x3+x2+x1+x0)]’ = [(x7’x6’x5’x4’)’ + (x3’x2’x1’x0’)’]’ =
NOR(NAND(x7’,x6’,x5’,x4’), NAND(x3’,x2’,x1’,x0’)).
– Alternatively, f = (x7+..+ x4)’ (x3+..+x0)’ = AND(NOR(x7,..,x4), NOR(x3,..x0)) =
NOT(NAND(NOR(x7,..,x4), NOR(x3,..x0)))
• In general, partition inputs into smaller sub-function subsets, and implement/realize
these smaller sub-functions using as NAND/NOR/NOT functions using De-Morgan’s
either directly for each sub-function or by bringing in the external/global complement, if
any, down to the sub-functions and using De-Morgan’s if needed
Copyright: Shantanu Dutt
Problem with Large Switching Networks (contd)
• The 8-i/p NOR function f can be decomposed as (and then impl as below):
– f = [(x7+x6+x5+x4) + (x3+x2+x1+x0)]’ = [(x7’x6’x5’x4’)’ + (x3’x2’x1’x0’)’]’ =
NOR(NAND(x7’,x6’,x5’,x4’), NAND(x3’,x2’,x1’,x0’)).
Vdd=3V x7’ Vdd=3V x3’ Longest-delay paths (parallel w/ other paths)
x6’ x2’ x7’
x6’
x5’
x4’
x5’ x1’ g
g h
Vdd f
x4’ x0’ x3’ h
x2’
2Rp x1’
x0’
delay = 4RpC
Rp Rp
delay = 4RpC delay = 2RpC Parallel paths
Compl Compl Compl
GND n/w for g GND n/w for h GND n/w for NOR
Total delay = ?
4Rp 4Rp Rp
Note: Delay of a circuit = delay of its longest-delay path from input [i/p] to output [o/p]
What about for an n-i/p NOR (n > 8)?
Copyright: Shantanu Dutt
Problem with Large Switching Networks (contd)
• These small switching networks are called gates
• Thus need to use small to medium-size (<= 4 inputs) gates to
implement large logic functions
need to analyze mainly:
1) circuit cost = total # of
gate i/ps across the ckt
(combinational ckts)
2) ckt delay (meaning
max/worst-case delay)
0
3) possibly power
strong 1
consumption
Vdd strong 1
0 strong 0
X strong 1
0
A cascade or series of NAND/NOR gates will produce strong 1’s as well as strong 0’s as well as smaller delay
than a large switching n/w for the corresponding logic expression.
Copyright: Shantanu Dutt
Circuit Delay—Definition, Model, Computation
• Assume R is the on-resistance of a single nMOS or pMOS transistor, and C its i/p or gate
capacitance.
Output capacitive load
Vdd
if driving 1 nand / nor / RC-type output delay =
and /or / not gate i/p = (kR)*(2C) = k*(2RC) = k delay
2C (2 trans. gate i/ps, units (1 delay unit = 2RC).
k inputs Rg OR 1 pmos, 1 nmos, Applies to nand / nor / and /or /
driven) not gate driving 1 input of a
2C similar gate type
GND
Max gate resistance Rg GND
(can be in top/bottom
n/w in nand / nor / and /
or / not gate) k
pmos/nmos trans. in
series = kR
Rg(g1)*CL(g2) = 2R*2C
= 2 units + Rg(g2)*CL(g3)
= 3R*2C = 3 units + Rg(g3)*CL(g4) = 2R*2C
= 2 units + Rg(g4)* CL(op)
g1 = 2R*2C = 2 units
g2
g3
g4
CL(op)
A circuit path (g1g2g3g4output) Path RC-type delay (assume
= 9 units
Fig. 1: CMOS realization of a 2-i/p NAND gate (ignoring gate intrinsic GND = 2C unless
Fig. 2: A path of a circuit and its delay otherwise
or switching delay)
specified)
See slides in Appendix for a detailed derivation of above simple delay model
Copyright: Shantanu Dutt
Determining Circuit Delay
Assume that the intrinsic delay d(gi) of
each = 1.5 ns, each RC delay between a
driving gate and driven i/p for
nand/nor/and/or/not is 2.5 ns, and an
additional 1.5 ns for each xor/xnor gate
i/p. Thus i/p -> o/p delay for each gate
driving a nand/nor/and/or/not = 4 ns,
while that for driving an xor/xnor is 6 ns.
For level-1 xor/xnor, delay is also 6 ns,
assuming level 1 nand/nor/and/or/not
i/p delays are 0, due to the additional 1.5
ns i/p delay for xor/xnor). The important
issue here is not how the various gate
delays are determined, but given each
gate delay, how to efficiently determine
the delay (max/wort-case) of a circuit.
(intrinsic gate delay) + RC delay at gi’s o/p
Start from 1st level gates and go forward to 2nd level, etc. until the output gate is reached.
Boundary condition: Primary i/ps are available at time 0.
Copyright: Shantanu Dutt
Appendix: Circuit Delay—Definition, Model, Computation
• Assume R is the on-resistance of a single nMOS or pMOS transistor, and C its i/p or gate
capacitance.
• Then the worst-case “top” network resistance Rtop of a gate gi is the k*R, where k = max. # of
transistors in series in the top n/w of gi. Similarly, for the resistance R bot of the “bottom” or
complementary n/w of gi. For most gates (NAND,NOR, AND, OR, XOR, XNOR), one or both of
Rtop and Rbot = k*R.
• If CL is the capacitive load seen by a gate gi (generally = the sum of gate capacitances C of the
transistors of the gate(s) that gi drives), then the delay in gi driving its output from 0 1 is Rtop* CL
and the delay in gi driving its output from 1 0 is Rbot* CL . In general, we define gate res. Rg =
max(Rtop , Rbot), and the delay of its output signal as Rg* CL = k*R*CL
• Example: For the 2 i/p NAND gate in Fig. 1, Rtop = R (note that in the worst-case only 1 pMOS
transistor is on, so the res. then is R, and *not* R/2), Rbot = 2R. Thus Rg = 2R, and the gate’s
output delay = Rg*CL = 2R*CL . If the gate is driving a 2-input NAND/NOR/AND/OR gate, then =
CL= 2C. What is CLof a 2-input XOR or XNOR gate?
• The delay of a path = S (output delays of gates on the path). The delay of the path shown in Fig. 2
= [d(g1) + Rg(g1)*CL(g2)] + [d(g2) + Rg(g2)*CL(g3)] + [d(g3) + Rg(g3)*CL(g4)] + [d(g4) +
Rg(g4)*CL(op)], where CL(op) is the load at the output of the path and d(gi) is the “intrinsic” delay
of a gate gi to switch from off to on.
Rg(g1)*CL(g2)
+ Rg(g2)*CL(g3)
+ Rg(g3)*CL(g4)
+ Rg(g4)*CL(op)
g1
g2
g3
g4
A circuit path (g1g2g3g4output)
Fig. 1: CMOS realization of a 2-i/p NAND gate Fig. 2: A path of a circuit and its delay
Note: For NAND/NOR/AND/OR/NOT gates: Driving resistance R is proportional to # of gate inputs of driving or
source gate g1, load capacitance of input of driven or sink gate g2 it drives is always 2C irrespective of the # of g2’s
inputs, and thus g1 g2 delay (ignoring intrinsic gate delay) is [Link] g1’s # of inputs Copyright: Shantanu Dutt
Appendix: Circuit Delay (cont’d)
• The delay of a path = S (output delays of gates on the path). The delay of the path shown in Fig. 2 =
[d(g1) + Rg(g1)*CL(g2)] + [d(g2) + Rg(g2)*CL(g3)] + [d(g3) + Rg(g3)*CL(g4)] + [d(g4) +
Rg(g4)*CL(op)], where CL(op) is the load at the output of the path and d(gi) is the “intrinsic” delay of
a gate gi to switch from off to on.
• Thus, assumimg that the d(gi) for all 2-i/p gates is the same and = d(g), the path delay = 4*d(g) +
2R*2C + 2R*2C + 2R*2C + 2R* CL(op) = 4*d(g) + 12RC + 2R* CL(op) = 4*d(g) + 16RC if CL(op) =
2C.
• If we ignore the d(gi)’s (which are typically small compared to the RC delays), the rest of the delay
is the RC delay, which for this ex. = 16RC = 4*(2R*2C)
• The 2C part of the delay expression will remain unchanged (for nand/nor/and/or gates) irrespective
if the gate sizes # of i/ps). However the 2R part in each term will change to kR where k = # of i/ps
(for nand/nor/and/or gates)
• If the gates in Fig. 2 were all 3-i/p gates, the RC delay expression will be 4*(3R*2C) = 24RC =
(3/2)*(16RC) (as the # of i/ps change from 2 to 3, delay increases proportionately by a factor of 3/2).
• Thus the delay is proportional to the sum of the # of each inputs along a path (8 for the path w/ 2-
i/p gates and 12 if the gates are 3 i/ps) as long as each gate is driving only one other gate input.
• Thus a simple delay model we will use is that the delay of a gate w/ k i/ps = k, and add up this
simplified gate-i/p delay units along a path to get the path’s delay. In the ex. below is will be
2+2+2+2 = 8 gate-i/p units
• Finally, the delay of a circuit is the delay in the longest (max-delay) path of the circuit from primary
inputs to any output
Rg(g1)*CL(g2)
+ Rg(g2)*CL(g3)
+ Rg(g3)*CL(g4)
+ Rg(g4)*CL(op)
g1
g2
g3
g4
A circuit path (g1g2g3g4output)
Copyright: Shantanu Dutt
Fig. 1: CMOS realization of a 2-i/p NAND gate Fig. 2: A path of a circuit and its delay
